2 * Performance counter support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_counter.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
18 #include <asm/machdep.h>
19 #include <asm/firmware.h>
20 #include <asm/ptrace.h>
22 struct cpu_hw_counters
{
29 struct perf_counter
*counter
[MAX_HWCOUNTERS
];
30 u64 events
[MAX_HWCOUNTERS
];
31 unsigned int flags
[MAX_HWCOUNTERS
];
33 struct perf_counter
*limited_counter
[MAX_LIMITED_HWCOUNTERS
];
34 u8 limited_hwidx
[MAX_LIMITED_HWCOUNTERS
];
36 DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
);
38 struct power_pmu
*ppmu
;
41 * Normally, to ignore kernel events we set the FCS (freeze counters
42 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
43 * hypervisor bit set in the MSR, or if we are running on a processor
44 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
45 * then we need to use the FCHV bit to ignore kernel events.
47 static unsigned int freeze_counters_kernel
= MMCR0_FCS
;
49 static void perf_counter_interrupt(struct pt_regs
*regs
);
51 void perf_counter_print_debug(void)
56 * Read one performance monitor counter (PMC).
58 static unsigned long read_pmc(int idx
)
64 val
= mfspr(SPRN_PMC1
);
67 val
= mfspr(SPRN_PMC2
);
70 val
= mfspr(SPRN_PMC3
);
73 val
= mfspr(SPRN_PMC4
);
76 val
= mfspr(SPRN_PMC5
);
79 val
= mfspr(SPRN_PMC6
);
82 val
= mfspr(SPRN_PMC7
);
85 val
= mfspr(SPRN_PMC8
);
88 printk(KERN_ERR
"oops trying to read PMC%d\n", idx
);
97 static void write_pmc(int idx
, unsigned long val
)
101 mtspr(SPRN_PMC1
, val
);
104 mtspr(SPRN_PMC2
, val
);
107 mtspr(SPRN_PMC3
, val
);
110 mtspr(SPRN_PMC4
, val
);
113 mtspr(SPRN_PMC5
, val
);
116 mtspr(SPRN_PMC6
, val
);
119 mtspr(SPRN_PMC7
, val
);
122 mtspr(SPRN_PMC8
, val
);
125 printk(KERN_ERR
"oops trying to write PMC%d\n", idx
);
130 * Check if a set of events can all go on the PMU at once.
131 * If they can't, this will look at alternative codes for the events
132 * and see if any combination of alternative codes is feasible.
133 * The feasible set is returned in event[].
135 static int power_check_constraints(u64 event
[], unsigned int cflags
[],
139 u64 alternatives
[MAX_HWCOUNTERS
][MAX_EVENT_ALTERNATIVES
];
140 u64 amasks
[MAX_HWCOUNTERS
][MAX_EVENT_ALTERNATIVES
];
141 u64 avalues
[MAX_HWCOUNTERS
][MAX_EVENT_ALTERNATIVES
];
142 u64 smasks
[MAX_HWCOUNTERS
], svalues
[MAX_HWCOUNTERS
];
143 int n_alt
[MAX_HWCOUNTERS
], choice
[MAX_HWCOUNTERS
];
145 u64 addf
= ppmu
->add_fields
;
146 u64 tadd
= ppmu
->test_adder
;
148 if (n_ev
> ppmu
->n_counter
)
151 /* First see if the events will go on as-is */
152 for (i
= 0; i
< n_ev
; ++i
) {
153 if ((cflags
[i
] & PPMU_LIMITED_PMC_REQD
)
154 && !ppmu
->limited_pmc_event(event
[i
])) {
155 ppmu
->get_alternatives(event
[i
], cflags
[i
],
157 event
[i
] = alternatives
[i
][0];
159 if (ppmu
->get_constraint(event
[i
], &amasks
[i
][0],
164 for (i
= 0; i
< n_ev
; ++i
) {
165 nv
= (value
| avalues
[i
][0]) + (value
& avalues
[i
][0] & addf
);
166 if ((((nv
+ tadd
) ^ value
) & mask
) != 0 ||
167 (((nv
+ tadd
) ^ avalues
[i
][0]) & amasks
[i
][0]) != 0)
170 mask
|= amasks
[i
][0];
173 return 0; /* all OK */
175 /* doesn't work, gather alternatives... */
176 if (!ppmu
->get_alternatives
)
178 for (i
= 0; i
< n_ev
; ++i
) {
180 n_alt
[i
] = ppmu
->get_alternatives(event
[i
], cflags
[i
],
182 for (j
= 1; j
< n_alt
[i
]; ++j
)
183 ppmu
->get_constraint(alternatives
[i
][j
],
184 &amasks
[i
][j
], &avalues
[i
][j
]);
187 /* enumerate all possibilities and see if any will work */
190 value
= mask
= nv
= 0;
193 /* we're backtracking, restore context */
199 * See if any alternative k for event i,
200 * where k > j, will satisfy the constraints.
202 while (++j
< n_alt
[i
]) {
203 nv
= (value
| avalues
[i
][j
]) +
204 (value
& avalues
[i
][j
] & addf
);
205 if ((((nv
+ tadd
) ^ value
) & mask
) == 0 &&
206 (((nv
+ tadd
) ^ avalues
[i
][j
])
207 & amasks
[i
][j
]) == 0)
212 * No feasible alternative, backtrack
213 * to event i-1 and continue enumerating its
214 * alternatives from where we got up to.
220 * Found a feasible alternative for event i,
221 * remember where we got up to with this event,
222 * go on to the next event, and start with
223 * the first alternative for it.
229 mask
|= amasks
[i
][j
];
235 /* OK, we have a feasible combination, tell the caller the solution */
236 for (i
= 0; i
< n_ev
; ++i
)
237 event
[i
] = alternatives
[i
][choice
[i
]];
242 * Check if newly-added counters have consistent settings for
243 * exclude_{user,kernel,hv} with each other and any previously
246 static int check_excludes(struct perf_counter
**ctrs
, unsigned int cflags
[],
247 int n_prev
, int n_new
)
249 int eu
= 0, ek
= 0, eh
= 0;
251 struct perf_counter
*counter
;
258 for (i
= 0; i
< n
; ++i
) {
259 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
) {
260 cflags
[i
] &= ~PPMU_LIMITED_PMC_REQD
;
265 eu
= counter
->attr
.exclude_user
;
266 ek
= counter
->attr
.exclude_kernel
;
267 eh
= counter
->attr
.exclude_hv
;
269 } else if (counter
->attr
.exclude_user
!= eu
||
270 counter
->attr
.exclude_kernel
!= ek
||
271 counter
->attr
.exclude_hv
!= eh
) {
277 for (i
= 0; i
< n
; ++i
)
278 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
)
279 cflags
[i
] |= PPMU_LIMITED_PMC_REQD
;
284 static void power_pmu_read(struct perf_counter
*counter
)
286 long val
, delta
, prev
;
288 if (!counter
->hw
.idx
)
291 * Performance monitor interrupts come even when interrupts
292 * are soft-disabled, as long as interrupts are hard-enabled.
293 * Therefore we treat them like NMIs.
296 prev
= atomic64_read(&counter
->hw
.prev_count
);
298 val
= read_pmc(counter
->hw
.idx
);
299 } while (atomic64_cmpxchg(&counter
->hw
.prev_count
, prev
, val
) != prev
);
301 /* The counters are only 32 bits wide */
302 delta
= (val
- prev
) & 0xfffffffful
;
303 atomic64_add(delta
, &counter
->count
);
304 atomic64_sub(delta
, &counter
->hw
.period_left
);
308 * On some machines, PMC5 and PMC6 can't be written, don't respect
309 * the freeze conditions, and don't generate interrupts. This tells
310 * us if `counter' is using such a PMC.
312 static int is_limited_pmc(int pmcnum
)
314 return (ppmu
->flags
& PPMU_LIMITED_PMC5_6
)
315 && (pmcnum
== 5 || pmcnum
== 6);
318 static void freeze_limited_counters(struct cpu_hw_counters
*cpuhw
,
319 unsigned long pmc5
, unsigned long pmc6
)
321 struct perf_counter
*counter
;
322 u64 val
, prev
, delta
;
325 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
326 counter
= cpuhw
->limited_counter
[i
];
327 if (!counter
->hw
.idx
)
329 val
= (counter
->hw
.idx
== 5) ? pmc5
: pmc6
;
330 prev
= atomic64_read(&counter
->hw
.prev_count
);
332 delta
= (val
- prev
) & 0xfffffffful
;
333 atomic64_add(delta
, &counter
->count
);
337 static void thaw_limited_counters(struct cpu_hw_counters
*cpuhw
,
338 unsigned long pmc5
, unsigned long pmc6
)
340 struct perf_counter
*counter
;
344 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
345 counter
= cpuhw
->limited_counter
[i
];
346 counter
->hw
.idx
= cpuhw
->limited_hwidx
[i
];
347 val
= (counter
->hw
.idx
== 5) ? pmc5
: pmc6
;
348 atomic64_set(&counter
->hw
.prev_count
, val
);
349 perf_counter_update_userpage(counter
);
354 * Since limited counters don't respect the freeze conditions, we
355 * have to read them immediately after freezing or unfreezing the
356 * other counters. We try to keep the values from the limited
357 * counters as consistent as possible by keeping the delay (in
358 * cycles and instructions) between freezing/unfreezing and reading
359 * the limited counters as small and consistent as possible.
360 * Therefore, if any limited counters are in use, we read them
361 * both, and always in the same order, to minimize variability,
362 * and do it inside the same asm that writes MMCR0.
364 static void write_mmcr0(struct cpu_hw_counters
*cpuhw
, unsigned long mmcr0
)
366 unsigned long pmc5
, pmc6
;
368 if (!cpuhw
->n_limited
) {
369 mtspr(SPRN_MMCR0
, mmcr0
);
374 * Write MMCR0, then read PMC5 and PMC6 immediately.
375 * To ensure we don't get a performance monitor interrupt
376 * between writing MMCR0 and freezing/thawing the limited
377 * counters, we first write MMCR0 with the counter overflow
378 * interrupt enable bits turned off.
380 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
381 : "=&r" (pmc5
), "=&r" (pmc6
)
382 : "r" (mmcr0
& ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
)),
384 "i" (SPRN_PMC5
), "i" (SPRN_PMC6
));
386 if (mmcr0
& MMCR0_FC
)
387 freeze_limited_counters(cpuhw
, pmc5
, pmc6
);
389 thaw_limited_counters(cpuhw
, pmc5
, pmc6
);
392 * Write the full MMCR0 including the counter overflow interrupt
393 * enable bits, if necessary.
395 if (mmcr0
& (MMCR0_PMC1CE
| MMCR0_PMCjCE
))
396 mtspr(SPRN_MMCR0
, mmcr0
);
400 * Disable all counters to prevent PMU interrupts and to allow
401 * counters to be added or removed.
403 void hw_perf_disable(void)
405 struct cpu_hw_counters
*cpuhw
;
409 local_irq_save(flags
);
410 cpuhw
= &__get_cpu_var(cpu_hw_counters
);
412 ret
= cpuhw
->disabled
;
418 * Check if we ever enabled the PMU on this cpu.
420 if (!cpuhw
->pmcs_enabled
) {
421 if (ppc_md
.enable_pmcs
)
422 ppc_md
.enable_pmcs();
423 cpuhw
->pmcs_enabled
= 1;
427 * Disable instruction sampling if it was enabled
429 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
431 cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
436 * Set the 'freeze counters' bit.
437 * The barrier is to make sure the mtspr has been
438 * executed and the PMU has frozen the counters
441 write_mmcr0(cpuhw
, mfspr(SPRN_MMCR0
) | MMCR0_FC
);
444 local_irq_restore(flags
);
448 * Re-enable all counters if disable == 0.
449 * If we were previously disabled and counters were added, then
450 * put the new config on the PMU.
452 void hw_perf_enable(void)
454 struct perf_counter
*counter
;
455 struct cpu_hw_counters
*cpuhw
;
460 unsigned int hwc_index
[MAX_HWCOUNTERS
];
464 local_irq_save(flags
);
465 cpuhw
= &__get_cpu_var(cpu_hw_counters
);
466 if (!cpuhw
->disabled
) {
467 local_irq_restore(flags
);
473 * If we didn't change anything, or only removed counters,
474 * no need to recalculate MMCR* settings and reset the PMCs.
475 * Just reenable the PMU with the current MMCR* settings
476 * (possibly updated for removal of counters).
478 if (!cpuhw
->n_added
) {
479 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
480 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
481 if (cpuhw
->n_counters
== 0)
482 get_lppaca()->pmcregs_in_use
= 0;
487 * Compute MMCR* values for the new set of counters
489 if (ppmu
->compute_mmcr(cpuhw
->events
, cpuhw
->n_counters
, hwc_index
,
491 /* shouldn't ever get here */
492 printk(KERN_ERR
"oops compute_mmcr failed\n");
497 * Add in MMCR0 freeze bits corresponding to the
498 * attr.exclude_* bits for the first counter.
499 * We have already checked that all counters have the
500 * same values for these bits as the first counter.
502 counter
= cpuhw
->counter
[0];
503 if (counter
->attr
.exclude_user
)
504 cpuhw
->mmcr
[0] |= MMCR0_FCP
;
505 if (counter
->attr
.exclude_kernel
)
506 cpuhw
->mmcr
[0] |= freeze_counters_kernel
;
507 if (counter
->attr
.exclude_hv
)
508 cpuhw
->mmcr
[0] |= MMCR0_FCHV
;
511 * Write the new configuration to MMCR* with the freeze
512 * bit set and set the hardware counters to their initial values.
513 * Then unfreeze the counters.
515 get_lppaca()->pmcregs_in_use
= 1;
516 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
517 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
518 mtspr(SPRN_MMCR0
, (cpuhw
->mmcr
[0] & ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
))
522 * Read off any pre-existing counters that need to move
525 for (i
= 0; i
< cpuhw
->n_counters
; ++i
) {
526 counter
= cpuhw
->counter
[i
];
527 if (counter
->hw
.idx
&& counter
->hw
.idx
!= hwc_index
[i
] + 1) {
528 power_pmu_read(counter
);
529 write_pmc(counter
->hw
.idx
, 0);
535 * Initialize the PMCs for all the new and moved counters.
537 cpuhw
->n_limited
= n_lim
= 0;
538 for (i
= 0; i
< cpuhw
->n_counters
; ++i
) {
539 counter
= cpuhw
->counter
[i
];
542 idx
= hwc_index
[i
] + 1;
543 if (is_limited_pmc(idx
)) {
544 cpuhw
->limited_counter
[n_lim
] = counter
;
545 cpuhw
->limited_hwidx
[n_lim
] = idx
;
550 if (counter
->hw
.sample_period
) {
551 left
= atomic64_read(&counter
->hw
.period_left
);
552 if (left
< 0x80000000L
)
553 val
= 0x80000000L
- left
;
555 atomic64_set(&counter
->hw
.prev_count
, val
);
556 counter
->hw
.idx
= idx
;
558 perf_counter_update_userpage(counter
);
560 cpuhw
->n_limited
= n_lim
;
561 cpuhw
->mmcr
[0] |= MMCR0_PMXE
| MMCR0_FCECE
;
565 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
568 * Enable instruction sampling if necessary
570 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
572 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2]);
576 local_irq_restore(flags
);
579 static int collect_events(struct perf_counter
*group
, int max_count
,
580 struct perf_counter
*ctrs
[], u64
*events
,
584 struct perf_counter
*counter
;
586 if (!is_software_counter(group
)) {
590 flags
[n
] = group
->hw
.counter_base
;
591 events
[n
++] = group
->hw
.config
;
593 list_for_each_entry(counter
, &group
->sibling_list
, list_entry
) {
594 if (!is_software_counter(counter
) &&
595 counter
->state
!= PERF_COUNTER_STATE_OFF
) {
599 flags
[n
] = counter
->hw
.counter_base
;
600 events
[n
++] = counter
->hw
.config
;
606 static void counter_sched_in(struct perf_counter
*counter
, int cpu
)
608 counter
->state
= PERF_COUNTER_STATE_ACTIVE
;
609 counter
->oncpu
= cpu
;
610 counter
->tstamp_running
+= counter
->ctx
->time
- counter
->tstamp_stopped
;
611 if (is_software_counter(counter
))
612 counter
->pmu
->enable(counter
);
616 * Called to enable a whole group of counters.
617 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
618 * Assumes the caller has disabled interrupts and has
619 * frozen the PMU with hw_perf_save_disable.
621 int hw_perf_group_sched_in(struct perf_counter
*group_leader
,
622 struct perf_cpu_context
*cpuctx
,
623 struct perf_counter_context
*ctx
, int cpu
)
625 struct cpu_hw_counters
*cpuhw
;
627 struct perf_counter
*sub
;
629 cpuhw
= &__get_cpu_var(cpu_hw_counters
);
630 n0
= cpuhw
->n_counters
;
631 n
= collect_events(group_leader
, ppmu
->n_counter
- n0
,
632 &cpuhw
->counter
[n0
], &cpuhw
->events
[n0
],
636 if (check_excludes(cpuhw
->counter
, cpuhw
->flags
, n0
, n
))
638 i
= power_check_constraints(cpuhw
->events
, cpuhw
->flags
, n
+ n0
);
641 cpuhw
->n_counters
= n0
+ n
;
645 * OK, this group can go on; update counter states etc.,
646 * and enable any software counters
648 for (i
= n0
; i
< n0
+ n
; ++i
)
649 cpuhw
->counter
[i
]->hw
.config
= cpuhw
->events
[i
];
650 cpuctx
->active_oncpu
+= n
;
652 counter_sched_in(group_leader
, cpu
);
653 list_for_each_entry(sub
, &group_leader
->sibling_list
, list_entry
) {
654 if (sub
->state
!= PERF_COUNTER_STATE_OFF
) {
655 counter_sched_in(sub
, cpu
);
665 * Add a counter to the PMU.
666 * If all counters are not already frozen, then we disable and
667 * re-enable the PMU in order to get hw_perf_enable to do the
668 * actual work of reconfiguring the PMU.
670 static int power_pmu_enable(struct perf_counter
*counter
)
672 struct cpu_hw_counters
*cpuhw
;
677 local_irq_save(flags
);
681 * Add the counter to the list (if there is room)
682 * and check whether the total set is still feasible.
684 cpuhw
= &__get_cpu_var(cpu_hw_counters
);
685 n0
= cpuhw
->n_counters
;
686 if (n0
>= ppmu
->n_counter
)
688 cpuhw
->counter
[n0
] = counter
;
689 cpuhw
->events
[n0
] = counter
->hw
.config
;
690 cpuhw
->flags
[n0
] = counter
->hw
.counter_base
;
691 if (check_excludes(cpuhw
->counter
, cpuhw
->flags
, n0
, 1))
693 if (power_check_constraints(cpuhw
->events
, cpuhw
->flags
, n0
+ 1))
696 counter
->hw
.config
= cpuhw
->events
[n0
];
703 local_irq_restore(flags
);
708 * Remove a counter from the PMU.
710 static void power_pmu_disable(struct perf_counter
*counter
)
712 struct cpu_hw_counters
*cpuhw
;
716 local_irq_save(flags
);
719 power_pmu_read(counter
);
721 cpuhw
= &__get_cpu_var(cpu_hw_counters
);
722 for (i
= 0; i
< cpuhw
->n_counters
; ++i
) {
723 if (counter
== cpuhw
->counter
[i
]) {
724 while (++i
< cpuhw
->n_counters
)
725 cpuhw
->counter
[i
-1] = cpuhw
->counter
[i
];
727 ppmu
->disable_pmc(counter
->hw
.idx
- 1, cpuhw
->mmcr
);
728 if (counter
->hw
.idx
) {
729 write_pmc(counter
->hw
.idx
, 0);
732 perf_counter_update_userpage(counter
);
736 for (i
= 0; i
< cpuhw
->n_limited
; ++i
)
737 if (counter
== cpuhw
->limited_counter
[i
])
739 if (i
< cpuhw
->n_limited
) {
740 while (++i
< cpuhw
->n_limited
) {
741 cpuhw
->limited_counter
[i
-1] = cpuhw
->limited_counter
[i
];
742 cpuhw
->limited_hwidx
[i
-1] = cpuhw
->limited_hwidx
[i
];
746 if (cpuhw
->n_counters
== 0) {
747 /* disable exceptions if no counters are running */
748 cpuhw
->mmcr
[0] &= ~(MMCR0_PMXE
| MMCR0_FCECE
);
752 local_irq_restore(flags
);
756 * Re-enable interrupts on a counter after they were throttled
757 * because they were coming too fast.
759 static void power_pmu_unthrottle(struct perf_counter
*counter
)
764 if (!counter
->hw
.idx
|| !counter
->hw
.sample_period
)
766 local_irq_save(flags
);
768 power_pmu_read(counter
);
769 left
= counter
->hw
.sample_period
;
771 if (left
< 0x80000000L
)
772 val
= 0x80000000L
- left
;
773 write_pmc(counter
->hw
.idx
, val
);
774 atomic64_set(&counter
->hw
.prev_count
, val
);
775 atomic64_set(&counter
->hw
.period_left
, left
);
776 perf_counter_update_userpage(counter
);
778 local_irq_restore(flags
);
781 struct pmu power_pmu
= {
782 .enable
= power_pmu_enable
,
783 .disable
= power_pmu_disable
,
784 .read
= power_pmu_read
,
785 .unthrottle
= power_pmu_unthrottle
,
789 * Return 1 if we might be able to put counter on a limited PMC,
791 * A counter can only go on a limited PMC if it counts something
792 * that a limited PMC can count, doesn't require interrupts, and
793 * doesn't exclude any processor mode.
795 static int can_go_on_limited_pmc(struct perf_counter
*counter
, u64 ev
,
799 u64 alt
[MAX_EVENT_ALTERNATIVES
];
801 if (counter
->attr
.exclude_user
802 || counter
->attr
.exclude_kernel
803 || counter
->attr
.exclude_hv
804 || counter
->attr
.sample_period
)
807 if (ppmu
->limited_pmc_event(ev
))
811 * The requested event isn't on a limited PMC already;
812 * see if any alternative code goes on a limited PMC.
814 if (!ppmu
->get_alternatives
)
817 flags
|= PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
;
818 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
824 * Find an alternative event that goes on a normal PMC, if possible,
825 * and return the event code, or 0 if there is no such alternative.
826 * (Note: event code 0 is "don't count" on all machines.)
828 static u64
normal_pmc_alternative(u64 ev
, unsigned long flags
)
830 u64 alt
[MAX_EVENT_ALTERNATIVES
];
833 flags
&= ~(PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
);
834 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
840 /* Number of perf_counters counting hardware events */
841 static atomic_t num_counters
;
842 /* Used to avoid races in calling reserve/release_pmc_hardware */
843 static DEFINE_MUTEX(pmc_reserve_mutex
);
846 * Release the PMU if this is the last perf_counter.
848 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
850 if (!atomic_add_unless(&num_counters
, -1, 1)) {
851 mutex_lock(&pmc_reserve_mutex
);
852 if (atomic_dec_return(&num_counters
) == 0)
853 release_pmc_hardware();
854 mutex_unlock(&pmc_reserve_mutex
);
858 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
862 struct perf_counter
*ctrs
[MAX_HWCOUNTERS
];
863 u64 events
[MAX_HWCOUNTERS
];
864 unsigned int cflags
[MAX_HWCOUNTERS
];
869 return ERR_PTR(-ENXIO
);
870 if (counter
->attr
.type
!= PERF_TYPE_RAW
) {
871 ev
= counter
->attr
.config
;
872 if (ev
>= ppmu
->n_generic
|| ppmu
->generic_events
[ev
] == 0)
873 return ERR_PTR(-EOPNOTSUPP
);
874 ev
= ppmu
->generic_events
[ev
];
876 ev
= counter
->attr
.config
;
878 counter
->hw
.config_base
= ev
;
882 * If we are not running on a hypervisor, force the
883 * exclude_hv bit to 0 so that we don't care what
884 * the user set it to.
886 if (!firmware_has_feature(FW_FEATURE_LPAR
))
887 counter
->attr
.exclude_hv
= 0;
890 * If this is a per-task counter, then we can use
891 * PM_RUN_* events interchangeably with their non RUN_*
892 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
893 * XXX we should check if the task is an idle task.
896 if (counter
->ctx
->task
)
897 flags
|= PPMU_ONLY_COUNT_RUN
;
900 * If this machine has limited counters, check whether this
901 * event could go on a limited counter.
903 if (ppmu
->flags
& PPMU_LIMITED_PMC5_6
) {
904 if (can_go_on_limited_pmc(counter
, ev
, flags
)) {
905 flags
|= PPMU_LIMITED_PMC_OK
;
906 } else if (ppmu
->limited_pmc_event(ev
)) {
908 * The requested event is on a limited PMC,
909 * but we can't use a limited PMC; see if any
910 * alternative goes on a normal PMC.
912 ev
= normal_pmc_alternative(ev
, flags
);
914 return ERR_PTR(-EINVAL
);
919 * If this is in a group, check if it can go on with all the
920 * other hardware counters in the group. We assume the counter
921 * hasn't been linked into its leader's sibling list at this point.
924 if (counter
->group_leader
!= counter
) {
925 n
= collect_events(counter
->group_leader
, ppmu
->n_counter
- 1,
926 ctrs
, events
, cflags
);
928 return ERR_PTR(-EINVAL
);
933 if (check_excludes(ctrs
, cflags
, n
, 1))
934 return ERR_PTR(-EINVAL
);
935 if (power_check_constraints(events
, cflags
, n
+ 1))
936 return ERR_PTR(-EINVAL
);
938 counter
->hw
.config
= events
[n
];
939 counter
->hw
.counter_base
= cflags
[n
];
940 atomic64_set(&counter
->hw
.period_left
, counter
->hw
.sample_period
);
943 * See if we need to reserve the PMU.
944 * If no counters are currently in use, then we have to take a
945 * mutex to ensure that we don't race with another task doing
946 * reserve_pmc_hardware or release_pmc_hardware.
949 if (!atomic_inc_not_zero(&num_counters
)) {
950 mutex_lock(&pmc_reserve_mutex
);
951 if (atomic_read(&num_counters
) == 0 &&
952 reserve_pmc_hardware(perf_counter_interrupt
))
955 atomic_inc(&num_counters
);
956 mutex_unlock(&pmc_reserve_mutex
);
958 counter
->destroy
= hw_perf_counter_destroy
;
966 * A counter has overflowed; update its count and record
967 * things if requested. Note that interrupts are hard-disabled
968 * here so there is no possibility of being interrupted.
970 static void record_and_restart(struct perf_counter
*counter
, long val
,
971 struct pt_regs
*regs
, int nmi
)
973 u64 period
= counter
->hw
.sample_period
;
974 s64 prev
, delta
, left
;
976 u64 addr
, mmcra
, sdsync
;
978 /* we don't have to worry about interrupts here */
979 prev
= atomic64_read(&counter
->hw
.prev_count
);
980 delta
= (val
- prev
) & 0xfffffffful
;
981 atomic64_add(delta
, &counter
->count
);
984 * See if the total period for this counter has expired,
985 * and update for the next period.
988 left
= atomic64_read(&counter
->hw
.period_left
) - delta
;
996 if (left
< 0x80000000L
)
997 val
= 0x80000000L
- left
;
1001 * Finally record data if requested.
1004 struct perf_sample_data data
= {
1009 if (counter
->attr
.sample_type
& PERF_SAMPLE_ADDR
) {
1011 * The user wants a data address recorded.
1012 * If we're not doing instruction sampling,
1013 * give them the SDAR (sampled data address).
1014 * If we are doing instruction sampling, then only
1015 * give them the SDAR if it corresponds to the
1016 * instruction pointed to by SIAR; this is indicated
1017 * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA.
1019 mmcra
= regs
->dsisr
;
1020 sdsync
= (ppmu
->flags
& PPMU_ALT_SIPR
) ?
1021 POWER6_MMCRA_SDSYNC
: MMCRA_SDSYNC
;
1022 if (!(mmcra
& MMCRA_SAMPLE_ENABLE
) || (mmcra
& sdsync
))
1023 data
.addr
= mfspr(SPRN_SDAR
);
1025 if (perf_counter_overflow(counter
, nmi
, &data
)) {
1027 * Interrupts are coming too fast - throttle them
1028 * by setting the counter to 0, so it will be
1029 * at least 2^30 cycles until the next interrupt
1030 * (assuming each counter counts at most 2 counts
1038 write_pmc(counter
->hw
.idx
, val
);
1039 atomic64_set(&counter
->hw
.prev_count
, val
);
1040 atomic64_set(&counter
->hw
.period_left
, left
);
1041 perf_counter_update_userpage(counter
);
1045 * Called from generic code to get the misc flags (i.e. processor mode)
1048 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1050 unsigned long mmcra
;
1052 if (TRAP(regs
) != 0xf00) {
1053 /* not a PMU interrupt */
1054 return user_mode(regs
) ? PERF_EVENT_MISC_USER
:
1055 PERF_EVENT_MISC_KERNEL
;
1058 mmcra
= regs
->dsisr
;
1059 if (ppmu
->flags
& PPMU_ALT_SIPR
) {
1060 if (mmcra
& POWER6_MMCRA_SIHV
)
1061 return PERF_EVENT_MISC_HYPERVISOR
;
1062 return (mmcra
& POWER6_MMCRA_SIPR
) ? PERF_EVENT_MISC_USER
:
1063 PERF_EVENT_MISC_KERNEL
;
1065 if (mmcra
& MMCRA_SIHV
)
1066 return PERF_EVENT_MISC_HYPERVISOR
;
1067 return (mmcra
& MMCRA_SIPR
) ? PERF_EVENT_MISC_USER
:
1068 PERF_EVENT_MISC_KERNEL
;
1072 * Called from generic code to get the instruction pointer
1075 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1077 unsigned long mmcra
;
1081 if (TRAP(regs
) != 0xf00)
1082 return regs
->nip
; /* not a PMU interrupt */
1084 ip
= mfspr(SPRN_SIAR
);
1085 mmcra
= regs
->dsisr
;
1086 if ((mmcra
& MMCRA_SAMPLE_ENABLE
) && !(ppmu
->flags
& PPMU_ALT_SIPR
)) {
1087 slot
= (mmcra
& MMCRA_SLOT
) >> MMCRA_SLOT_SHIFT
;
1089 ip
+= 4 * (slot
- 1);
1095 * Performance monitor interrupt stuff
1097 static void perf_counter_interrupt(struct pt_regs
*regs
)
1100 struct cpu_hw_counters
*cpuhw
= &__get_cpu_var(cpu_hw_counters
);
1101 struct perf_counter
*counter
;
1106 if (cpuhw
->n_limited
)
1107 freeze_limited_counters(cpuhw
, mfspr(SPRN_PMC5
),
1111 * Overload regs->dsisr to store MMCRA so we only need to read it once.
1113 regs
->dsisr
= mfspr(SPRN_MMCRA
);
1116 * If interrupts were soft-disabled when this PMU interrupt
1117 * occurred, treat it as an NMI.
1125 for (i
= 0; i
< cpuhw
->n_counters
; ++i
) {
1126 counter
= cpuhw
->counter
[i
];
1127 if (!counter
->hw
.idx
|| is_limited_pmc(counter
->hw
.idx
))
1129 val
= read_pmc(counter
->hw
.idx
);
1131 /* counter has overflowed */
1133 record_and_restart(counter
, val
, regs
, nmi
);
1138 * In case we didn't find and reset the counter that caused
1139 * the interrupt, scan all counters and reset any that are
1140 * negative, to avoid getting continual interrupts.
1141 * Any that we processed in the previous loop will not be negative.
1144 for (i
= 0; i
< ppmu
->n_counter
; ++i
) {
1145 if (is_limited_pmc(i
+ 1))
1147 val
= read_pmc(i
+ 1);
1149 write_pmc(i
+ 1, 0);
1154 * Reset MMCR0 to its normal value. This will set PMXE and
1155 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1156 * and thus allow interrupts to occur again.
1157 * XXX might want to use MSR.PM to keep the counters frozen until
1158 * we get back out of this interrupt.
1160 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
1168 void hw_perf_counter_setup(int cpu
)
1170 struct cpu_hw_counters
*cpuhw
= &per_cpu(cpu_hw_counters
, cpu
);
1172 memset(cpuhw
, 0, sizeof(*cpuhw
));
1173 cpuhw
->mmcr
[0] = MMCR0_FC
;
1176 extern struct power_pmu power4_pmu
;
1177 extern struct power_pmu ppc970_pmu
;
1178 extern struct power_pmu power5_pmu
;
1179 extern struct power_pmu power5p_pmu
;
1180 extern struct power_pmu power6_pmu
;
1182 static int init_perf_counters(void)
1186 /* XXX should get this from cputable */
1187 pvr
= mfspr(SPRN_PVR
);
1188 switch (PVR_VER(pvr
)) {
1202 ppmu
= &power5p_pmu
;
1210 * Use FCHV to ignore kernel events if MSR.HV is set.
1212 if (mfmsr() & MSR_HV
)
1213 freeze_counters_kernel
= MMCR0_FCHV
;
1218 arch_initcall(init_perf_counters
);