?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sata_mv errata workaround for sata25 part 1
[linux-2.6/verdex.git] / drivers / ata / sata_mv.c
blobfbccf215d501785866f4540e0c316c5447d9293e
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
72
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.20"
75
76 enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
93 MV_SATAHC0_REG_BASE = 0x20000,
94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
112 MV_MAX_SG_CT = 256,
113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
114
115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
116 MV_PORT_HC_SHIFT = 2,
117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
124 /* SoC integrated controllers, no PCI interface */
125 MV_FLAG_SOC = (1 << 28),
126
127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
131
132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
147 /* PCI interface registers */
148
149 PCI_COMMAND_OFS = 0xc00,
150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
151
152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
177
178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
223
224 LTMODE_OFS = 0x30c,
225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
227 PHY_MODE3 = 0x310,
228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
234
235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
238
239 MV5_PHY_MODE = 0x74,
240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
243
244 MV_M2_PREAMP_MASK = 0x7e0,
245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
272
273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
280
281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
289
290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
297 EDMA_ERR_LNK_CTRL_TX,
298
299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
305 EDMA_ERR_CRQB_PAR |
306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
313
314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
321 EDMA_ERR_CRQB_PAR |
322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
325
326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
345
346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
350
351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
359 MV_HP_ERRATA_XX42A0 = (1 << 5),
360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
365
366 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
369 };
370
371 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
373 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
374 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
375 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
376
377 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
380 enum {
381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
385
386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
391 /* ditto, for response queue */
392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393 };
394
395 enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
401 chip_6042,
402 chip_7042,
403 chip_soc,
404 };
405
406 /* Command ReQuest Block: 32B */
407 struct mv_crqb {
408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
412 };
413
414 struct mv_crqb_iie {
415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
420 };
421
422 /* Command ResPonse Block: 8B */
423 struct mv_crpb {
424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
427 };
428
429 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430 struct mv_sg {
431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
435 };
436
437 struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
448 u32 pp_flags;
449 };
450
451 struct mv_port_signal {
452 u32 amps;
453 u32 pre;
454 };
455
456 struct mv_host_priv {
457 u32 hp_flags;
458 struct mv_port_signal signal[8];
459 const struct mv_hw_ops *ops;
460 int n_ports;
461 void __iomem *base;
462 void __iomem *main_irq_cause_addr;
463 void __iomem *main_irq_mask_addr;
464 u32 irq_cause_ofs;
465 u32 irq_mask_ofs;
466 u32 unmask_all_irqs;
467 /*
468 * These consistent DMA memory pools give us guaranteed
469 * alignment for hardware-accessed data structures,
470 * and less memory waste in accomplishing the alignment.
471 */
472 struct dma_pool *crqb_pool;
473 struct dma_pool *crpb_pool;
474 struct dma_pool *sg_tbl_pool;
475 };
476
477 struct mv_hw_ops {
478 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
479 unsigned int port);
480 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
481 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
482 void __iomem *mmio);
483 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
484 unsigned int n_hc);
485 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
486 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
487 };
488
489 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
490 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
491 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
492 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
493 static int mv_port_start(struct ata_port *ap);
494 static void mv_port_stop(struct ata_port *ap);
495 static int mv_qc_defer(struct ata_queued_cmd *qc);
496 static void mv_qc_prep(struct ata_queued_cmd *qc);
497 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
498 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
499 static int mv_hardreset(struct ata_link *link, unsigned int *class,
500 unsigned long deadline);
501 static void mv_eh_freeze(struct ata_port *ap);
502 static void mv_eh_thaw(struct ata_port *ap);
503 static void mv6_dev_config(struct ata_device *dev);
504
505 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
506 unsigned int port);
507 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
508 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
509 void __iomem *mmio);
510 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
511 unsigned int n_hc);
512 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
513 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
514
515 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
516 unsigned int port);
517 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
518 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
519 void __iomem *mmio);
520 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
521 unsigned int n_hc);
522 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
523 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
524 void __iomem *mmio);
525 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
526 void __iomem *mmio);
527 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
528 void __iomem *mmio, unsigned int n_hc);
529 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
530 void __iomem *mmio);
531 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
532 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
533 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
534 unsigned int port_no);
535 static int mv_stop_edma(struct ata_port *ap);
536 static int mv_stop_edma_engine(void __iomem *port_mmio);
537 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
538
539 static void mv_pmp_select(struct ata_port *ap, int pmp);
540 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
541 unsigned long deadline);
542 static int mv_softreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline);
544
545 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
546 * because we have to allow room for worst case splitting of
547 * PRDs for 64K boundaries in mv_fill_sg().
548 */
549 static struct scsi_host_template mv5_sht = {
550 ATA_BASE_SHT(DRV_NAME),
551 .sg_tablesize = MV_MAX_SG_CT / 2,
552 .dma_boundary = MV_DMA_BOUNDARY,
553 };
554
555 static struct scsi_host_template mv6_sht = {
556 ATA_NCQ_SHT(DRV_NAME),
557 .can_queue = MV_MAX_Q_DEPTH - 1,
558 .sg_tablesize = MV_MAX_SG_CT / 2,
559 .dma_boundary = MV_DMA_BOUNDARY,
560 };
561
562 static struct ata_port_operations mv5_ops = {
563 .inherits = &ata_sff_port_ops,
564
565 .qc_defer = mv_qc_defer,
566 .qc_prep = mv_qc_prep,
567 .qc_issue = mv_qc_issue,
568
569 .freeze = mv_eh_freeze,
570 .thaw = mv_eh_thaw,
571 .hardreset = mv_hardreset,
572 .error_handler = ata_std_error_handler, /* avoid SFF EH */
573 .post_internal_cmd = ATA_OP_NULL,
574
575 .scr_read = mv5_scr_read,
576 .scr_write = mv5_scr_write,
577
578 .port_start = mv_port_start,
579 .port_stop = mv_port_stop,
580 };
581
582 static struct ata_port_operations mv6_ops = {
583 .inherits = &mv5_ops,
584 .dev_config = mv6_dev_config,
585 .scr_read = mv_scr_read,
586 .scr_write = mv_scr_write,
587
588 .pmp_hardreset = mv_pmp_hardreset,
589 .pmp_softreset = mv_softreset,
590 .softreset = mv_softreset,
591 .error_handler = sata_pmp_error_handler,
592 };
593
594 static struct ata_port_operations mv_iie_ops = {
595 .inherits = &mv6_ops,
596 .dev_config = ATA_OP_NULL,
597 .qc_prep = mv_qc_prep_iie,
598 };
599
600 static const struct ata_port_info mv_port_info[] = {
601 { /* chip_504x */
602 .flags = MV_COMMON_FLAGS,
603 .pio_mask = 0x1f, /* pio0-4 */
604 .udma_mask = ATA_UDMA6,
605 .port_ops = &mv5_ops,
606 },
607 { /* chip_508x */
608 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &mv5_ops,
612 },
613 { /* chip_5080 */
614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
615 .pio_mask = 0x1f, /* pio0-4 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &mv5_ops,
618 },
619 { /* chip_604x */
620 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
621 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
622 ATA_FLAG_NCQ,
623 .pio_mask = 0x1f, /* pio0-4 */
624 .udma_mask = ATA_UDMA6,
625 .port_ops = &mv6_ops,
626 },
627 { /* chip_608x */
628 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
629 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
630 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
631 .pio_mask = 0x1f, /* pio0-4 */
632 .udma_mask = ATA_UDMA6,
633 .port_ops = &mv6_ops,
634 },
635 { /* chip_6042 */
636 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
637 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
638 ATA_FLAG_NCQ,
639 .pio_mask = 0x1f, /* pio0-4 */
640 .udma_mask = ATA_UDMA6,
641 .port_ops = &mv_iie_ops,
642 },
643 { /* chip_7042 */
644 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
645 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
646 ATA_FLAG_NCQ,
647 .pio_mask = 0x1f, /* pio0-4 */
648 .udma_mask = ATA_UDMA6,
649 .port_ops = &mv_iie_ops,
650 },
651 { /* chip_soc */
652 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
653 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
654 ATA_FLAG_NCQ | MV_FLAG_SOC,
655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
658 },
659 };
660
661 static const struct pci_device_id mv_pci_tbl[] = {
662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
669
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
675
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
677
678 /* Adaptec 1430SA */
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
680
681 /* Marvell 7042 support */
682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
683
684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
687
688 { } /* terminate list */
689 };
690
691 static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
698 };
699
700 static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
707 };
708
709 static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
716 };
717
718 /*
719 * Functions
720 */
721
722 static inline void writelfl(unsigned long data, void __iomem *addr)
723 {
724 writel(data, addr);
725 (void) readl(addr); /* flush to avoid PCI posted write */
726 }
727
728 static inline unsigned int mv_hc_from_port(unsigned int port)
729 {
730 return port >> MV_PORT_HC_SHIFT;
731 }
732
733 static inline unsigned int mv_hardport_from_port(unsigned int port)
734 {
735 return port & MV_PORT_MASK;
736 }
737
738 /*
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
742 *
743 * port is the sole input, in range 0..7.
744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
746 *
747 * Note that port and hardport may be the same variable in some cases.
748 */
749 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750 { \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
754 }
755
756 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
757 {
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
759 }
760
761 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
762 unsigned int port)
763 {
764 return mv_hc_base(base, mv_hc_from_port(port));
765 }
766
767 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
768 {
769 return mv_hc_base_from_port(base, port) +
770 MV_SATAHC_ARBTR_REG_SZ +
771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
772 }
773
774 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
775 {
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
778
779 return hc_mmio + ofs;
780 }
781
782 static inline void __iomem *mv_host_base(struct ata_host *host)
783 {
784 struct mv_host_priv *hpriv = host->private_data;
785 return hpriv->base;
786 }
787
788 static inline void __iomem *mv_ap_base(struct ata_port *ap)
789 {
790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
791 }
792
793 static inline int mv_get_hc_count(unsigned long port_flags)
794 {
795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
796 }
797
798 static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
801 {
802 u32 index;
803
804 /*
805 * initialize request queue
806 */
807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
809
810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
816 writelfl((pp->crqb_dma & 0xffffffff) | index,
817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
820
821 /*
822 * initialize response queue
823 */
824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
826
827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
831 writelfl((pp->crpb_dma & 0xffffffff) | index,
832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835
836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
838 }
839
840 /**
841 * mv_start_dma - Enable eDMA engine
842 * @base: port base address
843 * @pp: port private data
844 *
845 * Verify the local cache of the eDMA state is accurate with a
846 * WARN_ON.
847 *
848 * LOCKING:
849 * Inherited from caller.
850 */
851 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
852 struct mv_port_priv *pp, u8 protocol)
853 {
854 int want_ncq = (protocol == ATA_PROT_NCQ);
855
856 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
857 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
858 if (want_ncq != using_ncq)
859 mv_stop_edma(ap);
860 }
861 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
862 struct mv_host_priv *hpriv = ap->host->private_data;
863 int hardport = mv_hardport_from_port(ap->port_no);
864 void __iomem *hc_mmio = mv_hc_base_from_port(
865 mv_host_base(ap->host), hardport);
866 u32 hc_irq_cause, ipending;
867
868 /* clear EDMA event indicators, if any */
869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
870
871 /* clear EDMA interrupt indicator, if any */
872 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
873 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
874 if (hc_irq_cause & ipending) {
875 writelfl(hc_irq_cause & ~ipending,
876 hc_mmio + HC_IRQ_CAUSE_OFS);
877 }
878
879 mv_edma_cfg(ap, want_ncq);
880
881 /* clear FIS IRQ Cause */
882 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
883
884 mv_set_edma_ptrs(port_mmio, hpriv, pp);
885
886 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
887 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
888 }
889 }
890
891 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
892 {
893 void __iomem *port_mmio = mv_ap_base(ap);
894 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
895 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
896 int i;
897
898 /*
899 * Wait for the EDMA engine to finish transactions in progress.
900 */
901 for (i = 0; i < timeout; ++i) {
902 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
903 if ((edma_stat & empty_idle) == empty_idle)
904 break;
905 udelay(per_loop);
906 }
907 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
908 }
909
910 /**
911 * mv_stop_edma_engine - Disable eDMA engine
912 * @port_mmio: io base address
913 *
914 * LOCKING:
915 * Inherited from caller.
916 */
917 static int mv_stop_edma_engine(void __iomem *port_mmio)
918 {
919 int i;
920
921 /* Disable eDMA. The disable bit auto clears. */
922 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
923
924 /* Wait for the chip to confirm eDMA is off. */
925 for (i = 10000; i > 0; i--) {
926 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
927 if (!(reg & EDMA_EN))
928 return 0;
929 udelay(10);
930 }
931 return -EIO;
932 }
933
934 static int mv_stop_edma(struct ata_port *ap)
935 {
936 void __iomem *port_mmio = mv_ap_base(ap);
937 struct mv_port_priv *pp = ap->private_data;
938
939 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
940 return 0;
941 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
942 mv_wait_for_edma_empty_idle(ap);
943 if (mv_stop_edma_engine(port_mmio)) {
944 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
945 return -EIO;
946 }
947 return 0;
948 }
949
950 #ifdef ATA_DEBUG
951 static void mv_dump_mem(void __iomem *start, unsigned bytes)
952 {
953 int b, w;
954 for (b = 0; b < bytes; ) {
955 DPRINTK("%p: ", start + b);
956 for (w = 0; b < bytes && w < 4; w++) {
957 printk("%08x ", readl(start + b));
958 b += sizeof(u32);
959 }
960 printk("\n");
961 }
962 }
963 #endif
964
965 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
966 {
967 #ifdef ATA_DEBUG
968 int b, w;
969 u32 dw;
970 for (b = 0; b < bytes; ) {
971 DPRINTK("%02x: ", b);
972 for (w = 0; b < bytes && w < 4; w++) {
973 (void) pci_read_config_dword(pdev, b, &dw);
974 printk("%08x ", dw);
975 b += sizeof(u32);
976 }
977 printk("\n");
978 }
979 #endif
980 }
981 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
982 struct pci_dev *pdev)
983 {
984 #ifdef ATA_DEBUG
985 void __iomem *hc_base = mv_hc_base(mmio_base,
986 port >> MV_PORT_HC_SHIFT);
987 void __iomem *port_base;
988 int start_port, num_ports, p, start_hc, num_hcs, hc;
989
990 if (0 > port) {
991 start_hc = start_port = 0;
992 num_ports = 8; /* shld be benign for 4 port devs */
993 num_hcs = 2;
994 } else {
995 start_hc = port >> MV_PORT_HC_SHIFT;
996 start_port = port;
997 num_ports = num_hcs = 1;
998 }
999 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1000 num_ports > 1 ? num_ports - 1 : start_port);
1001
1002 if (NULL != pdev) {
1003 DPRINTK("PCI config space regs:\n");
1004 mv_dump_pci_cfg(pdev, 0x68);
1005 }
1006 DPRINTK("PCI regs:\n");
1007 mv_dump_mem(mmio_base+0xc00, 0x3c);
1008 mv_dump_mem(mmio_base+0xd00, 0x34);
1009 mv_dump_mem(mmio_base+0xf00, 0x4);
1010 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1011 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1012 hc_base = mv_hc_base(mmio_base, hc);
1013 DPRINTK("HC regs (HC %i):\n", hc);
1014 mv_dump_mem(hc_base, 0x1c);
1015 }
1016 for (p = start_port; p < start_port + num_ports; p++) {
1017 port_base = mv_port_base(mmio_base, p);
1018 DPRINTK("EDMA regs (port %i):\n", p);
1019 mv_dump_mem(port_base, 0x54);
1020 DPRINTK("SATA regs (port %i):\n", p);
1021 mv_dump_mem(port_base+0x300, 0x60);
1022 }
1023 #endif
1024 }
1025
1026 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1027 {
1028 unsigned int ofs;
1029
1030 switch (sc_reg_in) {
1031 case SCR_STATUS:
1032 case SCR_CONTROL:
1033 case SCR_ERROR:
1034 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1035 break;
1036 case SCR_ACTIVE:
1037 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1038 break;
1039 default:
1040 ofs = 0xffffffffU;
1041 break;
1042 }
1043 return ofs;
1044 }
1045
1046 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1047 {
1048 unsigned int ofs = mv_scr_offset(sc_reg_in);
1049
1050 if (ofs != 0xffffffffU) {
1051 *val = readl(mv_ap_base(ap) + ofs);
1052 return 0;
1053 } else
1054 return -EINVAL;
1055 }
1056
1057 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1058 {
1059 unsigned int ofs = mv_scr_offset(sc_reg_in);
1060
1061 if (ofs != 0xffffffffU) {
1062 writelfl(val, mv_ap_base(ap) + ofs);
1063 return 0;
1064 } else
1065 return -EINVAL;
1066 }
1067
1068 static void mv6_dev_config(struct ata_device *adev)
1069 {
1070 /*
1071 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1072 *
1073 * Gen-II does not support NCQ over a port multiplier
1074 * (no FIS-based switching).
1075 *
1076 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1077 * See mv_qc_prep() for more info.
1078 */
1079 if (adev->flags & ATA_DFLAG_NCQ) {
1080 if (sata_pmp_attached(adev->link->ap)) {
1081 adev->flags &= ~ATA_DFLAG_NCQ;
1082 ata_dev_printk(adev, KERN_INFO,
1083 "NCQ disabled for command-based switching\n");
1084 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1085 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1086 ata_dev_printk(adev, KERN_INFO,
1087 "max_sectors limited to %u for NCQ\n",
1088 adev->max_sectors);
1089 }
1090 }
1091 }
1092
1093 static int mv_qc_defer(struct ata_queued_cmd *qc)
1094 {
1095 struct ata_link *link = qc->dev->link;
1096 struct ata_port *ap = link->ap;
1097 struct mv_port_priv *pp = ap->private_data;
1098
1099 /*
1100 * If the port is completely idle, then allow the new qc.
1101 */
1102 if (ap->nr_active_links == 0)
1103 return 0;
1104
1105 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1106 /*
1107 * The port is operating in host queuing mode (EDMA).
1108 * It can accomodate a new qc if the qc protocol
1109 * is compatible with the current host queue mode.
1110 */
1111 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1112 /*
1113 * The host queue (EDMA) is in NCQ mode.
1114 * If the new qc is also an NCQ command,
1115 * then allow the new qc.
1116 */
1117 if (qc->tf.protocol == ATA_PROT_NCQ)
1118 return 0;
1119 } else {
1120 /*
1121 * The host queue (EDMA) is in non-NCQ, DMA mode.
1122 * If the new qc is also a non-NCQ, DMA command,
1123 * then allow the new qc.
1124 */
1125 if (qc->tf.protocol == ATA_PROT_DMA)
1126 return 0;
1127 }
1128 }
1129 return ATA_DEFER_PORT;
1130 }
1131
1132 static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1133 {
1134 u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
1135 /*
1136 * Various bit settings required for operation
1137 * in FIS-based switching (fbs) mode on GenIIe:
1138 */
1139 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1140 old_ltmode = readl(port_mmio + LTMODE_OFS);
1141 if (enable_fbs) {
1142 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1143 new_ltmode = old_ltmode | LTMODE_BIT8;
1144 } else { /* disable fbs */
1145 new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
1146 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1147 }
1148 if (new_fiscfg != old_fiscfg)
1149 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1150 if (new_ltmode != old_ltmode)
1151 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1152 }
1153
1154 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1155 {
1156 struct mv_host_priv *hpriv = ap->host->private_data;
1157 u32 old, new;
1158
1159 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1160 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1161 if (want_ncq)
1162 new = old | (1 << 22);
1163 else
1164 new = old & ~(1 << 22);
1165 if (new != old)
1166 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1167 }
1168
1169 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1170 {
1171 u32 cfg;
1172 struct mv_port_priv *pp = ap->private_data;
1173 struct mv_host_priv *hpriv = ap->host->private_data;
1174 void __iomem *port_mmio = mv_ap_base(ap);
1175
1176 /* set up non-NCQ EDMA configuration */
1177 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1178
1179 if (IS_GEN_I(hpriv))
1180 cfg |= (1 << 8); /* enab config burst size mask */
1181
1182 else if (IS_GEN_II(hpriv)) {
1183 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1184 mv_60x1_errata_sata25(ap, want_ncq);
1185
1186 } else if (IS_GEN_IIE(hpriv)) {
1187 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1188 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1189 if (HAS_PCI(ap->host))
1190 cfg |= (1 << 18); /* enab early completion */
1191 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1192 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1193
1194 if (want_ncq && sata_pmp_attached(ap)) {
1195 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1196 mv_config_fbs(port_mmio, 1);
1197 } else {
1198 mv_config_fbs(port_mmio, 0);
1199 }
1200 }
1201
1202 if (want_ncq) {
1203 cfg |= EDMA_CFG_NCQ;
1204 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1205 } else
1206 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1207
1208 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1209 }
1210
1211 static void mv_port_free_dma_mem(struct ata_port *ap)
1212 {
1213 struct mv_host_priv *hpriv = ap->host->private_data;
1214 struct mv_port_priv *pp = ap->private_data;
1215 int tag;
1216
1217 if (pp->crqb) {
1218 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1219 pp->crqb = NULL;
1220 }
1221 if (pp->crpb) {
1222 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1223 pp->crpb = NULL;
1224 }
1225 /*
1226 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1227 * For later hardware, we have one unique sg_tbl per NCQ tag.
1228 */
1229 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1230 if (pp->sg_tbl[tag]) {
1231 if (tag == 0 || !IS_GEN_I(hpriv))
1232 dma_pool_free(hpriv->sg_tbl_pool,
1233 pp->sg_tbl[tag],
1234 pp->sg_tbl_dma[tag]);
1235 pp->sg_tbl[tag] = NULL;
1236 }
1237 }
1238 }
1239
1240 /**
1241 * mv_port_start - Port specific init/start routine.
1242 * @ap: ATA channel to manipulate
1243 *
1244 * Allocate and point to DMA memory, init port private memory,
1245 * zero indices.
1246 *
1247 * LOCKING:
1248 * Inherited from caller.
1249 */
1250 static int mv_port_start(struct ata_port *ap)
1251 {
1252 struct device *dev = ap->host->dev;
1253 struct mv_host_priv *hpriv = ap->host->private_data;
1254 struct mv_port_priv *pp;
1255 int tag;
1256
1257 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1258 if (!pp)
1259 return -ENOMEM;
1260 ap->private_data = pp;
1261
1262 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1263 if (!pp->crqb)
1264 return -ENOMEM;
1265 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1266
1267 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1268 if (!pp->crpb)
1269 goto out_port_free_dma_mem;
1270 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1271
1272 /*
1273 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1274 * For later hardware, we need one unique sg_tbl per NCQ tag.
1275 */
1276 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1277 if (tag == 0 || !IS_GEN_I(hpriv)) {
1278 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1279 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1280 if (!pp->sg_tbl[tag])
1281 goto out_port_free_dma_mem;
1282 } else {
1283 pp->sg_tbl[tag] = pp->sg_tbl[0];
1284 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1285 }
1286 }
1287 return 0;
1288
1289 out_port_free_dma_mem:
1290 mv_port_free_dma_mem(ap);
1291 return -ENOMEM;
1292 }
1293
1294 /**
1295 * mv_port_stop - Port specific cleanup/stop routine.
1296 * @ap: ATA channel to manipulate
1297 *
1298 * Stop DMA, cleanup port memory.
1299 *
1300 * LOCKING:
1301 * This routine uses the host lock to protect the DMA stop.
1302 */
1303 static void mv_port_stop(struct ata_port *ap)
1304 {
1305 mv_stop_edma(ap);
1306 mv_port_free_dma_mem(ap);
1307 }
1308
1309 /**
1310 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1311 * @qc: queued command whose SG list to source from
1312 *
1313 * Populate the SG list and mark the last entry.
1314 *
1315 * LOCKING:
1316 * Inherited from caller.
1317 */
1318 static void mv_fill_sg(struct ata_queued_cmd *qc)
1319 {
1320 struct mv_port_priv *pp = qc->ap->private_data;
1321 struct scatterlist *sg;
1322 struct mv_sg *mv_sg, *last_sg = NULL;
1323 unsigned int si;
1324
1325 mv_sg = pp->sg_tbl[qc->tag];
1326 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1327 dma_addr_t addr = sg_dma_address(sg);
1328 u32 sg_len = sg_dma_len(sg);
1329
1330 while (sg_len) {
1331 u32 offset = addr & 0xffff;
1332 u32 len = sg_len;
1333
1334 if ((offset + sg_len > 0x10000))
1335 len = 0x10000 - offset;
1336
1337 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1338 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1339 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1340
1341 sg_len -= len;
1342 addr += len;
1343
1344 last_sg = mv_sg;
1345 mv_sg++;
1346 }
1347 }
1348
1349 if (likely(last_sg))
1350 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1351 }
1352
1353 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1354 {
1355 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1356 (last ? CRQB_CMD_LAST : 0);
1357 *cmdw = cpu_to_le16(tmp);
1358 }
1359
1360 /**
1361 * mv_qc_prep - Host specific command preparation.
1362 * @qc: queued command to prepare
1363 *
1364 * This routine simply redirects to the general purpose routine
1365 * if command is not DMA. Else, it handles prep of the CRQB
1366 * (command request block), does some sanity checking, and calls
1367 * the SG load routine.
1368 *
1369 * LOCKING:
1370 * Inherited from caller.
1371 */
1372 static void mv_qc_prep(struct ata_queued_cmd *qc)
1373 {
1374 struct ata_port *ap = qc->ap;
1375 struct mv_port_priv *pp = ap->private_data;
1376 __le16 *cw;
1377 struct ata_taskfile *tf;
1378 u16 flags = 0;
1379 unsigned in_index;
1380
1381 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1382 (qc->tf.protocol != ATA_PROT_NCQ))
1383 return;
1384
1385 /* Fill in command request block
1386 */
1387 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1388 flags |= CRQB_FLAG_READ;
1389 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1390 flags |= qc->tag << CRQB_TAG_SHIFT;
1391 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1392
1393 /* get current queue index from software */
1394 in_index = pp->req_idx;
1395
1396 pp->crqb[in_index].sg_addr =
1397 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1398 pp->crqb[in_index].sg_addr_hi =
1399 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1400 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1401
1402 cw = &pp->crqb[in_index].ata_cmd[0];
1403 tf = &qc->tf;
1404
1405 /* Sadly, the CRQB cannot accomodate all registers--there are
1406 * only 11 bytes...so we must pick and choose required
1407 * registers based on the command. So, we drop feature and
1408 * hob_feature for [RW] DMA commands, but they are needed for
1409 * NCQ. NCQ will drop hob_nsect.
1410 */
1411 switch (tf->command) {
1412 case ATA_CMD_READ:
1413 case ATA_CMD_READ_EXT:
1414 case ATA_CMD_WRITE:
1415 case ATA_CMD_WRITE_EXT:
1416 case ATA_CMD_WRITE_FUA_EXT:
1417 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1418 break;
1419 case ATA_CMD_FPDMA_READ:
1420 case ATA_CMD_FPDMA_WRITE:
1421 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1422 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1423 break;
1424 default:
1425 /* The only other commands EDMA supports in non-queued and
1426 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1427 * of which are defined/used by Linux. If we get here, this
1428 * driver needs work.
1429 *
1430 * FIXME: modify libata to give qc_prep a return value and
1431 * return error here.
1432 */
1433 BUG_ON(tf->command);
1434 break;
1435 }
1436 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1437 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1438 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1439 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1440 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1441 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1442 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1443 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1444 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1445
1446 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1447 return;
1448 mv_fill_sg(qc);
1449 }
1450
1451 /**
1452 * mv_qc_prep_iie - Host specific command preparation.
1453 * @qc: queued command to prepare
1454 *
1455 * This routine simply redirects to the general purpose routine
1456 * if command is not DMA. Else, it handles prep of the CRQB
1457 * (command request block), does some sanity checking, and calls
1458 * the SG load routine.
1459 *
1460 * LOCKING:
1461 * Inherited from caller.
1462 */
1463 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1464 {
1465 struct ata_port *ap = qc->ap;
1466 struct mv_port_priv *pp = ap->private_data;
1467 struct mv_crqb_iie *crqb;
1468 struct ata_taskfile *tf;
1469 unsigned in_index;
1470 u32 flags = 0;
1471
1472 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1473 (qc->tf.protocol != ATA_PROT_NCQ))
1474 return;
1475
1476 /* Fill in Gen IIE command request block */
1477 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1478 flags |= CRQB_FLAG_READ;
1479
1480 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1481 flags |= qc->tag << CRQB_TAG_SHIFT;
1482 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1483 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1484
1485 /* get current queue index from software */
1486 in_index = pp->req_idx;
1487
1488 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1489 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1490 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1491 crqb->flags = cpu_to_le32(flags);
1492
1493 tf = &qc->tf;
1494 crqb->ata_cmd[0] = cpu_to_le32(
1495 (tf->command << 16) |
1496 (tf->feature << 24)
1497 );
1498 crqb->ata_cmd[1] = cpu_to_le32(
1499 (tf->lbal << 0) |
1500 (tf->lbam << 8) |
1501 (tf->lbah << 16) |
1502 (tf->device << 24)
1503 );
1504 crqb->ata_cmd[2] = cpu_to_le32(
1505 (tf->hob_lbal << 0) |
1506 (tf->hob_lbam << 8) |
1507 (tf->hob_lbah << 16) |
1508 (tf->hob_feature << 24)
1509 );
1510 crqb->ata_cmd[3] = cpu_to_le32(
1511 (tf->nsect << 0) |
1512 (tf->hob_nsect << 8)
1513 );
1514
1515 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1516 return;
1517 mv_fill_sg(qc);
1518 }
1519
1520 /**
1521 * mv_qc_issue - Initiate a command to the host
1522 * @qc: queued command to start
1523 *
1524 * This routine simply redirects to the general purpose routine
1525 * if command is not DMA. Else, it sanity checks our local
1526 * caches of the request producer/consumer indices then enables
1527 * DMA and bumps the request producer index.
1528 *
1529 * LOCKING:
1530 * Inherited from caller.
1531 */
1532 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1533 {
1534 struct ata_port *ap = qc->ap;
1535 void __iomem *port_mmio = mv_ap_base(ap);
1536 struct mv_port_priv *pp = ap->private_data;
1537 u32 in_index;
1538
1539 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1540 (qc->tf.protocol != ATA_PROT_NCQ)) {
1541 /*
1542 * We're about to send a non-EDMA capable command to the
1543 * port. Turn off EDMA so there won't be problems accessing
1544 * shadow block, etc registers.
1545 */
1546 mv_stop_edma(ap);
1547 mv_pmp_select(ap, qc->dev->link->pmp);
1548 return ata_sff_qc_issue(qc);
1549 }
1550
1551 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1552
1553 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1554 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1555
1556 /* and write the request in pointer to kick the EDMA to life */
1557 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1558 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1559
1560 return 0;
1561 }
1562
1563 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1564 {
1565 struct mv_port_priv *pp = ap->private_data;
1566 struct ata_queued_cmd *qc;
1567
1568 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1569 return NULL;
1570 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1571 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1572 qc = NULL;
1573 return qc;
1574 }
1575
1576 static void mv_unexpected_intr(struct ata_port *ap)
1577 {
1578 struct mv_port_priv *pp = ap->private_data;
1579 struct ata_eh_info *ehi = &ap->link.eh_info;
1580 char *when = "";
1581
1582 /*
1583 * We got a device interrupt from something that
1584 * was supposed to be using EDMA or polling.
1585 */
1586 ata_ehi_clear_desc(ehi);
1587 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1588 when = " while EDMA enabled";
1589 } else {
1590 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1591 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1592 when = " while polling";
1593 }
1594 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1595 ehi->err_mask |= AC_ERR_OTHER;
1596 ehi->action |= ATA_EH_RESET;
1597 ata_port_freeze(ap);
1598 }
1599
1600 /**
1601 * mv_err_intr - Handle error interrupts on the port
1602 * @ap: ATA channel to manipulate
1603 * @qc: affected command (non-NCQ), or NULL
1604 *
1605 * Most cases require a full reset of the chip's state machine,
1606 * which also performs a COMRESET.
1607 * Also, if the port disabled DMA, update our cached copy to match.
1608 *
1609 * LOCKING:
1610 * Inherited from caller.
1611 */
1612 static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1613 {
1614 void __iomem *port_mmio = mv_ap_base(ap);
1615 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1616 struct mv_port_priv *pp = ap->private_data;
1617 struct mv_host_priv *hpriv = ap->host->private_data;
1618 unsigned int action = 0, err_mask = 0;
1619 struct ata_eh_info *ehi = &ap->link.eh_info;
1620
1621 ata_ehi_clear_desc(ehi);
1622
1623 /*
1624 * Read and clear the err_cause bits. This won't actually
1625 * clear for some errors (eg. SError), but we will be doing
1626 * a hard reset in those cases regardless, which *will* clear it.
1627 */
1628 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1629 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1630
1631 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
1632
1633 /*
1634 * All generations share these EDMA error cause bits:
1635 */
1636 if (edma_err_cause & EDMA_ERR_DEV)
1637 err_mask |= AC_ERR_DEV;
1638 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1639 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1640 EDMA_ERR_INTRL_PAR)) {
1641 err_mask |= AC_ERR_ATA_BUS;
1642 action |= ATA_EH_RESET;
1643 ata_ehi_push_desc(ehi, "parity error");
1644 }
1645 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1646 ata_ehi_hotplugged(ehi);
1647 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1648 "dev disconnect" : "dev connect");
1649 action |= ATA_EH_RESET;
1650 }
1651
1652 /*
1653 * Gen-I has a different SELF_DIS bit,
1654 * different FREEZE bits, and no SERR bit:
1655 */
1656 if (IS_GEN_I(hpriv)) {
1657 eh_freeze_mask = EDMA_EH_FREEZE_5;
1658 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1659 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1660 ata_ehi_push_desc(ehi, "EDMA self-disable");
1661 }
1662 } else {
1663 eh_freeze_mask = EDMA_EH_FREEZE;
1664 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1665 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1666 ata_ehi_push_desc(ehi, "EDMA self-disable");
1667 }
1668 if (edma_err_cause & EDMA_ERR_SERR) {
1669 /*
1670 * Ensure that we read our own SCR, not a pmp link SCR:
1671 */
1672 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1673 /*
1674 * Don't clear SError here; leave it for libata-eh:
1675 */
1676 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1677 err_mask |= AC_ERR_ATA_BUS;
1678 action |= ATA_EH_RESET;
1679 }
1680 }
1681
1682 if (!err_mask) {
1683 err_mask = AC_ERR_OTHER;
1684 action |= ATA_EH_RESET;
1685 }
1686
1687 ehi->serror |= serr;
1688 ehi->action |= action;
1689
1690 if (qc)
1691 qc->err_mask |= err_mask;
1692 else
1693 ehi->err_mask |= err_mask;
1694
1695 if (edma_err_cause & eh_freeze_mask)
1696 ata_port_freeze(ap);
1697 else
1698 ata_port_abort(ap);
1699 }
1700
1701 static void mv_process_crpb_response(struct ata_port *ap,
1702 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1703 {
1704 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1705
1706 if (qc) {
1707 u8 ata_status;
1708 u16 edma_status = le16_to_cpu(response->flags);
1709 /*
1710 * edma_status from a response queue entry:
1711 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1712 * MSB is saved ATA status from command completion.
1713 */
1714 if (!ncq_enabled) {
1715 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1716 if (err_cause) {
1717 /*
1718 * Error will be seen/handled by mv_err_intr().
1719 * So do nothing at all here.
1720 */
1721 return;
1722 }
1723 }
1724 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1725 qc->err_mask |= ac_err_mask(ata_status);
1726 ata_qc_complete(qc);
1727 } else {
1728 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1729 __func__, tag);
1730 }
1731 }
1732
1733 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1734 {
1735 void __iomem *port_mmio = mv_ap_base(ap);
1736 struct mv_host_priv *hpriv = ap->host->private_data;
1737 u32 in_index;
1738 bool work_done = false;
1739 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1740
1741 /* Get the hardware queue position index */
1742 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1743 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1744
1745 /* Process new responses from since the last time we looked */
1746 while (in_index != pp->resp_idx) {
1747 unsigned int tag;
1748 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1749
1750 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1751
1752 if (IS_GEN_I(hpriv)) {
1753 /* 50xx: no NCQ, only one command active at a time */
1754 tag = ap->link.active_tag;
1755 } else {
1756 /* Gen II/IIE: get command tag from CRPB entry */
1757 tag = le16_to_cpu(response->id) & 0x1f;
1758 }
1759 mv_process_crpb_response(ap, response, tag, ncq_enabled);
1760 work_done = true;
1761 }
1762
1763 /* Update the software queue position index in hardware */
1764 if (work_done)
1765 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
1766 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
1767 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1768 }
1769
1770 /**
1771 * mv_host_intr - Handle all interrupts on the given host controller
1772 * @host: host specific structure
1773 * @main_irq_cause: Main interrupt cause register for the chip.
1774 *
1775 * LOCKING:
1776 * Inherited from caller.
1777 */
1778 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
1779 {
1780 struct mv_host_priv *hpriv = host->private_data;
1781 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1782 u32 hc_irq_cause = 0;
1783 unsigned int handled = 0, port;
1784
1785 for (port = 0; port < hpriv->n_ports; port++) {
1786 struct ata_port *ap = host->ports[port];
1787 struct mv_port_priv *pp;
1788 unsigned int shift, hardport, port_cause;
1789 /*
1790 * When we move to the second hc, flag our cached
1791 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1792 */
1793 if (port == MV_PORTS_PER_HC)
1794 hc_mmio = NULL;
1795 /*
1796 * Do nothing if port is not interrupting or is disabled:
1797 */
1798 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1799 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
1800 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
1801 continue;
1802 /*
1803 * Each hc within the host has its own hc_irq_cause register.
1804 * We defer reading it until we know we need it, right now:
1805 *
1806 * FIXME later: we don't really need to read this register
1807 * (some logic changes required below if we go that way),
1808 * because it doesn't tell us anything new. But we do need
1809 * to write to it, outside the top of this loop,
1810 * to reset the interrupt triggers for next time.
1811 */
1812 if (!hc_mmio) {
1813 hc_mmio = mv_hc_base_from_port(mmio, port);
1814 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1815 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1816 handled = 1;
1817 }
1818 /*
1819 * Process completed CRPB response(s) before other events.
1820 */
1821 pp = ap->private_data;
1822 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1823 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
1824 mv_process_crpb_entries(ap, pp);
1825 }
1826 /*
1827 * Handle chip-reported errors, or continue on to handle PIO.
1828 */
1829 if (unlikely(port_cause & ERR_IRQ)) {
1830 mv_err_intr(ap, mv_get_active_qc(ap));
1831 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1832 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1833 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1834 if (qc) {
1835 ata_sff_host_intr(ap, qc);
1836 continue;
1837 }
1838 }
1839 mv_unexpected_intr(ap);
1840 }
1841 }
1842 return handled;
1843 }
1844
1845 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
1846 {
1847 struct mv_host_priv *hpriv = host->private_data;
1848 struct ata_port *ap;
1849 struct ata_queued_cmd *qc;
1850 struct ata_eh_info *ehi;
1851 unsigned int i, err_mask, printed = 0;
1852 u32 err_cause;
1853
1854 err_cause = readl(mmio + hpriv->irq_cause_ofs);
1855
1856 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1857 err_cause);
1858
1859 DPRINTK("All regs @ PCI error\n");
1860 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1861
1862 writelfl(0, mmio + hpriv->irq_cause_ofs);
1863
1864 for (i = 0; i < host->n_ports; i++) {
1865 ap = host->ports[i];
1866 if (!ata_link_offline(&ap->link)) {
1867 ehi = &ap->link.eh_info;
1868 ata_ehi_clear_desc(ehi);
1869 if (!printed++)
1870 ata_ehi_push_desc(ehi,
1871 "PCI err cause 0x%08x", err_cause);
1872 err_mask = AC_ERR_HOST_BUS;
1873 ehi->action = ATA_EH_RESET;
1874 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1875 if (qc)
1876 qc->err_mask |= err_mask;
1877 else
1878 ehi->err_mask |= err_mask;
1879
1880 ata_port_freeze(ap);
1881 }
1882 }
1883 return 1; /* handled */
1884 }
1885
1886 /**
1887 * mv_interrupt - Main interrupt event handler
1888 * @irq: unused
1889 * @dev_instance: private data; in this case the host structure
1890 *
1891 * Read the read only register to determine if any host
1892 * controllers have pending interrupts. If so, call lower level
1893 * routine to handle. Also check for PCI errors which are only
1894 * reported here.
1895 *
1896 * LOCKING:
1897 * This routine holds the host lock while processing pending
1898 * interrupts.
1899 */
1900 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1901 {
1902 struct ata_host *host = dev_instance;
1903 struct mv_host_priv *hpriv = host->private_data;
1904 unsigned int handled = 0;
1905 u32 main_irq_cause, main_irq_mask;
1906
1907 spin_lock(&host->lock);
1908 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1909 main_irq_mask = readl(hpriv->main_irq_mask_addr);
1910 /*
1911 * Deal with cases where we either have nothing pending, or have read
1912 * a bogus register value which can indicate HW removal or PCI fault.
1913 */
1914 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1915 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
1916 handled = mv_pci_error(host, hpriv->base);
1917 else
1918 handled = mv_host_intr(host, main_irq_cause);
1919 }
1920 spin_unlock(&host->lock);
1921 return IRQ_RETVAL(handled);
1922 }
1923
1924 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1925 {
1926 unsigned int ofs;
1927
1928 switch (sc_reg_in) {
1929 case SCR_STATUS:
1930 case SCR_ERROR:
1931 case SCR_CONTROL:
1932 ofs = sc_reg_in * sizeof(u32);
1933 break;
1934 default:
1935 ofs = 0xffffffffU;
1936 break;
1937 }
1938 return ofs;
1939 }
1940
1941 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1942 {
1943 struct mv_host_priv *hpriv = ap->host->private_data;
1944 void __iomem *mmio = hpriv->base;
1945 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1946 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1947
1948 if (ofs != 0xffffffffU) {
1949 *val = readl(addr + ofs);
1950 return 0;
1951 } else
1952 return -EINVAL;
1953 }
1954
1955 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1956 {
1957 struct mv_host_priv *hpriv = ap->host->private_data;
1958 void __iomem *mmio = hpriv->base;
1959 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1960 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1961
1962 if (ofs != 0xffffffffU) {
1963 writelfl(val, addr + ofs);
1964 return 0;
1965 } else
1966 return -EINVAL;
1967 }
1968
1969 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
1970 {
1971 struct pci_dev *pdev = to_pci_dev(host->dev);
1972 int early_5080;
1973
1974 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
1975
1976 if (!early_5080) {
1977 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1978 tmp |= (1 << 0);
1979 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1980 }
1981
1982 mv_reset_pci_bus(host, mmio);
1983 }
1984
1985 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1986 {
1987 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
1988 }
1989
1990 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1991 void __iomem *mmio)
1992 {
1993 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1994 u32 tmp;
1995
1996 tmp = readl(phy_mmio + MV5_PHY_MODE);
1997
1998 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1999 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2000 }
2001
2002 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2003 {
2004 u32 tmp;
2005
2006 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2007
2008 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2009
2010 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2011 tmp |= ~(1 << 0);
2012 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2013 }
2014
2015 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2016 unsigned int port)
2017 {
2018 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2019 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2020 u32 tmp;
2021 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2022
2023 if (fix_apm_sq) {
2024 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2025 tmp |= (1 << 19);
2026 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2027
2028 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2029 tmp &= ~0x3;
2030 tmp |= 0x1;
2031 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2032 }
2033
2034 tmp = readl(phy_mmio + MV5_PHY_MODE);
2035 tmp &= ~mask;
2036 tmp |= hpriv->signal[port].pre;
2037 tmp |= hpriv->signal[port].amps;
2038 writel(tmp, phy_mmio + MV5_PHY_MODE);
2039 }
2040
2041
2042 #undef ZERO
2043 #define ZERO(reg) writel(0, port_mmio + (reg))
2044 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2045 unsigned int port)
2046 {
2047 void __iomem *port_mmio = mv_port_base(mmio, port);
2048
2049 mv_reset_channel(hpriv, mmio, port);
2050
2051 ZERO(0x028); /* command */
2052 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2053 ZERO(0x004); /* timer */
2054 ZERO(0x008); /* irq err cause */
2055 ZERO(0x00c); /* irq err mask */
2056 ZERO(0x010); /* rq bah */
2057 ZERO(0x014); /* rq inp */
2058 ZERO(0x018); /* rq outp */
2059 ZERO(0x01c); /* respq bah */
2060 ZERO(0x024); /* respq outp */
2061 ZERO(0x020); /* respq inp */
2062 ZERO(0x02c); /* test control */
2063 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2064 }
2065 #undef ZERO
2066
2067 #define ZERO(reg) writel(0, hc_mmio + (reg))
2068 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2069 unsigned int hc)
2070 {
2071 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2072 u32 tmp;
2073
2074 ZERO(0x00c);
2075 ZERO(0x010);
2076 ZERO(0x014);
2077 ZERO(0x018);
2078
2079 tmp = readl(hc_mmio + 0x20);
2080 tmp &= 0x1c1c1c1c;
2081 tmp |= 0x03030303;
2082 writel(tmp, hc_mmio + 0x20);
2083 }
2084 #undef ZERO
2085
2086 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2087 unsigned int n_hc)
2088 {
2089 unsigned int hc, port;
2090
2091 for (hc = 0; hc < n_hc; hc++) {
2092 for (port = 0; port < MV_PORTS_PER_HC; port++)
2093 mv5_reset_hc_port(hpriv, mmio,
2094 (hc * MV_PORTS_PER_HC) + port);
2095
2096 mv5_reset_one_hc(hpriv, mmio, hc);
2097 }
2098
2099 return 0;
2100 }
2101
2102 #undef ZERO
2103 #define ZERO(reg) writel(0, mmio + (reg))
2104 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2105 {
2106 struct mv_host_priv *hpriv = host->private_data;
2107 u32 tmp;
2108
2109 tmp = readl(mmio + MV_PCI_MODE_OFS);
2110 tmp &= 0xff00ffff;
2111 writel(tmp, mmio + MV_PCI_MODE_OFS);
2112
2113 ZERO(MV_PCI_DISC_TIMER);
2114 ZERO(MV_PCI_MSI_TRIGGER);
2115 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2116 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2117 ZERO(MV_PCI_SERR_MASK);
2118 ZERO(hpriv->irq_cause_ofs);
2119 ZERO(hpriv->irq_mask_ofs);
2120 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2121 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2122 ZERO(MV_PCI_ERR_ATTRIBUTE);
2123 ZERO(MV_PCI_ERR_COMMAND);
2124 }
2125 #undef ZERO
2126
2127 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2128 {
2129 u32 tmp;
2130
2131 mv5_reset_flash(hpriv, mmio);
2132
2133 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2134 tmp &= 0x3;
2135 tmp |= (1 << 5) | (1 << 6);
2136 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2137 }
2138
2139 /**
2140 * mv6_reset_hc - Perform the 6xxx global soft reset
2141 * @mmio: base address of the HBA
2142 *
2143 * This routine only applies to 6xxx parts.
2144 *
2145 * LOCKING:
2146 * Inherited from caller.
2147 */
2148 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2149 unsigned int n_hc)
2150 {
2151 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2152 int i, rc = 0;
2153 u32 t;
2154
2155 /* Following procedure defined in PCI "main command and status
2156 * register" table.
2157 */
2158 t = readl(reg);
2159 writel(t | STOP_PCI_MASTER, reg);
2160
2161 for (i = 0; i < 1000; i++) {
2162 udelay(1);
2163 t = readl(reg);
2164 if (PCI_MASTER_EMPTY & t)
2165 break;
2166 }
2167 if (!(PCI_MASTER_EMPTY & t)) {
2168 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2169 rc = 1;
2170 goto done;
2171 }
2172
2173 /* set reset */
2174 i = 5;
2175 do {
2176 writel(t | GLOB_SFT_RST, reg);
2177 t = readl(reg);
2178 udelay(1);
2179 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2180
2181 if (!(GLOB_SFT_RST & t)) {
2182 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2183 rc = 1;
2184 goto done;
2185 }
2186
2187 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2188 i = 5;
2189 do {
2190 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2191 t = readl(reg);
2192 udelay(1);
2193 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2194
2195 if (GLOB_SFT_RST & t) {
2196 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2197 rc = 1;
2198 }
2199 done:
2200 return rc;
2201 }
2202
2203 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2204 void __iomem *mmio)
2205 {
2206 void __iomem *port_mmio;
2207 u32 tmp;
2208
2209 tmp = readl(mmio + MV_RESET_CFG_OFS);
2210 if ((tmp & (1 << 0)) == 0) {
2211 hpriv->signal[idx].amps = 0x7 << 8;
2212 hpriv->signal[idx].pre = 0x1 << 5;
2213 return;
2214 }
2215
2216 port_mmio = mv_port_base(mmio, idx);
2217 tmp = readl(port_mmio + PHY_MODE2);
2218
2219 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2220 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2221 }
2222
2223 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2224 {
2225 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2226 }
2227
2228 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2229 unsigned int port)
2230 {
2231 void __iomem *port_mmio = mv_port_base(mmio, port);
2232
2233 u32 hp_flags = hpriv->hp_flags;
2234 int fix_phy_mode2 =
2235 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2236 int fix_phy_mode4 =
2237 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2238 u32 m2, tmp;
2239
2240 if (fix_phy_mode2) {
2241 m2 = readl(port_mmio + PHY_MODE2);
2242 m2 &= ~(1 << 16);
2243 m2 |= (1 << 31);
2244 writel(m2, port_mmio + PHY_MODE2);
2245
2246 udelay(200);
2247
2248 m2 = readl(port_mmio + PHY_MODE2);
2249 m2 &= ~((1 << 16) | (1 << 31));
2250 writel(m2, port_mmio + PHY_MODE2);
2251
2252 udelay(200);
2253 }
2254
2255 /* who knows what this magic does */
2256 tmp = readl(port_mmio + PHY_MODE3);
2257 tmp &= ~0x7F800000;
2258 tmp |= 0x2A800000;
2259 writel(tmp, port_mmio + PHY_MODE3);
2260
2261 if (fix_phy_mode4) {
2262 u32 m4;
2263
2264 m4 = readl(port_mmio + PHY_MODE4);
2265
2266 if (hp_flags & MV_HP_ERRATA_60X1B2)
2267 tmp = readl(port_mmio + PHY_MODE3);
2268
2269 /* workaround for errata FEr SATA#10 (part 1) */
2270 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2271
2272 writel(m4, port_mmio + PHY_MODE4);
2273
2274 if (hp_flags & MV_HP_ERRATA_60X1B2)
2275 writel(tmp, port_mmio + PHY_MODE3);
2276 }
2277
2278 /* Revert values of pre-emphasis and signal amps to the saved ones */
2279 m2 = readl(port_mmio + PHY_MODE2);
2280
2281 m2 &= ~MV_M2_PREAMP_MASK;
2282 m2 |= hpriv->signal[port].amps;
2283 m2 |= hpriv->signal[port].pre;
2284 m2 &= ~(1 << 16);
2285
2286 /* according to mvSata 3.6.1, some IIE values are fixed */
2287 if (IS_GEN_IIE(hpriv)) {
2288 m2 &= ~0xC30FF01F;
2289 m2 |= 0x0000900F;
2290 }
2291
2292 writel(m2, port_mmio + PHY_MODE2);
2293 }
2294
2295 /* TODO: use the generic LED interface to configure the SATA Presence */
2296 /* & Acitivy LEDs on the board */
2297 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2298 void __iomem *mmio)
2299 {
2300 return;
2301 }
2302
2303 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2304 void __iomem *mmio)
2305 {
2306 void __iomem *port_mmio;
2307 u32 tmp;
2308
2309 port_mmio = mv_port_base(mmio, idx);
2310 tmp = readl(port_mmio + PHY_MODE2);
2311
2312 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2313 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2314 }
2315
2316 #undef ZERO
2317 #define ZERO(reg) writel(0, port_mmio + (reg))
2318 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2319 void __iomem *mmio, unsigned int port)
2320 {
2321 void __iomem *port_mmio = mv_port_base(mmio, port);
2322
2323 mv_reset_channel(hpriv, mmio, port);
2324
2325 ZERO(0x028); /* command */
2326 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2327 ZERO(0x004); /* timer */
2328 ZERO(0x008); /* irq err cause */
2329 ZERO(0x00c); /* irq err mask */
2330 ZERO(0x010); /* rq bah */
2331 ZERO(0x014); /* rq inp */
2332 ZERO(0x018); /* rq outp */
2333 ZERO(0x01c); /* respq bah */
2334 ZERO(0x024); /* respq outp */
2335 ZERO(0x020); /* respq inp */
2336 ZERO(0x02c); /* test control */
2337 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2338 }
2339
2340 #undef ZERO
2341
2342 #define ZERO(reg) writel(0, hc_mmio + (reg))
2343 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2344 void __iomem *mmio)
2345 {
2346 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2347
2348 ZERO(0x00c);
2349 ZERO(0x010);
2350 ZERO(0x014);
2351
2352 }
2353
2354 #undef ZERO
2355
2356 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2357 void __iomem *mmio, unsigned int n_hc)
2358 {
2359 unsigned int port;
2360
2361 for (port = 0; port < hpriv->n_ports; port++)
2362 mv_soc_reset_hc_port(hpriv, mmio, port);
2363
2364 mv_soc_reset_one_hc(hpriv, mmio);
2365
2366 return 0;
2367 }
2368
2369 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2370 void __iomem *mmio)
2371 {
2372 return;
2373 }
2374
2375 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2376 {
2377 return;
2378 }
2379
2380 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2381 {
2382 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2383
2384 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2385 if (want_gen2i)
2386 ifcfg |= (1 << 7); /* enable gen2i speed */
2387 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2388 }
2389
2390 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2391 unsigned int port_no)
2392 {
2393 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2394
2395 /*
2396 * The datasheet warns against setting EDMA_RESET when EDMA is active
2397 * (but doesn't say what the problem might be). So we first try
2398 * to disable the EDMA engine before doing the EDMA_RESET operation.
2399 */
2400 mv_stop_edma_engine(port_mmio);
2401 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2402
2403 if (!IS_GEN_I(hpriv)) {
2404 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2405 mv_setup_ifcfg(port_mmio, 1);
2406 }
2407 /*
2408 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2409 * link, and physical layers. It resets all SATA interface registers
2410 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2411 */
2412 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2413 udelay(25); /* allow reset propagation */
2414 writelfl(0, port_mmio + EDMA_CMD_OFS);
2415
2416 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2417
2418 if (IS_GEN_I(hpriv))
2419 mdelay(1);
2420 }
2421
2422 static void mv_pmp_select(struct ata_port *ap, int pmp)
2423 {
2424 if (sata_pmp_supported(ap)) {
2425 void __iomem *port_mmio = mv_ap_base(ap);
2426 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2427 int old = reg & 0xf;
2428
2429 if (old != pmp) {
2430 reg = (reg & ~0xf) | pmp;
2431 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2432 }
2433 }
2434 }
2435
2436 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2437 unsigned long deadline)
2438 {
2439 mv_pmp_select(link->ap, sata_srst_pmp(link));
2440 return sata_std_hardreset(link, class, deadline);
2441 }
2442
2443 static int mv_softreset(struct ata_link *link, unsigned int *class,
2444 unsigned long deadline)
2445 {
2446 mv_pmp_select(link->ap, sata_srst_pmp(link));
2447 return ata_sff_softreset(link, class, deadline);
2448 }
2449
2450 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2451 unsigned long deadline)
2452 {
2453 struct ata_port *ap = link->ap;
2454 struct mv_host_priv *hpriv = ap->host->private_data;
2455 struct mv_port_priv *pp = ap->private_data;
2456 void __iomem *mmio = hpriv->base;
2457 int rc, attempts = 0, extra = 0;
2458 u32 sstatus;
2459 bool online;
2460
2461 mv_reset_channel(hpriv, mmio, ap->port_no);
2462 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2463
2464 /* Workaround for errata FEr SATA#10 (part 2) */
2465 do {
2466 const unsigned long *timing =
2467 sata_ehc_deb_timing(&link->eh_context);
2468
2469 rc = sata_link_hardreset(link, timing, deadline + extra,
2470 &online, NULL);
2471 if (rc)
2472 return rc;
2473 sata_scr_read(link, SCR_STATUS, &sstatus);
2474 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2475 /* Force 1.5gb/s link speed and try again */
2476 mv_setup_ifcfg(mv_ap_base(ap), 0);
2477 if (time_after(jiffies + HZ, deadline))
2478 extra = HZ; /* only extend it once, max */
2479 }
2480 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2481
2482 return rc;
2483 }
2484
2485 static void mv_eh_freeze(struct ata_port *ap)
2486 {
2487 struct mv_host_priv *hpriv = ap->host->private_data;
2488 unsigned int shift, hardport, port = ap->port_no;
2489 u32 main_irq_mask;
2490
2491 /* FIXME: handle coalescing completion events properly */
2492
2493 mv_stop_edma(ap);
2494 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2495
2496 /* disable assertion of portN err, done events */
2497 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2498 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2499 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2500 }
2501
2502 static void mv_eh_thaw(struct ata_port *ap)
2503 {
2504 struct mv_host_priv *hpriv = ap->host->private_data;
2505 unsigned int shift, hardport, port = ap->port_no;
2506 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2507 void __iomem *port_mmio = mv_ap_base(ap);
2508 u32 main_irq_mask, hc_irq_cause;
2509
2510 /* FIXME: handle coalescing completion events properly */
2511
2512 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2513
2514 /* clear EDMA errors on this port */
2515 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2516
2517 /* clear pending irq events */
2518 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2519 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2520 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2521
2522 /* enable assertion of portN err, done events */
2523 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2524 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2525 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2526 }
2527
2528 /**
2529 * mv_port_init - Perform some early initialization on a single port.
2530 * @port: libata data structure storing shadow register addresses
2531 * @port_mmio: base address of the port
2532 *
2533 * Initialize shadow register mmio addresses, clear outstanding
2534 * interrupts on the port, and unmask interrupts for the future
2535 * start of the port.
2536 *
2537 * LOCKING:
2538 * Inherited from caller.
2539 */
2540 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2541 {
2542 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2543 unsigned serr_ofs;
2544
2545 /* PIO related setup
2546 */
2547 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2548 port->error_addr =
2549 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2550 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2551 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2552 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2553 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2554 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2555 port->status_addr =
2556 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2557 /* special case: control/altstatus doesn't have ATA_REG_ address */
2558 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2559
2560 /* unused: */
2561 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2562
2563 /* Clear any currently outstanding port interrupt conditions */
2564 serr_ofs = mv_scr_offset(SCR_ERROR);
2565 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2566 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2567
2568 /* unmask all non-transient EDMA error interrupts */
2569 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2570
2571 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2572 readl(port_mmio + EDMA_CFG_OFS),
2573 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2574 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2575 }
2576
2577 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2578 {
2579 struct mv_host_priv *hpriv = host->private_data;
2580 void __iomem *mmio = hpriv->base;
2581 u32 reg;
2582
2583 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2584 return 0; /* not PCI-X capable */
2585 reg = readl(mmio + MV_PCI_MODE_OFS);
2586 if ((reg & MV_PCI_MODE_MASK) == 0)
2587 return 0; /* conventional PCI mode */
2588 return 1; /* chip is in PCI-X mode */
2589 }
2590
2591 static int mv_pci_cut_through_okay(struct ata_host *host)
2592 {
2593 struct mv_host_priv *hpriv = host->private_data;
2594 void __iomem *mmio = hpriv->base;
2595 u32 reg;
2596
2597 if (!mv_in_pcix_mode(host)) {
2598 reg = readl(mmio + PCI_COMMAND_OFS);
2599 if (reg & PCI_COMMAND_MRDTRIG)
2600 return 0; /* not okay */
2601 }
2602 return 1; /* okay */
2603 }
2604
2605 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2606 {
2607 struct pci_dev *pdev = to_pci_dev(host->dev);
2608 struct mv_host_priv *hpriv = host->private_data;
2609 u32 hp_flags = hpriv->hp_flags;
2610
2611 switch (board_idx) {
2612 case chip_5080:
2613 hpriv->ops = &mv5xxx_ops;
2614 hp_flags |= MV_HP_GEN_I;
2615
2616 switch (pdev->revision) {
2617 case 0x1:
2618 hp_flags |= MV_HP_ERRATA_50XXB0;
2619 break;
2620 case 0x3:
2621 hp_flags |= MV_HP_ERRATA_50XXB2;
2622 break;
2623 default:
2624 dev_printk(KERN_WARNING, &pdev->dev,
2625 "Applying 50XXB2 workarounds to unknown rev\n");
2626 hp_flags |= MV_HP_ERRATA_50XXB2;
2627 break;
2628 }
2629 break;
2630
2631 case chip_504x:
2632 case chip_508x:
2633 hpriv->ops = &mv5xxx_ops;
2634 hp_flags |= MV_HP_GEN_I;
2635
2636 switch (pdev->revision) {
2637 case 0x0:
2638 hp_flags |= MV_HP_ERRATA_50XXB0;
2639 break;
2640 case 0x3:
2641 hp_flags |= MV_HP_ERRATA_50XXB2;
2642 break;
2643 default:
2644 dev_printk(KERN_WARNING, &pdev->dev,
2645 "Applying B2 workarounds to unknown rev\n");
2646 hp_flags |= MV_HP_ERRATA_50XXB2;
2647 break;
2648 }
2649 break;
2650
2651 case chip_604x:
2652 case chip_608x:
2653 hpriv->ops = &mv6xxx_ops;
2654 hp_flags |= MV_HP_GEN_II;
2655
2656 switch (pdev->revision) {
2657 case 0x7:
2658 hp_flags |= MV_HP_ERRATA_60X1B2;
2659 break;
2660 case 0x9:
2661 hp_flags |= MV_HP_ERRATA_60X1C0;
2662 break;
2663 default:
2664 dev_printk(KERN_WARNING, &pdev->dev,
2665 "Applying B2 workarounds to unknown rev\n");
2666 hp_flags |= MV_HP_ERRATA_60X1B2;
2667 break;
2668 }
2669 break;
2670
2671 case chip_7042:
2672 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2673 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2674 (pdev->device == 0x2300 || pdev->device == 0x2310))
2675 {
2676 /*
2677 * Highpoint RocketRAID PCIe 23xx series cards:
2678 *
2679 * Unconfigured drives are treated as "Legacy"
2680 * by the BIOS, and it overwrites sector 8 with
2681 * a "Lgcy" metadata block prior to Linux boot.
2682 *
2683 * Configured drives (RAID or JBOD) leave sector 8
2684 * alone, but instead overwrite a high numbered
2685 * sector for the RAID metadata. This sector can
2686 * be determined exactly, by truncating the physical
2687 * drive capacity to a nice even GB value.
2688 *
2689 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2690 *
2691 * Warn the user, lest they think we're just buggy.
2692 */
2693 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2694 " BIOS CORRUPTS DATA on all attached drives,"
2695 " regardless of if/how they are configured."
2696 " BEWARE!\n");
2697 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2698 " use sectors 8-9 on \"Legacy\" drives,"
2699 " and avoid the final two gigabytes on"
2700 " all RocketRAID BIOS initialized drives.\n");
2701 }
2702 /* drop through */
2703 case chip_6042:
2704 hpriv->ops = &mv6xxx_ops;
2705 hp_flags |= MV_HP_GEN_IIE;
2706 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2707 hp_flags |= MV_HP_CUT_THROUGH;
2708
2709 switch (pdev->revision) {
2710 case 0x0:
2711 hp_flags |= MV_HP_ERRATA_XX42A0;
2712 break;
2713 case 0x1:
2714 hp_flags |= MV_HP_ERRATA_60X1C0;
2715 break;
2716 default:
2717 dev_printk(KERN_WARNING, &pdev->dev,
2718 "Applying 60X1C0 workarounds to unknown rev\n");
2719 hp_flags |= MV_HP_ERRATA_60X1C0;
2720 break;
2721 }
2722 break;
2723 case chip_soc:
2724 hpriv->ops = &mv_soc_ops;
2725 hp_flags |= MV_HP_ERRATA_60X1C0;
2726 break;
2727
2728 default:
2729 dev_printk(KERN_ERR, host->dev,
2730 "BUG: invalid board index %u\n", board_idx);
2731 return 1;
2732 }
2733
2734 hpriv->hp_flags = hp_flags;
2735 if (hp_flags & MV_HP_PCIE) {
2736 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2737 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2738 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2739 } else {
2740 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2741 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2742 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2743 }
2744
2745 return 0;
2746 }
2747
2748 /**
2749 * mv_init_host - Perform some early initialization of the host.
2750 * @host: ATA host to initialize
2751 * @board_idx: controller index
2752 *
2753 * If possible, do an early global reset of the host. Then do
2754 * our port init and clear/unmask all/relevant host interrupts.
2755 *
2756 * LOCKING:
2757 * Inherited from caller.
2758 */
2759 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2760 {
2761 int rc = 0, n_hc, port, hc;
2762 struct mv_host_priv *hpriv = host->private_data;
2763 void __iomem *mmio = hpriv->base;
2764
2765 rc = mv_chip_id(host, board_idx);
2766 if (rc)
2767 goto done;
2768
2769 if (HAS_PCI(host)) {
2770 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2771 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
2772 } else {
2773 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2774 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
2775 }
2776
2777 /* global interrupt mask: 0 == mask everything */
2778 writel(0, hpriv->main_irq_mask_addr);
2779
2780 n_hc = mv_get_hc_count(host->ports[0]->flags);
2781
2782 for (port = 0; port < host->n_ports; port++)
2783 hpriv->ops->read_preamp(hpriv, port, mmio);
2784
2785 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2786 if (rc)
2787 goto done;
2788
2789 hpriv->ops->reset_flash(hpriv, mmio);
2790 hpriv->ops->reset_bus(host, mmio);
2791 hpriv->ops->enable_leds(hpriv, mmio);
2792
2793 for (port = 0; port < host->n_ports; port++) {
2794 struct ata_port *ap = host->ports[port];
2795 void __iomem *port_mmio = mv_port_base(mmio, port);
2796
2797 mv_port_init(&ap->ioaddr, port_mmio);
2798
2799 #ifdef CONFIG_PCI
2800 if (HAS_PCI(host)) {
2801 unsigned int offset = port_mmio - mmio;
2802 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2803 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2804 }
2805 #endif
2806 }
2807
2808 for (hc = 0; hc < n_hc; hc++) {
2809 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2810
2811 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2812 "(before clear)=0x%08x\n", hc,
2813 readl(hc_mmio + HC_CFG_OFS),
2814 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2815
2816 /* Clear any currently outstanding hc interrupt conditions */
2817 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2818 }
2819
2820 if (HAS_PCI(host)) {
2821 /* Clear any currently outstanding host interrupt conditions */
2822 writelfl(0, mmio + hpriv->irq_cause_ofs);
2823
2824 /* and unmask interrupt generation for host regs */
2825 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2826 if (IS_GEN_I(hpriv))
2827 writelfl(~HC_MAIN_MASKED_IRQS_5,
2828 hpriv->main_irq_mask_addr);
2829 else
2830 writelfl(~HC_MAIN_MASKED_IRQS,
2831 hpriv->main_irq_mask_addr);
2832
2833 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2834 "PCI int cause/mask=0x%08x/0x%08x\n",
2835 readl(hpriv->main_irq_cause_addr),
2836 readl(hpriv->main_irq_mask_addr),
2837 readl(mmio + hpriv->irq_cause_ofs),
2838 readl(mmio + hpriv->irq_mask_ofs));
2839 } else {
2840 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
2841 hpriv->main_irq_mask_addr);
2842 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
2843 readl(hpriv->main_irq_cause_addr),
2844 readl(hpriv->main_irq_mask_addr));
2845 }
2846 done:
2847 return rc;
2848 }
2849
2850 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2851 {
2852 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2853 MV_CRQB_Q_SZ, 0);
2854 if (!hpriv->crqb_pool)
2855 return -ENOMEM;
2856
2857 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2858 MV_CRPB_Q_SZ, 0);
2859 if (!hpriv->crpb_pool)
2860 return -ENOMEM;
2861
2862 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2863 MV_SG_TBL_SZ, 0);
2864 if (!hpriv->sg_tbl_pool)
2865 return -ENOMEM;
2866
2867 return 0;
2868 }
2869
2870 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2871 struct mbus_dram_target_info *dram)
2872 {
2873 int i;
2874
2875 for (i = 0; i < 4; i++) {
2876 writel(0, hpriv->base + WINDOW_CTRL(i));
2877 writel(0, hpriv->base + WINDOW_BASE(i));
2878 }
2879
2880 for (i = 0; i < dram->num_cs; i++) {
2881 struct mbus_dram_window *cs = dram->cs + i;
2882
2883 writel(((cs->size - 1) & 0xffff0000) |
2884 (cs->mbus_attr << 8) |
2885 (dram->mbus_dram_target_id << 4) | 1,
2886 hpriv->base + WINDOW_CTRL(i));
2887 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2888 }
2889 }
2890
2891 /**
2892 * mv_platform_probe - handle a positive probe of an soc Marvell
2893 * host
2894 * @pdev: platform device found
2895 *
2896 * LOCKING:
2897 * Inherited from caller.
2898 */
2899 static int mv_platform_probe(struct platform_device *pdev)
2900 {
2901 static int printed_version;
2902 const struct mv_sata_platform_data *mv_platform_data;
2903 const struct ata_port_info *ppi[] =
2904 { &mv_port_info[chip_soc], NULL };
2905 struct ata_host *host;
2906 struct mv_host_priv *hpriv;
2907 struct resource *res;
2908 int n_ports, rc;
2909
2910 if (!printed_version++)
2911 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2912
2913 /*
2914 * Simple resource validation ..
2915 */
2916 if (unlikely(pdev->num_resources != 2)) {
2917 dev_err(&pdev->dev, "invalid number of resources\n");
2918 return -EINVAL;
2919 }
2920
2921 /*
2922 * Get the register base first
2923 */
2924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2925 if (res == NULL)
2926 return -EINVAL;
2927
2928 /* allocate host */
2929 mv_platform_data = pdev->dev.platform_data;
2930 n_ports = mv_platform_data->n_ports;
2931
2932 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2933 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2934
2935 if (!host || !hpriv)
2936 return -ENOMEM;
2937 host->private_data = hpriv;
2938 hpriv->n_ports = n_ports;
2939
2940 host->iomap = NULL;
2941 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2942 res->end - res->start + 1);
2943 hpriv->base -= MV_SATAHC0_REG_BASE;
2944
2945 /*
2946 * (Re-)program MBUS remapping windows if we are asked to.
2947 */
2948 if (mv_platform_data->dram != NULL)
2949 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2950
2951 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2952 if (rc)
2953 return rc;
2954
2955 /* initialize adapter */
2956 rc = mv_init_host(host, chip_soc);
2957 if (rc)
2958 return rc;
2959
2960 dev_printk(KERN_INFO, &pdev->dev,
2961 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2962 host->n_ports);
2963
2964 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2965 IRQF_SHARED, &mv6_sht);
2966 }
2967
2968 /*
2969 *
2970 * mv_platform_remove - unplug a platform interface
2971 * @pdev: platform device
2972 *
2973 * A platform bus SATA device has been unplugged. Perform the needed
2974 * cleanup. Also called on module unload for any active devices.
2975 */
2976 static int __devexit mv_platform_remove(struct platform_device *pdev)
2977 {
2978 struct device *dev = &pdev->dev;
2979 struct ata_host *host = dev_get_drvdata(dev);
2980
2981 ata_host_detach(host);
2982 return 0;
2983 }
2984
2985 static struct platform_driver mv_platform_driver = {
2986 .probe = mv_platform_probe,
2987 .remove = __devexit_p(mv_platform_remove),
2988 .driver = {
2989 .name = DRV_NAME,
2990 .owner = THIS_MODULE,
2991 },
2992 };
2993
2994
2995 #ifdef CONFIG_PCI
2996 static int mv_pci_init_one(struct pci_dev *pdev,
2997 const struct pci_device_id *ent);
2998
2999
3000 static struct pci_driver mv_pci_driver = {
3001 .name = DRV_NAME,
3002 .id_table = mv_pci_tbl,
3003 .probe = mv_pci_init_one,
3004 .remove = ata_pci_remove_one,
3005 };
3006
3007 /*
3008 * module options
3009 */
3010 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3011
3012
3013 /* move to PCI layer or libata core? */
3014 static int pci_go_64(struct pci_dev *pdev)
3015 {
3016 int rc;
3017
3018 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3019 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3020 if (rc) {
3021 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3022 if (rc) {
3023 dev_printk(KERN_ERR, &pdev->dev,
3024 "64-bit DMA enable failed\n");
3025 return rc;
3026 }
3027 }
3028 } else {
3029 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3030 if (rc) {
3031 dev_printk(KERN_ERR, &pdev->dev,
3032 "32-bit DMA enable failed\n");
3033 return rc;
3034 }
3035 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3036 if (rc) {
3037 dev_printk(KERN_ERR, &pdev->dev,
3038 "32-bit consistent DMA enable failed\n");
3039 return rc;
3040 }
3041 }
3042
3043 return rc;
3044 }
3045
3046 /**
3047 * mv_print_info - Dump key info to kernel log for perusal.
3048 * @host: ATA host to print info about
3049 *
3050 * FIXME: complete this.
3051 *
3052 * LOCKING:
3053 * Inherited from caller.
3054 */
3055 static void mv_print_info(struct ata_host *host)
3056 {
3057 struct pci_dev *pdev = to_pci_dev(host->dev);
3058 struct mv_host_priv *hpriv = host->private_data;
3059 u8 scc;
3060 const char *scc_s, *gen;
3061
3062 /* Use this to determine the HW stepping of the chip so we know
3063 * what errata to workaround
3064 */
3065 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3066 if (scc == 0)
3067 scc_s = "SCSI";
3068 else if (scc == 0x01)
3069 scc_s = "RAID";
3070 else
3071 scc_s = "?";
3072
3073 if (IS_GEN_I(hpriv))
3074 gen = "I";
3075 else if (IS_GEN_II(hpriv))
3076 gen = "II";
3077 else if (IS_GEN_IIE(hpriv))
3078 gen = "IIE";
3079 else
3080 gen = "?";
3081
3082 dev_printk(KERN_INFO, &pdev->dev,
3083 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3084 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3085 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3086 }
3087
3088 /**
3089 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3090 * @pdev: PCI device found
3091 * @ent: PCI device ID entry for the matched host
3092 *
3093 * LOCKING:
3094 * Inherited from caller.
3095 */
3096 static int mv_pci_init_one(struct pci_dev *pdev,
3097 const struct pci_device_id *ent)
3098 {
3099 static int printed_version;
3100 unsigned int board_idx = (unsigned int)ent->driver_data;
3101 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3102 struct ata_host *host;
3103 struct mv_host_priv *hpriv;
3104 int n_ports, rc;
3105
3106 if (!printed_version++)
3107 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3108
3109 /* allocate host */
3110 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3111
3112 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3113 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3114 if (!host || !hpriv)
3115 return -ENOMEM;
3116 host->private_data = hpriv;
3117 hpriv->n_ports = n_ports;
3118
3119 /* acquire resources */
3120 rc = pcim_enable_device(pdev);
3121 if (rc)
3122 return rc;
3123
3124 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3125 if (rc == -EBUSY)
3126 pcim_pin_device(pdev);
3127 if (rc)
3128 return rc;
3129 host->iomap = pcim_iomap_table(pdev);
3130 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3131
3132 rc = pci_go_64(pdev);
3133 if (rc)
3134 return rc;
3135
3136 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3137 if (rc)
3138 return rc;
3139
3140 /* initialize adapter */
3141 rc = mv_init_host(host, board_idx);
3142 if (rc)
3143 return rc;
3144
3145 /* Enable interrupts */
3146 if (msi && pci_enable_msi(pdev))
3147 pci_intx(pdev, 1);
3148
3149 mv_dump_pci_cfg(pdev, 0x68);
3150 mv_print_info(host);
3151
3152 pci_set_master(pdev);
3153 pci_try_set_mwi(pdev);
3154 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3155 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3156 }
3157 #endif
3158
3159 static int mv_platform_probe(struct platform_device *pdev);
3160 static int __devexit mv_platform_remove(struct platform_device *pdev);
3161
3162 static int __init mv_init(void)
3163 {
3164 int rc = -ENODEV;
3165 #ifdef CONFIG_PCI
3166 rc = pci_register_driver(&mv_pci_driver);
3167 if (rc < 0)
3168 return rc;
3169 #endif
3170 rc = platform_driver_register(&mv_platform_driver);
3171
3172 #ifdef CONFIG_PCI
3173 if (rc < 0)
3174 pci_unregister_driver(&mv_pci_driver);
3175 #endif
3176 return rc;
3177 }
3178
3179 static void __exit mv_exit(void)
3180 {
3181 #ifdef CONFIG_PCI
3182 pci_unregister_driver(&mv_pci_driver);
3183 #endif
3184 platform_driver_unregister(&mv_platform_driver);
3185 }
3186
3187 MODULE_AUTHOR("Brett Russ");
3188 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3189 MODULE_LICENSE("GPL");
3190 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3191 MODULE_VERSION(DRV_VERSION);
3192 MODULE_ALIAS("platform:" DRV_NAME);
3193
3194 #ifdef CONFIG_PCI
3195 module_param(msi, int, 0444);
3196 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3197 #endif
3198
3199 module_init(mv_init);
3200 module_exit(mv_exit);
Verdex Pro support