2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
26 #include "atmel_spi.h"
29 * The core SPI transfer engine just talks to a register bank to set up
30 * DMA transfers; transfer queue progress is driven by IRQs. The clock
31 * framework provides the base clock, subdivided for each spi_device.
33 * Newer controllers, marked with "new_1" flag, have:
35 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
36 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
38 * - SPI_CSRx.SBCR allows faster clocking
46 struct platform_device
*pdev
;
50 struct list_head queue
;
51 struct spi_transfer
*current_transfer
;
52 unsigned long remaining_bytes
;
55 dma_addr_t buffer_dma
;
58 #define BUFFER_SIZE PAGE_SIZE
59 #define INVALID_DMA_ADDRESS 0xffffffff
62 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
63 * they assume that spi slave device state will not change on deselect, so
64 * that automagic deselection is OK. Not so! Workaround uses nCSx pins
65 * as GPIOs; or newer controllers have CSAAT and friends.
67 * Since the CSAAT functionality is a bit weird on newer controllers
68 * as well, we use GPIO to control nCSx pins on all controllers.
71 static inline void cs_activate(struct spi_device
*spi
)
73 unsigned gpio
= (unsigned) spi
->controller_data
;
74 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
76 dev_dbg(&spi
->dev
, "activate %u%s\n", gpio
, active
? " (high)" : "");
77 gpio_set_value(gpio
, active
);
80 static inline void cs_deactivate(struct spi_device
*spi
)
82 unsigned gpio
= (unsigned) spi
->controller_data
;
83 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
85 dev_dbg(&spi
->dev
, "DEactivate %u%s\n", gpio
, active
? " (low)" : "");
86 gpio_set_value(gpio
, !active
);
90 * Submit next transfer for DMA.
91 * lock is held, spi irq is blocked
93 static void atmel_spi_next_xfer(struct spi_master
*master
,
94 struct spi_message
*msg
)
96 struct atmel_spi
*as
= spi_master_get_devdata(master
);
97 struct spi_transfer
*xfer
;
99 dma_addr_t tx_dma
, rx_dma
;
101 xfer
= as
->current_transfer
;
102 if (!xfer
|| as
->remaining_bytes
== 0) {
104 xfer
= list_entry(xfer
->transfer_list
.next
,
105 struct spi_transfer
, transfer_list
);
107 xfer
= list_entry(msg
->transfers
.next
,
108 struct spi_transfer
, transfer_list
);
109 as
->remaining_bytes
= xfer
->len
;
110 as
->current_transfer
= xfer
;
113 len
= as
->remaining_bytes
;
115 tx_dma
= xfer
->tx_dma
;
116 rx_dma
= xfer
->rx_dma
;
118 /* use scratch buffer only when rx or tx data is unspecified */
119 if (rx_dma
== INVALID_DMA_ADDRESS
) {
120 rx_dma
= as
->buffer_dma
;
121 if (len
> BUFFER_SIZE
)
124 if (tx_dma
== INVALID_DMA_ADDRESS
) {
125 tx_dma
= as
->buffer_dma
;
126 if (len
> BUFFER_SIZE
)
128 memset(as
->buffer
, 0, len
);
129 dma_sync_single_for_device(&as
->pdev
->dev
,
130 as
->buffer_dma
, len
, DMA_TO_DEVICE
);
133 spi_writel(as
, RPR
, rx_dma
);
134 spi_writel(as
, TPR
, tx_dma
);
136 as
->remaining_bytes
-= len
;
137 if (msg
->spi
->bits_per_word
> 8)
140 /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
141 * mechanism might help avoid the IRQ latency between transfers
143 * We're also waiting for ENDRX before we start the next
144 * transfer because we need to handle some difficult timing
145 * issues otherwise. If we wait for ENDTX in one transfer and
146 * then starts waiting for ENDRX in the next, it's difficult
147 * to tell the difference between the ENDRX interrupt we're
148 * actually waiting for and the ENDRX interrupt of the
151 * It should be doable, though. Just not now...
153 spi_writel(as
, TNCR
, 0);
154 spi_writel(as
, RNCR
, 0);
155 spi_writel(as
, IER
, SPI_BIT(ENDRX
) | SPI_BIT(OVRES
));
157 dev_dbg(&msg
->spi
->dev
,
158 " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
159 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->tx_dma
,
160 xfer
->rx_buf
, xfer
->rx_dma
, spi_readl(as
, IMR
));
162 spi_writel(as
, TCR
, len
);
163 spi_writel(as
, RCR
, len
);
164 spi_writel(as
, PTCR
, SPI_BIT(TXTEN
) | SPI_BIT(RXTEN
));
167 static void atmel_spi_next_message(struct spi_master
*master
)
169 struct atmel_spi
*as
= spi_master_get_devdata(master
);
170 struct spi_message
*msg
;
173 BUG_ON(as
->current_transfer
);
175 msg
= list_entry(as
->queue
.next
, struct spi_message
, queue
);
177 /* Select the chip */
178 mr
= spi_readl(as
, MR
);
179 mr
= SPI_BFINS(PCS
, ~(1 << msg
->spi
->chip_select
), mr
);
180 spi_writel(as
, MR
, mr
);
181 cs_activate(msg
->spi
);
183 atmel_spi_next_xfer(master
, msg
);
187 atmel_spi_dma_map_xfer(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
189 xfer
->tx_dma
= xfer
->rx_dma
= INVALID_DMA_ADDRESS
;
191 xfer
->tx_dma
= dma_map_single(&as
->pdev
->dev
,
192 (void *) xfer
->tx_buf
, xfer
->len
,
195 xfer
->rx_dma
= dma_map_single(&as
->pdev
->dev
,
196 xfer
->rx_buf
, xfer
->len
,
200 static void atmel_spi_dma_unmap_xfer(struct spi_master
*master
,
201 struct spi_transfer
*xfer
)
203 if (xfer
->tx_dma
!= INVALID_DMA_ADDRESS
)
204 dma_unmap_single(master
->cdev
.dev
, xfer
->tx_dma
,
205 xfer
->len
, DMA_TO_DEVICE
);
206 if (xfer
->rx_dma
!= INVALID_DMA_ADDRESS
)
207 dma_unmap_single(master
->cdev
.dev
, xfer
->rx_dma
,
208 xfer
->len
, DMA_FROM_DEVICE
);
212 atmel_spi_msg_done(struct spi_master
*master
, struct atmel_spi
*as
,
213 struct spi_message
*msg
, int status
)
215 cs_deactivate(msg
->spi
);
216 list_del(&msg
->queue
);
217 msg
->status
= status
;
219 dev_dbg(master
->cdev
.dev
,
220 "xfer complete: %u bytes transferred\n",
223 spin_unlock(&as
->lock
);
224 msg
->complete(msg
->context
);
225 spin_lock(&as
->lock
);
227 as
->current_transfer
= NULL
;
229 /* continue if needed */
230 if (list_empty(&as
->queue
) || as
->stopping
)
231 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
233 atmel_spi_next_message(master
);
237 atmel_spi_interrupt(int irq
, void *dev_id
)
239 struct spi_master
*master
= dev_id
;
240 struct atmel_spi
*as
= spi_master_get_devdata(master
);
241 struct spi_message
*msg
;
242 struct spi_transfer
*xfer
;
243 u32 status
, pending
, imr
;
246 spin_lock(&as
->lock
);
248 xfer
= as
->current_transfer
;
249 msg
= list_entry(as
->queue
.next
, struct spi_message
, queue
);
251 imr
= spi_readl(as
, IMR
);
252 status
= spi_readl(as
, SR
);
253 pending
= status
& imr
;
255 if (pending
& SPI_BIT(OVRES
)) {
260 spi_writel(as
, IDR
, (SPI_BIT(ENDTX
) | SPI_BIT(ENDRX
)
264 * When we get an overrun, we disregard the current
265 * transfer. Data will not be copied back from any
266 * bounce buffer and msg->actual_len will not be
267 * updated with the last xfer.
269 * We will also not process any remaning transfers in
272 * First, stop the transfer and unmap the DMA buffers.
274 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
275 if (!msg
->is_dma_mapped
)
276 atmel_spi_dma_unmap_xfer(master
, xfer
);
278 /* REVISIT: udelay in irq is unfriendly */
279 if (xfer
->delay_usecs
)
280 udelay(xfer
->delay_usecs
);
282 dev_warn(master
->cdev
.dev
, "fifo overrun (%u/%u remaining)\n",
283 spi_readl(as
, TCR
), spi_readl(as
, RCR
));
286 * Clean up DMA registers and make sure the data
287 * registers are empty.
289 spi_writel(as
, RNCR
, 0);
290 spi_writel(as
, TNCR
, 0);
291 spi_writel(as
, RCR
, 0);
292 spi_writel(as
, TCR
, 0);
293 for (timeout
= 1000; timeout
; timeout
--)
294 if (spi_readl(as
, SR
) & SPI_BIT(TXEMPTY
))
297 dev_warn(master
->cdev
.dev
,
298 "timeout waiting for TXEMPTY");
299 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
))
302 /* Clear any overrun happening while cleaning up */
305 atmel_spi_msg_done(master
, as
, msg
, -EIO
);
306 } else if (pending
& SPI_BIT(ENDRX
)) {
309 spi_writel(as
, IDR
, pending
);
311 if (as
->remaining_bytes
== 0) {
312 msg
->actual_length
+= xfer
->len
;
314 if (!msg
->is_dma_mapped
)
315 atmel_spi_dma_unmap_xfer(master
, xfer
);
317 /* REVISIT: udelay in irq is unfriendly */
318 if (xfer
->delay_usecs
)
319 udelay(xfer
->delay_usecs
);
321 if (msg
->transfers
.prev
== &xfer
->transfer_list
) {
322 /* report completed message */
323 atmel_spi_msg_done(master
, as
, msg
, 0);
325 if (xfer
->cs_change
) {
326 cs_deactivate(msg
->spi
);
328 cs_activate(msg
->spi
);
332 * Not done yet. Submit the next transfer.
334 * FIXME handle protocol options for xfer
336 atmel_spi_next_xfer(master
, msg
);
340 * Keep going, we still have data to send in
341 * the current transfer.
343 atmel_spi_next_xfer(master
, msg
);
347 spin_unlock(&as
->lock
);
352 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
354 static int atmel_spi_setup(struct spi_device
*spi
)
356 struct atmel_spi
*as
;
358 unsigned int bits
= spi
->bits_per_word
;
359 unsigned long bus_hz
, sck_hz
;
360 unsigned int npcs_pin
;
363 as
= spi_master_get_devdata(spi
->master
);
368 if (spi
->chip_select
> spi
->master
->num_chipselect
) {
370 "setup: invalid chipselect %u (%u defined)\n",
371 spi
->chip_select
, spi
->master
->num_chipselect
);
377 if (bits
< 8 || bits
> 16) {
379 "setup: invalid bits_per_word %u (8 to 16)\n",
384 if (spi
->mode
& ~MODEBITS
) {
385 dev_dbg(&spi
->dev
, "setup: unsupported mode bits %x\n",
386 spi
->mode
& ~MODEBITS
);
390 /* speed zero convention is used by some upper layers */
391 bus_hz
= clk_get_rate(as
->clk
);
392 if (spi
->max_speed_hz
) {
393 /* assume div32/fdiv/mbz == 0 */
396 scbr
= ((bus_hz
+ spi
->max_speed_hz
- 1)
397 / spi
->max_speed_hz
);
398 if (scbr
>= (1 << SPI_SCBR_SIZE
)) {
399 dev_dbg(&spi
->dev
, "setup: %d Hz too slow, scbr %u\n",
400 spi
->max_speed_hz
, scbr
);
405 sck_hz
= bus_hz
/ scbr
;
407 csr
= SPI_BF(SCBR
, scbr
) | SPI_BF(BITS
, bits
- 8);
408 if (spi
->mode
& SPI_CPOL
)
409 csr
|= SPI_BIT(CPOL
);
410 if (!(spi
->mode
& SPI_CPHA
))
411 csr
|= SPI_BIT(NCPHA
);
413 /* TODO: DLYBS and DLYBCT */
414 csr
|= SPI_BF(DLYBS
, 10);
415 csr
|= SPI_BF(DLYBCT
, 10);
417 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
418 npcs_pin
= (unsigned int)spi
->controller_data
;
419 if (!spi
->controller_state
) {
420 ret
= gpio_request(npcs_pin
, "spi_npcs");
423 spi
->controller_state
= (void *)npcs_pin
;
424 gpio_direction_output(npcs_pin
);
428 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
429 sck_hz
, bits
, spi
->mode
, spi
->chip_select
, csr
);
431 spi_writel(as
, CSR0
+ 4 * spi
->chip_select
, csr
);
436 static int atmel_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
438 struct atmel_spi
*as
;
439 struct spi_transfer
*xfer
;
441 struct device
*controller
= spi
->master
->cdev
.dev
;
443 as
= spi_master_get_devdata(spi
->master
);
445 dev_dbg(controller
, "new message %p submitted for %s\n",
446 msg
, spi
->dev
.bus_id
);
448 if (unlikely(list_empty(&msg
->transfers
)
449 || !spi
->max_speed_hz
))
455 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
456 if (!(xfer
->tx_buf
|| xfer
->rx_buf
)) {
457 dev_dbg(&spi
->dev
, "missing rx or tx buf\n");
461 /* FIXME implement these protocol options!! */
462 if (xfer
->bits_per_word
|| xfer
->speed_hz
) {
463 dev_dbg(&spi
->dev
, "no protocol options yet\n");
468 /* scrub dcache "early" */
469 if (!msg
->is_dma_mapped
) {
470 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
)
471 atmel_spi_dma_map_xfer(as
, xfer
);
474 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
476 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
478 xfer
->tx_buf
, xfer
->tx_dma
,
479 xfer
->rx_buf
, xfer
->rx_dma
);
482 msg
->status
= -EINPROGRESS
;
483 msg
->actual_length
= 0;
485 spin_lock_irqsave(&as
->lock
, flags
);
486 list_add_tail(&msg
->queue
, &as
->queue
);
487 if (!as
->current_transfer
)
488 atmel_spi_next_message(spi
->master
);
489 spin_unlock_irqrestore(&as
->lock
, flags
);
494 static void atmel_spi_cleanup(const struct spi_device
*spi
)
496 if (spi
->controller_state
)
497 gpio_free((unsigned int)spi
->controller_data
);
500 /*-------------------------------------------------------------------------*/
502 static int __init
atmel_spi_probe(struct platform_device
*pdev
)
504 struct resource
*regs
;
508 struct spi_master
*master
;
509 struct atmel_spi
*as
;
511 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
515 irq
= platform_get_irq(pdev
, 0);
519 clk
= clk_get(&pdev
->dev
, "spi_clk");
523 /* setup spi core then atmel-specific driver state */
525 master
= spi_alloc_master(&pdev
->dev
, sizeof *as
);
529 master
->bus_num
= pdev
->id
;
530 master
->num_chipselect
= 4;
531 master
->setup
= atmel_spi_setup
;
532 master
->transfer
= atmel_spi_transfer
;
533 master
->cleanup
= atmel_spi_cleanup
;
534 platform_set_drvdata(pdev
, master
);
536 as
= spi_master_get_devdata(master
);
538 as
->buffer
= dma_alloc_coherent(&pdev
->dev
, BUFFER_SIZE
,
539 &as
->buffer_dma
, GFP_KERNEL
);
543 spin_lock_init(&as
->lock
);
544 INIT_LIST_HEAD(&as
->queue
);
546 as
->regs
= ioremap(regs
->start
, (regs
->end
- regs
->start
) + 1);
548 goto out_free_buffer
;
551 #ifdef CONFIG_ARCH_AT91
552 if (!cpu_is_at91rm9200())
556 ret
= request_irq(irq
, atmel_spi_interrupt
, 0,
557 pdev
->dev
.bus_id
, master
);
561 /* Initialize the hardware */
563 spi_writel(as
, CR
, SPI_BIT(SWRST
));
564 spi_writel(as
, MR
, SPI_BIT(MSTR
) | SPI_BIT(MODFDIS
));
565 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
566 spi_writel(as
, CR
, SPI_BIT(SPIEN
));
569 dev_info(&pdev
->dev
, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
570 (unsigned long)regs
->start
, irq
);
572 ret
= spi_register_master(master
);
579 spi_writel(as
, CR
, SPI_BIT(SWRST
));
581 free_irq(irq
, master
);
585 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
589 spi_master_put(master
);
593 static int __exit
atmel_spi_remove(struct platform_device
*pdev
)
595 struct spi_master
*master
= platform_get_drvdata(pdev
);
596 struct atmel_spi
*as
= spi_master_get_devdata(master
);
597 struct spi_message
*msg
;
599 /* reset the hardware and block queue progress */
600 spin_lock_irq(&as
->lock
);
602 spi_writel(as
, CR
, SPI_BIT(SWRST
));
604 spin_unlock_irq(&as
->lock
);
606 /* Terminate remaining queued transfers */
607 list_for_each_entry(msg
, &as
->queue
, queue
) {
608 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
609 * but we shouldn't depend on that...
611 msg
->status
= -ESHUTDOWN
;
612 msg
->complete(msg
->context
);
615 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
618 clk_disable(as
->clk
);
620 free_irq(as
->irq
, master
);
623 spi_unregister_master(master
);
630 static int atmel_spi_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
632 struct spi_master
*master
= platform_get_drvdata(pdev
);
633 struct atmel_spi
*as
= spi_master_get_devdata(master
);
635 clk_disable(as
->clk
);
639 static int atmel_spi_resume(struct platform_device
*pdev
)
641 struct spi_master
*master
= platform_get_drvdata(pdev
);
642 struct atmel_spi
*as
= spi_master_get_devdata(master
);
649 #define atmel_spi_suspend NULL
650 #define atmel_spi_resume NULL
654 static struct platform_driver atmel_spi_driver
= {
657 .owner
= THIS_MODULE
,
659 .suspend
= atmel_spi_suspend
,
660 .resume
= atmel_spi_resume
,
661 .remove
= __exit_p(atmel_spi_remove
),
664 static int __init
atmel_spi_init(void)
666 return platform_driver_probe(&atmel_spi_driver
, atmel_spi_probe
);
668 module_init(atmel_spi_init
);
670 static void __exit
atmel_spi_exit(void)
672 platform_driver_unregister(&atmel_spi_driver
);
674 module_exit(atmel_spi_exit
);
676 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
677 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
678 MODULE_LICENSE("GPL");