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USB: xhci: fix less- and greater than confusion
[linux-2.6/verdex.git] / drivers / ata / sata_mv.c
blob23714aefb8256d742c56858b9a57e9614ecfb8c1
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/platform_device.h>
63 #include <linux/ata_platform.h>
64 #include <linux/mbus.h>
65 #include <linux/bitops.h>
66 #include <scsi/scsi_host.h>
67 #include <scsi/scsi_cmnd.h>
68 #include <scsi/scsi_device.h>
69 #include <linux/libata.h>
70
71 #define DRV_NAME "sata_mv"
72 #define DRV_VERSION "1.28"
73
74 /*
75 * module options
76 */
77
78 static int msi;
79 #ifdef CONFIG_PCI
80 module_param(msi, int, S_IRUGO);
81 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
82 #endif
83
84 static int irq_coalescing_io_count;
85 module_param(irq_coalescing_io_count, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_io_count,
87 "IRQ coalescing I/O count threshold (0..255)");
88
89 static int irq_coalescing_usecs;
90 module_param(irq_coalescing_usecs, int, S_IRUGO);
91 MODULE_PARM_DESC(irq_coalescing_usecs,
92 "IRQ coalescing time threshold in usecs");
93
94 enum {
95 /* BAR's are enumerated in terms of pci_resource_start() terms */
96 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
97 MV_IO_BAR = 2, /* offset 0x18: IO space */
98 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
99
100 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
101 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
102
103 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
104 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
105 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
106 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
107
108 MV_PCI_REG_BASE = 0,
109
110 /*
111 * Per-chip ("all ports") interrupt coalescing feature.
112 * This is only for GEN_II / GEN_IIE hardware.
113 *
114 * Coalescing defers the interrupt until either the IO_THRESHOLD
115 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
116 */
117 COAL_REG_BASE = 0x18000,
118 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
119 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
120
121 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
122 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
123
124 /*
125 * Registers for the (unused here) transaction coalescing feature:
126 */
127 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
128 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
129
130 SATAHC0_REG_BASE = 0x20000,
131 FLASH_CTL = 0x1046c,
132 GPIO_PORT_CTL = 0x104f0,
133 RESET_CFG = 0x180d8,
134
135 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
136 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
137 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
138 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
139
140 MV_MAX_Q_DEPTH = 32,
141 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
142
143 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
144 * CRPB needs alignment on a 256B boundary. Size == 256B
145 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
146 */
147 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
148 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
149 MV_MAX_SG_CT = 256,
150 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
151
152 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
153 MV_PORT_HC_SHIFT = 2,
154 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
155 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
156 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
157
158 /* Host Flags */
159 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
160
161 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
162 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
163
164 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
165
166 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
167 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
168
169 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
170
171 CRQB_FLAG_READ = (1 << 0),
172 CRQB_TAG_SHIFT = 1,
173 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
174 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
175 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
176 CRQB_CMD_ADDR_SHIFT = 8,
177 CRQB_CMD_CS = (0x2 << 11),
178 CRQB_CMD_LAST = (1 << 15),
179
180 CRPB_FLAG_STATUS_SHIFT = 8,
181 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
182 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
183
184 EPRD_FLAG_END_OF_TBL = (1 << 31),
185
186 /* PCI interface registers */
187
188 MV_PCI_COMMAND = 0xc00,
189 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
190 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
191
192 PCI_MAIN_CMD_STS = 0xd30,
193 STOP_PCI_MASTER = (1 << 2),
194 PCI_MASTER_EMPTY = (1 << 3),
195 GLOB_SFT_RST = (1 << 4),
196
197 MV_PCI_MODE = 0xd00,
198 MV_PCI_MODE_MASK = 0x30,
199
200 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
201 MV_PCI_DISC_TIMER = 0xd04,
202 MV_PCI_MSI_TRIGGER = 0xc38,
203 MV_PCI_SERR_MASK = 0xc28,
204 MV_PCI_XBAR_TMOUT = 0x1d04,
205 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
206 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
207 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
208 MV_PCI_ERR_COMMAND = 0x1d50,
209
210 PCI_IRQ_CAUSE = 0x1d58,
211 PCI_IRQ_MASK = 0x1d5c,
212 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
213
214 PCIE_IRQ_CAUSE = 0x1900,
215 PCIE_IRQ_MASK = 0x1910,
216 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
217
218 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
219 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
220 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
221 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
222 SOC_HC_MAIN_IRQ_MASK = 0x20024,
223 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
224 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
225 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
226 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
227 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
228 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
229 PCI_ERR = (1 << 18),
230 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
231 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
232 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
233 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
234 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
235 GPIO_INT = (1 << 22),
236 SELF_INT = (1 << 23),
237 TWSI_INT = (1 << 24),
238 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
239 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
240 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
241
242 /* SATAHC registers */
243 HC_CFG = 0x00,
244
245 HC_IRQ_CAUSE = 0x14,
246 DMA_IRQ = (1 << 0), /* shift by port # */
247 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
248 DEV_IRQ = (1 << 8), /* shift by port # */
249
250 /*
251 * Per-HC (Host-Controller) interrupt coalescing feature.
252 * This is present on all chip generations.
253 *
254 * Coalescing defers the interrupt until either the IO_THRESHOLD
255 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
256 */
257 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
258 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
259
260 SOC_LED_CTRL = 0x2c,
261 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
262 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
263 /* with dev activity LED */
264
265 /* Shadow block registers */
266 SHD_BLK = 0x100,
267 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
268
269 /* SATA registers */
270 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
271 SATA_ACTIVE = 0x350,
272 FIS_IRQ_CAUSE = 0x364,
273 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
274
275 LTMODE = 0x30c, /* requires read-after-write */
276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
277
278 PHY_MODE2 = 0x330,
279 PHY_MODE3 = 0x310,
280
281 PHY_MODE4 = 0x314, /* requires read-after-write */
282 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
283 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
284 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
285 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
286
287 SATA_IFCTL = 0x344,
288 SATA_TESTCTL = 0x348,
289 SATA_IFSTAT = 0x34c,
290 VENDOR_UNIQUE_FIS = 0x35c,
291
292 FISCFG = 0x360,
293 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
294 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
295
296 PHY_MODE9_GEN2 = 0x398,
297 PHY_MODE9_GEN1 = 0x39c,
298 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
299
300 MV5_PHY_MODE = 0x74,
301 MV5_LTMODE = 0x30,
302 MV5_PHY_CTL = 0x0C,
303 SATA_IFCFG = 0x050,
304
305 MV_M2_PREAMP_MASK = 0x7e0,
306
307 /* Port registers */
308 EDMA_CFG = 0,
309 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
310 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
311 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
312 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
313 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
314 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
315 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
316
317 EDMA_ERR_IRQ_CAUSE = 0x8,
318 EDMA_ERR_IRQ_MASK = 0xc,
319 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
320 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
321 EDMA_ERR_DEV = (1 << 2), /* device error */
322 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
323 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
324 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
325 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
326 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
327 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
328 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
329 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
330 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
331 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
332 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
333
334 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
335 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
336 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
337 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
338 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
339
340 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
341
342 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
343 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
344 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
345 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
346 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
347 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
348
349 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
350
351 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
352 EDMA_ERR_OVERRUN_5 = (1 << 5),
353 EDMA_ERR_UNDERRUN_5 = (1 << 6),
354
355 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
356 EDMA_ERR_LNK_CTRL_RX_1 |
357 EDMA_ERR_LNK_CTRL_RX_3 |
358 EDMA_ERR_LNK_CTRL_TX,
359
360 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
361 EDMA_ERR_PRD_PAR |
362 EDMA_ERR_DEV_DCON |
363 EDMA_ERR_DEV_CON |
364 EDMA_ERR_SERR |
365 EDMA_ERR_SELF_DIS |
366 EDMA_ERR_CRQB_PAR |
367 EDMA_ERR_CRPB_PAR |
368 EDMA_ERR_INTRL_PAR |
369 EDMA_ERR_IORDY |
370 EDMA_ERR_LNK_CTRL_RX_2 |
371 EDMA_ERR_LNK_DATA_RX |
372 EDMA_ERR_LNK_DATA_TX |
373 EDMA_ERR_TRANS_PROTO,
374
375 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
376 EDMA_ERR_PRD_PAR |
377 EDMA_ERR_DEV_DCON |
378 EDMA_ERR_DEV_CON |
379 EDMA_ERR_OVERRUN_5 |
380 EDMA_ERR_UNDERRUN_5 |
381 EDMA_ERR_SELF_DIS_5 |
382 EDMA_ERR_CRQB_PAR |
383 EDMA_ERR_CRPB_PAR |
384 EDMA_ERR_INTRL_PAR |
385 EDMA_ERR_IORDY,
386
387 EDMA_REQ_Q_BASE_HI = 0x10,
388 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
389
390 EDMA_REQ_Q_OUT_PTR = 0x18,
391 EDMA_REQ_Q_PTR_SHIFT = 5,
392
393 EDMA_RSP_Q_BASE_HI = 0x1c,
394 EDMA_RSP_Q_IN_PTR = 0x20,
395 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
396 EDMA_RSP_Q_PTR_SHIFT = 3,
397
398 EDMA_CMD = 0x28, /* EDMA command register */
399 EDMA_EN = (1 << 0), /* enable EDMA */
400 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
401 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
402
403 EDMA_STATUS = 0x30, /* EDMA engine status */
404 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
405 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
406
407 EDMA_IORDY_TMOUT = 0x34,
408 EDMA_ARB_CFG = 0x38,
409
410 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
411 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
412
413 BMDMA_CMD = 0x224, /* bmdma command register */
414 BMDMA_STATUS = 0x228, /* bmdma status register */
415 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
416 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
417
418 /* Host private flags (hp_flags) */
419 MV_HP_FLAG_MSI = (1 << 0),
420 MV_HP_ERRATA_50XXB0 = (1 << 1),
421 MV_HP_ERRATA_50XXB2 = (1 << 2),
422 MV_HP_ERRATA_60X1B2 = (1 << 3),
423 MV_HP_ERRATA_60X1C0 = (1 << 4),
424 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
425 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
426 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
427 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
428 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
429 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
430 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
431
432 /* Port private flags (pp_flags) */
433 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
434 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
435 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
436 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
437 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
438 };
439
440 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
441 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
442 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
443 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
444 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
445
446 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
447 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
448
449 enum {
450 /* DMA boundary 0xffff is required by the s/g splitting
451 * we need on /length/ in mv_fill-sg().
452 */
453 MV_DMA_BOUNDARY = 0xffffU,
454
455 /* mask of register bits containing lower 32 bits
456 * of EDMA request queue DMA address
457 */
458 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
459
460 /* ditto, for response queue */
461 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
462 };
463
464 enum chip_type {
465 chip_504x,
466 chip_508x,
467 chip_5080,
468 chip_604x,
469 chip_608x,
470 chip_6042,
471 chip_7042,
472 chip_soc,
473 };
474
475 /* Command ReQuest Block: 32B */
476 struct mv_crqb {
477 __le32 sg_addr;
478 __le32 sg_addr_hi;
479 __le16 ctrl_flags;
480 __le16 ata_cmd[11];
481 };
482
483 struct mv_crqb_iie {
484 __le32 addr;
485 __le32 addr_hi;
486 __le32 flags;
487 __le32 len;
488 __le32 ata_cmd[4];
489 };
490
491 /* Command ResPonse Block: 8B */
492 struct mv_crpb {
493 __le16 id;
494 __le16 flags;
495 __le32 tmstmp;
496 };
497
498 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
499 struct mv_sg {
500 __le32 addr;
501 __le32 flags_size;
502 __le32 addr_hi;
503 __le32 reserved;
504 };
505
506 /*
507 * We keep a local cache of a few frequently accessed port
508 * registers here, to avoid having to read them (very slow)
509 * when switching between EDMA and non-EDMA modes.
510 */
511 struct mv_cached_regs {
512 u32 fiscfg;
513 u32 ltmode;
514 u32 haltcond;
515 u32 unknown_rsvd;
516 };
517
518 struct mv_port_priv {
519 struct mv_crqb *crqb;
520 dma_addr_t crqb_dma;
521 struct mv_crpb *crpb;
522 dma_addr_t crpb_dma;
523 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
524 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
525
526 unsigned int req_idx;
527 unsigned int resp_idx;
528
529 u32 pp_flags;
530 struct mv_cached_regs cached;
531 unsigned int delayed_eh_pmp_map;
532 };
533
534 struct mv_port_signal {
535 u32 amps;
536 u32 pre;
537 };
538
539 struct mv_host_priv {
540 u32 hp_flags;
541 u32 main_irq_mask;
542 struct mv_port_signal signal[8];
543 const struct mv_hw_ops *ops;
544 int n_ports;
545 void __iomem *base;
546 void __iomem *main_irq_cause_addr;
547 void __iomem *main_irq_mask_addr;
548 u32 irq_cause_offset;
549 u32 irq_mask_offset;
550 u32 unmask_all_irqs;
551 /*
552 * These consistent DMA memory pools give us guaranteed
553 * alignment for hardware-accessed data structures,
554 * and less memory waste in accomplishing the alignment.
555 */
556 struct dma_pool *crqb_pool;
557 struct dma_pool *crpb_pool;
558 struct dma_pool *sg_tbl_pool;
559 };
560
561 struct mv_hw_ops {
562 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
563 unsigned int port);
564 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
565 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
566 void __iomem *mmio);
567 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
568 unsigned int n_hc);
569 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
570 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
571 };
572
573 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
574 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
575 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
576 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
577 static int mv_port_start(struct ata_port *ap);
578 static void mv_port_stop(struct ata_port *ap);
579 static int mv_qc_defer(struct ata_queued_cmd *qc);
580 static void mv_qc_prep(struct ata_queued_cmd *qc);
581 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
582 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
583 static int mv_hardreset(struct ata_link *link, unsigned int *class,
584 unsigned long deadline);
585 static void mv_eh_freeze(struct ata_port *ap);
586 static void mv_eh_thaw(struct ata_port *ap);
587 static void mv6_dev_config(struct ata_device *dev);
588
589 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
590 unsigned int port);
591 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
592 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
593 void __iomem *mmio);
594 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
595 unsigned int n_hc);
596 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
597 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
598
599 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
600 unsigned int port);
601 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
602 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
603 void __iomem *mmio);
604 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
605 unsigned int n_hc);
606 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
608 void __iomem *mmio);
609 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
612 void __iomem *mmio, unsigned int n_hc);
613 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
614 void __iomem *mmio);
615 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
616 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
617 void __iomem *mmio, unsigned int port);
618 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
619 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
620 unsigned int port_no);
621 static int mv_stop_edma(struct ata_port *ap);
622 static int mv_stop_edma_engine(void __iomem *port_mmio);
623 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
624
625 static void mv_pmp_select(struct ata_port *ap, int pmp);
626 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
627 unsigned long deadline);
628 static int mv_softreset(struct ata_link *link, unsigned int *class,
629 unsigned long deadline);
630 static void mv_pmp_error_handler(struct ata_port *ap);
631 static void mv_process_crpb_entries(struct ata_port *ap,
632 struct mv_port_priv *pp);
633
634 static void mv_sff_irq_clear(struct ata_port *ap);
635 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
636 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
637 static void mv_bmdma_start(struct ata_queued_cmd *qc);
638 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
639 static u8 mv_bmdma_status(struct ata_port *ap);
640 static u8 mv_sff_check_status(struct ata_port *ap);
641
642 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
643 * because we have to allow room for worst case splitting of
644 * PRDs for 64K boundaries in mv_fill_sg().
645 */
646 static struct scsi_host_template mv5_sht = {
647 ATA_BASE_SHT(DRV_NAME),
648 .sg_tablesize = MV_MAX_SG_CT / 2,
649 .dma_boundary = MV_DMA_BOUNDARY,
650 };
651
652 static struct scsi_host_template mv6_sht = {
653 ATA_NCQ_SHT(DRV_NAME),
654 .can_queue = MV_MAX_Q_DEPTH - 1,
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
657 };
658
659 static struct ata_port_operations mv5_ops = {
660 .inherits = &ata_sff_port_ops,
661
662 .lost_interrupt = ATA_OP_NULL,
663
664 .qc_defer = mv_qc_defer,
665 .qc_prep = mv_qc_prep,
666 .qc_issue = mv_qc_issue,
667
668 .freeze = mv_eh_freeze,
669 .thaw = mv_eh_thaw,
670 .hardreset = mv_hardreset,
671 .error_handler = ata_std_error_handler, /* avoid SFF EH */
672 .post_internal_cmd = ATA_OP_NULL,
673
674 .scr_read = mv5_scr_read,
675 .scr_write = mv5_scr_write,
676
677 .port_start = mv_port_start,
678 .port_stop = mv_port_stop,
679 };
680
681 static struct ata_port_operations mv6_ops = {
682 .inherits = &mv5_ops,
683 .dev_config = mv6_dev_config,
684 .scr_read = mv_scr_read,
685 .scr_write = mv_scr_write,
686
687 .pmp_hardreset = mv_pmp_hardreset,
688 .pmp_softreset = mv_softreset,
689 .softreset = mv_softreset,
690 .error_handler = mv_pmp_error_handler,
691
692 .sff_check_status = mv_sff_check_status,
693 .sff_irq_clear = mv_sff_irq_clear,
694 .check_atapi_dma = mv_check_atapi_dma,
695 .bmdma_setup = mv_bmdma_setup,
696 .bmdma_start = mv_bmdma_start,
697 .bmdma_stop = mv_bmdma_stop,
698 .bmdma_status = mv_bmdma_status,
699 };
700
701 static struct ata_port_operations mv_iie_ops = {
702 .inherits = &mv6_ops,
703 .dev_config = ATA_OP_NULL,
704 .qc_prep = mv_qc_prep_iie,
705 };
706
707 static const struct ata_port_info mv_port_info[] = {
708 { /* chip_504x */
709 .flags = MV_GEN_I_FLAGS,
710 .pio_mask = ATA_PIO4,
711 .udma_mask = ATA_UDMA6,
712 .port_ops = &mv5_ops,
713 },
714 { /* chip_508x */
715 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
716 .pio_mask = ATA_PIO4,
717 .udma_mask = ATA_UDMA6,
718 .port_ops = &mv5_ops,
719 },
720 { /* chip_5080 */
721 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
722 .pio_mask = ATA_PIO4,
723 .udma_mask = ATA_UDMA6,
724 .port_ops = &mv5_ops,
725 },
726 { /* chip_604x */
727 .flags = MV_GEN_II_FLAGS,
728 .pio_mask = ATA_PIO4,
729 .udma_mask = ATA_UDMA6,
730 .port_ops = &mv6_ops,
731 },
732 { /* chip_608x */
733 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
734 .pio_mask = ATA_PIO4,
735 .udma_mask = ATA_UDMA6,
736 .port_ops = &mv6_ops,
737 },
738 { /* chip_6042 */
739 .flags = MV_GEN_IIE_FLAGS,
740 .pio_mask = ATA_PIO4,
741 .udma_mask = ATA_UDMA6,
742 .port_ops = &mv_iie_ops,
743 },
744 { /* chip_7042 */
745 .flags = MV_GEN_IIE_FLAGS,
746 .pio_mask = ATA_PIO4,
747 .udma_mask = ATA_UDMA6,
748 .port_ops = &mv_iie_ops,
749 },
750 { /* chip_soc */
751 .flags = MV_GEN_IIE_FLAGS,
752 .pio_mask = ATA_PIO4,
753 .udma_mask = ATA_UDMA6,
754 .port_ops = &mv_iie_ops,
755 },
756 };
757
758 static const struct pci_device_id mv_pci_tbl[] = {
759 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
760 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
761 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
762 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
763 /* RocketRAID 1720/174x have different identifiers */
764 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
765 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
766 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
767
768 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
769 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
770 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
771 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
772 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
773
774 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
775
776 /* Adaptec 1430SA */
777 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
778
779 /* Marvell 7042 support */
780 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
781
782 /* Highpoint RocketRAID PCIe series */
783 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
784 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
785
786 { } /* terminate list */
787 };
788
789 static const struct mv_hw_ops mv5xxx_ops = {
790 .phy_errata = mv5_phy_errata,
791 .enable_leds = mv5_enable_leds,
792 .read_preamp = mv5_read_preamp,
793 .reset_hc = mv5_reset_hc,
794 .reset_flash = mv5_reset_flash,
795 .reset_bus = mv5_reset_bus,
796 };
797
798 static const struct mv_hw_ops mv6xxx_ops = {
799 .phy_errata = mv6_phy_errata,
800 .enable_leds = mv6_enable_leds,
801 .read_preamp = mv6_read_preamp,
802 .reset_hc = mv6_reset_hc,
803 .reset_flash = mv6_reset_flash,
804 .reset_bus = mv_reset_pci_bus,
805 };
806
807 static const struct mv_hw_ops mv_soc_ops = {
808 .phy_errata = mv6_phy_errata,
809 .enable_leds = mv_soc_enable_leds,
810 .read_preamp = mv_soc_read_preamp,
811 .reset_hc = mv_soc_reset_hc,
812 .reset_flash = mv_soc_reset_flash,
813 .reset_bus = mv_soc_reset_bus,
814 };
815
816 static const struct mv_hw_ops mv_soc_65n_ops = {
817 .phy_errata = mv_soc_65n_phy_errata,
818 .enable_leds = mv_soc_enable_leds,
819 .reset_hc = mv_soc_reset_hc,
820 .reset_flash = mv_soc_reset_flash,
821 .reset_bus = mv_soc_reset_bus,
822 };
823
824 /*
825 * Functions
826 */
827
828 static inline void writelfl(unsigned long data, void __iomem *addr)
829 {
830 writel(data, addr);
831 (void) readl(addr); /* flush to avoid PCI posted write */
832 }
833
834 static inline unsigned int mv_hc_from_port(unsigned int port)
835 {
836 return port >> MV_PORT_HC_SHIFT;
837 }
838
839 static inline unsigned int mv_hardport_from_port(unsigned int port)
840 {
841 return port & MV_PORT_MASK;
842 }
843
844 /*
845 * Consolidate some rather tricky bit shift calculations.
846 * This is hot-path stuff, so not a function.
847 * Simple code, with two return values, so macro rather than inline.
848 *
849 * port is the sole input, in range 0..7.
850 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
851 * hardport is the other output, in range 0..3.
852 *
853 * Note that port and hardport may be the same variable in some cases.
854 */
855 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
856 { \
857 shift = mv_hc_from_port(port) * HC_SHIFT; \
858 hardport = mv_hardport_from_port(port); \
859 shift += hardport * 2; \
860 }
861
862 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
863 {
864 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
865 }
866
867 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
868 unsigned int port)
869 {
870 return mv_hc_base(base, mv_hc_from_port(port));
871 }
872
873 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
874 {
875 return mv_hc_base_from_port(base, port) +
876 MV_SATAHC_ARBTR_REG_SZ +
877 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
878 }
879
880 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
881 {
882 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
883 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
884
885 return hc_mmio + ofs;
886 }
887
888 static inline void __iomem *mv_host_base(struct ata_host *host)
889 {
890 struct mv_host_priv *hpriv = host->private_data;
891 return hpriv->base;
892 }
893
894 static inline void __iomem *mv_ap_base(struct ata_port *ap)
895 {
896 return mv_port_base(mv_host_base(ap->host), ap->port_no);
897 }
898
899 static inline int mv_get_hc_count(unsigned long port_flags)
900 {
901 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
902 }
903
904 /**
905 * mv_save_cached_regs - (re-)initialize cached port registers
906 * @ap: the port whose registers we are caching
907 *
908 * Initialize the local cache of port registers,
909 * so that reading them over and over again can
910 * be avoided on the hotter paths of this driver.
911 * This saves a few microseconds each time we switch
912 * to/from EDMA mode to perform (eg.) a drive cache flush.
913 */
914 static void mv_save_cached_regs(struct ata_port *ap)
915 {
916 void __iomem *port_mmio = mv_ap_base(ap);
917 struct mv_port_priv *pp = ap->private_data;
918
919 pp->cached.fiscfg = readl(port_mmio + FISCFG);
920 pp->cached.ltmode = readl(port_mmio + LTMODE);
921 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
922 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
923 }
924
925 /**
926 * mv_write_cached_reg - write to a cached port register
927 * @addr: hardware address of the register
928 * @old: pointer to cached value of the register
929 * @new: new value for the register
930 *
931 * Write a new value to a cached register,
932 * but only if the value is different from before.
933 */
934 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
935 {
936 if (new != *old) {
937 unsigned long laddr;
938 *old = new;
939 /*
940 * Workaround for 88SX60x1-B2 FEr SATA#13:
941 * Read-after-write is needed to prevent generating 64-bit
942 * write cycles on the PCI bus for SATA interface registers
943 * at offsets ending in 0x4 or 0xc.
944 *
945 * Looks like a lot of fuss, but it avoids an unnecessary
946 * +1 usec read-after-write delay for unaffected registers.
947 */
948 laddr = (long)addr & 0xffff;
949 if (laddr >= 0x300 && laddr <= 0x33c) {
950 laddr &= 0x000f;
951 if (laddr == 0x4 || laddr == 0xc) {
952 writelfl(new, addr); /* read after write */
953 return;
954 }
955 }
956 writel(new, addr); /* unaffected by the errata */
957 }
958 }
959
960 static void mv_set_edma_ptrs(void __iomem *port_mmio,
961 struct mv_host_priv *hpriv,
962 struct mv_port_priv *pp)
963 {
964 u32 index;
965
966 /*
967 * initialize request queue
968 */
969 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
970 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
971
972 WARN_ON(pp->crqb_dma & 0x3ff);
973 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
974 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
975 port_mmio + EDMA_REQ_Q_IN_PTR);
976 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
977
978 /*
979 * initialize response queue
980 */
981 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
982 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
983
984 WARN_ON(pp->crpb_dma & 0xff);
985 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
986 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
987 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
988 port_mmio + EDMA_RSP_Q_OUT_PTR);
989 }
990
991 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
992 {
993 /*
994 * When writing to the main_irq_mask in hardware,
995 * we must ensure exclusivity between the interrupt coalescing bits
996 * and the corresponding individual port DONE_IRQ bits.
997 *
998 * Note that this register is really an "IRQ enable" register,
999 * not an "IRQ mask" register as Marvell's naming might suggest.
1000 */
1001 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1002 mask &= ~DONE_IRQ_0_3;
1003 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1004 mask &= ~DONE_IRQ_4_7;
1005 writelfl(mask, hpriv->main_irq_mask_addr);
1006 }
1007
1008 static void mv_set_main_irq_mask(struct ata_host *host,
1009 u32 disable_bits, u32 enable_bits)
1010 {
1011 struct mv_host_priv *hpriv = host->private_data;
1012 u32 old_mask, new_mask;
1013
1014 old_mask = hpriv->main_irq_mask;
1015 new_mask = (old_mask & ~disable_bits) | enable_bits;
1016 if (new_mask != old_mask) {
1017 hpriv->main_irq_mask = new_mask;
1018 mv_write_main_irq_mask(new_mask, hpriv);
1019 }
1020 }
1021
1022 static void mv_enable_port_irqs(struct ata_port *ap,
1023 unsigned int port_bits)
1024 {
1025 unsigned int shift, hardport, port = ap->port_no;
1026 u32 disable_bits, enable_bits;
1027
1028 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1029
1030 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1031 enable_bits = port_bits << shift;
1032 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1033 }
1034
1035 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1036 void __iomem *port_mmio,
1037 unsigned int port_irqs)
1038 {
1039 struct mv_host_priv *hpriv = ap->host->private_data;
1040 int hardport = mv_hardport_from_port(ap->port_no);
1041 void __iomem *hc_mmio = mv_hc_base_from_port(
1042 mv_host_base(ap->host), ap->port_no);
1043 u32 hc_irq_cause;
1044
1045 /* clear EDMA event indicators, if any */
1046 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1047
1048 /* clear pending irq events */
1049 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1050 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1051
1052 /* clear FIS IRQ Cause */
1053 if (IS_GEN_IIE(hpriv))
1054 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1055
1056 mv_enable_port_irqs(ap, port_irqs);
1057 }
1058
1059 static void mv_set_irq_coalescing(struct ata_host *host,
1060 unsigned int count, unsigned int usecs)
1061 {
1062 struct mv_host_priv *hpriv = host->private_data;
1063 void __iomem *mmio = hpriv->base, *hc_mmio;
1064 u32 coal_enable = 0;
1065 unsigned long flags;
1066 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1067 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1068 ALL_PORTS_COAL_DONE;
1069
1070 /* Disable IRQ coalescing if either threshold is zero */
1071 if (!usecs || !count) {
1072 clks = count = 0;
1073 } else {
1074 /* Respect maximum limits of the hardware */
1075 clks = usecs * COAL_CLOCKS_PER_USEC;
1076 if (clks > MAX_COAL_TIME_THRESHOLD)
1077 clks = MAX_COAL_TIME_THRESHOLD;
1078 if (count > MAX_COAL_IO_COUNT)
1079 count = MAX_COAL_IO_COUNT;
1080 }
1081
1082 spin_lock_irqsave(&host->lock, flags);
1083 mv_set_main_irq_mask(host, coal_disable, 0);
1084
1085 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1086 /*
1087 * GEN_II/GEN_IIE with dual host controllers:
1088 * one set of global thresholds for the entire chip.
1089 */
1090 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1091 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1092 /* clear leftover coal IRQ bit */
1093 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1094 if (count)
1095 coal_enable = ALL_PORTS_COAL_DONE;
1096 clks = count = 0; /* force clearing of regular regs below */
1097 }
1098
1099 /*
1100 * All chips: independent thresholds for each HC on the chip.
1101 */
1102 hc_mmio = mv_hc_base_from_port(mmio, 0);
1103 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1104 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1105 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1106 if (count)
1107 coal_enable |= PORTS_0_3_COAL_DONE;
1108 if (is_dual_hc) {
1109 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1110 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1111 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1112 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1113 if (count)
1114 coal_enable |= PORTS_4_7_COAL_DONE;
1115 }
1116
1117 mv_set_main_irq_mask(host, 0, coal_enable);
1118 spin_unlock_irqrestore(&host->lock, flags);
1119 }
1120
1121 /**
1122 * mv_start_edma - Enable eDMA engine
1123 * @base: port base address
1124 * @pp: port private data
1125 *
1126 * Verify the local cache of the eDMA state is accurate with a
1127 * WARN_ON.
1128 *
1129 * LOCKING:
1130 * Inherited from caller.
1131 */
1132 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1133 struct mv_port_priv *pp, u8 protocol)
1134 {
1135 int want_ncq = (protocol == ATA_PROT_NCQ);
1136
1137 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1138 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1139 if (want_ncq != using_ncq)
1140 mv_stop_edma(ap);
1141 }
1142 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1143 struct mv_host_priv *hpriv = ap->host->private_data;
1144
1145 mv_edma_cfg(ap, want_ncq, 1);
1146
1147 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1148 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1149
1150 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1151 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1152 }
1153 }
1154
1155 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1156 {
1157 void __iomem *port_mmio = mv_ap_base(ap);
1158 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1159 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1160 int i;
1161
1162 /*
1163 * Wait for the EDMA engine to finish transactions in progress.
1164 * No idea what a good "timeout" value might be, but measurements
1165 * indicate that it often requires hundreds of microseconds
1166 * with two drives in-use. So we use the 15msec value above
1167 * as a rough guess at what even more drives might require.
1168 */
1169 for (i = 0; i < timeout; ++i) {
1170 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1171 if ((edma_stat & empty_idle) == empty_idle)
1172 break;
1173 udelay(per_loop);
1174 }
1175 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1176 }
1177
1178 /**
1179 * mv_stop_edma_engine - Disable eDMA engine
1180 * @port_mmio: io base address
1181 *
1182 * LOCKING:
1183 * Inherited from caller.
1184 */
1185 static int mv_stop_edma_engine(void __iomem *port_mmio)
1186 {
1187 int i;
1188
1189 /* Disable eDMA. The disable bit auto clears. */
1190 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1191
1192 /* Wait for the chip to confirm eDMA is off. */
1193 for (i = 10000; i > 0; i--) {
1194 u32 reg = readl(port_mmio + EDMA_CMD);
1195 if (!(reg & EDMA_EN))
1196 return 0;
1197 udelay(10);
1198 }
1199 return -EIO;
1200 }
1201
1202 static int mv_stop_edma(struct ata_port *ap)
1203 {
1204 void __iomem *port_mmio = mv_ap_base(ap);
1205 struct mv_port_priv *pp = ap->private_data;
1206 int err = 0;
1207
1208 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1209 return 0;
1210 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1211 mv_wait_for_edma_empty_idle(ap);
1212 if (mv_stop_edma_engine(port_mmio)) {
1213 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1214 err = -EIO;
1215 }
1216 mv_edma_cfg(ap, 0, 0);
1217 return err;
1218 }
1219
1220 #ifdef ATA_DEBUG
1221 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1222 {
1223 int b, w;
1224 for (b = 0; b < bytes; ) {
1225 DPRINTK("%p: ", start + b);
1226 for (w = 0; b < bytes && w < 4; w++) {
1227 printk("%08x ", readl(start + b));
1228 b += sizeof(u32);
1229 }
1230 printk("\n");
1231 }
1232 }
1233 #endif
1234
1235 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1236 {
1237 #ifdef ATA_DEBUG
1238 int b, w;
1239 u32 dw;
1240 for (b = 0; b < bytes; ) {
1241 DPRINTK("%02x: ", b);
1242 for (w = 0; b < bytes && w < 4; w++) {
1243 (void) pci_read_config_dword(pdev, b, &dw);
1244 printk("%08x ", dw);
1245 b += sizeof(u32);
1246 }
1247 printk("\n");
1248 }
1249 #endif
1250 }
1251 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1252 struct pci_dev *pdev)
1253 {
1254 #ifdef ATA_DEBUG
1255 void __iomem *hc_base = mv_hc_base(mmio_base,
1256 port >> MV_PORT_HC_SHIFT);
1257 void __iomem *port_base;
1258 int start_port, num_ports, p, start_hc, num_hcs, hc;
1259
1260 if (0 > port) {
1261 start_hc = start_port = 0;
1262 num_ports = 8; /* shld be benign for 4 port devs */
1263 num_hcs = 2;
1264 } else {
1265 start_hc = port >> MV_PORT_HC_SHIFT;
1266 start_port = port;
1267 num_ports = num_hcs = 1;
1268 }
1269 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1270 num_ports > 1 ? num_ports - 1 : start_port);
1271
1272 if (NULL != pdev) {
1273 DPRINTK("PCI config space regs:\n");
1274 mv_dump_pci_cfg(pdev, 0x68);
1275 }
1276 DPRINTK("PCI regs:\n");
1277 mv_dump_mem(mmio_base+0xc00, 0x3c);
1278 mv_dump_mem(mmio_base+0xd00, 0x34);
1279 mv_dump_mem(mmio_base+0xf00, 0x4);
1280 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1281 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1282 hc_base = mv_hc_base(mmio_base, hc);
1283 DPRINTK("HC regs (HC %i):\n", hc);
1284 mv_dump_mem(hc_base, 0x1c);
1285 }
1286 for (p = start_port; p < start_port + num_ports; p++) {
1287 port_base = mv_port_base(mmio_base, p);
1288 DPRINTK("EDMA regs (port %i):\n", p);
1289 mv_dump_mem(port_base, 0x54);
1290 DPRINTK("SATA regs (port %i):\n", p);
1291 mv_dump_mem(port_base+0x300, 0x60);
1292 }
1293 #endif
1294 }
1295
1296 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1297 {
1298 unsigned int ofs;
1299
1300 switch (sc_reg_in) {
1301 case SCR_STATUS:
1302 case SCR_CONTROL:
1303 case SCR_ERROR:
1304 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1305 break;
1306 case SCR_ACTIVE:
1307 ofs = SATA_ACTIVE; /* active is not with the others */
1308 break;
1309 default:
1310 ofs = 0xffffffffU;
1311 break;
1312 }
1313 return ofs;
1314 }
1315
1316 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1317 {
1318 unsigned int ofs = mv_scr_offset(sc_reg_in);
1319
1320 if (ofs != 0xffffffffU) {
1321 *val = readl(mv_ap_base(link->ap) + ofs);
1322 return 0;
1323 } else
1324 return -EINVAL;
1325 }
1326
1327 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1328 {
1329 unsigned int ofs = mv_scr_offset(sc_reg_in);
1330
1331 if (ofs != 0xffffffffU) {
1332 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1333 if (sc_reg_in == SCR_CONTROL) {
1334 /*
1335 * Workaround for 88SX60x1 FEr SATA#26:
1336 *
1337 * COMRESETs have to take care not to accidently
1338 * put the drive to sleep when writing SCR_CONTROL.
1339 * Setting bits 12..15 prevents this problem.
1340 *
1341 * So if we see an outbound COMMRESET, set those bits.
1342 * Ditto for the followup write that clears the reset.
1343 *
1344 * The proprietary driver does this for
1345 * all chip versions, and so do we.
1346 */
1347 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1348 val |= 0xf000;
1349 }
1350 writelfl(val, addr);
1351 return 0;
1352 } else
1353 return -EINVAL;
1354 }
1355
1356 static void mv6_dev_config(struct ata_device *adev)
1357 {
1358 /*
1359 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1360 *
1361 * Gen-II does not support NCQ over a port multiplier
1362 * (no FIS-based switching).
1363 */
1364 if (adev->flags & ATA_DFLAG_NCQ) {
1365 if (sata_pmp_attached(adev->link->ap)) {
1366 adev->flags &= ~ATA_DFLAG_NCQ;
1367 ata_dev_printk(adev, KERN_INFO,
1368 "NCQ disabled for command-based switching\n");
1369 }
1370 }
1371 }
1372
1373 static int mv_qc_defer(struct ata_queued_cmd *qc)
1374 {
1375 struct ata_link *link = qc->dev->link;
1376 struct ata_port *ap = link->ap;
1377 struct mv_port_priv *pp = ap->private_data;
1378
1379 /*
1380 * Don't allow new commands if we're in a delayed EH state
1381 * for NCQ and/or FIS-based switching.
1382 */
1383 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1384 return ATA_DEFER_PORT;
1385 /*
1386 * If the port is completely idle, then allow the new qc.
1387 */
1388 if (ap->nr_active_links == 0)
1389 return 0;
1390
1391 /*
1392 * The port is operating in host queuing mode (EDMA) with NCQ
1393 * enabled, allow multiple NCQ commands. EDMA also allows
1394 * queueing multiple DMA commands but libata core currently
1395 * doesn't allow it.
1396 */
1397 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1398 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1399 return 0;
1400
1401 return ATA_DEFER_PORT;
1402 }
1403
1404 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1405 {
1406 struct mv_port_priv *pp = ap->private_data;
1407 void __iomem *port_mmio;
1408
1409 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1410 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1411 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1412
1413 ltmode = *old_ltmode & ~LTMODE_BIT8;
1414 haltcond = *old_haltcond | EDMA_ERR_DEV;
1415
1416 if (want_fbs) {
1417 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1418 ltmode = *old_ltmode | LTMODE_BIT8;
1419 if (want_ncq)
1420 haltcond &= ~EDMA_ERR_DEV;
1421 else
1422 fiscfg |= FISCFG_WAIT_DEV_ERR;
1423 } else {
1424 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1425 }
1426
1427 port_mmio = mv_ap_base(ap);
1428 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1429 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1430 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1431 }
1432
1433 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1434 {
1435 struct mv_host_priv *hpriv = ap->host->private_data;
1436 u32 old, new;
1437
1438 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1439 old = readl(hpriv->base + GPIO_PORT_CTL);
1440 if (want_ncq)
1441 new = old | (1 << 22);
1442 else
1443 new = old & ~(1 << 22);
1444 if (new != old)
1445 writel(new, hpriv->base + GPIO_PORT_CTL);
1446 }
1447
1448 /**
1449 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1450 * @ap: Port being initialized
1451 *
1452 * There are two DMA modes on these chips: basic DMA, and EDMA.
1453 *
1454 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1455 * of basic DMA on the GEN_IIE versions of the chips.
1456 *
1457 * This bit survives EDMA resets, and must be set for basic DMA
1458 * to function, and should be cleared when EDMA is active.
1459 */
1460 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1461 {
1462 struct mv_port_priv *pp = ap->private_data;
1463 u32 new, *old = &pp->cached.unknown_rsvd;
1464
1465 if (enable_bmdma)
1466 new = *old | 1;
1467 else
1468 new = *old & ~1;
1469 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1470 }
1471
1472 /*
1473 * SOC chips have an issue whereby the HDD LEDs don't always blink
1474 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1475 * of the SOC takes care of it, generating a steady blink rate when
1476 * any drive on the chip is active.
1477 *
1478 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1479 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1480 *
1481 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1482 * LED operation works then, and provides better (more accurate) feedback.
1483 *
1484 * Note that this code assumes that an SOC never has more than one HC onboard.
1485 */
1486 static void mv_soc_led_blink_enable(struct ata_port *ap)
1487 {
1488 struct ata_host *host = ap->host;
1489 struct mv_host_priv *hpriv = host->private_data;
1490 void __iomem *hc_mmio;
1491 u32 led_ctrl;
1492
1493 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1494 return;
1495 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1496 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1497 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1498 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1499 }
1500
1501 static void mv_soc_led_blink_disable(struct ata_port *ap)
1502 {
1503 struct ata_host *host = ap->host;
1504 struct mv_host_priv *hpriv = host->private_data;
1505 void __iomem *hc_mmio;
1506 u32 led_ctrl;
1507 unsigned int port;
1508
1509 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1510 return;
1511
1512 /* disable led-blink only if no ports are using NCQ */
1513 for (port = 0; port < hpriv->n_ports; port++) {
1514 struct ata_port *this_ap = host->ports[port];
1515 struct mv_port_priv *pp = this_ap->private_data;
1516
1517 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1518 return;
1519 }
1520
1521 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1522 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1523 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1524 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1525 }
1526
1527 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1528 {
1529 u32 cfg;
1530 struct mv_port_priv *pp = ap->private_data;
1531 struct mv_host_priv *hpriv = ap->host->private_data;
1532 void __iomem *port_mmio = mv_ap_base(ap);
1533
1534 /* set up non-NCQ EDMA configuration */
1535 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1536 pp->pp_flags &=
1537 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1538
1539 if (IS_GEN_I(hpriv))
1540 cfg |= (1 << 8); /* enab config burst size mask */
1541
1542 else if (IS_GEN_II(hpriv)) {
1543 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1544 mv_60x1_errata_sata25(ap, want_ncq);
1545
1546 } else if (IS_GEN_IIE(hpriv)) {
1547 int want_fbs = sata_pmp_attached(ap);
1548 /*
1549 * Possible future enhancement:
1550 *
1551 * The chip can use FBS with non-NCQ, if we allow it,
1552 * But first we need to have the error handling in place
1553 * for this mode (datasheet section 7.3.15.4.2.3).
1554 * So disallow non-NCQ FBS for now.
1555 */
1556 want_fbs &= want_ncq;
1557
1558 mv_config_fbs(ap, want_ncq, want_fbs);
1559
1560 if (want_fbs) {
1561 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1562 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1563 }
1564
1565 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1566 if (want_edma) {
1567 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1568 if (!IS_SOC(hpriv))
1569 cfg |= (1 << 18); /* enab early completion */
1570 }
1571 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1572 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1573 mv_bmdma_enable_iie(ap, !want_edma);
1574
1575 if (IS_SOC(hpriv)) {
1576 if (want_ncq)
1577 mv_soc_led_blink_enable(ap);
1578 else
1579 mv_soc_led_blink_disable(ap);
1580 }
1581 }
1582
1583 if (want_ncq) {
1584 cfg |= EDMA_CFG_NCQ;
1585 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1586 }
1587
1588 writelfl(cfg, port_mmio + EDMA_CFG);
1589 }
1590
1591 static void mv_port_free_dma_mem(struct ata_port *ap)
1592 {
1593 struct mv_host_priv *hpriv = ap->host->private_data;
1594 struct mv_port_priv *pp = ap->private_data;
1595 int tag;
1596
1597 if (pp->crqb) {
1598 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1599 pp->crqb = NULL;
1600 }
1601 if (pp->crpb) {
1602 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1603 pp->crpb = NULL;
1604 }
1605 /*
1606 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1607 * For later hardware, we have one unique sg_tbl per NCQ tag.
1608 */
1609 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1610 if (pp->sg_tbl[tag]) {
1611 if (tag == 0 || !IS_GEN_I(hpriv))
1612 dma_pool_free(hpriv->sg_tbl_pool,
1613 pp->sg_tbl[tag],
1614 pp->sg_tbl_dma[tag]);
1615 pp->sg_tbl[tag] = NULL;
1616 }
1617 }
1618 }
1619
1620 /**
1621 * mv_port_start - Port specific init/start routine.
1622 * @ap: ATA channel to manipulate
1623 *
1624 * Allocate and point to DMA memory, init port private memory,
1625 * zero indices.
1626 *
1627 * LOCKING:
1628 * Inherited from caller.
1629 */
1630 static int mv_port_start(struct ata_port *ap)
1631 {
1632 struct device *dev = ap->host->dev;
1633 struct mv_host_priv *hpriv = ap->host->private_data;
1634 struct mv_port_priv *pp;
1635 unsigned long flags;
1636 int tag;
1637
1638 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1639 if (!pp)
1640 return -ENOMEM;
1641 ap->private_data = pp;
1642
1643 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1644 if (!pp->crqb)
1645 return -ENOMEM;
1646 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1647
1648 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1649 if (!pp->crpb)
1650 goto out_port_free_dma_mem;
1651 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1652
1653 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1654 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1655 ap->flags |= ATA_FLAG_AN;
1656 /*
1657 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1658 * For later hardware, we need one unique sg_tbl per NCQ tag.
1659 */
1660 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1661 if (tag == 0 || !IS_GEN_I(hpriv)) {
1662 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1663 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1664 if (!pp->sg_tbl[tag])
1665 goto out_port_free_dma_mem;
1666 } else {
1667 pp->sg_tbl[tag] = pp->sg_tbl[0];
1668 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1669 }
1670 }
1671
1672 spin_lock_irqsave(ap->lock, flags);
1673 mv_save_cached_regs(ap);
1674 mv_edma_cfg(ap, 0, 0);
1675 spin_unlock_irqrestore(ap->lock, flags);
1676
1677 return 0;
1678
1679 out_port_free_dma_mem:
1680 mv_port_free_dma_mem(ap);
1681 return -ENOMEM;
1682 }
1683
1684 /**
1685 * mv_port_stop - Port specific cleanup/stop routine.
1686 * @ap: ATA channel to manipulate
1687 *
1688 * Stop DMA, cleanup port memory.
1689 *
1690 * LOCKING:
1691 * This routine uses the host lock to protect the DMA stop.
1692 */
1693 static void mv_port_stop(struct ata_port *ap)
1694 {
1695 unsigned long flags;
1696
1697 spin_lock_irqsave(ap->lock, flags);
1698 mv_stop_edma(ap);
1699 mv_enable_port_irqs(ap, 0);
1700 spin_unlock_irqrestore(ap->lock, flags);
1701 mv_port_free_dma_mem(ap);
1702 }
1703
1704 /**
1705 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1706 * @qc: queued command whose SG list to source from
1707 *
1708 * Populate the SG list and mark the last entry.
1709 *
1710 * LOCKING:
1711 * Inherited from caller.
1712 */
1713 static void mv_fill_sg(struct ata_queued_cmd *qc)
1714 {
1715 struct mv_port_priv *pp = qc->ap->private_data;
1716 struct scatterlist *sg;
1717 struct mv_sg *mv_sg, *last_sg = NULL;
1718 unsigned int si;
1719
1720 mv_sg = pp->sg_tbl[qc->tag];
1721 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1722 dma_addr_t addr = sg_dma_address(sg);
1723 u32 sg_len = sg_dma_len(sg);
1724
1725 while (sg_len) {
1726 u32 offset = addr & 0xffff;
1727 u32 len = sg_len;
1728
1729 if (offset + len > 0x10000)
1730 len = 0x10000 - offset;
1731
1732 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1733 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1734 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1735 mv_sg->reserved = 0;
1736
1737 sg_len -= len;
1738 addr += len;
1739
1740 last_sg = mv_sg;
1741 mv_sg++;
1742 }
1743 }
1744
1745 if (likely(last_sg))
1746 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1747 mb(); /* ensure data structure is visible to the chipset */
1748 }
1749
1750 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1751 {
1752 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1753 (last ? CRQB_CMD_LAST : 0);
1754 *cmdw = cpu_to_le16(tmp);
1755 }
1756
1757 /**
1758 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1759 * @ap: Port associated with this ATA transaction.
1760 *
1761 * We need this only for ATAPI bmdma transactions,
1762 * as otherwise we experience spurious interrupts
1763 * after libata-sff handles the bmdma interrupts.
1764 */
1765 static void mv_sff_irq_clear(struct ata_port *ap)
1766 {
1767 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1768 }
1769
1770 /**
1771 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1772 * @qc: queued command to check for chipset/DMA compatibility.
1773 *
1774 * The bmdma engines cannot handle speculative data sizes
1775 * (bytecount under/over flow). So only allow DMA for
1776 * data transfer commands with known data sizes.
1777 *
1778 * LOCKING:
1779 * Inherited from caller.
1780 */
1781 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1782 {
1783 struct scsi_cmnd *scmd = qc->scsicmd;
1784
1785 if (scmd) {
1786 switch (scmd->cmnd[0]) {
1787 case READ_6:
1788 case READ_10:
1789 case READ_12:
1790 case WRITE_6:
1791 case WRITE_10:
1792 case WRITE_12:
1793 case GPCMD_READ_CD:
1794 case GPCMD_SEND_DVD_STRUCTURE:
1795 case GPCMD_SEND_CUE_SHEET:
1796 return 0; /* DMA is safe */
1797 }
1798 }
1799 return -EOPNOTSUPP; /* use PIO instead */
1800 }
1801
1802 /**
1803 * mv_bmdma_setup - Set up BMDMA transaction
1804 * @qc: queued command to prepare DMA for.
1805 *
1806 * LOCKING:
1807 * Inherited from caller.
1808 */
1809 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1810 {
1811 struct ata_port *ap = qc->ap;
1812 void __iomem *port_mmio = mv_ap_base(ap);
1813 struct mv_port_priv *pp = ap->private_data;
1814
1815 mv_fill_sg(qc);
1816
1817 /* clear all DMA cmd bits */
1818 writel(0, port_mmio + BMDMA_CMD);
1819
1820 /* load PRD table addr. */
1821 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1822 port_mmio + BMDMA_PRD_HIGH);
1823 writelfl(pp->sg_tbl_dma[qc->tag],
1824 port_mmio + BMDMA_PRD_LOW);
1825
1826 /* issue r/w command */
1827 ap->ops->sff_exec_command(ap, &qc->tf);
1828 }
1829
1830 /**
1831 * mv_bmdma_start - Start a BMDMA transaction
1832 * @qc: queued command to start DMA on.
1833 *
1834 * LOCKING:
1835 * Inherited from caller.
1836 */
1837 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1838 {
1839 struct ata_port *ap = qc->ap;
1840 void __iomem *port_mmio = mv_ap_base(ap);
1841 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1842 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1843
1844 /* start host DMA transaction */
1845 writelfl(cmd, port_mmio + BMDMA_CMD);
1846 }
1847
1848 /**
1849 * mv_bmdma_stop - Stop BMDMA transfer
1850 * @qc: queued command to stop DMA on.
1851 *
1852 * Clears the ATA_DMA_START flag in the bmdma control register
1853 *
1854 * LOCKING:
1855 * Inherited from caller.
1856 */
1857 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1858 {
1859 struct ata_port *ap = qc->ap;
1860 void __iomem *port_mmio = mv_ap_base(ap);
1861 u32 cmd;
1862
1863 /* clear start/stop bit */
1864 cmd = readl(port_mmio + BMDMA_CMD);
1865 cmd &= ~ATA_DMA_START;
1866 writelfl(cmd, port_mmio + BMDMA_CMD);
1867
1868 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1869 ata_sff_dma_pause(ap);
1870 }
1871
1872 /**
1873 * mv_bmdma_status - Read BMDMA status
1874 * @ap: port for which to retrieve DMA status.
1875 *
1876 * Read and return equivalent of the sff BMDMA status register.
1877 *
1878 * LOCKING:
1879 * Inherited from caller.
1880 */
1881 static u8 mv_bmdma_status(struct ata_port *ap)
1882 {
1883 void __iomem *port_mmio = mv_ap_base(ap);
1884 u32 reg, status;
1885
1886 /*
1887 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1888 * and the ATA_DMA_INTR bit doesn't exist.
1889 */
1890 reg = readl(port_mmio + BMDMA_STATUS);
1891 if (reg & ATA_DMA_ACTIVE)
1892 status = ATA_DMA_ACTIVE;
1893 else
1894 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1895 return status;
1896 }
1897
1898 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1899 {
1900 struct ata_taskfile *tf = &qc->tf;
1901 /*
1902 * Workaround for 88SX60x1 FEr SATA#24.
1903 *
1904 * Chip may corrupt WRITEs if multi_count >= 4kB.
1905 * Note that READs are unaffected.
1906 *
1907 * It's not clear if this errata really means "4K bytes",
1908 * or if it always happens for multi_count > 7
1909 * regardless of device sector_size.
1910 *
1911 * So, for safety, any write with multi_count > 7
1912 * gets converted here into a regular PIO write instead:
1913 */
1914 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1915 if (qc->dev->multi_count > 7) {
1916 switch (tf->command) {
1917 case ATA_CMD_WRITE_MULTI:
1918 tf->command = ATA_CMD_PIO_WRITE;
1919 break;
1920 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1921 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1922 /* fall through */
1923 case ATA_CMD_WRITE_MULTI_EXT:
1924 tf->command = ATA_CMD_PIO_WRITE_EXT;
1925 break;
1926 }
1927 }
1928 }
1929 }
1930
1931 /**
1932 * mv_qc_prep - Host specific command preparation.
1933 * @qc: queued command to prepare
1934 *
1935 * This routine simply redirects to the general purpose routine
1936 * if command is not DMA. Else, it handles prep of the CRQB
1937 * (command request block), does some sanity checking, and calls
1938 * the SG load routine.
1939 *
1940 * LOCKING:
1941 * Inherited from caller.
1942 */
1943 static void mv_qc_prep(struct ata_queued_cmd *qc)
1944 {
1945 struct ata_port *ap = qc->ap;
1946 struct mv_port_priv *pp = ap->private_data;
1947 __le16 *cw;
1948 struct ata_taskfile *tf = &qc->tf;
1949 u16 flags = 0;
1950 unsigned in_index;
1951
1952 switch (tf->protocol) {
1953 case ATA_PROT_DMA:
1954 case ATA_PROT_NCQ:
1955 break; /* continue below */
1956 case ATA_PROT_PIO:
1957 mv_rw_multi_errata_sata24(qc);
1958 return;
1959 default:
1960 return;
1961 }
1962
1963 /* Fill in command request block
1964 */
1965 if (!(tf->flags & ATA_TFLAG_WRITE))
1966 flags |= CRQB_FLAG_READ;
1967 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1968 flags |= qc->tag << CRQB_TAG_SHIFT;
1969 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1970
1971 /* get current queue index from software */
1972 in_index = pp->req_idx;
1973
1974 pp->crqb[in_index].sg_addr =
1975 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1976 pp->crqb[in_index].sg_addr_hi =
1977 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1978 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1979
1980 cw = &pp->crqb[in_index].ata_cmd[0];
1981
1982 /* Sadly, the CRQB cannot accomodate all registers--there are
1983 * only 11 bytes...so we must pick and choose required
1984 * registers based on the command. So, we drop feature and
1985 * hob_feature for [RW] DMA commands, but they are needed for
1986 * NCQ. NCQ will drop hob_nsect, which is not needed there
1987 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1988 */
1989 switch (tf->command) {
1990 case ATA_CMD_READ:
1991 case ATA_CMD_READ_EXT:
1992 case ATA_CMD_WRITE:
1993 case ATA_CMD_WRITE_EXT:
1994 case ATA_CMD_WRITE_FUA_EXT:
1995 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1996 break;
1997 case ATA_CMD_FPDMA_READ:
1998 case ATA_CMD_FPDMA_WRITE:
1999 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2000 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2001 break;
2002 default:
2003 /* The only other commands EDMA supports in non-queued and
2004 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2005 * of which are defined/used by Linux. If we get here, this
2006 * driver needs work.
2007 *
2008 * FIXME: modify libata to give qc_prep a return value and
2009 * return error here.
2010 */
2011 BUG_ON(tf->command);
2012 break;
2013 }
2014 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2015 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2016 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2017 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2018 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2019 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2020 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2021 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2022 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2023
2024 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2025 return;
2026 mv_fill_sg(qc);
2027 }
2028
2029 /**
2030 * mv_qc_prep_iie - Host specific command preparation.
2031 * @qc: queued command to prepare
2032 *
2033 * This routine simply redirects to the general purpose routine
2034 * if command is not DMA. Else, it handles prep of the CRQB
2035 * (command request block), does some sanity checking, and calls
2036 * the SG load routine.
2037 *
2038 * LOCKING:
2039 * Inherited from caller.
2040 */
2041 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2042 {
2043 struct ata_port *ap = qc->ap;
2044 struct mv_port_priv *pp = ap->private_data;
2045 struct mv_crqb_iie *crqb;
2046 struct ata_taskfile *tf = &qc->tf;
2047 unsigned in_index;
2048 u32 flags = 0;
2049
2050 if ((tf->protocol != ATA_PROT_DMA) &&
2051 (tf->protocol != ATA_PROT_NCQ))
2052 return;
2053
2054 /* Fill in Gen IIE command request block */
2055 if (!(tf->flags & ATA_TFLAG_WRITE))
2056 flags |= CRQB_FLAG_READ;
2057
2058 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2059 flags |= qc->tag << CRQB_TAG_SHIFT;
2060 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2061 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2062
2063 /* get current queue index from software */
2064 in_index = pp->req_idx;
2065
2066 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2067 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2068 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2069 crqb->flags = cpu_to_le32(flags);
2070
2071 crqb->ata_cmd[0] = cpu_to_le32(
2072 (tf->command << 16) |
2073 (tf->feature << 24)
2074 );
2075 crqb->ata_cmd[1] = cpu_to_le32(
2076 (tf->lbal << 0) |
2077 (tf->lbam << 8) |
2078 (tf->lbah << 16) |
2079 (tf->device << 24)
2080 );
2081 crqb->ata_cmd[2] = cpu_to_le32(
2082 (tf->hob_lbal << 0) |
2083 (tf->hob_lbam << 8) |
2084 (tf->hob_lbah << 16) |
2085 (tf->hob_feature << 24)
2086 );
2087 crqb->ata_cmd[3] = cpu_to_le32(
2088 (tf->nsect << 0) |
2089 (tf->hob_nsect << 8)
2090 );
2091
2092 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2093 return;
2094 mv_fill_sg(qc);
2095 }
2096
2097 /**
2098 * mv_sff_check_status - fetch device status, if valid
2099 * @ap: ATA port to fetch status from
2100 *
2101 * When using command issue via mv_qc_issue_fis(),
2102 * the initial ATA_BUSY state does not show up in the
2103 * ATA status (shadow) register. This can confuse libata!
2104 *
2105 * So we have a hook here to fake ATA_BUSY for that situation,
2106 * until the first time a BUSY, DRQ, or ERR bit is seen.
2107 *
2108 * The rest of the time, it simply returns the ATA status register.
2109 */
2110 static u8 mv_sff_check_status(struct ata_port *ap)
2111 {
2112 u8 stat = ioread8(ap->ioaddr.status_addr);
2113 struct mv_port_priv *pp = ap->private_data;
2114
2115 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2116 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2117 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2118 else
2119 stat = ATA_BUSY;
2120 }
2121 return stat;
2122 }
2123
2124 /**
2125 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2126 * @fis: fis to be sent
2127 * @nwords: number of 32-bit words in the fis
2128 */
2129 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2130 {
2131 void __iomem *port_mmio = mv_ap_base(ap);
2132 u32 ifctl, old_ifctl, ifstat;
2133 int i, timeout = 200, final_word = nwords - 1;
2134
2135 /* Initiate FIS transmission mode */
2136 old_ifctl = readl(port_mmio + SATA_IFCTL);
2137 ifctl = 0x100 | (old_ifctl & 0xf);
2138 writelfl(ifctl, port_mmio + SATA_IFCTL);
2139
2140 /* Send all words of the FIS except for the final word */
2141 for (i = 0; i < final_word; ++i)
2142 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2143
2144 /* Flag end-of-transmission, and then send the final word */
2145 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2146 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2147
2148 /*
2149 * Wait for FIS transmission to complete.
2150 * This typically takes just a single iteration.
2151 */
2152 do {
2153 ifstat = readl(port_mmio + SATA_IFSTAT);
2154 } while (!(ifstat & 0x1000) && --timeout);
2155
2156 /* Restore original port configuration */
2157 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2158
2159 /* See if it worked */
2160 if ((ifstat & 0x3000) != 0x1000) {
2161 ata_port_printk(ap, KERN_WARNING,
2162 "%s transmission error, ifstat=%08x\n",
2163 __func__, ifstat);
2164 return AC_ERR_OTHER;
2165 }
2166 return 0;
2167 }
2168
2169 /**
2170 * mv_qc_issue_fis - Issue a command directly as a FIS
2171 * @qc: queued command to start
2172 *
2173 * Note that the ATA shadow registers are not updated
2174 * after command issue, so the device will appear "READY"
2175 * if polled, even while it is BUSY processing the command.
2176 *
2177 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2178 *
2179 * Note: we don't get updated shadow regs on *completion*
2180 * of non-data commands. So avoid sending them via this function,
2181 * as they will appear to have completed immediately.
2182 *
2183 * GEN_IIE has special registers that we could get the result tf from,
2184 * but earlier chipsets do not. For now, we ignore those registers.
2185 */
2186 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2187 {
2188 struct ata_port *ap = qc->ap;
2189 struct mv_port_priv *pp = ap->private_data;
2190 struct ata_link *link = qc->dev->link;
2191 u32 fis[5];
2192 int err = 0;
2193
2194 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2195 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2196 if (err)
2197 return err;
2198
2199 switch (qc->tf.protocol) {
2200 case ATAPI_PROT_PIO:
2201 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2202 /* fall through */
2203 case ATAPI_PROT_NODATA:
2204 ap->hsm_task_state = HSM_ST_FIRST;
2205 break;
2206 case ATA_PROT_PIO:
2207 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2208 if (qc->tf.flags & ATA_TFLAG_WRITE)
2209 ap->hsm_task_state = HSM_ST_FIRST;
2210 else
2211 ap->hsm_task_state = HSM_ST;
2212 break;
2213 default:
2214 ap->hsm_task_state = HSM_ST_LAST;
2215 break;
2216 }
2217
2218 if (qc->tf.flags & ATA_TFLAG_POLLING)
2219 ata_pio_queue_task(ap, qc, 0);
2220 return 0;
2221 }
2222
2223 /**
2224 * mv_qc_issue - Initiate a command to the host
2225 * @qc: queued command to start
2226 *
2227 * This routine simply redirects to the general purpose routine
2228 * if command is not DMA. Else, it sanity checks our local
2229 * caches of the request producer/consumer indices then enables
2230 * DMA and bumps the request producer index.
2231 *
2232 * LOCKING:
2233 * Inherited from caller.
2234 */
2235 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2236 {
2237 static int limit_warnings = 10;
2238 struct ata_port *ap = qc->ap;
2239 void __iomem *port_mmio = mv_ap_base(ap);
2240 struct mv_port_priv *pp = ap->private_data;
2241 u32 in_index;
2242 unsigned int port_irqs;
2243
2244 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2245
2246 switch (qc->tf.protocol) {
2247 case ATA_PROT_DMA:
2248 case ATA_PROT_NCQ:
2249 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2250 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2251 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2252
2253 /* Write the request in pointer to kick the EDMA to life */
2254 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2255 port_mmio + EDMA_REQ_Q_IN_PTR);
2256 return 0;
2257
2258 case ATA_PROT_PIO:
2259 /*
2260 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2261 *
2262 * Someday, we might implement special polling workarounds
2263 * for these, but it all seems rather unnecessary since we
2264 * normally use only DMA for commands which transfer more
2265 * than a single block of data.
2266 *
2267 * Much of the time, this could just work regardless.
2268 * So for now, just log the incident, and allow the attempt.
2269 */
2270 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2271 --limit_warnings;
2272 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2273 ": attempting PIO w/multiple DRQ: "
2274 "this may fail due to h/w errata\n");
2275 }
2276 /* drop through */
2277 case ATA_PROT_NODATA:
2278 case ATAPI_PROT_PIO:
2279 case ATAPI_PROT_NODATA:
2280 if (ap->flags & ATA_FLAG_PIO_POLLING)
2281 qc->tf.flags |= ATA_TFLAG_POLLING;
2282 break;
2283 }
2284
2285 if (qc->tf.flags & ATA_TFLAG_POLLING)
2286 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2287 else
2288 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2289
2290 /*
2291 * We're about to send a non-EDMA capable command to the
2292 * port. Turn off EDMA so there won't be problems accessing
2293 * shadow block, etc registers.
2294 */
2295 mv_stop_edma(ap);
2296 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2297 mv_pmp_select(ap, qc->dev->link->pmp);
2298
2299 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2300 struct mv_host_priv *hpriv = ap->host->private_data;
2301 /*
2302 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2303 *
2304 * After any NCQ error, the READ_LOG_EXT command
2305 * from libata-eh *must* use mv_qc_issue_fis().
2306 * Otherwise it might fail, due to chip errata.
2307 *
2308 * Rather than special-case it, we'll just *always*
2309 * use this method here for READ_LOG_EXT, making for
2310 * easier testing.
2311 */
2312 if (IS_GEN_II(hpriv))
2313 return mv_qc_issue_fis(qc);
2314 }
2315 return ata_sff_qc_issue(qc);
2316 }
2317
2318 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2319 {
2320 struct mv_port_priv *pp = ap->private_data;
2321 struct ata_queued_cmd *qc;
2322
2323 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2324 return NULL;
2325 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2326 if (qc) {
2327 if (qc->tf.flags & ATA_TFLAG_POLLING)
2328 qc = NULL;
2329 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2330 qc = NULL;
2331 }
2332 return qc;
2333 }
2334
2335 static void mv_pmp_error_handler(struct ata_port *ap)
2336 {
2337 unsigned int pmp, pmp_map;
2338 struct mv_port_priv *pp = ap->private_data;
2339
2340 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2341 /*
2342 * Perform NCQ error analysis on failed PMPs
2343 * before we freeze the port entirely.
2344 *
2345 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2346 */
2347 pmp_map = pp->delayed_eh_pmp_map;
2348 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2349 for (pmp = 0; pmp_map != 0; pmp++) {
2350 unsigned int this_pmp = (1 << pmp);
2351 if (pmp_map & this_pmp) {
2352 struct ata_link *link = &ap->pmp_link[pmp];
2353 pmp_map &= ~this_pmp;
2354 ata_eh_analyze_ncq_error(link);
2355 }
2356 }
2357 ata_port_freeze(ap);
2358 }
2359 sata_pmp_error_handler(ap);
2360 }
2361
2362 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2363 {
2364 void __iomem *port_mmio = mv_ap_base(ap);
2365
2366 return readl(port_mmio + SATA_TESTCTL) >> 16;
2367 }
2368
2369 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2370 {
2371 struct ata_eh_info *ehi;
2372 unsigned int pmp;
2373
2374 /*
2375 * Initialize EH info for PMPs which saw device errors
2376 */
2377 ehi = &ap->link.eh_info;
2378 for (pmp = 0; pmp_map != 0; pmp++) {
2379 unsigned int this_pmp = (1 << pmp);
2380 if (pmp_map & this_pmp) {
2381 struct ata_link *link = &ap->pmp_link[pmp];
2382
2383 pmp_map &= ~this_pmp;
2384 ehi = &link->eh_info;
2385 ata_ehi_clear_desc(ehi);
2386 ata_ehi_push_desc(ehi, "dev err");
2387 ehi->err_mask |= AC_ERR_DEV;
2388 ehi->action |= ATA_EH_RESET;
2389 ata_link_abort(link);
2390 }
2391 }
2392 }
2393
2394 static int mv_req_q_empty(struct ata_port *ap)
2395 {
2396 void __iomem *port_mmio = mv_ap_base(ap);
2397 u32 in_ptr, out_ptr;
2398
2399 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2400 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2401 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2402 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2403 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2404 }
2405
2406 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2407 {
2408 struct mv_port_priv *pp = ap->private_data;
2409 int failed_links;
2410 unsigned int old_map, new_map;
2411
2412 /*
2413 * Device error during FBS+NCQ operation:
2414 *
2415 * Set a port flag to prevent further I/O being enqueued.
2416 * Leave the EDMA running to drain outstanding commands from this port.
2417 * Perform the post-mortem/EH only when all responses are complete.
2418 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2419 */
2420 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2421 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2422 pp->delayed_eh_pmp_map = 0;
2423 }
2424 old_map = pp->delayed_eh_pmp_map;
2425 new_map = old_map | mv_get_err_pmp_map(ap);
2426
2427 if (old_map != new_map) {
2428 pp->delayed_eh_pmp_map = new_map;
2429 mv_pmp_eh_prep(ap, new_map & ~old_map);
2430 }
2431 failed_links = hweight16(new_map);
2432
2433 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2434 "failed_links=%d nr_active_links=%d\n",
2435 __func__, pp->delayed_eh_pmp_map,
2436 ap->qc_active, failed_links,
2437 ap->nr_active_links);
2438
2439 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2440 mv_process_crpb_entries(ap, pp);
2441 mv_stop_edma(ap);
2442 mv_eh_freeze(ap);
2443 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2444 return 1; /* handled */
2445 }
2446 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2447 return 1; /* handled */
2448 }
2449
2450 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2451 {
2452 /*
2453 * Possible future enhancement:
2454 *
2455 * FBS+non-NCQ operation is not yet implemented.
2456 * See related notes in mv_edma_cfg().
2457 *
2458 * Device error during FBS+non-NCQ operation:
2459 *
2460 * We need to snapshot the shadow registers for each failed command.
2461 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2462 */
2463 return 0; /* not handled */
2464 }
2465
2466 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2467 {
2468 struct mv_port_priv *pp = ap->private_data;
2469
2470 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2471 return 0; /* EDMA was not active: not handled */
2472 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2473 return 0; /* FBS was not active: not handled */
2474
2475 if (!(edma_err_cause & EDMA_ERR_DEV))
2476 return 0; /* non DEV error: not handled */
2477 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2478 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2479 return 0; /* other problems: not handled */
2480
2481 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2482 /*
2483 * EDMA should NOT have self-disabled for this case.
2484 * If it did, then something is wrong elsewhere,
2485 * and we cannot handle it here.
2486 */
2487 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2488 ata_port_printk(ap, KERN_WARNING,
2489 "%s: err_cause=0x%x pp_flags=0x%x\n",
2490 __func__, edma_err_cause, pp->pp_flags);
2491 return 0; /* not handled */
2492 }
2493 return mv_handle_fbs_ncq_dev_err(ap);
2494 } else {
2495 /*
2496 * EDMA should have self-disabled for this case.
2497 * If it did not, then something is wrong elsewhere,
2498 * and we cannot handle it here.
2499 */
2500 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2501 ata_port_printk(ap, KERN_WARNING,
2502 "%s: err_cause=0x%x pp_flags=0x%x\n",
2503 __func__, edma_err_cause, pp->pp_flags);
2504 return 0; /* not handled */
2505 }
2506 return mv_handle_fbs_non_ncq_dev_err(ap);
2507 }
2508 return 0; /* not handled */
2509 }
2510
2511 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2512 {
2513 struct ata_eh_info *ehi = &ap->link.eh_info;
2514 char *when = "idle";
2515
2516 ata_ehi_clear_desc(ehi);
2517 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2518 when = "disabled";
2519 } else if (edma_was_enabled) {
2520 when = "EDMA enabled";
2521 } else {
2522 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2523 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2524 when = "polling";
2525 }
2526 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2527 ehi->err_mask |= AC_ERR_OTHER;
2528 ehi->action |= ATA_EH_RESET;
2529 ata_port_freeze(ap);
2530 }
2531
2532 /**
2533 * mv_err_intr - Handle error interrupts on the port
2534 * @ap: ATA channel to manipulate
2535 *
2536 * Most cases require a full reset of the chip's state machine,
2537 * which also performs a COMRESET.
2538 * Also, if the port disabled DMA, update our cached copy to match.
2539 *
2540 * LOCKING:
2541 * Inherited from caller.
2542 */
2543 static void mv_err_intr(struct ata_port *ap)
2544 {
2545 void __iomem *port_mmio = mv_ap_base(ap);
2546 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2547 u32 fis_cause = 0;
2548 struct mv_port_priv *pp = ap->private_data;
2549 struct mv_host_priv *hpriv = ap->host->private_data;
2550 unsigned int action = 0, err_mask = 0;
2551 struct ata_eh_info *ehi = &ap->link.eh_info;
2552 struct ata_queued_cmd *qc;
2553 int abort = 0;
2554
2555 /*
2556 * Read and clear the SError and err_cause bits.
2557 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2558 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2559 */
2560 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2561 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2562
2563 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2564 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2565 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2566 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2567 }
2568 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2569
2570 if (edma_err_cause & EDMA_ERR_DEV) {
2571 /*
2572 * Device errors during FIS-based switching operation
2573 * require special handling.
2574 */
2575 if (mv_handle_dev_err(ap, edma_err_cause))
2576 return;
2577 }
2578
2579 qc = mv_get_active_qc(ap);
2580 ata_ehi_clear_desc(ehi);
2581 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2582 edma_err_cause, pp->pp_flags);
2583
2584 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2585 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2586 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2587 u32 ec = edma_err_cause &
2588 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2589 sata_async_notification(ap);
2590 if (!ec)
2591 return; /* Just an AN; no need for the nukes */
2592 ata_ehi_push_desc(ehi, "SDB notify");
2593 }
2594 }
2595 /*
2596 * All generations share these EDMA error cause bits:
2597 */
2598 if (edma_err_cause & EDMA_ERR_DEV) {
2599 err_mask |= AC_ERR_DEV;
2600 action |= ATA_EH_RESET;
2601 ata_ehi_push_desc(ehi, "dev error");
2602 }
2603 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2604 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2605 EDMA_ERR_INTRL_PAR)) {
2606 err_mask |= AC_ERR_ATA_BUS;
2607 action |= ATA_EH_RESET;
2608 ata_ehi_push_desc(ehi, "parity error");
2609 }
2610 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2611 ata_ehi_hotplugged(ehi);
2612 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2613 "dev disconnect" : "dev connect");
2614 action |= ATA_EH_RESET;
2615 }
2616
2617 /*
2618 * Gen-I has a different SELF_DIS bit,
2619 * different FREEZE bits, and no SERR bit:
2620 */
2621 if (IS_GEN_I(hpriv)) {
2622 eh_freeze_mask = EDMA_EH_FREEZE_5;
2623 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2624 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2625 ata_ehi_push_desc(ehi, "EDMA self-disable");
2626 }
2627 } else {
2628 eh_freeze_mask = EDMA_EH_FREEZE;
2629 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2630 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2631 ata_ehi_push_desc(ehi, "EDMA self-disable");
2632 }
2633 if (edma_err_cause & EDMA_ERR_SERR) {
2634 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2635 err_mask |= AC_ERR_ATA_BUS;
2636 action |= ATA_EH_RESET;
2637 }
2638 }
2639
2640 if (!err_mask) {
2641 err_mask = AC_ERR_OTHER;
2642 action |= ATA_EH_RESET;
2643 }
2644
2645 ehi->serror |= serr;
2646 ehi->action |= action;
2647
2648 if (qc)
2649 qc->err_mask |= err_mask;
2650 else
2651 ehi->err_mask |= err_mask;
2652
2653 if (err_mask == AC_ERR_DEV) {
2654 /*
2655 * Cannot do ata_port_freeze() here,
2656 * because it would kill PIO access,
2657 * which is needed for further diagnosis.
2658 */
2659 mv_eh_freeze(ap);
2660 abort = 1;
2661 } else if (edma_err_cause & eh_freeze_mask) {
2662 /*
2663 * Note to self: ata_port_freeze() calls ata_port_abort()
2664 */
2665 ata_port_freeze(ap);
2666 } else {
2667 abort = 1;
2668 }
2669
2670 if (abort) {
2671 if (qc)
2672 ata_link_abort(qc->dev->link);
2673 else
2674 ata_port_abort(ap);
2675 }
2676 }
2677
2678 static void mv_process_crpb_response(struct ata_port *ap,
2679 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2680 {
2681 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2682
2683 if (qc) {
2684 u8 ata_status;
2685 u16 edma_status = le16_to_cpu(response->flags);
2686 /*
2687 * edma_status from a response queue entry:
2688 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2689 * MSB is saved ATA status from command completion.
2690 */
2691 if (!ncq_enabled) {
2692 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2693 if (err_cause) {
2694 /*
2695 * Error will be seen/handled by mv_err_intr().
2696 * So do nothing at all here.
2697 */
2698 return;
2699 }
2700 }
2701 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2702 if (!ac_err_mask(ata_status))
2703 ata_qc_complete(qc);
2704 /* else: leave it for mv_err_intr() */
2705 } else {
2706 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2707 __func__, tag);
2708 }
2709 }
2710
2711 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2712 {
2713 void __iomem *port_mmio = mv_ap_base(ap);
2714 struct mv_host_priv *hpriv = ap->host->private_data;
2715 u32 in_index;
2716 bool work_done = false;
2717 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2718
2719 /* Get the hardware queue position index */
2720 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2721 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2722
2723 /* Process new responses from since the last time we looked */
2724 while (in_index != pp->resp_idx) {
2725 unsigned int tag;
2726 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2727
2728 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2729
2730 if (IS_GEN_I(hpriv)) {
2731 /* 50xx: no NCQ, only one command active at a time */
2732 tag = ap->link.active_tag;
2733 } else {
2734 /* Gen II/IIE: get command tag from CRPB entry */
2735 tag = le16_to_cpu(response->id) & 0x1f;
2736 }
2737 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2738 work_done = true;
2739 }
2740
2741 /* Update the software queue position index in hardware */
2742 if (work_done)
2743 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2744 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2745 port_mmio + EDMA_RSP_Q_OUT_PTR);
2746 }
2747
2748 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2749 {
2750 struct mv_port_priv *pp;
2751 int edma_was_enabled;
2752
2753 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2754 mv_unexpected_intr(ap, 0);
2755 return;
2756 }
2757 /*
2758 * Grab a snapshot of the EDMA_EN flag setting,
2759 * so that we have a consistent view for this port,
2760 * even if something we call of our routines changes it.
2761 */
2762 pp = ap->private_data;
2763 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2764 /*
2765 * Process completed CRPB response(s) before other events.
2766 */
2767 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2768 mv_process_crpb_entries(ap, pp);
2769 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2770 mv_handle_fbs_ncq_dev_err(ap);
2771 }
2772 /*
2773 * Handle chip-reported errors, or continue on to handle PIO.
2774 */
2775 if (unlikely(port_cause & ERR_IRQ)) {
2776 mv_err_intr(ap);
2777 } else if (!edma_was_enabled) {
2778 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2779 if (qc)
2780 ata_sff_host_intr(ap, qc);
2781 else
2782 mv_unexpected_intr(ap, edma_was_enabled);
2783 }
2784 }
2785
2786 /**
2787 * mv_host_intr - Handle all interrupts on the given host controller
2788 * @host: host specific structure
2789 * @main_irq_cause: Main interrupt cause register for the chip.
2790 *
2791 * LOCKING:
2792 * Inherited from caller.
2793 */
2794 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2795 {
2796 struct mv_host_priv *hpriv = host->private_data;
2797 void __iomem *mmio = hpriv->base, *hc_mmio;
2798 unsigned int handled = 0, port;
2799
2800 /* If asserted, clear the "all ports" IRQ coalescing bit */
2801 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2802 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2803
2804 for (port = 0; port < hpriv->n_ports; port++) {
2805 struct ata_port *ap = host->ports[port];
2806 unsigned int p, shift, hardport, port_cause;
2807
2808 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2809 /*
2810 * Each hc within the host has its own hc_irq_cause register,
2811 * where the interrupting ports bits get ack'd.
2812 */
2813 if (hardport == 0) { /* first port on this hc ? */
2814 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2815 u32 port_mask, ack_irqs;
2816 /*
2817 * Skip this entire hc if nothing pending for any ports
2818 */
2819 if (!hc_cause) {
2820 port += MV_PORTS_PER_HC - 1;
2821 continue;
2822 }
2823 /*
2824 * We don't need/want to read the hc_irq_cause register,
2825 * because doing so hurts performance, and
2826 * main_irq_cause already gives us everything we need.
2827 *
2828 * But we do have to *write* to the hc_irq_cause to ack
2829 * the ports that we are handling this time through.
2830 *
2831 * This requires that we create a bitmap for those
2832 * ports which interrupted us, and use that bitmap
2833 * to ack (only) those ports via hc_irq_cause.
2834 */
2835 ack_irqs = 0;
2836 if (hc_cause & PORTS_0_3_COAL_DONE)
2837 ack_irqs = HC_COAL_IRQ;
2838 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2839 if ((port + p) >= hpriv->n_ports)
2840 break;
2841 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2842 if (hc_cause & port_mask)
2843 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2844 }
2845 hc_mmio = mv_hc_base_from_port(mmio, port);
2846 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2847 handled = 1;
2848 }
2849 /*
2850 * Handle interrupts signalled for this port:
2851 */
2852 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2853 if (port_cause)
2854 mv_port_intr(ap, port_cause);
2855 }
2856 return handled;
2857 }
2858
2859 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2860 {
2861 struct mv_host_priv *hpriv = host->private_data;
2862 struct ata_port *ap;
2863 struct ata_queued_cmd *qc;
2864 struct ata_eh_info *ehi;
2865 unsigned int i, err_mask, printed = 0;
2866 u32 err_cause;
2867
2868 err_cause = readl(mmio + hpriv->irq_cause_offset);
2869
2870 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2871 err_cause);
2872
2873 DPRINTK("All regs @ PCI error\n");
2874 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2875
2876 writelfl(0, mmio + hpriv->irq_cause_offset);
2877
2878 for (i = 0; i < host->n_ports; i++) {
2879 ap = host->ports[i];
2880 if (!ata_link_offline(&ap->link)) {
2881 ehi = &ap->link.eh_info;
2882 ata_ehi_clear_desc(ehi);
2883 if (!printed++)
2884 ata_ehi_push_desc(ehi,
2885 "PCI err cause 0x%08x", err_cause);
2886 err_mask = AC_ERR_HOST_BUS;
2887 ehi->action = ATA_EH_RESET;
2888 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2889 if (qc)
2890 qc->err_mask |= err_mask;
2891 else
2892 ehi->err_mask |= err_mask;
2893
2894 ata_port_freeze(ap);
2895 }
2896 }
2897 return 1; /* handled */
2898 }
2899
2900 /**
2901 * mv_interrupt - Main interrupt event handler
2902 * @irq: unused
2903 * @dev_instance: private data; in this case the host structure
2904 *
2905 * Read the read only register to determine if any host
2906 * controllers have pending interrupts. If so, call lower level
2907 * routine to handle. Also check for PCI errors which are only
2908 * reported here.
2909 *
2910 * LOCKING:
2911 * This routine holds the host lock while processing pending
2912 * interrupts.
2913 */
2914 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2915 {
2916 struct ata_host *host = dev_instance;
2917 struct mv_host_priv *hpriv = host->private_data;
2918 unsigned int handled = 0;
2919 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2920 u32 main_irq_cause, pending_irqs;
2921
2922 spin_lock(&host->lock);
2923
2924 /* for MSI: block new interrupts while in here */
2925 if (using_msi)
2926 mv_write_main_irq_mask(0, hpriv);
2927
2928 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2929 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2930 /*
2931 * Deal with cases where we either have nothing pending, or have read
2932 * a bogus register value which can indicate HW removal or PCI fault.
2933 */
2934 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2935 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2936 handled = mv_pci_error(host, hpriv->base);
2937 else
2938 handled = mv_host_intr(host, pending_irqs);
2939 }
2940
2941 /* for MSI: unmask; interrupt cause bits will retrigger now */
2942 if (using_msi)
2943 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2944
2945 spin_unlock(&host->lock);
2946
2947 return IRQ_RETVAL(handled);
2948 }
2949
2950 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2951 {
2952 unsigned int ofs;
2953
2954 switch (sc_reg_in) {
2955 case SCR_STATUS:
2956 case SCR_ERROR:
2957 case SCR_CONTROL:
2958 ofs = sc_reg_in * sizeof(u32);
2959 break;
2960 default:
2961 ofs = 0xffffffffU;
2962 break;
2963 }
2964 return ofs;
2965 }
2966
2967 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2968 {
2969 struct mv_host_priv *hpriv = link->ap->host->private_data;
2970 void __iomem *mmio = hpriv->base;
2971 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2972 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2973
2974 if (ofs != 0xffffffffU) {
2975 *val = readl(addr + ofs);
2976 return 0;
2977 } else
2978 return -EINVAL;
2979 }
2980
2981 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2982 {
2983 struct mv_host_priv *hpriv = link->ap->host->private_data;
2984 void __iomem *mmio = hpriv->base;
2985 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2986 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2987
2988 if (ofs != 0xffffffffU) {
2989 writelfl(val, addr + ofs);
2990 return 0;
2991 } else
2992 return -EINVAL;
2993 }
2994
2995 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2996 {
2997 struct pci_dev *pdev = to_pci_dev(host->dev);
2998 int early_5080;
2999
3000 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3001
3002 if (!early_5080) {
3003 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3004 tmp |= (1 << 0);
3005 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3006 }
3007
3008 mv_reset_pci_bus(host, mmio);
3009 }
3010
3011 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3012 {
3013 writel(0x0fcfffff, mmio + FLASH_CTL);
3014 }
3015
3016 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3017 void __iomem *mmio)
3018 {
3019 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3020 u32 tmp;
3021
3022 tmp = readl(phy_mmio + MV5_PHY_MODE);
3023
3024 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3025 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3026 }
3027
3028 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3029 {
3030 u32 tmp;
3031
3032 writel(0, mmio + GPIO_PORT_CTL);
3033
3034 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3035
3036 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3037 tmp |= ~(1 << 0);
3038 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3039 }
3040
3041 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3042 unsigned int port)
3043 {
3044 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3045 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3046 u32 tmp;
3047 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3048
3049 if (fix_apm_sq) {
3050 tmp = readl(phy_mmio + MV5_LTMODE);
3051 tmp |= (1 << 19);
3052 writel(tmp, phy_mmio + MV5_LTMODE);
3053
3054 tmp = readl(phy_mmio + MV5_PHY_CTL);
3055 tmp &= ~0x3;
3056 tmp |= 0x1;
3057 writel(tmp, phy_mmio + MV5_PHY_CTL);
3058 }
3059
3060 tmp = readl(phy_mmio + MV5_PHY_MODE);
3061 tmp &= ~mask;
3062 tmp |= hpriv->signal[port].pre;
3063 tmp |= hpriv->signal[port].amps;
3064 writel(tmp, phy_mmio + MV5_PHY_MODE);
3065 }
3066
3067
3068 #undef ZERO
3069 #define ZERO(reg) writel(0, port_mmio + (reg))
3070 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3071 unsigned int port)
3072 {
3073 void __iomem *port_mmio = mv_port_base(mmio, port);
3074
3075 mv_reset_channel(hpriv, mmio, port);
3076
3077 ZERO(0x028); /* command */
3078 writel(0x11f, port_mmio + EDMA_CFG);
3079 ZERO(0x004); /* timer */
3080 ZERO(0x008); /* irq err cause */
3081 ZERO(0x00c); /* irq err mask */
3082 ZERO(0x010); /* rq bah */
3083 ZERO(0x014); /* rq inp */
3084 ZERO(0x018); /* rq outp */
3085 ZERO(0x01c); /* respq bah */
3086 ZERO(0x024); /* respq outp */
3087 ZERO(0x020); /* respq inp */
3088 ZERO(0x02c); /* test control */
3089 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3090 }
3091 #undef ZERO
3092
3093 #define ZERO(reg) writel(0, hc_mmio + (reg))
3094 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3095 unsigned int hc)
3096 {
3097 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3098 u32 tmp;
3099
3100 ZERO(0x00c);
3101 ZERO(0x010);
3102 ZERO(0x014);
3103 ZERO(0x018);
3104
3105 tmp = readl(hc_mmio + 0x20);
3106 tmp &= 0x1c1c1c1c;
3107 tmp |= 0x03030303;
3108 writel(tmp, hc_mmio + 0x20);
3109 }
3110 #undef ZERO
3111
3112 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3113 unsigned int n_hc)
3114 {
3115 unsigned int hc, port;
3116
3117 for (hc = 0; hc < n_hc; hc++) {
3118 for (port = 0; port < MV_PORTS_PER_HC; port++)
3119 mv5_reset_hc_port(hpriv, mmio,
3120 (hc * MV_PORTS_PER_HC) + port);
3121
3122 mv5_reset_one_hc(hpriv, mmio, hc);
3123 }
3124
3125 return 0;
3126 }
3127
3128 #undef ZERO
3129 #define ZERO(reg) writel(0, mmio + (reg))
3130 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3131 {
3132 struct mv_host_priv *hpriv = host->private_data;
3133 u32 tmp;
3134
3135 tmp = readl(mmio + MV_PCI_MODE);
3136 tmp &= 0xff00ffff;
3137 writel(tmp, mmio + MV_PCI_MODE);
3138
3139 ZERO(MV_PCI_DISC_TIMER);
3140 ZERO(MV_PCI_MSI_TRIGGER);
3141 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3142 ZERO(MV_PCI_SERR_MASK);
3143 ZERO(hpriv->irq_cause_offset);
3144 ZERO(hpriv->irq_mask_offset);
3145 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3146 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3147 ZERO(MV_PCI_ERR_ATTRIBUTE);
3148 ZERO(MV_PCI_ERR_COMMAND);
3149 }
3150 #undef ZERO
3151
3152 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3153 {
3154 u32 tmp;
3155
3156 mv5_reset_flash(hpriv, mmio);
3157
3158 tmp = readl(mmio + GPIO_PORT_CTL);
3159 tmp &= 0x3;
3160 tmp |= (1 << 5) | (1 << 6);
3161 writel(tmp, mmio + GPIO_PORT_CTL);
3162 }
3163
3164 /**
3165 * mv6_reset_hc - Perform the 6xxx global soft reset
3166 * @mmio: base address of the HBA
3167 *
3168 * This routine only applies to 6xxx parts.
3169 *
3170 * LOCKING:
3171 * Inherited from caller.
3172 */
3173 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3174 unsigned int n_hc)
3175 {
3176 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3177 int i, rc = 0;
3178 u32 t;
3179
3180 /* Following procedure defined in PCI "main command and status
3181 * register" table.
3182 */
3183 t = readl(reg);
3184 writel(t | STOP_PCI_MASTER, reg);
3185
3186 for (i = 0; i < 1000; i++) {
3187 udelay(1);
3188 t = readl(reg);
3189 if (PCI_MASTER_EMPTY & t)
3190 break;
3191 }
3192 if (!(PCI_MASTER_EMPTY & t)) {
3193 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3194 rc = 1;
3195 goto done;
3196 }
3197
3198 /* set reset */
3199 i = 5;
3200 do {
3201 writel(t | GLOB_SFT_RST, reg);
3202 t = readl(reg);
3203 udelay(1);
3204 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3205
3206 if (!(GLOB_SFT_RST & t)) {
3207 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3208 rc = 1;
3209 goto done;
3210 }
3211
3212 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3213 i = 5;
3214 do {
3215 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3216 t = readl(reg);
3217 udelay(1);
3218 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3219
3220 if (GLOB_SFT_RST & t) {
3221 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3222 rc = 1;
3223 }
3224 done:
3225 return rc;
3226 }
3227
3228 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3229 void __iomem *mmio)
3230 {
3231 void __iomem *port_mmio;
3232 u32 tmp;
3233
3234 tmp = readl(mmio + RESET_CFG);
3235 if ((tmp & (1 << 0)) == 0) {
3236 hpriv->signal[idx].amps = 0x7 << 8;
3237 hpriv->signal[idx].pre = 0x1 << 5;
3238 return;
3239 }
3240
3241 port_mmio = mv_port_base(mmio, idx);
3242 tmp = readl(port_mmio + PHY_MODE2);
3243
3244 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3245 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3246 }
3247
3248 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3249 {
3250 writel(0x00000060, mmio + GPIO_PORT_CTL);
3251 }
3252
3253 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3254 unsigned int port)
3255 {
3256 void __iomem *port_mmio = mv_port_base(mmio, port);
3257
3258 u32 hp_flags = hpriv->hp_flags;
3259 int fix_phy_mode2 =
3260 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3261 int fix_phy_mode4 =
3262 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3263 u32 m2, m3;
3264
3265 if (fix_phy_mode2) {
3266 m2 = readl(port_mmio + PHY_MODE2);
3267 m2 &= ~(1 << 16);
3268 m2 |= (1 << 31);
3269 writel(m2, port_mmio + PHY_MODE2);
3270
3271 udelay(200);
3272
3273 m2 = readl(port_mmio + PHY_MODE2);
3274 m2 &= ~((1 << 16) | (1 << 31));
3275 writel(m2, port_mmio + PHY_MODE2);
3276
3277 udelay(200);
3278 }
3279
3280 /*
3281 * Gen-II/IIe PHY_MODE3 errata RM#2:
3282 * Achieves better receiver noise performance than the h/w default:
3283 */
3284 m3 = readl(port_mmio + PHY_MODE3);
3285 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3286
3287 /* Guideline 88F5182 (GL# SATA-S11) */
3288 if (IS_SOC(hpriv))
3289 m3 &= ~0x1c;
3290
3291 if (fix_phy_mode4) {
3292 u32 m4 = readl(port_mmio + PHY_MODE4);
3293 /*
3294 * Enforce reserved-bit restrictions on GenIIe devices only.
3295 * For earlier chipsets, force only the internal config field
3296 * (workaround for errata FEr SATA#10 part 1).
3297 */
3298 if (IS_GEN_IIE(hpriv))
3299 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3300 else
3301 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3302 writel(m4, port_mmio + PHY_MODE4);
3303 }
3304 /*
3305 * Workaround for 60x1-B2 errata SATA#13:
3306 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3307 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3308 * Or ensure we use writelfl() when writing PHY_MODE4.
3309 */
3310 writel(m3, port_mmio + PHY_MODE3);
3311
3312 /* Revert values of pre-emphasis and signal amps to the saved ones */
3313 m2 = readl(port_mmio + PHY_MODE2);
3314
3315 m2 &= ~MV_M2_PREAMP_MASK;
3316 m2 |= hpriv->signal[port].amps;
3317 m2 |= hpriv->signal[port].pre;
3318 m2 &= ~(1 << 16);
3319
3320 /* according to mvSata 3.6.1, some IIE values are fixed */
3321 if (IS_GEN_IIE(hpriv)) {
3322 m2 &= ~0xC30FF01F;
3323 m2 |= 0x0000900F;
3324 }
3325
3326 writel(m2, port_mmio + PHY_MODE2);
3327 }
3328
3329 /* TODO: use the generic LED interface to configure the SATA Presence */
3330 /* & Acitivy LEDs on the board */
3331 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3332 void __iomem *mmio)
3333 {
3334 return;
3335 }
3336
3337 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3338 void __iomem *mmio)
3339 {
3340 void __iomem *port_mmio;
3341 u32 tmp;
3342
3343 port_mmio = mv_port_base(mmio, idx);
3344 tmp = readl(port_mmio + PHY_MODE2);
3345
3346 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3347 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3348 }
3349
3350 #undef ZERO
3351 #define ZERO(reg) writel(0, port_mmio + (reg))
3352 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3353 void __iomem *mmio, unsigned int port)
3354 {
3355 void __iomem *port_mmio = mv_port_base(mmio, port);
3356
3357 mv_reset_channel(hpriv, mmio, port);
3358
3359 ZERO(0x028); /* command */
3360 writel(0x101f, port_mmio + EDMA_CFG);
3361 ZERO(0x004); /* timer */
3362 ZERO(0x008); /* irq err cause */
3363 ZERO(0x00c); /* irq err mask */
3364 ZERO(0x010); /* rq bah */
3365 ZERO(0x014); /* rq inp */
3366 ZERO(0x018); /* rq outp */
3367 ZERO(0x01c); /* respq bah */
3368 ZERO(0x024); /* respq outp */
3369 ZERO(0x020); /* respq inp */
3370 ZERO(0x02c); /* test control */
3371 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3372 }
3373
3374 #undef ZERO
3375
3376 #define ZERO(reg) writel(0, hc_mmio + (reg))
3377 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3378 void __iomem *mmio)
3379 {
3380 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3381
3382 ZERO(0x00c);
3383 ZERO(0x010);
3384 ZERO(0x014);
3385
3386 }
3387
3388 #undef ZERO
3389
3390 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3391 void __iomem *mmio, unsigned int n_hc)
3392 {
3393 unsigned int port;
3394
3395 for (port = 0; port < hpriv->n_ports; port++)
3396 mv_soc_reset_hc_port(hpriv, mmio, port);
3397
3398 mv_soc_reset_one_hc(hpriv, mmio);
3399
3400 return 0;
3401 }
3402
3403 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3404 void __iomem *mmio)
3405 {
3406 return;
3407 }
3408
3409 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3410 {
3411 return;
3412 }
3413
3414 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3415 void __iomem *mmio, unsigned int port)
3416 {
3417 void __iomem *port_mmio = mv_port_base(mmio, port);
3418 u32 reg;
3419
3420 reg = readl(port_mmio + PHY_MODE3);
3421 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3422 reg |= (0x1 << 27);
3423 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3424 reg |= (0x1 << 29);
3425 writel(reg, port_mmio + PHY_MODE3);
3426
3427 reg = readl(port_mmio + PHY_MODE4);
3428 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3429 reg |= (0x1 << 16);
3430 writel(reg, port_mmio + PHY_MODE4);
3431
3432 reg = readl(port_mmio + PHY_MODE9_GEN2);
3433 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3434 reg |= 0x8;
3435 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3436 writel(reg, port_mmio + PHY_MODE9_GEN2);
3437
3438 reg = readl(port_mmio + PHY_MODE9_GEN1);
3439 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3440 reg |= 0x8;
3441 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3442 writel(reg, port_mmio + PHY_MODE9_GEN1);
3443 }
3444
3445 /**
3446 * soc_is_65 - check if the soc is 65 nano device
3447 *
3448 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3449 * register, this register should contain non-zero value and it exists only
3450 * in the 65 nano devices, when reading it from older devices we get 0.
3451 */
3452 static bool soc_is_65n(struct mv_host_priv *hpriv)
3453 {
3454 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3455
3456 if (readl(port0_mmio + PHYCFG_OFS))
3457 return true;
3458 return false;
3459 }
3460
3461 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3462 {
3463 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3464
3465 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3466 if (want_gen2i)
3467 ifcfg |= (1 << 7); /* enable gen2i speed */
3468 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3469 }
3470
3471 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3472 unsigned int port_no)
3473 {
3474 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3475
3476 /*
3477 * The datasheet warns against setting EDMA_RESET when EDMA is active
3478 * (but doesn't say what the problem might be). So we first try
3479 * to disable the EDMA engine before doing the EDMA_RESET operation.
3480 */
3481 mv_stop_edma_engine(port_mmio);
3482 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3483
3484 if (!IS_GEN_I(hpriv)) {
3485 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3486 mv_setup_ifcfg(port_mmio, 1);
3487 }
3488 /*
3489 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3490 * link, and physical layers. It resets all SATA interface registers
3491 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3492 */
3493 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3494 udelay(25); /* allow reset propagation */
3495 writelfl(0, port_mmio + EDMA_CMD);
3496
3497 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3498
3499 if (IS_GEN_I(hpriv))
3500 mdelay(1);
3501 }
3502
3503 static void mv_pmp_select(struct ata_port *ap, int pmp)
3504 {
3505 if (sata_pmp_supported(ap)) {
3506 void __iomem *port_mmio = mv_ap_base(ap);
3507 u32 reg = readl(port_mmio + SATA_IFCTL);
3508 int old = reg & 0xf;
3509
3510 if (old != pmp) {
3511 reg = (reg & ~0xf) | pmp;
3512 writelfl(reg, port_mmio + SATA_IFCTL);
3513 }
3514 }
3515 }
3516
3517 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3518 unsigned long deadline)
3519 {
3520 mv_pmp_select(link->ap, sata_srst_pmp(link));
3521 return sata_std_hardreset(link, class, deadline);
3522 }
3523
3524 static int mv_softreset(struct ata_link *link, unsigned int *class,
3525 unsigned long deadline)
3526 {
3527 mv_pmp_select(link->ap, sata_srst_pmp(link));
3528 return ata_sff_softreset(link, class, deadline);
3529 }
3530
3531 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3532 unsigned long deadline)
3533 {
3534 struct ata_port *ap = link->ap;
3535 struct mv_host_priv *hpriv = ap->host->private_data;
3536 struct mv_port_priv *pp = ap->private_data;
3537 void __iomem *mmio = hpriv->base;
3538 int rc, attempts = 0, extra = 0;
3539 u32 sstatus;
3540 bool online;
3541
3542 mv_reset_channel(hpriv, mmio, ap->port_no);
3543 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3544 pp->pp_flags &=
3545 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3546
3547 /* Workaround for errata FEr SATA#10 (part 2) */
3548 do {
3549 const unsigned long *timing =
3550 sata_ehc_deb_timing(&link->eh_context);
3551
3552 rc = sata_link_hardreset(link, timing, deadline + extra,
3553 &online, NULL);
3554 rc = online ? -EAGAIN : rc;
3555 if (rc)
3556 return rc;
3557 sata_scr_read(link, SCR_STATUS, &sstatus);
3558 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3559 /* Force 1.5gb/s link speed and try again */
3560 mv_setup_ifcfg(mv_ap_base(ap), 0);
3561 if (time_after(jiffies + HZ, deadline))
3562 extra = HZ; /* only extend it once, max */
3563 }
3564 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3565 mv_save_cached_regs(ap);
3566 mv_edma_cfg(ap, 0, 0);
3567
3568 return rc;
3569 }
3570
3571 static void mv_eh_freeze(struct ata_port *ap)
3572 {
3573 mv_stop_edma(ap);
3574 mv_enable_port_irqs(ap, 0);
3575 }
3576
3577 static void mv_eh_thaw(struct ata_port *ap)
3578 {
3579 struct mv_host_priv *hpriv = ap->host->private_data;
3580 unsigned int port = ap->port_no;
3581 unsigned int hardport = mv_hardport_from_port(port);
3582 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3583 void __iomem *port_mmio = mv_ap_base(ap);
3584 u32 hc_irq_cause;
3585
3586 /* clear EDMA errors on this port */
3587 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3588
3589 /* clear pending irq events */
3590 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3591 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3592
3593 mv_enable_port_irqs(ap, ERR_IRQ);
3594 }
3595
3596 /**
3597 * mv_port_init - Perform some early initialization on a single port.
3598 * @port: libata data structure storing shadow register addresses
3599 * @port_mmio: base address of the port
3600 *
3601 * Initialize shadow register mmio addresses, clear outstanding
3602 * interrupts on the port, and unmask interrupts for the future
3603 * start of the port.
3604 *
3605 * LOCKING:
3606 * Inherited from caller.
3607 */
3608 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3609 {
3610 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3611
3612 /* PIO related setup
3613 */
3614 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3615 port->error_addr =
3616 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3617 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3618 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3619 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3620 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3621 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3622 port->status_addr =
3623 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3624 /* special case: control/altstatus doesn't have ATA_REG_ address */
3625 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3626
3627 /* unused: */
3628 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3629
3630 /* Clear any currently outstanding port interrupt conditions */
3631 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3632 writelfl(readl(serr), serr);
3633 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3634
3635 /* unmask all non-transient EDMA error interrupts */
3636 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3637
3638 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3639 readl(port_mmio + EDMA_CFG),
3640 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3641 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3642 }
3643
3644 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3645 {
3646 struct mv_host_priv *hpriv = host->private_data;
3647 void __iomem *mmio = hpriv->base;
3648 u32 reg;
3649
3650 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3651 return 0; /* not PCI-X capable */
3652 reg = readl(mmio + MV_PCI_MODE);
3653 if ((reg & MV_PCI_MODE_MASK) == 0)
3654 return 0; /* conventional PCI mode */
3655 return 1; /* chip is in PCI-X mode */
3656 }
3657
3658 static int mv_pci_cut_through_okay(struct ata_host *host)
3659 {
3660 struct mv_host_priv *hpriv = host->private_data;
3661 void __iomem *mmio = hpriv->base;
3662 u32 reg;
3663
3664 if (!mv_in_pcix_mode(host)) {
3665 reg = readl(mmio + MV_PCI_COMMAND);
3666 if (reg & MV_PCI_COMMAND_MRDTRIG)
3667 return 0; /* not okay */
3668 }
3669 return 1; /* okay */
3670 }
3671
3672 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3673 {
3674 struct mv_host_priv *hpriv = host->private_data;
3675 void __iomem *mmio = hpriv->base;
3676
3677 /* workaround for 60x1-B2 errata PCI#7 */
3678 if (mv_in_pcix_mode(host)) {
3679 u32 reg = readl(mmio + MV_PCI_COMMAND);
3680 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3681 }
3682 }
3683
3684 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3685 {
3686 struct pci_dev *pdev = to_pci_dev(host->dev);
3687 struct mv_host_priv *hpriv = host->private_data;
3688 u32 hp_flags = hpriv->hp_flags;
3689
3690 switch (board_idx) {
3691 case chip_5080:
3692 hpriv->ops = &mv5xxx_ops;
3693 hp_flags |= MV_HP_GEN_I;
3694
3695 switch (pdev->revision) {
3696 case 0x1:
3697 hp_flags |= MV_HP_ERRATA_50XXB0;
3698 break;
3699 case 0x3:
3700 hp_flags |= MV_HP_ERRATA_50XXB2;
3701 break;
3702 default:
3703 dev_printk(KERN_WARNING, &pdev->dev,
3704 "Applying 50XXB2 workarounds to unknown rev\n");
3705 hp_flags |= MV_HP_ERRATA_50XXB2;
3706 break;
3707 }
3708 break;
3709
3710 case chip_504x:
3711 case chip_508x:
3712 hpriv->ops = &mv5xxx_ops;
3713 hp_flags |= MV_HP_GEN_I;
3714
3715 switch (pdev->revision) {
3716 case 0x0:
3717 hp_flags |= MV_HP_ERRATA_50XXB0;
3718 break;
3719 case 0x3:
3720 hp_flags |= MV_HP_ERRATA_50XXB2;
3721 break;
3722 default:
3723 dev_printk(KERN_WARNING, &pdev->dev,
3724 "Applying B2 workarounds to unknown rev\n");
3725 hp_flags |= MV_HP_ERRATA_50XXB2;
3726 break;
3727 }
3728 break;
3729
3730 case chip_604x:
3731 case chip_608x:
3732 hpriv->ops = &mv6xxx_ops;
3733 hp_flags |= MV_HP_GEN_II;
3734
3735 switch (pdev->revision) {
3736 case 0x7:
3737 mv_60x1b2_errata_pci7(host);
3738 hp_flags |= MV_HP_ERRATA_60X1B2;
3739 break;
3740 case 0x9:
3741 hp_flags |= MV_HP_ERRATA_60X1C0;
3742 break;
3743 default:
3744 dev_printk(KERN_WARNING, &pdev->dev,
3745 "Applying B2 workarounds to unknown rev\n");
3746 hp_flags |= MV_HP_ERRATA_60X1B2;
3747 break;
3748 }
3749 break;
3750
3751 case chip_7042:
3752 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3753 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3754 (pdev->device == 0x2300 || pdev->device == 0x2310))
3755 {
3756 /*
3757 * Highpoint RocketRAID PCIe 23xx series cards:
3758 *
3759 * Unconfigured drives are treated as "Legacy"
3760 * by the BIOS, and it overwrites sector 8 with
3761 * a "Lgcy" metadata block prior to Linux boot.
3762 *
3763 * Configured drives (RAID or JBOD) leave sector 8
3764 * alone, but instead overwrite a high numbered
3765 * sector for the RAID metadata. This sector can
3766 * be determined exactly, by truncating the physical
3767 * drive capacity to a nice even GB value.
3768 *
3769 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3770 *
3771 * Warn the user, lest they think we're just buggy.
3772 */
3773 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3774 " BIOS CORRUPTS DATA on all attached drives,"
3775 " regardless of if/how they are configured."
3776 " BEWARE!\n");
3777 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3778 " use sectors 8-9 on \"Legacy\" drives,"
3779 " and avoid the final two gigabytes on"
3780 " all RocketRAID BIOS initialized drives.\n");
3781 }
3782 /* drop through */
3783 case chip_6042:
3784 hpriv->ops = &mv6xxx_ops;
3785 hp_flags |= MV_HP_GEN_IIE;
3786 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3787 hp_flags |= MV_HP_CUT_THROUGH;
3788
3789 switch (pdev->revision) {
3790 case 0x2: /* Rev.B0: the first/only public release */
3791 hp_flags |= MV_HP_ERRATA_60X1C0;
3792 break;
3793 default:
3794 dev_printk(KERN_WARNING, &pdev->dev,
3795 "Applying 60X1C0 workarounds to unknown rev\n");
3796 hp_flags |= MV_HP_ERRATA_60X1C0;
3797 break;
3798 }
3799 break;
3800 case chip_soc:
3801 if (soc_is_65n(hpriv))
3802 hpriv->ops = &mv_soc_65n_ops;
3803 else
3804 hpriv->ops = &mv_soc_ops;
3805 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3806 MV_HP_ERRATA_60X1C0;
3807 break;
3808
3809 default:
3810 dev_printk(KERN_ERR, host->dev,
3811 "BUG: invalid board index %u\n", board_idx);
3812 return 1;
3813 }
3814
3815 hpriv->hp_flags = hp_flags;
3816 if (hp_flags & MV_HP_PCIE) {
3817 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3818 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3819 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3820 } else {
3821 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3822 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3823 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3824 }
3825
3826 return 0;
3827 }
3828
3829 /**
3830 * mv_init_host - Perform some early initialization of the host.
3831 * @host: ATA host to initialize
3832 * @board_idx: controller index
3833 *
3834 * If possible, do an early global reset of the host. Then do
3835 * our port init and clear/unmask all/relevant host interrupts.
3836 *
3837 * LOCKING:
3838 * Inherited from caller.
3839 */
3840 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3841 {
3842 int rc = 0, n_hc, port, hc;
3843 struct mv_host_priv *hpriv = host->private_data;
3844 void __iomem *mmio = hpriv->base;
3845
3846 rc = mv_chip_id(host, board_idx);
3847 if (rc)
3848 goto done;
3849
3850 if (IS_SOC(hpriv)) {
3851 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3852 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3853 } else {
3854 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3855 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3856 }
3857
3858 /* initialize shadow irq mask with register's value */
3859 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3860
3861 /* global interrupt mask: 0 == mask everything */
3862 mv_set_main_irq_mask(host, ~0, 0);
3863
3864 n_hc = mv_get_hc_count(host->ports[0]->flags);
3865
3866 for (port = 0; port < host->n_ports; port++)
3867 if (hpriv->ops->read_preamp)
3868 hpriv->ops->read_preamp(hpriv, port, mmio);
3869
3870 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3871 if (rc)
3872 goto done;
3873
3874 hpriv->ops->reset_flash(hpriv, mmio);
3875 hpriv->ops->reset_bus(host, mmio);
3876 hpriv->ops->enable_leds(hpriv, mmio);
3877
3878 for (port = 0; port < host->n_ports; port++) {
3879 struct ata_port *ap = host->ports[port];
3880 void __iomem *port_mmio = mv_port_base(mmio, port);
3881
3882 mv_port_init(&ap->ioaddr, port_mmio);
3883
3884 #ifdef CONFIG_PCI
3885 if (!IS_SOC(hpriv)) {
3886 unsigned int offset = port_mmio - mmio;
3887 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3888 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3889 }
3890 #endif
3891 }
3892
3893 for (hc = 0; hc < n_hc; hc++) {
3894 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3895
3896 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3897 "(before clear)=0x%08x\n", hc,
3898 readl(hc_mmio + HC_CFG),
3899 readl(hc_mmio + HC_IRQ_CAUSE));
3900
3901 /* Clear any currently outstanding hc interrupt conditions */
3902 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3903 }
3904
3905 if (!IS_SOC(hpriv)) {
3906 /* Clear any currently outstanding host interrupt conditions */
3907 writelfl(0, mmio + hpriv->irq_cause_offset);
3908
3909 /* and unmask interrupt generation for host regs */
3910 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3911 }
3912
3913 /*
3914 * enable only global host interrupts for now.
3915 * The per-port interrupts get done later as ports are set up.
3916 */
3917 mv_set_main_irq_mask(host, 0, PCI_ERR);
3918 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3919 irq_coalescing_usecs);
3920 done:
3921 return rc;
3922 }
3923
3924 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3925 {
3926 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3927 MV_CRQB_Q_SZ, 0);
3928 if (!hpriv->crqb_pool)
3929 return -ENOMEM;
3930
3931 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3932 MV_CRPB_Q_SZ, 0);
3933 if (!hpriv->crpb_pool)
3934 return -ENOMEM;
3935
3936 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3937 MV_SG_TBL_SZ, 0);
3938 if (!hpriv->sg_tbl_pool)
3939 return -ENOMEM;
3940
3941 return 0;
3942 }
3943
3944 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3945 struct mbus_dram_target_info *dram)
3946 {
3947 int i;
3948
3949 for (i = 0; i < 4; i++) {
3950 writel(0, hpriv->base + WINDOW_CTRL(i));
3951 writel(0, hpriv->base + WINDOW_BASE(i));
3952 }
3953
3954 for (i = 0; i < dram->num_cs; i++) {
3955 struct mbus_dram_window *cs = dram->cs + i;
3956
3957 writel(((cs->size - 1) & 0xffff0000) |
3958 (cs->mbus_attr << 8) |
3959 (dram->mbus_dram_target_id << 4) | 1,
3960 hpriv->base + WINDOW_CTRL(i));
3961 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3962 }
3963 }
3964
3965 /**
3966 * mv_platform_probe - handle a positive probe of an soc Marvell
3967 * host
3968 * @pdev: platform device found
3969 *
3970 * LOCKING:
3971 * Inherited from caller.
3972 */
3973 static int mv_platform_probe(struct platform_device *pdev)
3974 {
3975 static int printed_version;
3976 const struct mv_sata_platform_data *mv_platform_data;
3977 const struct ata_port_info *ppi[] =
3978 { &mv_port_info[chip_soc], NULL };
3979 struct ata_host *host;
3980 struct mv_host_priv *hpriv;
3981 struct resource *res;
3982 int n_ports, rc;
3983
3984 if (!printed_version++)
3985 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3986
3987 /*
3988 * Simple resource validation ..
3989 */
3990 if (unlikely(pdev->num_resources != 2)) {
3991 dev_err(&pdev->dev, "invalid number of resources\n");
3992 return -EINVAL;
3993 }
3994
3995 /*
3996 * Get the register base first
3997 */
3998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3999 if (res == NULL)
4000 return -EINVAL;
4001
4002 /* allocate host */
4003 mv_platform_data = pdev->dev.platform_data;
4004 n_ports = mv_platform_data->n_ports;
4005
4006 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4007 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4008
4009 if (!host || !hpriv)
4010 return -ENOMEM;
4011 host->private_data = hpriv;
4012 hpriv->n_ports = n_ports;
4013
4014 host->iomap = NULL;
4015 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4016 res->end - res->start + 1);
4017 hpriv->base -= SATAHC0_REG_BASE;
4018
4019 /*
4020 * (Re-)program MBUS remapping windows if we are asked to.
4021 */
4022 if (mv_platform_data->dram != NULL)
4023 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4024
4025 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4026 if (rc)
4027 return rc;
4028
4029 /* initialize adapter */
4030 rc = mv_init_host(host, chip_soc);
4031 if (rc)
4032 return rc;
4033
4034 dev_printk(KERN_INFO, &pdev->dev,
4035 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4036 host->n_ports);
4037
4038 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4039 IRQF_SHARED, &mv6_sht);
4040 }
4041
4042 /*
4043 *
4044 * mv_platform_remove - unplug a platform interface
4045 * @pdev: platform device
4046 *
4047 * A platform bus SATA device has been unplugged. Perform the needed
4048 * cleanup. Also called on module unload for any active devices.
4049 */
4050 static int __devexit mv_platform_remove(struct platform_device *pdev)
4051 {
4052 struct device *dev = &pdev->dev;
4053 struct ata_host *host = dev_get_drvdata(dev);
4054
4055 ata_host_detach(host);
4056 return 0;
4057 }
4058
4059 static struct platform_driver mv_platform_driver = {
4060 .probe = mv_platform_probe,
4061 .remove = __devexit_p(mv_platform_remove),
4062 .driver = {
4063 .name = DRV_NAME,
4064 .owner = THIS_MODULE,
4065 },
4066 };
4067
4068
4069 #ifdef CONFIG_PCI
4070 static int mv_pci_init_one(struct pci_dev *pdev,
4071 const struct pci_device_id *ent);
4072
4073
4074 static struct pci_driver mv_pci_driver = {
4075 .name = DRV_NAME,
4076 .id_table = mv_pci_tbl,
4077 .probe = mv_pci_init_one,
4078 .remove = ata_pci_remove_one,
4079 };
4080
4081 /* move to PCI layer or libata core? */
4082 static int pci_go_64(struct pci_dev *pdev)
4083 {
4084 int rc;
4085
4086 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4087 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4088 if (rc) {
4089 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4090 if (rc) {
4091 dev_printk(KERN_ERR, &pdev->dev,
4092 "64-bit DMA enable failed\n");
4093 return rc;
4094 }
4095 }
4096 } else {
4097 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4098 if (rc) {
4099 dev_printk(KERN_ERR, &pdev->dev,
4100 "32-bit DMA enable failed\n");
4101 return rc;
4102 }
4103 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4104 if (rc) {
4105 dev_printk(KERN_ERR, &pdev->dev,
4106 "32-bit consistent DMA enable failed\n");
4107 return rc;
4108 }
4109 }
4110
4111 return rc;
4112 }
4113
4114 /**
4115 * mv_print_info - Dump key info to kernel log for perusal.
4116 * @host: ATA host to print info about
4117 *
4118 * FIXME: complete this.
4119 *
4120 * LOCKING:
4121 * Inherited from caller.
4122 */
4123 static void mv_print_info(struct ata_host *host)
4124 {
4125 struct pci_dev *pdev = to_pci_dev(host->dev);
4126 struct mv_host_priv *hpriv = host->private_data;
4127 u8 scc;
4128 const char *scc_s, *gen;
4129
4130 /* Use this to determine the HW stepping of the chip so we know
4131 * what errata to workaround
4132 */
4133 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4134 if (scc == 0)
4135 scc_s = "SCSI";
4136 else if (scc == 0x01)
4137 scc_s = "RAID";
4138 else
4139 scc_s = "?";
4140
4141 if (IS_GEN_I(hpriv))
4142 gen = "I";
4143 else if (IS_GEN_II(hpriv))
4144 gen = "II";
4145 else if (IS_GEN_IIE(hpriv))
4146 gen = "IIE";
4147 else
4148 gen = "?";
4149
4150 dev_printk(KERN_INFO, &pdev->dev,
4151 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4152 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4153 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4154 }
4155
4156 /**
4157 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4158 * @pdev: PCI device found
4159 * @ent: PCI device ID entry for the matched host
4160 *
4161 * LOCKING:
4162 * Inherited from caller.
4163 */
4164 static int mv_pci_init_one(struct pci_dev *pdev,
4165 const struct pci_device_id *ent)
4166 {
4167 static int printed_version;
4168 unsigned int board_idx = (unsigned int)ent->driver_data;
4169 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4170 struct ata_host *host;
4171 struct mv_host_priv *hpriv;
4172 int n_ports, rc;
4173
4174 if (!printed_version++)
4175 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4176
4177 /* allocate host */
4178 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4179
4180 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4181 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4182 if (!host || !hpriv)
4183 return -ENOMEM;
4184 host->private_data = hpriv;
4185 hpriv->n_ports = n_ports;
4186
4187 /* acquire resources */
4188 rc = pcim_enable_device(pdev);
4189 if (rc)
4190 return rc;
4191
4192 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4193 if (rc == -EBUSY)
4194 pcim_pin_device(pdev);
4195 if (rc)
4196 return rc;
4197 host->iomap = pcim_iomap_table(pdev);
4198 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4199
4200 rc = pci_go_64(pdev);
4201 if (rc)
4202 return rc;
4203
4204 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4205 if (rc)
4206 return rc;
4207
4208 /* initialize adapter */
4209 rc = mv_init_host(host, board_idx);
4210 if (rc)
4211 return rc;
4212
4213 /* Enable message-switched interrupts, if requested */
4214 if (msi && pci_enable_msi(pdev) == 0)
4215 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4216
4217 mv_dump_pci_cfg(pdev, 0x68);
4218 mv_print_info(host);
4219
4220 pci_set_master(pdev);
4221 pci_try_set_mwi(pdev);
4222 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4223 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4224 }
4225 #endif
4226
4227 static int mv_platform_probe(struct platform_device *pdev);
4228 static int __devexit mv_platform_remove(struct platform_device *pdev);
4229
4230 static int __init mv_init(void)
4231 {
4232 int rc = -ENODEV;
4233 #ifdef CONFIG_PCI
4234 rc = pci_register_driver(&mv_pci_driver);
4235 if (rc < 0)
4236 return rc;
4237 #endif
4238 rc = platform_driver_register(&mv_platform_driver);
4239
4240 #ifdef CONFIG_PCI
4241 if (rc < 0)
4242 pci_unregister_driver(&mv_pci_driver);
4243 #endif
4244 return rc;
4245 }
4246
4247 static void __exit mv_exit(void)
4248 {
4249 #ifdef CONFIG_PCI
4250 pci_unregister_driver(&mv_pci_driver);
4251 #endif
4252 platform_driver_unregister(&mv_platform_driver);
4253 }
4254
4255 MODULE_AUTHOR("Brett Russ");
4256 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4257 MODULE_LICENSE("GPL");
4258 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4259 MODULE_VERSION(DRV_VERSION);
4260 MODULE_ALIAS("platform:" DRV_NAME);
4261
4262 module_init(mv_init);
4263 module_exit(mv_exit);
Verdex Pro support