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netxen: add receive side scaling (rss) support
[linux-2.6/verdex.git] / drivers / net / netxen / netxen_nic_hw.c
blobc89c791e281cb1b972262e45f178252edf4b4598
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33 #include "netxen_nic_phan_reg.h"
34
35 #include <linux/firmware.h>
36 #include <net/ip.h>
37
38 #define MASK(n) ((1ULL<<(n))-1)
39 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
40 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
41 #define MS_WIN(addr) (addr & 0x0ffc0000)
42
43 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
44
45 #define CRB_BLK(off) ((off >> 20) & 0x3f)
46 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
47 #define CRB_WINDOW_2M (0x130060)
48 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49 #define CRB_INDIRECT_2M (0x1e0000UL)
50
51 #define CRB_WIN_LOCK_TIMEOUT 100000000
52 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207 };
208
209 /*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212 static unsigned crb_hub_agt[64] =
213 {
214 0,
215 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
216 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
217 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
218 0,
219 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
220 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
221 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
223 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
224 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
226 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
227 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
228 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
229 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
230 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
231 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
233 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
241 0,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
243 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
246 0,
247 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
248 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
249 0,
250 0,
251 0,
252 0,
253 0,
254 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
255 0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
266 0,
267 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
269 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
270 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
271 0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
273 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
275 0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
277 0,
278 };
279
280 /* PCI Windowing for DDR regions. */
281
282 #define ADDR_IN_RANGE(addr, low, high) \
283 (((addr) <= (high)) && ((addr) >= (low)))
284
285 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
286
287 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
288 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
289 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
290 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
291
292 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
293
294 int netxen_nic_set_mac(struct net_device *netdev, void *p)
295 {
296 struct netxen_adapter *adapter = netdev_priv(netdev);
297 struct sockaddr *addr = p;
298
299 if (netif_running(netdev))
300 return -EBUSY;
301
302 if (!is_valid_ether_addr(addr->sa_data))
303 return -EADDRNOTAVAIL;
304
305 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
306
307 /* For P3, MAC addr is not set in NIU */
308 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
309 if (adapter->macaddr_set)
310 adapter->macaddr_set(adapter, addr->sa_data);
311
312 return 0;
313 }
314
315 #define NETXEN_UNICAST_ADDR(port, index) \
316 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
317 #define NETXEN_MCAST_ADDR(port, index) \
318 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
319 #define MAC_HI(addr) \
320 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
321 #define MAC_LO(addr) \
322 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
323
324 static int
325 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
326 {
327 u32 val = 0;
328 u16 port = adapter->physical_port;
329 u8 *addr = adapter->netdev->dev_addr;
330
331 if (adapter->mc_enabled)
332 return 0;
333
334 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
335 val |= (1UL << (28+port));
336 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
337
338 /* add broadcast addr to filter */
339 val = 0xffffff;
340 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_UNICAST_ADDR(port, 0)+4, val);
343
344 /* add station addr to filter */
345 val = MAC_HI(addr);
346 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
347 val = MAC_LO(addr);
348 netxen_crb_writelit_adapter(adapter,
349 NETXEN_UNICAST_ADDR(port, 1)+4, val);
350
351 adapter->mc_enabled = 1;
352 return 0;
353 }
354
355 static int
356 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
357 {
358 u32 val = 0;
359 u16 port = adapter->physical_port;
360 u8 *addr = adapter->netdev->dev_addr;
361
362 if (!adapter->mc_enabled)
363 return 0;
364
365 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
366 val &= ~(1UL << (28+port));
367 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
368
369 val = MAC_HI(addr);
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 val = MAC_LO(addr);
372 netxen_crb_writelit_adapter(adapter,
373 NETXEN_UNICAST_ADDR(port, 0)+4, val);
374
375 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
377
378 adapter->mc_enabled = 0;
379 return 0;
380 }
381
382 static int
383 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
384 int index, u8 *addr)
385 {
386 u32 hi = 0, lo = 0;
387 u16 port = adapter->physical_port;
388
389 lo = MAC_LO(addr);
390 hi = MAC_HI(addr);
391
392 netxen_crb_writelit_adapter(adapter,
393 NETXEN_MCAST_ADDR(port, index), hi);
394 netxen_crb_writelit_adapter(adapter,
395 NETXEN_MCAST_ADDR(port, index)+4, lo);
396
397 return 0;
398 }
399
400 void netxen_p2_nic_set_multi(struct net_device *netdev)
401 {
402 struct netxen_adapter *adapter = netdev_priv(netdev);
403 struct dev_mc_list *mc_ptr;
404 u8 null_addr[6];
405 int index = 0;
406
407 memset(null_addr, 0, 6);
408
409 if (netdev->flags & IFF_PROMISC) {
410
411 adapter->set_promisc(adapter,
412 NETXEN_NIU_PROMISC_MODE);
413
414 /* Full promiscuous mode */
415 netxen_nic_disable_mcast_filter(adapter);
416
417 return;
418 }
419
420 if (netdev->mc_count == 0) {
421 adapter->set_promisc(adapter,
422 NETXEN_NIU_NON_PROMISC_MODE);
423 netxen_nic_disable_mcast_filter(adapter);
424 return;
425 }
426
427 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
428 if (netdev->flags & IFF_ALLMULTI ||
429 netdev->mc_count > adapter->max_mc_count) {
430 netxen_nic_disable_mcast_filter(adapter);
431 return;
432 }
433
434 netxen_nic_enable_mcast_filter(adapter);
435
436 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
437 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
438
439 if (index != netdev->mc_count)
440 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
441 netxen_nic_driver_name, netdev->name);
442
443 /* Clear out remaining addresses */
444 for (; index < adapter->max_mc_count; index++)
445 netxen_nic_set_mcast_addr(adapter, index, null_addr);
446 }
447
448 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
449 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
450 {
451 nx_mac_list_t *cur, *prev;
452
453 /* if in del_list, move it to adapter->mac_list */
454 for (cur = *del_list, prev = NULL; cur;) {
455 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
456 if (prev == NULL)
457 *del_list = cur->next;
458 else
459 prev->next = cur->next;
460 cur->next = adapter->mac_list;
461 adapter->mac_list = cur;
462 return 0;
463 }
464 prev = cur;
465 cur = cur->next;
466 }
467
468 /* make sure to add each mac address only once */
469 for (cur = adapter->mac_list; cur; cur = cur->next) {
470 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
471 return 0;
472 }
473 /* not in del_list, create new entry and add to add_list */
474 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
475 if (cur == NULL) {
476 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
477 "not work properly from now.\n", __func__);
478 return -1;
479 }
480
481 memcpy(cur->mac_addr, addr, ETH_ALEN);
482 cur->next = *add_list;
483 *add_list = cur;
484 return 0;
485 }
486
487 static int
488 netxen_send_cmd_descs(struct netxen_adapter *adapter,
489 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
490 {
491 uint32_t i, producer;
492 struct netxen_cmd_buffer *pbuf;
493 struct cmd_desc_type0 *cmd_desc;
494
495 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
496 printk(KERN_WARNING "%s: Too many command descriptors in a "
497 "request\n", __func__);
498 return -EINVAL;
499 }
500
501 i = 0;
502
503 netif_tx_lock_bh(adapter->netdev);
504
505 producer = adapter->cmd_producer;
506 do {
507 cmd_desc = &cmd_desc_arr[i];
508
509 pbuf = &adapter->cmd_buf_arr[producer];
510 pbuf->skb = NULL;
511 pbuf->frag_count = 0;
512
513 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
514 memcpy(&adapter->ahw.cmd_desc_head[producer],
515 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
516
517 producer = get_next_index(producer,
518 adapter->num_txd);
519 i++;
520
521 } while (i != nr_elements);
522
523 adapter->cmd_producer = producer;
524
525 /* write producer index to start the xmit */
526
527 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
528
529 netif_tx_unlock_bh(adapter->netdev);
530
531 return 0;
532 }
533
534 static int nx_p3_sre_macaddr_change(struct net_device *dev,
535 u8 *addr, unsigned op)
536 {
537 struct netxen_adapter *adapter = netdev_priv(dev);
538 nx_nic_req_t req;
539 nx_mac_req_t *mac_req;
540 u64 word;
541 int rv;
542
543 memset(&req, 0, sizeof(nx_nic_req_t));
544 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
545
546 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
547 req.req_hdr = cpu_to_le64(word);
548
549 mac_req = (nx_mac_req_t *)&req.words[0];
550 mac_req->op = op;
551 memcpy(mac_req->mac_addr, addr, 6);
552
553 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
554 if (rv != 0) {
555 printk(KERN_ERR "ERROR. Could not send mac update\n");
556 return rv;
557 }
558
559 return 0;
560 }
561
562 void netxen_p3_nic_set_multi(struct net_device *netdev)
563 {
564 struct netxen_adapter *adapter = netdev_priv(netdev);
565 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
566 struct dev_mc_list *mc_ptr;
567 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
568 u32 mode = VPORT_MISS_MODE_DROP;
569
570 del_list = adapter->mac_list;
571 adapter->mac_list = NULL;
572
573 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
574 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
575
576 if (netdev->flags & IFF_PROMISC) {
577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
578 goto send_fw_cmd;
579 }
580
581 if ((netdev->flags & IFF_ALLMULTI) ||
582 (netdev->mc_count > adapter->max_mc_count)) {
583 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
584 goto send_fw_cmd;
585 }
586
587 if (netdev->mc_count > 0) {
588 for (mc_ptr = netdev->mc_list; mc_ptr;
589 mc_ptr = mc_ptr->next) {
590 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
591 &add_list, &del_list);
592 }
593 }
594
595 send_fw_cmd:
596 adapter->set_promisc(adapter, mode);
597 for (cur = del_list; cur;) {
598 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
599 next = cur->next;
600 kfree(cur);
601 cur = next;
602 }
603 for (cur = add_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
605 next = cur->next;
606 cur->next = adapter->mac_list;
607 adapter->mac_list = cur;
608 cur = next;
609 }
610 }
611
612 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
613 {
614 nx_nic_req_t req;
615 u64 word;
616
617 memset(&req, 0, sizeof(nx_nic_req_t));
618
619 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
620
621 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
622 ((u64)adapter->portnum << 16);
623 req.req_hdr = cpu_to_le64(word);
624
625 req.words[0] = cpu_to_le64(mode);
626
627 return netxen_send_cmd_descs(adapter,
628 (struct cmd_desc_type0 *)&req, 1);
629 }
630
631 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
632 {
633 nx_mac_list_t *cur, *next;
634
635 cur = adapter->mac_list;
636
637 while (cur) {
638 next = cur->next;
639 kfree(cur);
640 cur = next;
641 }
642 }
643
644 #define NETXEN_CONFIG_INTR_COALESCE 3
645
646 /*
647 * Send the interrupt coalescing parameter set by ethtool to the card.
648 */
649 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
650 {
651 nx_nic_req_t req;
652 u64 word;
653 int rv;
654
655 memset(&req, 0, sizeof(nx_nic_req_t));
656
657 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
658
659 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
660 req.req_hdr = cpu_to_le64(word);
661
662 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
663
664 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
665 if (rv != 0) {
666 printk(KERN_ERR "ERROR. Could not send "
667 "interrupt coalescing parameters\n");
668 }
669
670 return rv;
671 }
672
673 #define RSS_HASHTYPE_IP_TCP 0x3
674
675 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
676 {
677 nx_nic_req_t req;
678 u64 word;
679 int i, rv;
680
681 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
682 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
683 0x255b0ec26d5a56daULL };
684
685
686 memset(&req, 0, sizeof(nx_nic_req_t));
687 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
688
689 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
690 req.req_hdr = cpu_to_le64(word);
691
692 /*
693 * RSS request:
694 * bits 3-0: hash_method
695 * 5-4: hash_type_ipv4
696 * 7-6: hash_type_ipv6
697 * 8: enable
698 * 9: use indirection table
699 * 47-10: reserved
700 * 63-48: indirection table mask
701 */
702 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
703 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
704 ((u64)(enable & 0x1) << 8) |
705 ((0x7ULL) << 48);
706 req.words[0] = cpu_to_le64(word);
707 for (i = 0; i < 5; i++)
708 req.words[i+1] = cpu_to_le64(key[i]);
709
710
711 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
712 if (rv != 0) {
713 printk(KERN_ERR "%s: could not configure RSS\n",
714 adapter->netdev->name);
715 }
716
717 return rv;
718 }
719
720 /*
721 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
722 * @returns 0 on success, negative on failure
723 */
724
725 #define MTU_FUDGE_FACTOR 100
726
727 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
728 {
729 struct netxen_adapter *adapter = netdev_priv(netdev);
730 int max_mtu;
731 int rc = 0;
732
733 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
734 max_mtu = P3_MAX_MTU;
735 else
736 max_mtu = P2_MAX_MTU;
737
738 if (mtu > max_mtu) {
739 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
740 netdev->name, max_mtu);
741 return -EINVAL;
742 }
743
744 if (adapter->set_mtu)
745 rc = adapter->set_mtu(adapter, mtu);
746
747 if (!rc)
748 netdev->mtu = mtu;
749
750 return rc;
751 }
752
753 int netxen_is_flash_supported(struct netxen_adapter *adapter)
754 {
755 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
756 int addr, val01, val02, i, j;
757
758 /* if the flash size less than 4Mb, make huge war cry and die */
759 for (j = 1; j < 4; j++) {
760 addr = j * NETXEN_NIC_WINDOW_MARGIN;
761 for (i = 0; i < ARRAY_SIZE(locs); i++) {
762 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
763 && netxen_rom_fast_read(adapter, (addr + locs[i]),
764 &val02) == 0) {
765 if (val01 == val02)
766 return -1;
767 } else
768 return -1;
769 }
770 }
771
772 return 0;
773 }
774
775 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
776 int size, __le32 * buf)
777 {
778 int i, v, addr;
779 __le32 *ptr32;
780
781 addr = base;
782 ptr32 = buf;
783 for (i = 0; i < size / sizeof(u32); i++) {
784 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
785 return -1;
786 *ptr32 = cpu_to_le32(v);
787 ptr32++;
788 addr += sizeof(u32);
789 }
790 if ((char *)buf + size > (char *)ptr32) {
791 __le32 local;
792 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
793 return -1;
794 local = cpu_to_le32(v);
795 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
796 }
797
798 return 0;
799 }
800
801 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
802 {
803 __le32 *pmac = (__le32 *) mac;
804 u32 offset;
805
806 offset = NETXEN_USER_START +
807 offsetof(struct netxen_new_user_info, mac_addr) +
808 adapter->portnum * sizeof(u64);
809
810 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
811 return -1;
812
813 if (*mac == cpu_to_le64(~0ULL)) {
814
815 offset = NETXEN_USER_START_OLD +
816 offsetof(struct netxen_user_old_info, mac_addr) +
817 adapter->portnum * sizeof(u64);
818
819 if (netxen_get_flash_block(adapter,
820 offset, sizeof(u64), pmac) == -1)
821 return -1;
822
823 if (*mac == cpu_to_le64(~0ULL))
824 return -1;
825 }
826 return 0;
827 }
828
829 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
830 {
831 uint32_t crbaddr, mac_hi, mac_lo;
832 int pci_func = adapter->ahw.pci_func;
833
834 crbaddr = CRB_MAC_BLOCK_START +
835 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
836
837 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
838 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
839
840 if (pci_func & 1)
841 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
842 else
843 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
844
845 return 0;
846 }
847
848 #define CRB_WIN_LOCK_TIMEOUT 100000000
849
850 static int crb_win_lock(struct netxen_adapter *adapter)
851 {
852 int done = 0, timeout = 0;
853
854 while (!done) {
855 /* acquire semaphore3 from PCI HW block */
856 adapter->hw_read_wx(adapter,
857 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
858 if (done == 1)
859 break;
860 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
861 return -1;
862 timeout++;
863 udelay(1);
864 }
865 netxen_crb_writelit_adapter(adapter,
866 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
867 return 0;
868 }
869
870 static void crb_win_unlock(struct netxen_adapter *adapter)
871 {
872 int val;
873
874 adapter->hw_read_wx(adapter,
875 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
876 }
877
878 /*
879 * Changes the CRB window to the specified window.
880 */
881 void
882 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
883 {
884 void __iomem *offset;
885 u32 tmp;
886 int count = 0;
887 uint8_t func = adapter->ahw.pci_func;
888
889 if (adapter->curr_window == wndw)
890 return;
891 /*
892 * Move the CRB window.
893 * We need to write to the "direct access" region of PCI
894 * to avoid a race condition where the window register has
895 * not been successfully written across CRB before the target
896 * register address is received by PCI. The direct region bypasses
897 * the CRB bus.
898 */
899 offset = PCI_OFFSET_SECOND_RANGE(adapter,
900 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
901
902 if (wndw & 0x1)
903 wndw = NETXEN_WINDOW_ONE;
904
905 writel(wndw, offset);
906
907 /* MUST make sure window is set before we forge on... */
908 while ((tmp = readl(offset)) != wndw) {
909 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
910 "registered properly: 0x%08x.\n",
911 netxen_nic_driver_name, __func__, tmp);
912 mdelay(1);
913 if (count >= 10)
914 break;
915 count++;
916 }
917
918 if (wndw == NETXEN_WINDOW_ONE)
919 adapter->curr_window = 1;
920 else
921 adapter->curr_window = 0;
922 }
923
924 /*
925 * Return -1 if off is not valid,
926 * 1 if window access is needed. 'off' is set to offset from
927 * CRB space in 128M pci map
928 * 0 if no window access is needed. 'off' is set to 2M addr
929 * In: 'off' is offset from base in 128M pci map
930 */
931 static int
932 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
933 ulong *off, int len)
934 {
935 unsigned long end = *off + len;
936 crb_128M_2M_sub_block_map_t *m;
937
938
939 if (*off >= NETXEN_CRB_MAX)
940 return -1;
941
942 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
943 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
944 (ulong)adapter->ahw.pci_base0;
945 return 0;
946 }
947
948 if (*off < NETXEN_PCI_CRBSPACE)
949 return -1;
950
951 *off -= NETXEN_PCI_CRBSPACE;
952 end = *off + len;
953
954 /*
955 * Try direct map
956 */
957 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
958
959 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
960 *off = *off + m->start_2M - m->start_128M +
961 (ulong)adapter->ahw.pci_base0;
962 return 0;
963 }
964
965 /*
966 * Not in direct map, use crb window
967 */
968 return 1;
969 }
970
971 /*
972 * In: 'off' is offset from CRB space in 128M pci map
973 * Out: 'off' is 2M pci map addr
974 * side effect: lock crb window
975 */
976 static void
977 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
978 {
979 u32 win_read;
980
981 adapter->crb_win = CRB_HI(*off);
982 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
983 /*
984 * Read back value to make sure write has gone through before trying
985 * to use it.
986 */
987 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
988 if (win_read != adapter->crb_win) {
989 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
990 "Read crbwin (0x%x), off=0x%lx\n",
991 __func__, adapter->crb_win, win_read, *off);
992 }
993 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
994 (ulong)adapter->ahw.pci_base0;
995 }
996
997 static int
998 netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
999 const struct firmware *fw)
1000 {
1001 u64 *ptr64;
1002 u32 i, flashaddr, size;
1003 struct pci_dev *pdev = adapter->pdev;
1004
1005 if (fw)
1006 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
1007 else
1008 dev_info(&pdev->dev, "loading firmware from flash\n");
1009
1010 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1011 adapter->pci_write_normalize(adapter,
1012 NETXEN_ROMUSB_GLB_CAS_RST, 1);
1013
1014 if (fw) {
1015 __le64 data;
1016
1017 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1018
1019 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
1020 flashaddr = NETXEN_BOOTLD_START;
1021
1022 for (i = 0; i < size; i++) {
1023 data = cpu_to_le64(ptr64[i]);
1024 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
1025 flashaddr += 8;
1026 }
1027
1028 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
1029 size = (__force u32)cpu_to_le32(size) / 8;
1030
1031 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
1032 flashaddr = NETXEN_IMAGE_START;
1033
1034 for (i = 0; i < size; i++) {
1035 data = cpu_to_le64(ptr64[i]);
1036
1037 if (adapter->pci_mem_write(adapter,
1038 flashaddr, &data, 8))
1039 return -EIO;
1040
1041 flashaddr += 8;
1042 }
1043 } else {
1044 u32 data;
1045
1046 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1047 flashaddr = NETXEN_BOOTLD_START;
1048
1049 for (i = 0; i < size; i++) {
1050 if (netxen_rom_fast_read(adapter,
1051 flashaddr, (int *)&data) != 0)
1052 return -EIO;
1053
1054 if (adapter->pci_mem_write(adapter,
1055 flashaddr, &data, 4))
1056 return -EIO;
1057
1058 flashaddr += 4;
1059 }
1060 }
1061 msleep(1);
1062
1063 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1064 adapter->pci_write_normalize(adapter,
1065 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1066 else {
1067 adapter->pci_write_normalize(adapter,
1068 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1069 adapter->pci_write_normalize(adapter,
1070 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1071 }
1072
1073 return 0;
1074 }
1075
1076 static int
1077 netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1078 const struct firmware *fw)
1079 {
1080 __le32 val;
1081 u32 major, minor, build, ver, min_ver, bios;
1082 struct pci_dev *pdev = adapter->pdev;
1083
1084 if (fw->size < NX_FW_MIN_SIZE)
1085 return -EINVAL;
1086
1087 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1088 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1089 return -EINVAL;
1090
1091 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1092 major = (__force u32)val & 0xff;
1093 minor = ((__force u32)val >> 8) & 0xff;
1094 build = (__force u32)val >> 16;
1095
1096 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1097 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1098 else
1099 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1100
1101 ver = NETXEN_VERSION_CODE(major, minor, build);
1102
1103 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1104 dev_err(&pdev->dev,
1105 "%s: firmware version %d.%d.%d unsupported\n",
1106 fwname, major, minor, build);
1107 return -EINVAL;
1108 }
1109
1110 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1111 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1112 if ((__force u32)val != bios) {
1113 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1114 fwname);
1115 return -EINVAL;
1116 }
1117
1118 /* check if flashed firmware is newer */
1119 if (netxen_rom_fast_read(adapter,
1120 NX_FW_VERSION_OFFSET, (int *)&val))
1121 return -EIO;
1122 major = (__force u32)val & 0xff;
1123 minor = ((__force u32)val >> 8) & 0xff;
1124 build = (__force u32)val >> 16;
1125 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1126 return -EINVAL;
1127
1128 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc),
1129 NETXEN_BDINFO_MAGIC);
1130 return 0;
1131 }
1132
1133 int netxen_load_firmware(struct netxen_adapter *adapter)
1134 {
1135 u32 capability, flashed_ver;
1136 const struct firmware *fw;
1137 char *fw_name = NULL;
1138 struct pci_dev *pdev = adapter->pdev;
1139 int rc = 0;
1140
1141 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1142 fw_name = NX_P2_MN_ROMIMAGE;
1143 goto request_fw;
1144 }
1145
1146 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1147 fw_name = NX_P3_CT_ROMIMAGE;
1148 goto request_fw;
1149 }
1150
1151 request_mn:
1152 capability = 0;
1153
1154 netxen_rom_fast_read(adapter,
1155 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1156 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1157 adapter->hw_read_wx(adapter,
1158 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1159 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1160 fw_name = NX_P3_MN_ROMIMAGE;
1161 goto request_fw;
1162 }
1163 }
1164
1165 request_fw:
1166 rc = request_firmware(&fw, fw_name, &pdev->dev);
1167 if (rc != 0) {
1168 if (fw_name == NX_P3_CT_ROMIMAGE) {
1169 msleep(1);
1170 goto request_mn;
1171 }
1172
1173 fw = NULL;
1174 goto load_fw;
1175 }
1176
1177 rc = netxen_validate_firmware(adapter, fw_name, fw);
1178 if (rc != 0) {
1179 release_firmware(fw);
1180
1181 if (fw_name == NX_P3_CT_ROMIMAGE) {
1182 msleep(1);
1183 goto request_mn;
1184 }
1185
1186 fw = NULL;
1187 }
1188
1189 load_fw:
1190 rc = netxen_do_load_firmware(adapter, fw_name, fw);
1191
1192 if (fw)
1193 release_firmware(fw);
1194 return rc;
1195 }
1196
1197 int
1198 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1199 ulong off, void *data, int len)
1200 {
1201 void __iomem *addr;
1202
1203 BUG_ON(len != 4);
1204
1205 if (ADDR_IN_WINDOW1(off)) {
1206 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1207 } else { /* Window 0 */
1208 addr = pci_base_offset(adapter, off);
1209 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1210 }
1211
1212 if (!addr) {
1213 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1214 return 1;
1215 }
1216
1217 writel(*(u32 *) data, addr);
1218
1219 if (!ADDR_IN_WINDOW1(off))
1220 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1221
1222 return 0;
1223 }
1224
1225 int
1226 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1227 ulong off, void *data, int len)
1228 {
1229 void __iomem *addr;
1230
1231 BUG_ON(len != 4);
1232
1233 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1234 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1235 } else { /* Window 0 */
1236 addr = pci_base_offset(adapter, off);
1237 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1238 }
1239
1240 if (!addr) {
1241 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1242 return 1;
1243 }
1244
1245 *(u32 *)data = readl(addr);
1246
1247 if (!ADDR_IN_WINDOW1(off))
1248 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1249
1250 return 0;
1251 }
1252
1253 int
1254 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1255 ulong off, void *data, int len)
1256 {
1257 unsigned long flags = 0;
1258 int rv;
1259
1260 BUG_ON(len != 4);
1261
1262 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1263
1264 if (rv == -1) {
1265 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1266 __func__, off);
1267 dump_stack();
1268 return -1;
1269 }
1270
1271 if (rv == 1) {
1272 write_lock_irqsave(&adapter->adapter_lock, flags);
1273 crb_win_lock(adapter);
1274 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1275 writel(*(uint32_t *)data, (void __iomem *)off);
1276 crb_win_unlock(adapter);
1277 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1278 } else
1279 writel(*(uint32_t *)data, (void __iomem *)off);
1280
1281
1282 return 0;
1283 }
1284
1285 int
1286 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1287 ulong off, void *data, int len)
1288 {
1289 unsigned long flags = 0;
1290 int rv;
1291
1292 BUG_ON(len != 4);
1293
1294 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1295
1296 if (rv == -1) {
1297 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1298 __func__, off);
1299 dump_stack();
1300 return -1;
1301 }
1302
1303 if (rv == 1) {
1304 write_lock_irqsave(&adapter->adapter_lock, flags);
1305 crb_win_lock(adapter);
1306 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1307 *(uint32_t *)data = readl((void __iomem *)off);
1308 crb_win_unlock(adapter);
1309 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1310 } else
1311 *(uint32_t *)data = readl((void __iomem *)off);
1312
1313 return 0;
1314 }
1315
1316 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1317 {
1318 adapter->hw_write_wx(adapter, off, &val, 4);
1319 }
1320
1321 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1322 {
1323 int val;
1324 adapter->hw_read_wx(adapter, off, &val, 4);
1325 return val;
1326 }
1327
1328 /* Change the window to 0, write and change back to window 1. */
1329 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1330 {
1331 adapter->hw_write_wx(adapter, index, &value, 4);
1332 }
1333
1334 /* Change the window to 0, read and change back to window 1. */
1335 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1336 {
1337 adapter->hw_read_wx(adapter, index, value, 4);
1338 }
1339
1340 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1341 {
1342 adapter->hw_write_wx(adapter, index, &value, 4);
1343 }
1344
1345 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1346 {
1347 adapter->hw_read_wx(adapter, index, value, 4);
1348 }
1349
1350 /*
1351 * check memory access boundary.
1352 * used by test agent. support ddr access only for now
1353 */
1354 static unsigned long
1355 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1356 unsigned long long addr, int size)
1357 {
1358 if (!ADDR_IN_RANGE(addr,
1359 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1360 !ADDR_IN_RANGE(addr+size-1,
1361 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1362 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1363 return 0;
1364 }
1365
1366 return 1;
1367 }
1368
1369 static int netxen_pci_set_window_warning_count;
1370
1371 unsigned long
1372 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1373 unsigned long long addr)
1374 {
1375 void __iomem *offset;
1376 int window;
1377 unsigned long long qdr_max;
1378 uint8_t func = adapter->ahw.pci_func;
1379
1380 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1381 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1382 } else {
1383 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1384 }
1385
1386 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1387 /* DDR network side */
1388 addr -= NETXEN_ADDR_DDR_NET;
1389 window = (addr >> 25) & 0x3ff;
1390 if (adapter->ahw.ddr_mn_window != window) {
1391 adapter->ahw.ddr_mn_window = window;
1392 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1393 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1394 writel(window, offset);
1395 /* MUST make sure window is set before we forge on... */
1396 readl(offset);
1397 }
1398 addr -= (window * NETXEN_WINDOW_ONE);
1399 addr += NETXEN_PCI_DDR_NET;
1400 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1401 addr -= NETXEN_ADDR_OCM0;
1402 addr += NETXEN_PCI_OCM0;
1403 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1404 addr -= NETXEN_ADDR_OCM1;
1405 addr += NETXEN_PCI_OCM1;
1406 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1407 /* QDR network side */
1408 addr -= NETXEN_ADDR_QDR_NET;
1409 window = (addr >> 22) & 0x3f;
1410 if (adapter->ahw.qdr_sn_window != window) {
1411 adapter->ahw.qdr_sn_window = window;
1412 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1413 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1414 writel((window << 22), offset);
1415 /* MUST make sure window is set before we forge on... */
1416 readl(offset);
1417 }
1418 addr -= (window * 0x400000);
1419 addr += NETXEN_PCI_QDR_NET;
1420 } else {
1421 /*
1422 * peg gdb frequently accesses memory that doesn't exist,
1423 * this limits the chit chat so debugging isn't slowed down.
1424 */
1425 if ((netxen_pci_set_window_warning_count++ < 8)
1426 || (netxen_pci_set_window_warning_count % 64 == 0))
1427 printk("%s: Warning:netxen_nic_pci_set_window()"
1428 " Unknown address range!\n",
1429 netxen_nic_driver_name);
1430 addr = -1UL;
1431 }
1432 return addr;
1433 }
1434
1435 /*
1436 * Note : only 32-bit writes!
1437 */
1438 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1439 u64 off, u32 data)
1440 {
1441 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1442 return 0;
1443 }
1444
1445 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1446 {
1447 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1448 }
1449
1450 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1451 u64 off, u32 data)
1452 {
1453 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1454 }
1455
1456 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1457 {
1458 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1459 }
1460
1461 unsigned long
1462 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1463 unsigned long long addr)
1464 {
1465 int window;
1466 u32 win_read;
1467
1468 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1469 /* DDR network side */
1470 window = MN_WIN(addr);
1471 adapter->ahw.ddr_mn_window = window;
1472 adapter->hw_write_wx(adapter,
1473 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1474 &window, 4);
1475 adapter->hw_read_wx(adapter,
1476 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1477 &win_read, 4);
1478 if ((win_read << 17) != window) {
1479 printk(KERN_INFO "Written MNwin (0x%x) != "
1480 "Read MNwin (0x%x)\n", window, win_read);
1481 }
1482 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1483 } else if (ADDR_IN_RANGE(addr,
1484 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1485 if ((addr & 0x00ff800) == 0xff800) {
1486 printk("%s: QM access not handled.\n", __func__);
1487 addr = -1UL;
1488 }
1489
1490 window = OCM_WIN(addr);
1491 adapter->ahw.ddr_mn_window = window;
1492 adapter->hw_write_wx(adapter,
1493 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1494 &window, 4);
1495 adapter->hw_read_wx(adapter,
1496 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1497 &win_read, 4);
1498 if ((win_read >> 7) != window) {
1499 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1500 "Read OCMwin (0x%x)\n",
1501 __func__, window, win_read);
1502 }
1503 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1504
1505 } else if (ADDR_IN_RANGE(addr,
1506 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1507 /* QDR network side */
1508 window = MS_WIN(addr);
1509 adapter->ahw.qdr_sn_window = window;
1510 adapter->hw_write_wx(adapter,
1511 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1512 &window, 4);
1513 adapter->hw_read_wx(adapter,
1514 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1515 &win_read, 4);
1516 if (win_read != window) {
1517 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1518 "Read MSwin (0x%x)\n",
1519 __func__, window, win_read);
1520 }
1521 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1522
1523 } else {
1524 /*
1525 * peg gdb frequently accesses memory that doesn't exist,
1526 * this limits the chit chat so debugging isn't slowed down.
1527 */
1528 if ((netxen_pci_set_window_warning_count++ < 8)
1529 || (netxen_pci_set_window_warning_count%64 == 0)) {
1530 printk("%s: Warning:%s Unknown address range!\n",
1531 __func__, netxen_nic_driver_name);
1532 }
1533 addr = -1UL;
1534 }
1535 return addr;
1536 }
1537
1538 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1539 unsigned long long addr)
1540 {
1541 int window;
1542 unsigned long long qdr_max;
1543
1544 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1545 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1546 else
1547 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1548
1549 if (ADDR_IN_RANGE(addr,
1550 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1551 /* DDR network side */
1552 BUG(); /* MN access can not come here */
1553 } else if (ADDR_IN_RANGE(addr,
1554 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1555 return 1;
1556 } else if (ADDR_IN_RANGE(addr,
1557 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1558 return 1;
1559 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1560 /* QDR network side */
1561 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1562 if (adapter->ahw.qdr_sn_window == window)
1563 return 1;
1564 }
1565
1566 return 0;
1567 }
1568
1569 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1570 u64 off, void *data, int size)
1571 {
1572 unsigned long flags;
1573 void __iomem *addr, *mem_ptr = NULL;
1574 int ret = 0;
1575 u64 start;
1576 unsigned long mem_base;
1577 unsigned long mem_page;
1578
1579 write_lock_irqsave(&adapter->adapter_lock, flags);
1580
1581 /*
1582 * If attempting to access unknown address or straddle hw windows,
1583 * do not access.
1584 */
1585 start = adapter->pci_set_window(adapter, off);
1586 if ((start == -1UL) ||
1587 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1588 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1589 printk(KERN_ERR "%s out of bound pci memory access. "
1590 "offset is 0x%llx\n", netxen_nic_driver_name,
1591 (unsigned long long)off);
1592 return -1;
1593 }
1594
1595 addr = pci_base_offset(adapter, start);
1596 if (!addr) {
1597 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1598 mem_base = pci_resource_start(adapter->pdev, 0);
1599 mem_page = start & PAGE_MASK;
1600 /* Map two pages whenever user tries to access addresses in two
1601 consecutive pages.
1602 */
1603 if (mem_page != ((start + size - 1) & PAGE_MASK))
1604 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1605 else
1606 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1607 if (mem_ptr == NULL) {
1608 *(uint8_t *)data = 0;
1609 return -1;
1610 }
1611 addr = mem_ptr;
1612 addr += start & (PAGE_SIZE - 1);
1613 write_lock_irqsave(&adapter->adapter_lock, flags);
1614 }
1615
1616 switch (size) {
1617 case 1:
1618 *(uint8_t *)data = readb(addr);
1619 break;
1620 case 2:
1621 *(uint16_t *)data = readw(addr);
1622 break;
1623 case 4:
1624 *(uint32_t *)data = readl(addr);
1625 break;
1626 case 8:
1627 *(uint64_t *)data = readq(addr);
1628 break;
1629 default:
1630 ret = -1;
1631 break;
1632 }
1633 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1634
1635 if (mem_ptr)
1636 iounmap(mem_ptr);
1637 return ret;
1638 }
1639
1640 static int
1641 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1642 void *data, int size)
1643 {
1644 unsigned long flags;
1645 void __iomem *addr, *mem_ptr = NULL;
1646 int ret = 0;
1647 u64 start;
1648 unsigned long mem_base;
1649 unsigned long mem_page;
1650
1651 write_lock_irqsave(&adapter->adapter_lock, flags);
1652
1653 /*
1654 * If attempting to access unknown address or straddle hw windows,
1655 * do not access.
1656 */
1657 start = adapter->pci_set_window(adapter, off);
1658 if ((start == -1UL) ||
1659 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1660 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1661 printk(KERN_ERR "%s out of bound pci memory access. "
1662 "offset is 0x%llx\n", netxen_nic_driver_name,
1663 (unsigned long long)off);
1664 return -1;
1665 }
1666
1667 addr = pci_base_offset(adapter, start);
1668 if (!addr) {
1669 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1670 mem_base = pci_resource_start(adapter->pdev, 0);
1671 mem_page = start & PAGE_MASK;
1672 /* Map two pages whenever user tries to access addresses in two
1673 * consecutive pages.
1674 */
1675 if (mem_page != ((start + size - 1) & PAGE_MASK))
1676 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1677 else
1678 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1679 if (mem_ptr == NULL)
1680 return -1;
1681 addr = mem_ptr;
1682 addr += start & (PAGE_SIZE - 1);
1683 write_lock_irqsave(&adapter->adapter_lock, flags);
1684 }
1685
1686 switch (size) {
1687 case 1:
1688 writeb(*(uint8_t *)data, addr);
1689 break;
1690 case 2:
1691 writew(*(uint16_t *)data, addr);
1692 break;
1693 case 4:
1694 writel(*(uint32_t *)data, addr);
1695 break;
1696 case 8:
1697 writeq(*(uint64_t *)data, addr);
1698 break;
1699 default:
1700 ret = -1;
1701 break;
1702 }
1703 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1704 if (mem_ptr)
1705 iounmap(mem_ptr);
1706 return ret;
1707 }
1708
1709 #define MAX_CTL_CHECK 1000
1710
1711 int
1712 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1713 u64 off, void *data, int size)
1714 {
1715 unsigned long flags;
1716 int i, j, ret = 0, loop, sz[2], off0;
1717 uint32_t temp;
1718 uint64_t off8, tmpw, word[2] = {0, 0};
1719 void __iomem *mem_crb;
1720
1721 /*
1722 * If not MN, go check for MS or invalid.
1723 */
1724 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1725 return netxen_nic_pci_mem_write_direct(adapter,
1726 off, data, size);
1727
1728 off8 = off & 0xfffffff8;
1729 off0 = off & 0x7;
1730 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1731 sz[1] = size - sz[0];
1732 loop = ((off0 + size - 1) >> 3) + 1;
1733 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1734
1735 if ((size != 8) || (off0 != 0)) {
1736 for (i = 0; i < loop; i++) {
1737 if (adapter->pci_mem_read(adapter,
1738 off8 + (i << 3), &word[i], 8))
1739 return -1;
1740 }
1741 }
1742
1743 switch (size) {
1744 case 1:
1745 tmpw = *((uint8_t *)data);
1746 break;
1747 case 2:
1748 tmpw = *((uint16_t *)data);
1749 break;
1750 case 4:
1751 tmpw = *((uint32_t *)data);
1752 break;
1753 case 8:
1754 default:
1755 tmpw = *((uint64_t *)data);
1756 break;
1757 }
1758 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1759 word[0] |= tmpw << (off0 * 8);
1760
1761 if (loop == 2) {
1762 word[1] &= ~(~0ULL << (sz[1] * 8));
1763 word[1] |= tmpw >> (sz[0] * 8);
1764 }
1765
1766 write_lock_irqsave(&adapter->adapter_lock, flags);
1767 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1768
1769 for (i = 0; i < loop; i++) {
1770 writel((uint32_t)(off8 + (i << 3)),
1771 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1772 writel(0,
1773 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1774 writel(word[i] & 0xffffffff,
1775 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1776 writel((word[i] >> 32) & 0xffffffff,
1777 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1778 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1779 (mem_crb+MIU_TEST_AGT_CTRL));
1780 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1781 (mem_crb+MIU_TEST_AGT_CTRL));
1782
1783 for (j = 0; j < MAX_CTL_CHECK; j++) {
1784 temp = readl(
1785 (mem_crb+MIU_TEST_AGT_CTRL));
1786 if ((temp & MIU_TA_CTL_BUSY) == 0)
1787 break;
1788 }
1789
1790 if (j >= MAX_CTL_CHECK) {
1791 if (printk_ratelimit())
1792 dev_err(&adapter->pdev->dev,
1793 "failed to write through agent\n");
1794 ret = -1;
1795 break;
1796 }
1797 }
1798
1799 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1800 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1801 return ret;
1802 }
1803
1804 int
1805 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1806 u64 off, void *data, int size)
1807 {
1808 unsigned long flags;
1809 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1810 uint32_t temp;
1811 uint64_t off8, val, word[2] = {0, 0};
1812 void __iomem *mem_crb;
1813
1814
1815 /*
1816 * If not MN, go check for MS or invalid.
1817 */
1818 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1819 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1820
1821 off8 = off & 0xfffffff8;
1822 off0[0] = off & 0x7;
1823 off0[1] = 0;
1824 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1825 sz[1] = size - sz[0];
1826 loop = ((off0[0] + size - 1) >> 3) + 1;
1827 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1828
1829 write_lock_irqsave(&adapter->adapter_lock, flags);
1830 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1831
1832 for (i = 0; i < loop; i++) {
1833 writel((uint32_t)(off8 + (i << 3)),
1834 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1835 writel(0,
1836 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1837 writel(MIU_TA_CTL_ENABLE,
1838 (mem_crb+MIU_TEST_AGT_CTRL));
1839 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1840 (mem_crb+MIU_TEST_AGT_CTRL));
1841
1842 for (j = 0; j < MAX_CTL_CHECK; j++) {
1843 temp = readl(
1844 (mem_crb+MIU_TEST_AGT_CTRL));
1845 if ((temp & MIU_TA_CTL_BUSY) == 0)
1846 break;
1847 }
1848
1849 if (j >= MAX_CTL_CHECK) {
1850 if (printk_ratelimit())
1851 dev_err(&adapter->pdev->dev,
1852 "failed to read through agent\n");
1853 break;
1854 }
1855
1856 start = off0[i] >> 2;
1857 end = (off0[i] + sz[i] - 1) >> 2;
1858 for (k = start; k <= end; k++) {
1859 word[i] |= ((uint64_t) readl(
1860 (mem_crb +
1861 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1862 }
1863 }
1864
1865 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1866 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1867
1868 if (j >= MAX_CTL_CHECK)
1869 return -1;
1870
1871 if (sz[0] == 8) {
1872 val = word[0];
1873 } else {
1874 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1875 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1876 }
1877
1878 switch (size) {
1879 case 1:
1880 *(uint8_t *)data = val;
1881 break;
1882 case 2:
1883 *(uint16_t *)data = val;
1884 break;
1885 case 4:
1886 *(uint32_t *)data = val;
1887 break;
1888 case 8:
1889 *(uint64_t *)data = val;
1890 break;
1891 }
1892 return 0;
1893 }
1894
1895 int
1896 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1897 u64 off, void *data, int size)
1898 {
1899 int i, j, ret = 0, loop, sz[2], off0;
1900 uint32_t temp;
1901 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1902
1903 /*
1904 * If not MN, go check for MS or invalid.
1905 */
1906 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1907 mem_crb = NETXEN_CRB_QDR_NET;
1908 else {
1909 mem_crb = NETXEN_CRB_DDR_NET;
1910 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1911 return netxen_nic_pci_mem_write_direct(adapter,
1912 off, data, size);
1913 }
1914
1915 off8 = off & 0xfffffff8;
1916 off0 = off & 0x7;
1917 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1918 sz[1] = size - sz[0];
1919 loop = ((off0 + size - 1) >> 3) + 1;
1920
1921 if ((size != 8) || (off0 != 0)) {
1922 for (i = 0; i < loop; i++) {
1923 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1924 &word[i], 8))
1925 return -1;
1926 }
1927 }
1928
1929 switch (size) {
1930 case 1:
1931 tmpw = *((uint8_t *)data);
1932 break;
1933 case 2:
1934 tmpw = *((uint16_t *)data);
1935 break;
1936 case 4:
1937 tmpw = *((uint32_t *)data);
1938 break;
1939 case 8:
1940 default:
1941 tmpw = *((uint64_t *)data);
1942 break;
1943 }
1944
1945 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1946 word[0] |= tmpw << (off0 * 8);
1947
1948 if (loop == 2) {
1949 word[1] &= ~(~0ULL << (sz[1] * 8));
1950 word[1] |= tmpw >> (sz[0] * 8);
1951 }
1952
1953 /*
1954 * don't lock here - write_wx gets the lock if each time
1955 * write_lock_irqsave(&adapter->adapter_lock, flags);
1956 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1957 */
1958
1959 for (i = 0; i < loop; i++) {
1960 temp = off8 + (i << 3);
1961 adapter->hw_write_wx(adapter,
1962 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1963 temp = 0;
1964 adapter->hw_write_wx(adapter,
1965 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1966 temp = word[i] & 0xffffffff;
1967 adapter->hw_write_wx(adapter,
1968 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1969 temp = (word[i] >> 32) & 0xffffffff;
1970 adapter->hw_write_wx(adapter,
1971 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1972 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1973 adapter->hw_write_wx(adapter,
1974 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1975 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1976 adapter->hw_write_wx(adapter,
1977 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1978
1979 for (j = 0; j < MAX_CTL_CHECK; j++) {
1980 adapter->hw_read_wx(adapter,
1981 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1982 if ((temp & MIU_TA_CTL_BUSY) == 0)
1983 break;
1984 }
1985
1986 if (j >= MAX_CTL_CHECK) {
1987 if (printk_ratelimit())
1988 dev_err(&adapter->pdev->dev,
1989 "failed to write through agent\n");
1990 ret = -1;
1991 break;
1992 }
1993 }
1994
1995 /*
1996 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1997 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1998 */
1999 return ret;
2000 }
2001
2002 int
2003 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2004 u64 off, void *data, int size)
2005 {
2006 int i, j = 0, k, start, end, loop, sz[2], off0[2];
2007 uint32_t temp;
2008 uint64_t off8, val, mem_crb, word[2] = {0, 0};
2009
2010 /*
2011 * If not MN, go check for MS or invalid.
2012 */
2013
2014 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
2015 mem_crb = NETXEN_CRB_QDR_NET;
2016 else {
2017 mem_crb = NETXEN_CRB_DDR_NET;
2018 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
2019 return netxen_nic_pci_mem_read_direct(adapter,
2020 off, data, size);
2021 }
2022
2023 off8 = off & 0xfffffff8;
2024 off0[0] = off & 0x7;
2025 off0[1] = 0;
2026 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
2027 sz[1] = size - sz[0];
2028 loop = ((off0[0] + size - 1) >> 3) + 1;
2029
2030 /*
2031 * don't lock here - write_wx gets the lock if each time
2032 * write_lock_irqsave(&adapter->adapter_lock, flags);
2033 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
2034 */
2035
2036 for (i = 0; i < loop; i++) {
2037 temp = off8 + (i << 3);
2038 adapter->hw_write_wx(adapter,
2039 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
2040 temp = 0;
2041 adapter->hw_write_wx(adapter,
2042 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
2043 temp = MIU_TA_CTL_ENABLE;
2044 adapter->hw_write_wx(adapter,
2045 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2046 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2047 adapter->hw_write_wx(adapter,
2048 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2049
2050 for (j = 0; j < MAX_CTL_CHECK; j++) {
2051 adapter->hw_read_wx(adapter,
2052 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2053 if ((temp & MIU_TA_CTL_BUSY) == 0)
2054 break;
2055 }
2056
2057 if (j >= MAX_CTL_CHECK) {
2058 if (printk_ratelimit())
2059 dev_err(&adapter->pdev->dev,
2060 "failed to read through agent\n");
2061 break;
2062 }
2063
2064 start = off0[i] >> 2;
2065 end = (off0[i] + sz[i] - 1) >> 2;
2066 for (k = start; k <= end; k++) {
2067 adapter->hw_read_wx(adapter,
2068 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
2069 word[i] |= ((uint64_t)temp << (32 * k));
2070 }
2071 }
2072
2073 /*
2074 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2075 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2076 */
2077
2078 if (j >= MAX_CTL_CHECK)
2079 return -1;
2080
2081 if (sz[0] == 8) {
2082 val = word[0];
2083 } else {
2084 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2085 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2086 }
2087
2088 switch (size) {
2089 case 1:
2090 *(uint8_t *)data = val;
2091 break;
2092 case 2:
2093 *(uint16_t *)data = val;
2094 break;
2095 case 4:
2096 *(uint32_t *)data = val;
2097 break;
2098 case 8:
2099 *(uint64_t *)data = val;
2100 break;
2101 }
2102 return 0;
2103 }
2104
2105 /*
2106 * Note : only 32-bit writes!
2107 */
2108 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2109 u64 off, u32 data)
2110 {
2111 adapter->hw_write_wx(adapter, off, &data, 4);
2112
2113 return 0;
2114 }
2115
2116 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2117 {
2118 u32 temp;
2119 adapter->hw_read_wx(adapter, off, &temp, 4);
2120 return temp;
2121 }
2122
2123 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2124 u64 off, u32 data)
2125 {
2126 adapter->hw_write_wx(adapter, off, &data, 4);
2127 }
2128
2129 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2130 {
2131 u32 temp;
2132 adapter->hw_read_wx(adapter, off, &temp, 4);
2133 return temp;
2134 }
2135
2136 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2137 {
2138 int offset, board_type, magic, header_version;
2139 struct pci_dev *pdev = adapter->pdev;
2140
2141 offset = NETXEN_BRDCFG_START +
2142 offsetof(struct netxen_board_info, magic);
2143 if (netxen_rom_fast_read(adapter, offset, &magic))
2144 return -EIO;
2145
2146 offset = NETXEN_BRDCFG_START +
2147 offsetof(struct netxen_board_info, header_version);
2148 if (netxen_rom_fast_read(adapter, offset, &header_version))
2149 return -EIO;
2150
2151 if (magic != NETXEN_BDINFO_MAGIC ||
2152 header_version != NETXEN_BDINFO_VERSION) {
2153 dev_err(&pdev->dev,
2154 "invalid board config, magic=%08x, version=%08x\n",
2155 magic, header_version);
2156 return -EIO;
2157 }
2158
2159 offset = NETXEN_BRDCFG_START +
2160 offsetof(struct netxen_board_info, board_type);
2161 if (netxen_rom_fast_read(adapter, offset, &board_type))
2162 return -EIO;
2163
2164 adapter->ahw.board_type = board_type;
2165
2166 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2167 u32 gpio = netxen_nic_reg_read(adapter,
2168 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2169 if ((gpio & 0x8000) == 0)
2170 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2171 }
2172
2173 switch ((netxen_brdtype_t)board_type) {
2174 case NETXEN_BRDTYPE_P2_SB35_4G:
2175 adapter->ahw.port_type = NETXEN_NIC_GBE;
2176 break;
2177 case NETXEN_BRDTYPE_P2_SB31_10G:
2178 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2179 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2180 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2181 case NETXEN_BRDTYPE_P3_HMEZ:
2182 case NETXEN_BRDTYPE_P3_XG_LOM:
2183 case NETXEN_BRDTYPE_P3_10G_CX4:
2184 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2185 case NETXEN_BRDTYPE_P3_IMEZ:
2186 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2187 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2188 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2189 case NETXEN_BRDTYPE_P3_10G_XFP:
2190 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2191 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2192 break;
2193 case NETXEN_BRDTYPE_P1_BD:
2194 case NETXEN_BRDTYPE_P1_SB:
2195 case NETXEN_BRDTYPE_P1_SMAX:
2196 case NETXEN_BRDTYPE_P1_SOCK:
2197 case NETXEN_BRDTYPE_P3_REF_QG:
2198 case NETXEN_BRDTYPE_P3_4_GB:
2199 case NETXEN_BRDTYPE_P3_4_GB_MM:
2200 adapter->ahw.port_type = NETXEN_NIC_GBE;
2201 break;
2202 case NETXEN_BRDTYPE_P3_10G_TP:
2203 adapter->ahw.port_type = (adapter->portnum < 2) ?
2204 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2205 break;
2206 default:
2207 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2208 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2209 break;
2210 }
2211
2212 return 0;
2213 }
2214
2215 /* NIU access sections */
2216
2217 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2218 {
2219 new_mtu += MTU_FUDGE_FACTOR;
2220 netxen_nic_write_w0(adapter,
2221 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2222 new_mtu);
2223 return 0;
2224 }
2225
2226 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2227 {
2228 new_mtu += MTU_FUDGE_FACTOR;
2229 if (adapter->physical_port == 0)
2230 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2231 new_mtu);
2232 else
2233 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2234 new_mtu);
2235 return 0;
2236 }
2237
2238 void
2239 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2240 unsigned long off, int data)
2241 {
2242 adapter->hw_write_wx(adapter, off, &data, 4);
2243 }
2244
2245 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2246 {
2247 __u32 status;
2248 __u32 autoneg;
2249 __u32 port_mode;
2250
2251 if (!netif_carrier_ok(adapter->netdev)) {
2252 adapter->link_speed = 0;
2253 adapter->link_duplex = -1;
2254 adapter->link_autoneg = AUTONEG_ENABLE;
2255 return;
2256 }
2257
2258 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2259 adapter->hw_read_wx(adapter,
2260 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2261 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2262 adapter->link_speed = SPEED_1000;
2263 adapter->link_duplex = DUPLEX_FULL;
2264 adapter->link_autoneg = AUTONEG_DISABLE;
2265 return;
2266 }
2267
2268 if (adapter->phy_read
2269 && adapter->phy_read(adapter,
2270 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2271 &status) == 0) {
2272 if (netxen_get_phy_link(status)) {
2273 switch (netxen_get_phy_speed(status)) {
2274 case 0:
2275 adapter->link_speed = SPEED_10;
2276 break;
2277 case 1:
2278 adapter->link_speed = SPEED_100;
2279 break;
2280 case 2:
2281 adapter->link_speed = SPEED_1000;
2282 break;
2283 default:
2284 adapter->link_speed = 0;
2285 break;
2286 }
2287 switch (netxen_get_phy_duplex(status)) {
2288 case 0:
2289 adapter->link_duplex = DUPLEX_HALF;
2290 break;
2291 case 1:
2292 adapter->link_duplex = DUPLEX_FULL;
2293 break;
2294 default:
2295 adapter->link_duplex = -1;
2296 break;
2297 }
2298 if (adapter->phy_read
2299 && adapter->phy_read(adapter,
2300 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2301 &autoneg) != 0)
2302 adapter->link_autoneg = autoneg;
2303 } else
2304 goto link_down;
2305 } else {
2306 link_down:
2307 adapter->link_speed = 0;
2308 adapter->link_duplex = -1;
2309 }
2310 }
2311 }
2312
2313 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2314 {
2315 u32 fw_major, fw_minor, fw_build;
2316 char brd_name[NETXEN_MAX_SHORT_NAME];
2317 char serial_num[32];
2318 int i, addr, val;
2319 int *ptr32;
2320 struct pci_dev *pdev = adapter->pdev;
2321
2322 adapter->driver_mismatch = 0;
2323
2324 ptr32 = (int *)&serial_num;
2325 addr = NETXEN_USER_START +
2326 offsetof(struct netxen_new_user_info, serial_num);
2327 for (i = 0; i < 8; i++) {
2328 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2329 dev_err(&pdev->dev, "error reading board info\n");
2330 adapter->driver_mismatch = 1;
2331 return;
2332 }
2333 ptr32[i] = cpu_to_le32(val);
2334 addr += sizeof(u32);
2335 }
2336
2337 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2338 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2339 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2340
2341 adapter->fw_major = fw_major;
2342 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2343
2344 if (adapter->portnum == 0) {
2345 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2346
2347 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2348 brd_name, serial_num, adapter->ahw.revision_id);
2349 }
2350
2351 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2352 adapter->driver_mismatch = 1;
2353 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2354 fw_major, fw_minor, fw_build);
2355 return;
2356 }
2357
2358 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2359 fw_major, fw_minor, fw_build);
2360
2361 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2362 adapter->hw_read_wx(adapter,
2363 NETXEN_MIU_MN_CONTROL, &i, 4);
2364 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2365 dev_info(&pdev->dev, "firmware running in %s mode\n",
2366 adapter->ahw.cut_through ? "cut-through" : "legacy");
2367 }
2368 }
2369
2370 int
2371 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2372 {
2373 u32 wol_cfg;
2374
2375 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2376 return 0;
2377
2378 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV);
2379 if (wol_cfg & (1UL << adapter->portnum)) {
2380 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG);
2381 if (wol_cfg & (1 << adapter->portnum))
2382 return 1;
2383 }
2384
2385 return 0;
2386 }
Verdex Pro support