arch/arm/common/it8152.c

   1 /*
   2  * linux/arch/arm/common/it8152.c
   3  *
   4  * Copyright Compulab Ltd, 2002-2007
   5  * Mike Rapoport <mike@compulab.co.il>
   6  *
   7  * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
   8  * (see this file for respective copyrights)
   9  *
  10  * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
  11  * and demux code.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/ptrace.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/mm.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/ioport.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/mach/pci.h>
  31 #include <asm/hardware/it8152.h>
  32
  33 #define MAX_SLOTS               21
  34
  35 static void it8152_mask_irq(unsigned int irq)
  36 {
  37        if (irq >= IT8152_LD_IRQ(0)) {
  38                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
  39                             (1 << (irq - IT8152_LD_IRQ(0)))),
  40                             IT8152_INTC_LDCNIMR);
  41        } else if (irq >= IT8152_LP_IRQ(0)) {
  42                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
  43                             (1 << (irq - IT8152_LP_IRQ(0)))),
  44                             IT8152_INTC_LPCNIMR);
  45        } else if (irq >= IT8152_PD_IRQ(0)) {
  46                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
  47                             (1 << (irq - IT8152_PD_IRQ(0)))),
  48                             IT8152_INTC_PDCNIMR);
  49        }
  50 }
  51
  52 static void it8152_unmask_irq(unsigned int irq)
  53 {
  54        if (irq >= IT8152_LD_IRQ(0)) {
  55                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
  56                              ~(1 << (irq - IT8152_LD_IRQ(0)))),
  57                             IT8152_INTC_LDCNIMR);
  58        } else if (irq >= IT8152_LP_IRQ(0)) {
  59                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
  60                              ~(1 << (irq - IT8152_LP_IRQ(0)))),
  61                             IT8152_INTC_LPCNIMR);
  62        } else if (irq >= IT8152_PD_IRQ(0)) {
  63                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
  64                              ~(1 << (irq - IT8152_PD_IRQ(0)))),
  65                             IT8152_INTC_PDCNIMR);
  66        }
  67 }
  68
  69 static inline void it8152_irq(int irq)
  70 {
  71         struct irq_desc *desc;
  72
  73         desc = irq_desc + irq;
  74         desc_handle_irq(irq, desc);
  75 }
  76
  77 static struct irq_chip it8152_irq_chip = {
  78         .name           = "it8152",
  79         .ack            = it8152_mask_irq,
  80         .mask           = it8152_mask_irq,
  81         .unmask         = it8152_unmask_irq,
  82 };
  83
  84 void it8152_init_irq(void)
  85 {
  86         int irq;
  87
  88         __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
  89         __raw_writel((0), IT8152_INTC_PDCNIRR);
  90         __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
  91         __raw_writel((0), IT8152_INTC_LPCNIRR);
  92         __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
  93         __raw_writel((0), IT8152_INTC_LDCNIRR);
  94
  95         for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
  96                 set_irq_chip(irq, &it8152_irq_chip);
  97                 set_irq_handler(irq, handle_level_irq);
  98                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  99         }
 100 }
 101
 102 void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
 103 {
 104        int bits_pd, bits_lp, bits_ld;
 105        int i;
 106
 107        while (1) {
 108                /* Read all */
 109                bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
 110                bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
 111                bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
 112
 113                /* Ack */
 114                __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
 115                __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
 116                __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
 117
 118                if (!(bits_ld | bits_lp | bits_pd)) {
 119                        /* Re-read to guarantee, that there was a moment of
 120                           time, when they all three were 0. */
 121                        bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
 122                        bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
 123                        bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
 124                        if (!(bits_ld | bits_lp | bits_pd))
 125                                return;
 126                }
 127
 128                bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
 129                while (bits_pd) {
 130                        i = __ffs(bits_pd);
 131                        it8152_irq(IT8152_PD_IRQ(i));
 132                        bits_pd &= ~(1 << i);
 133                }
 134
 135                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
 136                while (bits_lp) {
 137                        i = __ffs(bits_lp);
 138                        it8152_irq(IT8152_LP_IRQ(i));
 139                        bits_lp &= ~(1 << i);
 140                }
 141
 142                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
 143                while (bits_ld) {
 144                        i = __ffs(bits_ld);
 145                        it8152_irq(IT8152_LD_IRQ(i));
 146                        bits_ld &= ~(1 << i);
 147                }
 148        }
 149 }
 150
 151 /* mapping for on-chip devices */
 152 int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 153 {
 154         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
 155             (dev->device == PCI_DEVICE_ID_ITE_8152)) {
 156                 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
 157                         return IT8152_AUDIO_INT;
 158                 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
 159                         return IT8152_USB_INT;
 160                 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
 161                         return IT8152_CDMA_INT;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
 168                                                  unsigned int devfn)
 169 {
 170         unsigned long addr = 0;
 171
 172         if (bus->number == 0) {
 173                         if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
 174                                 addr = (devfn << 8);
 175         } else
 176                 addr = (bus->number << 16) | (devfn << 8);
 177
 178         return addr;
 179 }
 180
 181 static int it8152_pci_read_config(struct pci_bus *bus,
 182                                   unsigned int devfn, int where,
 183                                   int size, u32 *value)
 184 {
 185         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
 186         u32 v;
 187         int shift;
 188
 189         shift = (where & 3);
 190
 191         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 192         v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));
 193
 194         *value = v;
 195
 196         return PCIBIOS_SUCCESSFUL;
 197 }
 198
 199 static int it8152_pci_write_config(struct pci_bus *bus,
 200                                    unsigned int devfn, int where,
 201                                    int size, u32 value)
 202 {
 203         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
 204         u32 v, vtemp, mask = 0;
 205         int shift;
 206
 207         if (size == 1)
 208                 mask = 0xff;
 209         if (size == 2)
 210                 mask = 0xffff;
 211
 212         shift = (where & 3);
 213
 214         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 215         vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
 216
 217         if (mask)
 218                 vtemp &= ~(mask << (8 * shift));
 219         else
 220                 vtemp = 0;
 221
 222         v = (value << (8 * shift));
 223         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 224         __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
 225
 226         return PCIBIOS_SUCCESSFUL;
 227 }
 228
 229 static struct pci_ops it8152_ops = {
 230         .read = it8152_pci_read_config,
 231         .write = it8152_pci_write_config,
 232 };
 233
 234 static struct resource it8152_io = {
 235         .name   = "IT8152 PCI I/O region",
 236         .flags  = IORESOURCE_IO,
 237 };
 238
 239 static struct resource it8152_mem = {
 240         .name   = "IT8152 PCI memory region",
 241         .start  = 0x10000000,
 242         .end    = 0x13e00000,
 243         .flags  = IORESOURCE_MEM,
 244 };
 245
 246 /*
 247  * The following functions are needed for DMA bouncing.
 248  * ITE8152 chip can addrees up to 64MByte, so all the devices
 249  * connected to ITE8152 (PCI and USB) should have limited DMA window
 250  */
 251
 252 /*
 253  * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
 254  * other devices.
 255  */
 256 static int it8152_pci_platform_notify(struct device *dev)
 257 {
 258         if (dev->bus == &pci_bus_type) {
 259                 if (dev->dma_mask)
 260                         *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
 261                 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
 262                 dmabounce_register_dev(dev, 2048, 4096);
 263         }
 264         return 0;
 265 }
 266
 267 static int it8152_pci_platform_notify_remove(struct device *dev)
 268 {
 269         if (dev->bus == &pci_bus_type)
 270                 dmabounce_unregister_dev(dev);
 271
 272         return 0;
 273 }
 274
 275 int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
 276 {
 277         dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
 278                 __func__, dma_addr, size);
 279         return (dev->bus == &pci_bus_type) &&
 280                 ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
 281 }
 282
 283 /*
 284  * We override these so we properly do dmabounce otherwise drivers
 285  * are able to set the dma_mask to 0xffffffff and we can no longer
 286  * trap bounces. :(
 287  *
 288  * We just return true on everyhing except for < 64MB in which case
 289  * we will fail miseralby and die since we can't handle that case.
 290  */
 291 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
 292 {
 293         dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
 294         if (mask >= PHYS_OFFSET + SZ_64M - 1)
 295                 return 0;
 296
 297         return -EIO;
 298 }
 299
 300 int
 301 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
 302 {
 303         dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
 304         if (mask >= PHYS_OFFSET + SZ_64M - 1)
 305                 return 0;
 306
 307         return -EIO;
 308 }
 309
 310 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 311 {
 312         it8152_io.start = IT8152_IO_BASE + 0x12000;
 313         it8152_io.end   = IT8152_IO_BASE + 0x12000 + 0x100000;
 314
 315         sys->mem_offset = 0x10000000;
 316         sys->io_offset  = IT8152_IO_BASE;
 317
 318         if (request_resource(&ioport_resource, &it8152_io)) {
 319                 printk(KERN_ERR "PCI: unable to allocate IO region\n");
 320                 goto err0;
 321         }
 322         if (request_resource(&iomem_resource, &it8152_mem)) {
 323                 printk(KERN_ERR "PCI: unable to allocate memory region\n");
 324                 goto err1;
 325         }
 326
 327         sys->resource[0] = &it8152_io;
 328         sys->resource[1] = &it8152_mem;
 329
 330         if (platform_notify || platform_notify_remove) {
 331                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
 332                 goto err2;
 333         }
 334
 335         platform_notify = it8152_pci_platform_notify;
 336         platform_notify_remove = it8152_pci_platform_notify_remove;
 337
 338         return 1;
 339
 340 err2:
 341         release_resource(&it8152_io);
 342 err1:
 343         release_resource(&it8152_mem);
 344 err0:
 345         return -EBUSY;
 346 }
 347
 348 /*
 349  * If we set up a device for bus mastering, we need to check the latency
 350  * timer as we don't have even crappy BIOSes to set it properly.
 351  * The implementation is from arch/i386/pci/i386.c
 352  */
 353 unsigned int pcibios_max_latency = 255;
 354
 355 void pcibios_set_master(struct pci_dev *dev)
 356 {
 357         u8 lat;
 358
 359         /* no need to update on-chip OHCI controller */
 360         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
 361             (dev->device == PCI_DEVICE_ID_ITE_8152) &&
 362             ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
 363                 return;
 364
 365         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 366         if (lat < 16)
 367                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 368         else if (lat > pcibios_max_latency)
 369                 lat = pcibios_max_latency;
 370         else
 371                 return;
 372         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
 373                pci_name(dev), lat);
 374         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 375 }
 376
 377
 378 struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
 379 {
 380         return pci_scan_bus(nr, &it8152_ops, sys);
 381 }
 382