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ath9k: Store HW version information in a separate structure
[linux-2.6/verdex.git] / drivers / net / wireless / ath9k / hw.c
blob164a543248d39506d373e8f8c665bfdad50fd03c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47 if (!ah->ah_curchan) /* should really check for CCK instead */
48 return clks / ATH9K_CLOCK_RATE_CCK;
49 if (conf->channel->band == IEEE80211_BAND_2GHZ)
50 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
51 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
52 }
53
54 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
55 {
56 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
57 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61 }
62
63 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
64 {
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
66 if (!ah->ah_curchan) /* should really check for CCK instead */
67 return usecs *ATH9K_CLOCK_RATE_CCK;
68 if (conf->channel->band == IEEE80211_BAND_2GHZ)
69 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
70 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
71 }
72
73 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
74 {
75 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
76 if (conf_is_ht40(conf))
77 return ath9k_hw_mac_clks(ah, usecs) * 2;
78 else
79 return ath9k_hw_mac_clks(ah, usecs);
80 }
81
82 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
83 {
84 int i;
85
86 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
87 if ((REG_READ(ah, reg) & mask) == val)
88 return true;
89
90 udelay(AH_TIME_QUANTUM);
91 }
92
93 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
94 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
95 reg, REG_READ(ah, reg), mask, val);
96
97 return false;
98 }
99
100 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
101 {
102 u32 retval;
103 int i;
104
105 for (i = 0, retval = 0; i < n; i++) {
106 retval = (retval << 1) | (val & 1);
107 val >>= 1;
108 }
109 return retval;
110 }
111
112 bool ath9k_get_channel_edges(struct ath_hal *ah,
113 u16 flags, u16 *low,
114 u16 *high)
115 {
116 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
117
118 if (flags & CHANNEL_5GHZ) {
119 *low = pCap->low_5ghz_chan;
120 *high = pCap->high_5ghz_chan;
121 return true;
122 }
123 if ((flags & CHANNEL_2GHZ)) {
124 *low = pCap->low_2ghz_chan;
125 *high = pCap->high_2ghz_chan;
126 return true;
127 }
128 return false;
129 }
130
131 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
132 struct ath_rate_table *rates,
133 u32 frameLen, u16 rateix,
134 bool shortPreamble)
135 {
136 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
137 u32 kbps;
138
139 kbps = rates->info[rateix].ratekbps;
140
141 if (kbps == 0)
142 return 0;
143
144 switch (rates->info[rateix].phy) {
145 case WLAN_RC_PHY_CCK:
146 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
147 if (shortPreamble && rates->info[rateix].short_preamble)
148 phyTime >>= 1;
149 numBits = frameLen << 3;
150 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
151 break;
152 case WLAN_RC_PHY_OFDM:
153 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
154 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
155 numBits = OFDM_PLCP_BITS + (frameLen << 3);
156 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
157 txTime = OFDM_SIFS_TIME_QUARTER
158 + OFDM_PREAMBLE_TIME_QUARTER
159 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
160 } else if (ah->ah_curchan &&
161 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
162 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
163 numBits = OFDM_PLCP_BITS + (frameLen << 3);
164 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
165 txTime = OFDM_SIFS_TIME_HALF +
166 OFDM_PREAMBLE_TIME_HALF
167 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
168 } else {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
173 + (numSymbols * OFDM_SYMBOL_TIME);
174 }
175 break;
176 default:
177 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
178 "Unknown phy %u (rate ix %u)\n",
179 rates->info[rateix].phy, rateix);
180 txTime = 0;
181 break;
182 }
183
184 return txTime;
185 }
186
187 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
188 struct ath9k_channel *chan,
189 struct chan_centers *centers)
190 {
191 int8_t extoff;
192 struct ath_hal_5416 *ahp = AH5416(ah);
193
194 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center =
196 centers->synth_center = chan->channel;
197 return;
198 }
199
200 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
201 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
202 centers->synth_center =
203 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
204 extoff = 1;
205 } else {
206 centers->synth_center =
207 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
208 extoff = -1;
209 }
210
211 centers->ctl_center =
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
213 centers->ext_center =
214 centers->synth_center + (extoff *
215 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
216 HT40_CHANNEL_CENTER_SHIFT : 15));
217
218 }
219
220 /******************/
221 /* Chip Revisions */
222 /******************/
223
224 static void ath9k_hw_read_revisions(struct ath_hal *ah)
225 {
226 u32 val;
227
228 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
229
230 if (val == 0xFF) {
231 val = REG_READ(ah, AR_SREV);
232 ah->hw_version.macVersion =
233 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
234 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
235 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
236 } else {
237 if (!AR_SREV_9100(ah))
238 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
239
240 ah->hw_version.macRev = val & AR_SREV_REVISION;
241
242 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
243 ah->ah_isPciExpress = true;
244 }
245 }
246
247 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
248 {
249 u32 val;
250 int i;
251
252 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
253
254 for (i = 0; i < 8; i++)
255 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
256 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
257 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
258
259 return ath9k_hw_reverse_bits(val, 8);
260 }
261
262 /************************************/
263 /* HW Attach, Detach, Init Routines */
264 /************************************/
265
266 static void ath9k_hw_disablepcie(struct ath_hal *ah)
267 {
268 if (AR_SREV_9100(ah))
269 return;
270
271 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
272 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
273 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
280
281 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
282 }
283
284 static bool ath9k_hw_chip_test(struct ath_hal *ah)
285 {
286 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
287 u32 regHold[2];
288 u32 patternData[4] = { 0x55555555,
289 0xaaaaaaaa,
290 0x66666666,
291 0x99999999 };
292 int i, j;
293
294 for (i = 0; i < 2; i++) {
295 u32 addr = regAddr[i];
296 u32 wrData, rdData;
297
298 regHold[i] = REG_READ(ah, addr);
299 for (j = 0; j < 0x100; j++) {
300 wrData = (j << 16) | j;
301 REG_WRITE(ah, addr, wrData);
302 rdData = REG_READ(ah, addr);
303 if (rdData != wrData) {
304 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
305 "address test failed "
306 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
307 addr, wrData, rdData);
308 return false;
309 }
310 }
311 for (j = 0; j < 4; j++) {
312 wrData = patternData[j];
313 REG_WRITE(ah, addr, wrData);
314 rdData = REG_READ(ah, addr);
315 if (wrData != rdData) {
316 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
317 "address test failed "
318 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
319 addr, wrData, rdData);
320 return false;
321 }
322 }
323 REG_WRITE(ah, regAddr[i], regHold[i]);
324 }
325 udelay(100);
326 return true;
327 }
328
329 static const char *ath9k_hw_devname(u16 devid)
330 {
331 switch (devid) {
332 case AR5416_DEVID_PCI:
333 return "Atheros 5416";
334 case AR5416_DEVID_PCIE:
335 return "Atheros 5418";
336 case AR9160_DEVID_PCI:
337 return "Atheros 9160";
338 case AR5416_AR9100_DEVID:
339 return "Atheros 9100";
340 case AR9280_DEVID_PCI:
341 case AR9280_DEVID_PCIE:
342 return "Atheros 9280";
343 case AR9285_DEVID_PCIE:
344 return "Atheros 9285";
345 }
346
347 return NULL;
348 }
349
350 static void ath9k_hw_set_defaults(struct ath_hal *ah)
351 {
352 int i;
353
354 ah->ah_config.dma_beacon_response_time = 2;
355 ah->ah_config.sw_beacon_response_time = 10;
356 ah->ah_config.additional_swba_backoff = 0;
357 ah->ah_config.ack_6mb = 0x0;
358 ah->ah_config.cwm_ignore_extcca = 0;
359 ah->ah_config.pcie_powersave_enable = 0;
360 ah->ah_config.pcie_l1skp_enable = 0;
361 ah->ah_config.pcie_clock_req = 0;
362 ah->ah_config.pcie_power_reset = 0x100;
363 ah->ah_config.pcie_restore = 0;
364 ah->ah_config.pcie_waen = 0;
365 ah->ah_config.analog_shiftreg = 1;
366 ah->ah_config.ht_enable = 1;
367 ah->ah_config.ofdm_trig_low = 200;
368 ah->ah_config.ofdm_trig_high = 500;
369 ah->ah_config.cck_trig_high = 200;
370 ah->ah_config.cck_trig_low = 100;
371 ah->ah_config.enable_ani = 1;
372 ah->ah_config.noise_immunity_level = 4;
373 ah->ah_config.ofdm_weaksignal_det = 1;
374 ah->ah_config.cck_weaksignal_thr = 0;
375 ah->ah_config.spur_immunity_level = 2;
376 ah->ah_config.firstep_level = 0;
377 ah->ah_config.rssi_thr_high = 40;
378 ah->ah_config.rssi_thr_low = 7;
379 ah->ah_config.diversity_control = 0;
380 ah->ah_config.antenna_switch_swap = 0;
381
382 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
383 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
384 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
385 }
386
387 ah->ah_config.intr_mitigation = 1;
388 }
389
390 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
391 struct ath_softc *sc,
392 void __iomem *mem,
393 int *status)
394 {
395 static const u8 defbssidmask[ETH_ALEN] =
396 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
397 struct ath_hal_5416 *ahp;
398 struct ath_hal *ah;
399
400 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
401 if (ahp == NULL) {
402 DPRINTF(sc, ATH_DBG_FATAL,
403 "Cannot allocate memory for state block\n");
404 *status = -ENOMEM;
405 return NULL;
406 }
407
408 ah = &ahp->ah;
409 ah->ah_sc = sc;
410 ah->ah_sh = mem;
411 ah->hw_version.magic = AR5416_MAGIC;
412 ah->ah_countryCode = CTRY_DEFAULT;
413 ah->hw_version.devid = devid;
414 ah->hw_version.subvendorid = 0;
415
416 ah->ah_flags = 0;
417 if ((devid == AR5416_AR9100_DEVID))
418 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
419 if (!AR_SREV_9100(ah))
420 ah->ah_flags = AH_USE_EEPROM;
421
422 ah->ah_powerLimit = MAX_RATE_POWER;
423 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
424 ahp->ah_atimWindow = 0;
425 ahp->ah_diversityControl = ah->ah_config.diversity_control;
426 ahp->ah_antennaSwitchSwap =
427 ah->ah_config.antenna_switch_swap;
428 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
429 ahp->ah_beaconInterval = 100;
430 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
431 ahp->ah_slottime = (u32) -1;
432 ahp->ah_acktimeout = (u32) -1;
433 ahp->ah_ctstimeout = (u32) -1;
434 ahp->ah_globaltxtimeout = (u32) -1;
435 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
436
437 ahp->ah_gBeaconRate = 0;
438
439 return ahp;
440 }
441
442 static int ath9k_hw_rfattach(struct ath_hal *ah)
443 {
444 bool rfStatus = false;
445 int ecode = 0;
446
447 rfStatus = ath9k_hw_init_rf(ah, &ecode);
448 if (!rfStatus) {
449 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
450 "RF setup failed, status %u\n", ecode);
451 return ecode;
452 }
453
454 return 0;
455 }
456
457 static int ath9k_hw_rf_claim(struct ath_hal *ah)
458 {
459 u32 val;
460
461 REG_WRITE(ah, AR_PHY(0), 0x00000007);
462
463 val = ath9k_hw_get_radiorev(ah);
464 switch (val & AR_RADIO_SREV_MAJOR) {
465 case 0:
466 val = AR_RAD5133_SREV_MAJOR;
467 break;
468 case AR_RAD5133_SREV_MAJOR:
469 case AR_RAD5122_SREV_MAJOR:
470 case AR_RAD2133_SREV_MAJOR:
471 case AR_RAD2122_SREV_MAJOR:
472 break;
473 default:
474 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
475 "5G Radio Chip Rev 0x%02X is not "
476 "supported by this driver\n",
477 ah->hw_version.analog5GhzRev);
478 return -EOPNOTSUPP;
479 }
480
481 ah->hw_version.analog5GhzRev = val;
482
483 return 0;
484 }
485
486 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
487 {
488 u32 sum;
489 int i;
490 u16 eeval;
491 struct ath_hal_5416 *ahp = AH5416(ah);
492
493 sum = 0;
494 for (i = 0; i < 3; i++) {
495 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
496 sum += eeval;
497 ahp->ah_macaddr[2 * i] = eeval >> 8;
498 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
499 }
500 if (sum == 0 || sum == 0xffff * 3) {
501 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
502 "mac address read failed: %pM\n",
503 ahp->ah_macaddr);
504 return -EADDRNOTAVAIL;
505 }
506
507 return 0;
508 }
509
510 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
511 {
512 u32 rxgain_type;
513 struct ath_hal_5416 *ahp = AH5416(ah);
514
515 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
516 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
517
518 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
519 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
520 ar9280Modes_backoff_13db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
522 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
523 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
524 ar9280Modes_backoff_23db_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
526 else
527 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
530 } else
531 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
532 ar9280Modes_original_rxgain_9280_2,
533 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
534 }
535
536 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
537 {
538 u32 txgain_type;
539 struct ath_hal_5416 *ahp = AH5416(ah);
540
541 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
542 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
543
544 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
545 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
546 ar9280Modes_high_power_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
548 else
549 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
552 } else
553 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
554 ar9280Modes_original_tx_gain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
556 }
557
558 static int ath9k_hw_post_attach(struct ath_hal *ah)
559 {
560 int ecode;
561
562 if (!ath9k_hw_chip_test(ah)) {
563 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
564 "hardware self-test failed\n");
565 return -ENODEV;
566 }
567
568 ecode = ath9k_hw_rf_claim(ah);
569 if (ecode != 0)
570 return ecode;
571
572 ecode = ath9k_hw_eeprom_attach(ah);
573 if (ecode != 0)
574 return ecode;
575 ecode = ath9k_hw_rfattach(ah);
576 if (ecode != 0)
577 return ecode;
578
579 if (!AR_SREV_9100(ah)) {
580 ath9k_hw_ani_setup(ah);
581 ath9k_hw_ani_attach(ah);
582 }
583
584 return 0;
585 }
586
587 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
588 void __iomem *mem, int *status)
589 {
590 struct ath_hal_5416 *ahp;
591 struct ath_hal *ah;
592 int ecode;
593 u32 i, j;
594
595 ahp = ath9k_hw_newstate(devid, sc, mem, status);
596 if (ahp == NULL)
597 return NULL;
598
599 ah = &ahp->ah;
600
601 ath9k_hw_set_defaults(ah);
602
603 if (ah->ah_config.intr_mitigation != 0)
604 ahp->ah_intrMitigation = true;
605
606 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
607 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
608 ecode = -EIO;
609 goto bad;
610 }
611
612 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
613 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
614 ecode = -EIO;
615 goto bad;
616 }
617
618 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
619 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
620 ah->ah_config.serialize_regmode =
621 SER_REG_MODE_ON;
622 } else {
623 ah->ah_config.serialize_regmode =
624 SER_REG_MODE_OFF;
625 }
626 }
627
628 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
629 "serialize_regmode is %d\n",
630 ah->ah_config.serialize_regmode);
631
632 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
633 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
634 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
635 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
636 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
637 "Mac Chip Rev 0x%02x.%x is not supported by "
638 "this driver\n", ah->hw_version.macVersion,
639 ah->hw_version.macRev);
640 ecode = -EOPNOTSUPP;
641 goto bad;
642 }
643
644 if (AR_SREV_9100(ah)) {
645 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
646 ahp->ah_suppCals = IQ_MISMATCH_CAL;
647 ah->ah_isPciExpress = false;
648 }
649 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
650
651 if (AR_SREV_9160_10_OR_LATER(ah)) {
652 if (AR_SREV_9280_10_OR_LATER(ah)) {
653 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
654 ahp->ah_adcGainCalData.calData =
655 &adc_gain_cal_single_sample;
656 ahp->ah_adcDcCalData.calData =
657 &adc_dc_cal_single_sample;
658 ahp->ah_adcDcCalInitData.calData =
659 &adc_init_dc_cal;
660 } else {
661 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
662 ahp->ah_adcGainCalData.calData =
663 &adc_gain_cal_multi_sample;
664 ahp->ah_adcDcCalData.calData =
665 &adc_dc_cal_multi_sample;
666 ahp->ah_adcDcCalInitData.calData =
667 &adc_init_dc_cal;
668 }
669 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
670 }
671
672 if (AR_SREV_9160(ah)) {
673 ah->ah_config.enable_ani = 1;
674 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
675 ATH9K_ANI_FIRSTEP_LEVEL);
676 } else {
677 ahp->ah_ani_function = ATH9K_ANI_ALL;
678 if (AR_SREV_9280_10_OR_LATER(ah)) {
679 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
680 }
681 }
682
683 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
684 "This Mac Chip Rev 0x%02x.%x is \n",
685 ah->hw_version.macVersion, ah->hw_version.macRev);
686
687 if (AR_SREV_9285_12_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
689 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
690 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
691 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
692
693 if (ah->ah_config.pcie_clock_req) {
694 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
695 ar9285PciePhy_clkreq_off_L1_9285_1_2,
696 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
697 } else {
698 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
699 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
700 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
701 2);
702 }
703 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
704 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
705 ARRAY_SIZE(ar9285Modes_9285), 6);
706 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
707 ARRAY_SIZE(ar9285Common_9285), 2);
708
709 if (ah->ah_config.pcie_clock_req) {
710 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
711 ar9285PciePhy_clkreq_off_L1_9285,
712 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
713 } else {
714 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
715 ar9285PciePhy_clkreq_always_on_L1_9285,
716 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
717 }
718 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
719 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
720 ARRAY_SIZE(ar9280Modes_9280_2), 6);
721 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
722 ARRAY_SIZE(ar9280Common_9280_2), 2);
723
724 if (ah->ah_config.pcie_clock_req) {
725 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
726 ar9280PciePhy_clkreq_off_L1_9280,
727 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
728 } else {
729 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
730 ar9280PciePhy_clkreq_always_on_L1_9280,
731 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
732 }
733 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
734 ar9280Modes_fast_clock_9280_2,
735 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
736 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
737 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
738 ARRAY_SIZE(ar9280Modes_9280), 6);
739 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
740 ARRAY_SIZE(ar9280Common_9280), 2);
741 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
742 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
743 ARRAY_SIZE(ar5416Modes_9160), 6);
744 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
745 ARRAY_SIZE(ar5416Common_9160), 2);
746 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
747 ARRAY_SIZE(ar5416Bank0_9160), 2);
748 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
749 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
750 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
751 ARRAY_SIZE(ar5416Bank1_9160), 2);
752 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
753 ARRAY_SIZE(ar5416Bank2_9160), 2);
754 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
755 ARRAY_SIZE(ar5416Bank3_9160), 3);
756 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
757 ARRAY_SIZE(ar5416Bank6_9160), 3);
758 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
759 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
760 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
761 ARRAY_SIZE(ar5416Bank7_9160), 2);
762 if (AR_SREV_9160_11(ah)) {
763 INIT_INI_ARRAY(&ahp->ah_iniAddac,
764 ar5416Addac_91601_1,
765 ARRAY_SIZE(ar5416Addac_91601_1), 2);
766 } else {
767 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
768 ARRAY_SIZE(ar5416Addac_9160), 2);
769 }
770 } else if (AR_SREV_9100_OR_LATER(ah)) {
771 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
772 ARRAY_SIZE(ar5416Modes_9100), 6);
773 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
774 ARRAY_SIZE(ar5416Common_9100), 2);
775 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
776 ARRAY_SIZE(ar5416Bank0_9100), 2);
777 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
778 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
779 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
780 ARRAY_SIZE(ar5416Bank1_9100), 2);
781 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
782 ARRAY_SIZE(ar5416Bank2_9100), 2);
783 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
784 ARRAY_SIZE(ar5416Bank3_9100), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
786 ARRAY_SIZE(ar5416Bank6_9100), 3);
787 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
788 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
789 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
790 ARRAY_SIZE(ar5416Bank7_9100), 2);
791 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
792 ARRAY_SIZE(ar5416Addac_9100), 2);
793 } else {
794 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
795 ARRAY_SIZE(ar5416Modes), 6);
796 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
797 ARRAY_SIZE(ar5416Common), 2);
798 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
799 ARRAY_SIZE(ar5416Bank0), 2);
800 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
801 ARRAY_SIZE(ar5416BB_RfGain), 3);
802 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
803 ARRAY_SIZE(ar5416Bank1), 2);
804 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
805 ARRAY_SIZE(ar5416Bank2), 2);
806 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
807 ARRAY_SIZE(ar5416Bank3), 3);
808 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
809 ARRAY_SIZE(ar5416Bank6), 3);
810 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
811 ARRAY_SIZE(ar5416Bank6TPC), 3);
812 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
813 ARRAY_SIZE(ar5416Bank7), 2);
814 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
815 ARRAY_SIZE(ar5416Addac), 2);
816 }
817
818 if (ah->ah_isPciExpress)
819 ath9k_hw_configpcipowersave(ah, 0);
820 else
821 ath9k_hw_disablepcie(ah);
822
823 ecode = ath9k_hw_post_attach(ah);
824 if (ecode != 0)
825 goto bad;
826
827 /* rxgain table */
828 if (AR_SREV_9280_20(ah))
829 ath9k_hw_init_rxgain_ini(ah);
830
831 /* txgain table */
832 if (AR_SREV_9280_20(ah))
833 ath9k_hw_init_txgain_ini(ah);
834
835 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
836 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
837 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
838
839 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
840 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
841
842 INI_RA(&ahp->ah_iniModes, i, j) =
843 ath9k_hw_ini_fixup(ah,
844 &ahp->ah_eeprom.def,
845 reg, val);
846 }
847 }
848 }
849
850 if (!ath9k_hw_fill_cap_info(ah)) {
851 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
852 "failed ath9k_hw_fill_cap_info\n");
853 ecode = -EINVAL;
854 goto bad;
855 }
856
857 ecode = ath9k_hw_init_macaddr(ah);
858 if (ecode != 0) {
859 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
860 "failed initializing mac address\n");
861 goto bad;
862 }
863
864 if (AR_SREV_9285(ah))
865 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
866 else
867 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
868
869 ath9k_init_nfcal_hist_buffer(ah);
870
871 return ah;
872 bad:
873 if (ahp)
874 ath9k_hw_detach((struct ath_hal *) ahp);
875 if (status)
876 *status = ecode;
877
878 return NULL;
879 }
880
881 static void ath9k_hw_init_bb(struct ath_hal *ah,
882 struct ath9k_channel *chan)
883 {
884 u32 synthDelay;
885
886 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
887 if (IS_CHAN_B(chan))
888 synthDelay = (4 * synthDelay) / 22;
889 else
890 synthDelay /= 10;
891
892 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
893
894 udelay(synthDelay + BASE_ACTIVATE_DELAY);
895 }
896
897 static void ath9k_hw_init_qos(struct ath_hal *ah)
898 {
899 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
900 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
901
902 REG_WRITE(ah, AR_QOS_NO_ACK,
903 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
904 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
905 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
906
907 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
908 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
909 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
910 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
911 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
912 }
913
914 static void ath9k_hw_init_pll(struct ath_hal *ah,
915 struct ath9k_channel *chan)
916 {
917 u32 pll;
918
919 if (AR_SREV_9100(ah)) {
920 if (chan && IS_CHAN_5GHZ(chan))
921 pll = 0x1450;
922 else
923 pll = 0x1458;
924 } else {
925 if (AR_SREV_9280_10_OR_LATER(ah)) {
926 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
927
928 if (chan && IS_CHAN_HALF_RATE(chan))
929 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
930 else if (chan && IS_CHAN_QUARTER_RATE(chan))
931 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
932
933 if (chan && IS_CHAN_5GHZ(chan)) {
934 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
935
936
937 if (AR_SREV_9280_20(ah)) {
938 if (((chan->channel % 20) == 0)
939 || ((chan->channel % 10) == 0))
940 pll = 0x2850;
941 else
942 pll = 0x142c;
943 }
944 } else {
945 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
946 }
947
948 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
949
950 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
951
952 if (chan && IS_CHAN_HALF_RATE(chan))
953 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
954 else if (chan && IS_CHAN_QUARTER_RATE(chan))
955 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
956
957 if (chan && IS_CHAN_5GHZ(chan))
958 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
959 else
960 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
961 } else {
962 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
963
964 if (chan && IS_CHAN_HALF_RATE(chan))
965 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
966 else if (chan && IS_CHAN_QUARTER_RATE(chan))
967 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
968
969 if (chan && IS_CHAN_5GHZ(chan))
970 pll |= SM(0xa, AR_RTC_PLL_DIV);
971 else
972 pll |= SM(0xb, AR_RTC_PLL_DIV);
973 }
974 }
975 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
976
977 udelay(RTC_PLL_SETTLE_DELAY);
978
979 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
980 }
981
982 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
983 {
984 struct ath_hal_5416 *ahp = AH5416(ah);
985 int rx_chainmask, tx_chainmask;
986
987 rx_chainmask = ahp->ah_rxchainmask;
988 tx_chainmask = ahp->ah_txchainmask;
989
990 switch (rx_chainmask) {
991 case 0x5:
992 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
993 AR_PHY_SWAP_ALT_CHAIN);
994 case 0x3:
995 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
996 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
997 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
998 break;
999 }
1000 case 0x1:
1001 case 0x2:
1002 case 0x7:
1003 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1004 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1005 break;
1006 default:
1007 break;
1008 }
1009
1010 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1011 if (tx_chainmask == 0x5) {
1012 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1013 AR_PHY_SWAP_ALT_CHAIN);
1014 }
1015 if (AR_SREV_9100(ah))
1016 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1017 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1018 }
1019
1020 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1021 enum nl80211_iftype opmode)
1022 {
1023 struct ath_hal_5416 *ahp = AH5416(ah);
1024
1025 ahp->ah_maskReg = AR_IMR_TXERR |
1026 AR_IMR_TXURN |
1027 AR_IMR_RXERR |
1028 AR_IMR_RXORN |
1029 AR_IMR_BCNMISC;
1030
1031 if (ahp->ah_intrMitigation)
1032 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1033 else
1034 ahp->ah_maskReg |= AR_IMR_RXOK;
1035
1036 ahp->ah_maskReg |= AR_IMR_TXOK;
1037
1038 if (opmode == NL80211_IFTYPE_AP)
1039 ahp->ah_maskReg |= AR_IMR_MIB;
1040
1041 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1042 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1043
1044 if (!AR_SREV_9100(ah)) {
1045 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1046 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1047 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1048 }
1049 }
1050
1051 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1052 {
1053 struct ath_hal_5416 *ahp = AH5416(ah);
1054
1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1057 ahp->ah_acktimeout = (u32) -1;
1058 return false;
1059 } else {
1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1061 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1062 ahp->ah_acktimeout = us;
1063 return true;
1064 }
1065 }
1066
1067 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1068 {
1069 struct ath_hal_5416 *ahp = AH5416(ah);
1070
1071 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1072 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1073 ahp->ah_ctstimeout = (u32) -1;
1074 return false;
1075 } else {
1076 REG_RMW_FIELD(ah, AR_TIME_OUT,
1077 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1078 ahp->ah_ctstimeout = us;
1079 return true;
1080 }
1081 }
1082
1083 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1084 {
1085 struct ath_hal_5416 *ahp = AH5416(ah);
1086
1087 if (tu > 0xFFFF) {
1088 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1089 "bad global tx timeout %u\n", tu);
1090 ahp->ah_globaltxtimeout = (u32) -1;
1091 return false;
1092 } else {
1093 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1094 ahp->ah_globaltxtimeout = tu;
1095 return true;
1096 }
1097 }
1098
1099 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1100 {
1101 struct ath_hal_5416 *ahp = AH5416(ah);
1102
1103 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1104 ahp->ah_miscMode);
1105
1106 if (ahp->ah_miscMode != 0)
1107 REG_WRITE(ah, AR_PCU_MISC,
1108 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1109 if (ahp->ah_slottime != (u32) -1)
1110 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1111 if (ahp->ah_acktimeout != (u32) -1)
1112 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1113 if (ahp->ah_ctstimeout != (u32) -1)
1114 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1115 if (ahp->ah_globaltxtimeout != (u32) -1)
1116 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1117 }
1118
1119 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1120 {
1121 return vendorid == ATHEROS_VENDOR_ID ?
1122 ath9k_hw_devname(devid) : NULL;
1123 }
1124
1125 void ath9k_hw_detach(struct ath_hal *ah)
1126 {
1127 if (!AR_SREV_9100(ah))
1128 ath9k_hw_ani_detach(ah);
1129
1130 ath9k_hw_rfdetach(ah);
1131 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1132 kfree(ah);
1133 }
1134
1135 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1136 void __iomem *mem, int *error)
1137 {
1138 struct ath_hal *ah = NULL;
1139
1140 switch (devid) {
1141 case AR5416_DEVID_PCI:
1142 case AR5416_DEVID_PCIE:
1143 case AR5416_AR9100_DEVID:
1144 case AR9160_DEVID_PCI:
1145 case AR9280_DEVID_PCI:
1146 case AR9280_DEVID_PCIE:
1147 case AR9285_DEVID_PCIE:
1148 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1149 break;
1150 default:
1151 *error = -ENXIO;
1152 break;
1153 }
1154
1155 return ah;
1156 }
1157
1158 /*******/
1159 /* INI */
1160 /*******/
1161
1162 static void ath9k_hw_override_ini(struct ath_hal *ah,
1163 struct ath9k_channel *chan)
1164 {
1165 /*
1166 * Set the RX_ABORT and RX_DIS and clear if off only after
1167 * RXE is set for MAC. This prevents frames with corrupted
1168 * descriptor status.
1169 */
1170 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1171
1172
1173 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1174 AR_SREV_9280_10_OR_LATER(ah))
1175 return;
1176
1177 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1178 }
1179
1180 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1181 struct ar5416_eeprom_def *pEepData,
1182 u32 reg, u32 value)
1183 {
1184 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1185
1186 switch (ah->hw_version.devid) {
1187 case AR9280_DEVID_PCI:
1188 if (reg == 0x7894) {
1189 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1190 "ini VAL: %x EEPROM: %x\n", value,
1191 (pBase->version & 0xff));
1192
1193 if ((pBase->version & 0xff) > 0x0a) {
1194 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1195 "PWDCLKIND: %d\n",
1196 pBase->pwdclkind);
1197 value &= ~AR_AN_TOP2_PWDCLKIND;
1198 value |= AR_AN_TOP2_PWDCLKIND &
1199 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1200 } else {
1201 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1202 "PWDCLKIND Earlier Rev\n");
1203 }
1204
1205 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1206 "final ini VAL: %x\n", value);
1207 }
1208 break;
1209 }
1210
1211 return value;
1212 }
1213
1214 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1215 struct ar5416_eeprom_def *pEepData,
1216 u32 reg, u32 value)
1217 {
1218 struct ath_hal_5416 *ahp = AH5416(ah);
1219
1220 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1221 return value;
1222 else
1223 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1224 }
1225
1226 static int ath9k_hw_process_ini(struct ath_hal *ah,
1227 struct ath9k_channel *chan,
1228 enum ath9k_ht_macmode macmode)
1229 {
1230 int i, regWrites = 0;
1231 struct ath_hal_5416 *ahp = AH5416(ah);
1232 struct ieee80211_channel *channel = chan->chan;
1233 u32 modesIndex, freqIndex;
1234 int status;
1235
1236 switch (chan->chanmode) {
1237 case CHANNEL_A:
1238 case CHANNEL_A_HT20:
1239 modesIndex = 1;
1240 freqIndex = 1;
1241 break;
1242 case CHANNEL_A_HT40PLUS:
1243 case CHANNEL_A_HT40MINUS:
1244 modesIndex = 2;
1245 freqIndex = 1;
1246 break;
1247 case CHANNEL_G:
1248 case CHANNEL_G_HT20:
1249 case CHANNEL_B:
1250 modesIndex = 4;
1251 freqIndex = 2;
1252 break;
1253 case CHANNEL_G_HT40PLUS:
1254 case CHANNEL_G_HT40MINUS:
1255 modesIndex = 3;
1256 freqIndex = 2;
1257 break;
1258
1259 default:
1260 return -EINVAL;
1261 }
1262
1263 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1264
1265 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1266
1267 ath9k_hw_set_addac(ah, chan);
1268
1269 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1270 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1271 } else {
1272 struct ar5416IniArray temp;
1273 u32 addacSize =
1274 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1275 ahp->ah_iniAddac.ia_columns;
1276
1277 memcpy(ahp->ah_addac5416_21,
1278 ahp->ah_iniAddac.ia_array, addacSize);
1279
1280 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1281
1282 temp.ia_array = ahp->ah_addac5416_21;
1283 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1284 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1285 REG_WRITE_ARRAY(&temp, 1, regWrites);
1286 }
1287
1288 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1289
1290 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1291 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1292 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1293
1294 REG_WRITE(ah, reg, val);
1295
1296 if (reg >= 0x7800 && reg < 0x78a0
1297 && ah->ah_config.analog_shiftreg) {
1298 udelay(100);
1299 }
1300
1301 DO_DELAY(regWrites);
1302 }
1303
1304 if (AR_SREV_9280(ah))
1305 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1306
1307 if (AR_SREV_9280(ah))
1308 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1309
1310 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1311 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1312 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1313
1314 REG_WRITE(ah, reg, val);
1315
1316 if (reg >= 0x7800 && reg < 0x78a0
1317 && ah->ah_config.analog_shiftreg) {
1318 udelay(100);
1319 }
1320
1321 DO_DELAY(regWrites);
1322 }
1323
1324 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1325
1326 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1327 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1328 regWrites);
1329 }
1330
1331 ath9k_hw_override_ini(ah, chan);
1332 ath9k_hw_set_regs(ah, chan, macmode);
1333 ath9k_hw_init_chain_masks(ah);
1334
1335 status = ath9k_hw_set_txpower(ah, chan,
1336 ath9k_regd_get_ctl(ah, chan),
1337 channel->max_antenna_gain * 2,
1338 channel->max_power * 2,
1339 min((u32) MAX_RATE_POWER,
1340 (u32) ah->ah_powerLimit));
1341 if (status != 0) {
1342 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1343 "error init'ing transmit power\n");
1344 return -EIO;
1345 }
1346
1347 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1348 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1349 "ar5416SetRfRegs failed\n");
1350 return -EIO;
1351 }
1352
1353 return 0;
1354 }
1355
1356 /****************************************/
1357 /* Reset and Channel Switching Routines */
1358 /****************************************/
1359
1360 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1361 {
1362 u32 rfMode = 0;
1363
1364 if (chan == NULL)
1365 return;
1366
1367 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1368 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1369
1370 if (!AR_SREV_9280_10_OR_LATER(ah))
1371 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1372 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1373
1374 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1375 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1376
1377 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1378 }
1379
1380 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1381 {
1382 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1383 }
1384
1385 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1386 {
1387 u32 regval;
1388
1389 regval = REG_READ(ah, AR_AHB_MODE);
1390 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1391
1392 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1393 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1394
1395 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1396
1397 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1398 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1399
1400 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1401
1402 if (AR_SREV_9285(ah)) {
1403 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1404 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1405 } else {
1406 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1407 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1408 }
1409 }
1410
1411 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1412 {
1413 u32 val;
1414
1415 val = REG_READ(ah, AR_STA_ID1);
1416 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1417 switch (opmode) {
1418 case NL80211_IFTYPE_AP:
1419 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1420 | AR_STA_ID1_KSRCH_MODE);
1421 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1422 break;
1423 case NL80211_IFTYPE_ADHOC:
1424 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1425 | AR_STA_ID1_KSRCH_MODE);
1426 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1427 break;
1428 case NL80211_IFTYPE_STATION:
1429 case NL80211_IFTYPE_MONITOR:
1430 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1431 break;
1432 }
1433 }
1434
1435 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1436 u32 coef_scaled,
1437 u32 *coef_mantissa,
1438 u32 *coef_exponent)
1439 {
1440 u32 coef_exp, coef_man;
1441
1442 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1443 if ((coef_scaled >> coef_exp) & 0x1)
1444 break;
1445
1446 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1447
1448 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1449
1450 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1451 *coef_exponent = coef_exp - 16;
1452 }
1453
1454 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1455 struct ath9k_channel *chan)
1456 {
1457 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1458 u32 clockMhzScaled = 0x64000000;
1459 struct chan_centers centers;
1460
1461 if (IS_CHAN_HALF_RATE(chan))
1462 clockMhzScaled = clockMhzScaled >> 1;
1463 else if (IS_CHAN_QUARTER_RATE(chan))
1464 clockMhzScaled = clockMhzScaled >> 2;
1465
1466 ath9k_hw_get_channel_centers(ah, chan, &centers);
1467 coef_scaled = clockMhzScaled / centers.synth_center;
1468
1469 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1470 &ds_coef_exp);
1471
1472 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1473 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1474 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1475 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1476
1477 coef_scaled = (9 * coef_scaled) / 10;
1478
1479 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1480 &ds_coef_exp);
1481
1482 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1483 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1484 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1485 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1486 }
1487
1488 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1489 {
1490 u32 rst_flags;
1491 u32 tmpReg;
1492
1493 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1494 AR_RTC_FORCE_WAKE_ON_INT);
1495
1496 if (AR_SREV_9100(ah)) {
1497 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1498 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1499 } else {
1500 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1501 if (tmpReg &
1502 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1503 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1504 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1505 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1506 } else {
1507 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1508 }
1509
1510 rst_flags = AR_RTC_RC_MAC_WARM;
1511 if (type == ATH9K_RESET_COLD)
1512 rst_flags |= AR_RTC_RC_MAC_COLD;
1513 }
1514
1515 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1516 udelay(50);
1517
1518 REG_WRITE(ah, AR_RTC_RC, 0);
1519 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1520 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1521 "RTC stuck in MAC reset\n");
1522 return false;
1523 }
1524
1525 if (!AR_SREV_9100(ah))
1526 REG_WRITE(ah, AR_RC, 0);
1527
1528 ath9k_hw_init_pll(ah, NULL);
1529
1530 if (AR_SREV_9100(ah))
1531 udelay(50);
1532
1533 return true;
1534 }
1535
1536 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1537 {
1538 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1539 AR_RTC_FORCE_WAKE_ON_INT);
1540
1541 REG_WRITE(ah, AR_RTC_RESET, 0);
1542 REG_WRITE(ah, AR_RTC_RESET, 1);
1543
1544 if (!ath9k_hw_wait(ah,
1545 AR_RTC_STATUS,
1546 AR_RTC_STATUS_M,
1547 AR_RTC_STATUS_ON)) {
1548 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1549 return false;
1550 }
1551
1552 ath9k_hw_read_revisions(ah);
1553
1554 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1555 }
1556
1557 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1558 {
1559 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1560 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1561
1562 switch (type) {
1563 case ATH9K_RESET_POWER_ON:
1564 return ath9k_hw_set_reset_power_on(ah);
1565 break;
1566 case ATH9K_RESET_WARM:
1567 case ATH9K_RESET_COLD:
1568 return ath9k_hw_set_reset(ah, type);
1569 break;
1570 default:
1571 return false;
1572 }
1573 }
1574
1575 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1576 enum ath9k_ht_macmode macmode)
1577 {
1578 u32 phymode;
1579 u32 enableDacFifo = 0;
1580 struct ath_hal_5416 *ahp = AH5416(ah);
1581
1582 if (AR_SREV_9285_10_OR_LATER(ah))
1583 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1584 AR_PHY_FC_ENABLE_DAC_FIFO);
1585
1586 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1587 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1588
1589 if (IS_CHAN_HT40(chan)) {
1590 phymode |= AR_PHY_FC_DYN2040_EN;
1591
1592 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1593 (chan->chanmode == CHANNEL_G_HT40PLUS))
1594 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1595
1596 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1597 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1598 }
1599 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1600
1601 ath9k_hw_set11nmac2040(ah, macmode);
1602
1603 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1604 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1605 }
1606
1607 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1608 struct ath9k_channel *chan)
1609 {
1610 struct ath_hal_5416 *ahp = AH5416(ah);
1611
1612 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1613 return false;
1614
1615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1616 return false;
1617
1618 ahp->ah_chipFullSleep = false;
1619
1620 ath9k_hw_init_pll(ah, chan);
1621
1622 ath9k_hw_set_rfmode(ah, chan);
1623
1624 return true;
1625 }
1626
1627 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1628 struct ath9k_channel *chan,
1629 enum ath9k_ht_macmode macmode)
1630 {
1631 struct ieee80211_channel *channel = chan->chan;
1632 u32 synthDelay, qnum;
1633
1634 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1635 if (ath9k_hw_numtxpending(ah, qnum)) {
1636 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1637 "Transmit frames pending on queue %d\n", qnum);
1638 return false;
1639 }
1640 }
1641
1642 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1643 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1644 AR_PHY_RFBUS_GRANT_EN)) {
1645 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1646 "Could not kill baseband RX\n");
1647 return false;
1648 }
1649
1650 ath9k_hw_set_regs(ah, chan, macmode);
1651
1652 if (AR_SREV_9280_10_OR_LATER(ah)) {
1653 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1654 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1655 "failed to set channel\n");
1656 return false;
1657 }
1658 } else {
1659 if (!(ath9k_hw_set_channel(ah, chan))) {
1660 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1661 "failed to set channel\n");
1662 return false;
1663 }
1664 }
1665
1666 if (ath9k_hw_set_txpower(ah, chan,
1667 ath9k_regd_get_ctl(ah, chan),
1668 channel->max_antenna_gain * 2,
1669 channel->max_power * 2,
1670 min((u32) MAX_RATE_POWER,
1671 (u32) ah->ah_powerLimit)) != 0) {
1672 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1673 "error init'ing transmit power\n");
1674 return false;
1675 }
1676
1677 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1678 if (IS_CHAN_B(chan))
1679 synthDelay = (4 * synthDelay) / 22;
1680 else
1681 synthDelay /= 10;
1682
1683 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1684
1685 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1686
1687 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1688 ath9k_hw_set_delta_slope(ah, chan);
1689
1690 if (AR_SREV_9280_10_OR_LATER(ah))
1691 ath9k_hw_9280_spur_mitigate(ah, chan);
1692 else
1693 ath9k_hw_spur_mitigate(ah, chan);
1694
1695 if (!chan->oneTimeCalsDone)
1696 chan->oneTimeCalsDone = true;
1697
1698 return true;
1699 }
1700
1701 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1702 {
1703 int bb_spur = AR_NO_SPUR;
1704 int freq;
1705 int bin, cur_bin;
1706 int bb_spur_off, spur_subchannel_sd;
1707 int spur_freq_sd;
1708 int spur_delta_phase;
1709 int denominator;
1710 int upper, lower, cur_vit_mask;
1711 int tmp, newVal;
1712 int i;
1713 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1714 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1715 };
1716 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1717 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1718 };
1719 int inc[4] = { 0, 100, 0, 0 };
1720 struct chan_centers centers;
1721
1722 int8_t mask_m[123];
1723 int8_t mask_p[123];
1724 int8_t mask_amt;
1725 int tmp_mask;
1726 int cur_bb_spur;
1727 bool is2GHz = IS_CHAN_2GHZ(chan);
1728
1729 memset(&mask_m, 0, sizeof(int8_t) * 123);
1730 memset(&mask_p, 0, sizeof(int8_t) * 123);
1731
1732 ath9k_hw_get_channel_centers(ah, chan, &centers);
1733 freq = centers.synth_center;
1734
1735 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1736 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1737 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1738
1739 if (is2GHz)
1740 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1741 else
1742 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1743
1744 if (AR_NO_SPUR == cur_bb_spur)
1745 break;
1746 cur_bb_spur = cur_bb_spur - freq;
1747
1748 if (IS_CHAN_HT40(chan)) {
1749 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1750 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1751 bb_spur = cur_bb_spur;
1752 break;
1753 }
1754 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1755 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1756 bb_spur = cur_bb_spur;
1757 break;
1758 }
1759 }
1760
1761 if (AR_NO_SPUR == bb_spur) {
1762 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1763 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1764 return;
1765 } else {
1766 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1767 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1768 }
1769
1770 bin = bb_spur * 320;
1771
1772 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1773
1774 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1775 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1776 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1777 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1778 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1779
1780 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1781 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1782 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1783 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1784 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1785 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1786
1787 if (IS_CHAN_HT40(chan)) {
1788 if (bb_spur < 0) {
1789 spur_subchannel_sd = 1;
1790 bb_spur_off = bb_spur + 10;
1791 } else {
1792 spur_subchannel_sd = 0;
1793 bb_spur_off = bb_spur - 10;
1794 }
1795 } else {
1796 spur_subchannel_sd = 0;
1797 bb_spur_off = bb_spur;
1798 }
1799
1800 if (IS_CHAN_HT40(chan))
1801 spur_delta_phase =
1802 ((bb_spur * 262144) /
1803 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1804 else
1805 spur_delta_phase =
1806 ((bb_spur * 524288) /
1807 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1808
1809 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1810 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1811
1812 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1813 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1814 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1815 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1816
1817 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1818 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1819
1820 cur_bin = -6000;
1821 upper = bin + 100;
1822 lower = bin - 100;
1823
1824 for (i = 0; i < 4; i++) {
1825 int pilot_mask = 0;
1826 int chan_mask = 0;
1827 int bp = 0;
1828 for (bp = 0; bp < 30; bp++) {
1829 if ((cur_bin > lower) && (cur_bin < upper)) {
1830 pilot_mask = pilot_mask | 0x1 << bp;
1831 chan_mask = chan_mask | 0x1 << bp;
1832 }
1833 cur_bin += 100;
1834 }
1835 cur_bin += inc[i];
1836 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1837 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1838 }
1839
1840 cur_vit_mask = 6100;
1841 upper = bin + 120;
1842 lower = bin - 120;
1843
1844 for (i = 0; i < 123; i++) {
1845 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1846
1847 /* workaround for gcc bug #37014 */
1848 volatile int tmp_v = abs(cur_vit_mask - bin);
1849
1850 if (tmp_v < 75)
1851 mask_amt = 1;
1852 else
1853 mask_amt = 0;
1854 if (cur_vit_mask < 0)
1855 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1856 else
1857 mask_p[cur_vit_mask / 100] = mask_amt;
1858 }
1859 cur_vit_mask -= 100;
1860 }
1861
1862 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1863 | (mask_m[48] << 26) | (mask_m[49] << 24)
1864 | (mask_m[50] << 22) | (mask_m[51] << 20)
1865 | (mask_m[52] << 18) | (mask_m[53] << 16)
1866 | (mask_m[54] << 14) | (mask_m[55] << 12)
1867 | (mask_m[56] << 10) | (mask_m[57] << 8)
1868 | (mask_m[58] << 6) | (mask_m[59] << 4)
1869 | (mask_m[60] << 2) | (mask_m[61] << 0);
1870 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1871 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1872
1873 tmp_mask = (mask_m[31] << 28)
1874 | (mask_m[32] << 26) | (mask_m[33] << 24)
1875 | (mask_m[34] << 22) | (mask_m[35] << 20)
1876 | (mask_m[36] << 18) | (mask_m[37] << 16)
1877 | (mask_m[48] << 14) | (mask_m[39] << 12)
1878 | (mask_m[40] << 10) | (mask_m[41] << 8)
1879 | (mask_m[42] << 6) | (mask_m[43] << 4)
1880 | (mask_m[44] << 2) | (mask_m[45] << 0);
1881 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1882 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1883
1884 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1885 | (mask_m[18] << 26) | (mask_m[18] << 24)
1886 | (mask_m[20] << 22) | (mask_m[20] << 20)
1887 | (mask_m[22] << 18) | (mask_m[22] << 16)
1888 | (mask_m[24] << 14) | (mask_m[24] << 12)
1889 | (mask_m[25] << 10) | (mask_m[26] << 8)
1890 | (mask_m[27] << 6) | (mask_m[28] << 4)
1891 | (mask_m[29] << 2) | (mask_m[30] << 0);
1892 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1893 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1894
1895 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1896 | (mask_m[2] << 26) | (mask_m[3] << 24)
1897 | (mask_m[4] << 22) | (mask_m[5] << 20)
1898 | (mask_m[6] << 18) | (mask_m[7] << 16)
1899 | (mask_m[8] << 14) | (mask_m[9] << 12)
1900 | (mask_m[10] << 10) | (mask_m[11] << 8)
1901 | (mask_m[12] << 6) | (mask_m[13] << 4)
1902 | (mask_m[14] << 2) | (mask_m[15] << 0);
1903 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1905
1906 tmp_mask = (mask_p[15] << 28)
1907 | (mask_p[14] << 26) | (mask_p[13] << 24)
1908 | (mask_p[12] << 22) | (mask_p[11] << 20)
1909 | (mask_p[10] << 18) | (mask_p[9] << 16)
1910 | (mask_p[8] << 14) | (mask_p[7] << 12)
1911 | (mask_p[6] << 10) | (mask_p[5] << 8)
1912 | (mask_p[4] << 6) | (mask_p[3] << 4)
1913 | (mask_p[2] << 2) | (mask_p[1] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1916
1917 tmp_mask = (mask_p[30] << 28)
1918 | (mask_p[29] << 26) | (mask_p[28] << 24)
1919 | (mask_p[27] << 22) | (mask_p[26] << 20)
1920 | (mask_p[25] << 18) | (mask_p[24] << 16)
1921 | (mask_p[23] << 14) | (mask_p[22] << 12)
1922 | (mask_p[21] << 10) | (mask_p[20] << 8)
1923 | (mask_p[19] << 6) | (mask_p[18] << 4)
1924 | (mask_p[17] << 2) | (mask_p[16] << 0);
1925 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1927
1928 tmp_mask = (mask_p[45] << 28)
1929 | (mask_p[44] << 26) | (mask_p[43] << 24)
1930 | (mask_p[42] << 22) | (mask_p[41] << 20)
1931 | (mask_p[40] << 18) | (mask_p[39] << 16)
1932 | (mask_p[38] << 14) | (mask_p[37] << 12)
1933 | (mask_p[36] << 10) | (mask_p[35] << 8)
1934 | (mask_p[34] << 6) | (mask_p[33] << 4)
1935 | (mask_p[32] << 2) | (mask_p[31] << 0);
1936 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1938
1939 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1940 | (mask_p[59] << 26) | (mask_p[58] << 24)
1941 | (mask_p[57] << 22) | (mask_p[56] << 20)
1942 | (mask_p[55] << 18) | (mask_p[54] << 16)
1943 | (mask_p[53] << 14) | (mask_p[52] << 12)
1944 | (mask_p[51] << 10) | (mask_p[50] << 8)
1945 | (mask_p[49] << 6) | (mask_p[48] << 4)
1946 | (mask_p[47] << 2) | (mask_p[46] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1949 }
1950
1951 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1952 {
1953 int bb_spur = AR_NO_SPUR;
1954 int bin, cur_bin;
1955 int spur_freq_sd;
1956 int spur_delta_phase;
1957 int denominator;
1958 int upper, lower, cur_vit_mask;
1959 int tmp, new;
1960 int i;
1961 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1962 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1963 };
1964 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1965 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1966 };
1967 int inc[4] = { 0, 100, 0, 0 };
1968
1969 int8_t mask_m[123];
1970 int8_t mask_p[123];
1971 int8_t mask_amt;
1972 int tmp_mask;
1973 int cur_bb_spur;
1974 bool is2GHz = IS_CHAN_2GHZ(chan);
1975
1976 memset(&mask_m, 0, sizeof(int8_t) * 123);
1977 memset(&mask_p, 0, sizeof(int8_t) * 123);
1978
1979 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1980 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1981 if (AR_NO_SPUR == cur_bb_spur)
1982 break;
1983 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1984 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1985 bb_spur = cur_bb_spur;
1986 break;
1987 }
1988 }
1989
1990 if (AR_NO_SPUR == bb_spur)
1991 return;
1992
1993 bin = bb_spur * 32;
1994
1995 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1996 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1997 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1998 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1999 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2000
2001 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2002
2003 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2004 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2005 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2006 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2007 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2008 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2009
2010 spur_delta_phase = ((bb_spur * 524288) / 100) &
2011 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2012
2013 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2014 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2015
2016 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2017 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2018 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2019 REG_WRITE(ah, AR_PHY_TIMING11, new);
2020
2021 cur_bin = -6000;
2022 upper = bin + 100;
2023 lower = bin - 100;
2024
2025 for (i = 0; i < 4; i++) {
2026 int pilot_mask = 0;
2027 int chan_mask = 0;
2028 int bp = 0;
2029 for (bp = 0; bp < 30; bp++) {
2030 if ((cur_bin > lower) && (cur_bin < upper)) {
2031 pilot_mask = pilot_mask | 0x1 << bp;
2032 chan_mask = chan_mask | 0x1 << bp;
2033 }
2034 cur_bin += 100;
2035 }
2036 cur_bin += inc[i];
2037 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2038 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2039 }
2040
2041 cur_vit_mask = 6100;
2042 upper = bin + 120;
2043 lower = bin - 120;
2044
2045 for (i = 0; i < 123; i++) {
2046 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2047
2048 /* workaround for gcc bug #37014 */
2049 volatile int tmp_v = abs(cur_vit_mask - bin);
2050
2051 if (tmp_v < 75)
2052 mask_amt = 1;
2053 else
2054 mask_amt = 0;
2055 if (cur_vit_mask < 0)
2056 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2057 else
2058 mask_p[cur_vit_mask / 100] = mask_amt;
2059 }
2060 cur_vit_mask -= 100;
2061 }
2062
2063 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2064 | (mask_m[48] << 26) | (mask_m[49] << 24)
2065 | (mask_m[50] << 22) | (mask_m[51] << 20)
2066 | (mask_m[52] << 18) | (mask_m[53] << 16)
2067 | (mask_m[54] << 14) | (mask_m[55] << 12)
2068 | (mask_m[56] << 10) | (mask_m[57] << 8)
2069 | (mask_m[58] << 6) | (mask_m[59] << 4)
2070 | (mask_m[60] << 2) | (mask_m[61] << 0);
2071 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2072 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2073
2074 tmp_mask = (mask_m[31] << 28)
2075 | (mask_m[32] << 26) | (mask_m[33] << 24)
2076 | (mask_m[34] << 22) | (mask_m[35] << 20)
2077 | (mask_m[36] << 18) | (mask_m[37] << 16)
2078 | (mask_m[48] << 14) | (mask_m[39] << 12)
2079 | (mask_m[40] << 10) | (mask_m[41] << 8)
2080 | (mask_m[42] << 6) | (mask_m[43] << 4)
2081 | (mask_m[44] << 2) | (mask_m[45] << 0);
2082 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2083 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2084
2085 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2086 | (mask_m[18] << 26) | (mask_m[18] << 24)
2087 | (mask_m[20] << 22) | (mask_m[20] << 20)
2088 | (mask_m[22] << 18) | (mask_m[22] << 16)
2089 | (mask_m[24] << 14) | (mask_m[24] << 12)
2090 | (mask_m[25] << 10) | (mask_m[26] << 8)
2091 | (mask_m[27] << 6) | (mask_m[28] << 4)
2092 | (mask_m[29] << 2) | (mask_m[30] << 0);
2093 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2094 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2095
2096 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2097 | (mask_m[2] << 26) | (mask_m[3] << 24)
2098 | (mask_m[4] << 22) | (mask_m[5] << 20)
2099 | (mask_m[6] << 18) | (mask_m[7] << 16)
2100 | (mask_m[8] << 14) | (mask_m[9] << 12)
2101 | (mask_m[10] << 10) | (mask_m[11] << 8)
2102 | (mask_m[12] << 6) | (mask_m[13] << 4)
2103 | (mask_m[14] << 2) | (mask_m[15] << 0);
2104 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2106
2107 tmp_mask = (mask_p[15] << 28)
2108 | (mask_p[14] << 26) | (mask_p[13] << 24)
2109 | (mask_p[12] << 22) | (mask_p[11] << 20)
2110 | (mask_p[10] << 18) | (mask_p[9] << 16)
2111 | (mask_p[8] << 14) | (mask_p[7] << 12)
2112 | (mask_p[6] << 10) | (mask_p[5] << 8)
2113 | (mask_p[4] << 6) | (mask_p[3] << 4)
2114 | (mask_p[2] << 2) | (mask_p[1] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2117
2118 tmp_mask = (mask_p[30] << 28)
2119 | (mask_p[29] << 26) | (mask_p[28] << 24)
2120 | (mask_p[27] << 22) | (mask_p[26] << 20)
2121 | (mask_p[25] << 18) | (mask_p[24] << 16)
2122 | (mask_p[23] << 14) | (mask_p[22] << 12)
2123 | (mask_p[21] << 10) | (mask_p[20] << 8)
2124 | (mask_p[19] << 6) | (mask_p[18] << 4)
2125 | (mask_p[17] << 2) | (mask_p[16] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2128
2129 tmp_mask = (mask_p[45] << 28)
2130 | (mask_p[44] << 26) | (mask_p[43] << 24)
2131 | (mask_p[42] << 22) | (mask_p[41] << 20)
2132 | (mask_p[40] << 18) | (mask_p[39] << 16)
2133 | (mask_p[38] << 14) | (mask_p[37] << 12)
2134 | (mask_p[36] << 10) | (mask_p[35] << 8)
2135 | (mask_p[34] << 6) | (mask_p[33] << 4)
2136 | (mask_p[32] << 2) | (mask_p[31] << 0);
2137 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2139
2140 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2141 | (mask_p[59] << 26) | (mask_p[58] << 24)
2142 | (mask_p[57] << 22) | (mask_p[56] << 20)
2143 | (mask_p[55] << 18) | (mask_p[54] << 16)
2144 | (mask_p[53] << 14) | (mask_p[52] << 12)
2145 | (mask_p[51] << 10) | (mask_p[50] << 8)
2146 | (mask_p[49] << 6) | (mask_p[48] << 4)
2147 | (mask_p[47] << 2) | (mask_p[46] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2150 }
2151
2152 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2153 bool bChannelChange)
2154 {
2155 u32 saveLedState;
2156 struct ath_softc *sc = ah->ah_sc;
2157 struct ath_hal_5416 *ahp = AH5416(ah);
2158 struct ath9k_channel *curchan = ah->ah_curchan;
2159 u32 saveDefAntenna;
2160 u32 macStaId1;
2161 int i, rx_chainmask, r;
2162
2163 ahp->ah_extprotspacing = sc->ht_extprotspacing;
2164 ahp->ah_txchainmask = sc->tx_chainmask;
2165 ahp->ah_rxchainmask = sc->rx_chainmask;
2166
2167 if (AR_SREV_9285(ah)) {
2168 ahp->ah_txchainmask &= 0x1;
2169 ahp->ah_rxchainmask &= 0x1;
2170 } else if (AR_SREV_9280(ah)) {
2171 ahp->ah_txchainmask &= 0x3;
2172 ahp->ah_rxchainmask &= 0x3;
2173 }
2174
2175 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2176 return -EIO;
2177
2178 if (curchan)
2179 ath9k_hw_getnf(ah, curchan);
2180
2181 if (bChannelChange &&
2182 (ahp->ah_chipFullSleep != true) &&
2183 (ah->ah_curchan != NULL) &&
2184 (chan->channel != ah->ah_curchan->channel) &&
2185 ((chan->channelFlags & CHANNEL_ALL) ==
2186 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2187 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2188 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2189
2190 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2191 ath9k_hw_loadnf(ah, ah->ah_curchan);
2192 ath9k_hw_start_nfcal(ah);
2193 return 0;
2194 }
2195 }
2196
2197 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2198 if (saveDefAntenna == 0)
2199 saveDefAntenna = 1;
2200
2201 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2202
2203 saveLedState = REG_READ(ah, AR_CFG_LED) &
2204 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2205 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2206
2207 ath9k_hw_mark_phy_inactive(ah);
2208
2209 if (!ath9k_hw_chip_reset(ah, chan)) {
2210 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2211 return -EINVAL;
2212 }
2213
2214 if (AR_SREV_9280_10_OR_LATER(ah))
2215 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2216
2217 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2218 if (r)
2219 return r;
2220
2221 /* Setup MFP options for CCMP */
2222 if (AR_SREV_9280_20_OR_LATER(ah)) {
2223 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2224 * frames when constructing CCMP AAD. */
2225 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2226 0xc7ff);
2227 ah->sw_mgmt_crypto = false;
2228 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2229 /* Disable hardware crypto for management frames */
2230 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2231 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2232 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2233 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2234 ah->sw_mgmt_crypto = true;
2235 } else
2236 ah->sw_mgmt_crypto = true;
2237
2238 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2239 ath9k_hw_set_delta_slope(ah, chan);
2240
2241 if (AR_SREV_9280_10_OR_LATER(ah))
2242 ath9k_hw_9280_spur_mitigate(ah, chan);
2243 else
2244 ath9k_hw_spur_mitigate(ah, chan);
2245
2246 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2247 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2248 "error setting board options\n");
2249 return -EIO;
2250 }
2251
2252 ath9k_hw_decrease_chain_power(ah, chan);
2253
2254 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2255 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2256 | macStaId1
2257 | AR_STA_ID1_RTS_USE_DEF
2258 | (ah->ah_config.
2259 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2260 | ahp->ah_staId1Defaults);
2261 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2262
2263 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2264 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2265
2266 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2267
2268 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2269 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2270 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2271
2272 REG_WRITE(ah, AR_ISR, ~0);
2273
2274 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2275
2276 if (AR_SREV_9280_10_OR_LATER(ah)) {
2277 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2278 return -EIO;
2279 } else {
2280 if (!(ath9k_hw_set_channel(ah, chan)))
2281 return -EIO;
2282 }
2283
2284 for (i = 0; i < AR_NUM_DCU; i++)
2285 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2286
2287 ahp->ah_intrTxqs = 0;
2288 for (i = 0; i < ah->ah_caps.total_queues; i++)
2289 ath9k_hw_resettxqueue(ah, i);
2290
2291 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2292 ath9k_hw_init_qos(ah);
2293
2294 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2295 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2296 ath9k_enable_rfkill(ah);
2297 #endif
2298 ath9k_hw_init_user_settings(ah);
2299
2300 REG_WRITE(ah, AR_STA_ID1,
2301 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2302
2303 ath9k_hw_set_dma(ah);
2304
2305 REG_WRITE(ah, AR_OBS, 8);
2306
2307 if (ahp->ah_intrMitigation) {
2308
2309 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2310 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2311 }
2312
2313 ath9k_hw_init_bb(ah, chan);
2314
2315 if (!ath9k_hw_init_cal(ah, chan))
2316 return -EIO;;
2317
2318 rx_chainmask = ahp->ah_rxchainmask;
2319 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2320 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2321 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2322 }
2323
2324 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2325
2326 if (AR_SREV_9100(ah)) {
2327 u32 mask;
2328 mask = REG_READ(ah, AR_CFG);
2329 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2330 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2331 "CFG Byte Swap Set 0x%x\n", mask);
2332 } else {
2333 mask =
2334 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2335 REG_WRITE(ah, AR_CFG, mask);
2336 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2337 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2338 }
2339 } else {
2340 #ifdef __BIG_ENDIAN
2341 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2342 #endif
2343 }
2344
2345 return 0;
2346 }
2347
2348 /************************/
2349 /* Key Cache Management */
2350 /************************/
2351
2352 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2353 {
2354 u32 keyType;
2355
2356 if (entry >= ah->ah_caps.keycache_size) {
2357 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2358 "entry %u out of range\n", entry);
2359 return false;
2360 }
2361
2362 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2363
2364 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2366 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2367 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2368 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2369 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2370 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2371 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2372
2373 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2374 u16 micentry = entry + 64;
2375
2376 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2377 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2378 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2379 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2380
2381 }
2382
2383 if (ah->ah_curchan == NULL)
2384 return true;
2385
2386 return true;
2387 }
2388
2389 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2390 {
2391 u32 macHi, macLo;
2392
2393 if (entry >= ah->ah_caps.keycache_size) {
2394 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2395 "entry %u out of range\n", entry);
2396 return false;
2397 }
2398
2399 if (mac != NULL) {
2400 macHi = (mac[5] << 8) | mac[4];
2401 macLo = (mac[3] << 24) |
2402 (mac[2] << 16) |
2403 (mac[1] << 8) |
2404 mac[0];
2405 macLo >>= 1;
2406 macLo |= (macHi & 1) << 31;
2407 macHi >>= 1;
2408 } else {
2409 macLo = macHi = 0;
2410 }
2411 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2412 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2413
2414 return true;
2415 }
2416
2417 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2418 const struct ath9k_keyval *k,
2419 const u8 *mac, int xorKey)
2420 {
2421 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2422 u32 key0, key1, key2, key3, key4;
2423 u32 keyType;
2424 u32 xorMask = xorKey ?
2425 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2426 | ATH9K_KEY_XOR) : 0;
2427 struct ath_hal_5416 *ahp = AH5416(ah);
2428
2429 if (entry >= pCap->keycache_size) {
2430 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2431 "entry %u out of range\n", entry);
2432 return false;
2433 }
2434
2435 switch (k->kv_type) {
2436 case ATH9K_CIPHER_AES_OCB:
2437 keyType = AR_KEYTABLE_TYPE_AES;
2438 break;
2439 case ATH9K_CIPHER_AES_CCM:
2440 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2441 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2442 "AES-CCM not supported by mac rev 0x%x\n",
2443 ah->hw_version.macRev);
2444 return false;
2445 }
2446 keyType = AR_KEYTABLE_TYPE_CCM;
2447 break;
2448 case ATH9K_CIPHER_TKIP:
2449 keyType = AR_KEYTABLE_TYPE_TKIP;
2450 if (ATH9K_IS_MIC_ENABLED(ah)
2451 && entry + 64 >= pCap->keycache_size) {
2452 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2453 "entry %u inappropriate for TKIP\n", entry);
2454 return false;
2455 }
2456 break;
2457 case ATH9K_CIPHER_WEP:
2458 if (k->kv_len < LEN_WEP40) {
2459 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2460 "WEP key length %u too small\n", k->kv_len);
2461 return false;
2462 }
2463 if (k->kv_len <= LEN_WEP40)
2464 keyType = AR_KEYTABLE_TYPE_40;
2465 else if (k->kv_len <= LEN_WEP104)
2466 keyType = AR_KEYTABLE_TYPE_104;
2467 else
2468 keyType = AR_KEYTABLE_TYPE_128;
2469 break;
2470 case ATH9K_CIPHER_CLR:
2471 keyType = AR_KEYTABLE_TYPE_CLR;
2472 break;
2473 default:
2474 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2475 "cipher %u not supported\n", k->kv_type);
2476 return false;
2477 }
2478
2479 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2480 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2481 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2482 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2483 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2484 if (k->kv_len <= LEN_WEP104)
2485 key4 &= 0xff;
2486
2487 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2488 u16 micentry = entry + 64;
2489
2490 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2491 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2492 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2493 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2494 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2495 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2496 (void) ath9k_hw_keysetmac(ah, entry, mac);
2497
2498 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2499 u32 mic0, mic1, mic2, mic3, mic4;
2500
2501 mic0 = get_unaligned_le32(k->kv_mic + 0);
2502 mic2 = get_unaligned_le32(k->kv_mic + 4);
2503 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2504 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2505 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2506 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2507 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2508 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2509 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2510 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2511 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2512 AR_KEYTABLE_TYPE_CLR);
2513
2514 } else {
2515 u32 mic0, mic2;
2516
2517 mic0 = get_unaligned_le32(k->kv_mic + 0);
2518 mic2 = get_unaligned_le32(k->kv_mic + 4);
2519 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2520 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2521 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2522 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2523 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2524 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2525 AR_KEYTABLE_TYPE_CLR);
2526 }
2527 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2528 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2529 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2530 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2531 } else {
2532 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2533 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2534 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2535 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2536 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2537 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2538
2539 (void) ath9k_hw_keysetmac(ah, entry, mac);
2540 }
2541
2542 if (ah->ah_curchan == NULL)
2543 return true;
2544
2545 return true;
2546 }
2547
2548 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2549 {
2550 if (entry < ah->ah_caps.keycache_size) {
2551 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2552 if (val & AR_KEYTABLE_VALID)
2553 return true;
2554 }
2555 return false;
2556 }
2557
2558 /******************************/
2559 /* Power Management (Chipset) */
2560 /******************************/
2561
2562 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2563 {
2564 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2565 if (setChip) {
2566 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2567 AR_RTC_FORCE_WAKE_EN);
2568 if (!AR_SREV_9100(ah))
2569 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2570
2571 REG_CLR_BIT(ah, (AR_RTC_RESET),
2572 AR_RTC_RESET_EN);
2573 }
2574 }
2575
2576 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2577 {
2578 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2579 if (setChip) {
2580 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2581
2582 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2583 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2584 AR_RTC_FORCE_WAKE_ON_INT);
2585 } else {
2586 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2587 AR_RTC_FORCE_WAKE_EN);
2588 }
2589 }
2590 }
2591
2592 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2593 int setChip)
2594 {
2595 u32 val;
2596 int i;
2597
2598 if (setChip) {
2599 if ((REG_READ(ah, AR_RTC_STATUS) &
2600 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2601 if (ath9k_hw_set_reset_reg(ah,
2602 ATH9K_RESET_POWER_ON) != true) {
2603 return false;
2604 }
2605 }
2606 if (AR_SREV_9100(ah))
2607 REG_SET_BIT(ah, AR_RTC_RESET,
2608 AR_RTC_RESET_EN);
2609
2610 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2611 AR_RTC_FORCE_WAKE_EN);
2612 udelay(50);
2613
2614 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2615 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2616 if (val == AR_RTC_STATUS_ON)
2617 break;
2618 udelay(50);
2619 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2620 AR_RTC_FORCE_WAKE_EN);
2621 }
2622 if (i == 0) {
2623 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2624 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2625 return false;
2626 }
2627 }
2628
2629 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2630
2631 return true;
2632 }
2633
2634 bool ath9k_hw_setpower(struct ath_hal *ah,
2635 enum ath9k_power_mode mode)
2636 {
2637 struct ath_hal_5416 *ahp = AH5416(ah);
2638 static const char *modes[] = {
2639 "AWAKE",
2640 "FULL-SLEEP",
2641 "NETWORK SLEEP",
2642 "UNDEFINED"
2643 };
2644 int status = true, setChip = true;
2645
2646 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2647 modes[ah->ah_power_mode], modes[mode],
2648 setChip ? "set chip " : "");
2649
2650 switch (mode) {
2651 case ATH9K_PM_AWAKE:
2652 status = ath9k_hw_set_power_awake(ah, setChip);
2653 break;
2654 case ATH9K_PM_FULL_SLEEP:
2655 ath9k_set_power_sleep(ah, setChip);
2656 ahp->ah_chipFullSleep = true;
2657 break;
2658 case ATH9K_PM_NETWORK_SLEEP:
2659 ath9k_set_power_network_sleep(ah, setChip);
2660 break;
2661 default:
2662 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2663 "Unknown power mode %u\n", mode);
2664 return false;
2665 }
2666 ah->ah_power_mode = mode;
2667
2668 return status;
2669 }
2670
2671 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2672 {
2673 struct ath_hal_5416 *ahp = AH5416(ah);
2674 u8 i;
2675
2676 if (ah->ah_isPciExpress != true)
2677 return;
2678
2679 if (ah->ah_config.pcie_powersave_enable == 2)
2680 return;
2681
2682 if (restore)
2683 return;
2684
2685 if (AR_SREV_9280_20_OR_LATER(ah)) {
2686 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2687 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2688 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2689 }
2690 udelay(1000);
2691 } else if (AR_SREV_9280(ah) &&
2692 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2693 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2694 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2695
2696 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2697 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2698 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2699
2700 if (ah->ah_config.pcie_clock_req)
2701 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2702 else
2703 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2704
2705 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2706 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2707 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2708
2709 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2710
2711 udelay(1000);
2712 } else {
2713 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2714 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2715 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2716 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2717 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2718 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2719 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2720 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2721 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2722 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2723 }
2724
2725 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2726
2727 if (ah->ah_config.pcie_waen) {
2728 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2729 } else {
2730 if (AR_SREV_9285(ah))
2731 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2732 else if (AR_SREV_9280(ah))
2733 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2734 else
2735 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2736 }
2737
2738 }
2739
2740 /**********************/
2741 /* Interrupt Handling */
2742 /**********************/
2743
2744 bool ath9k_hw_intrpend(struct ath_hal *ah)
2745 {
2746 u32 host_isr;
2747
2748 if (AR_SREV_9100(ah))
2749 return true;
2750
2751 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2752 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2753 return true;
2754
2755 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2756 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2757 && (host_isr != AR_INTR_SPURIOUS))
2758 return true;
2759
2760 return false;
2761 }
2762
2763 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2764 {
2765 u32 isr = 0;
2766 u32 mask2 = 0;
2767 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2768 u32 sync_cause = 0;
2769 bool fatal_int = false;
2770 struct ath_hal_5416 *ahp = AH5416(ah);
2771
2772 if (!AR_SREV_9100(ah)) {
2773 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2774 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2775 == AR_RTC_STATUS_ON) {
2776 isr = REG_READ(ah, AR_ISR);
2777 }
2778 }
2779
2780 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2781 AR_INTR_SYNC_DEFAULT;
2782
2783 *masked = 0;
2784
2785 if (!isr && !sync_cause)
2786 return false;
2787 } else {
2788 *masked = 0;
2789 isr = REG_READ(ah, AR_ISR);
2790 }
2791
2792 if (isr) {
2793 if (isr & AR_ISR_BCNMISC) {
2794 u32 isr2;
2795 isr2 = REG_READ(ah, AR_ISR_S2);
2796 if (isr2 & AR_ISR_S2_TIM)
2797 mask2 |= ATH9K_INT_TIM;
2798 if (isr2 & AR_ISR_S2_DTIM)
2799 mask2 |= ATH9K_INT_DTIM;
2800 if (isr2 & AR_ISR_S2_DTIMSYNC)
2801 mask2 |= ATH9K_INT_DTIMSYNC;
2802 if (isr2 & (AR_ISR_S2_CABEND))
2803 mask2 |= ATH9K_INT_CABEND;
2804 if (isr2 & AR_ISR_S2_GTT)
2805 mask2 |= ATH9K_INT_GTT;
2806 if (isr2 & AR_ISR_S2_CST)
2807 mask2 |= ATH9K_INT_CST;
2808 }
2809
2810 isr = REG_READ(ah, AR_ISR_RAC);
2811 if (isr == 0xffffffff) {
2812 *masked = 0;
2813 return false;
2814 }
2815
2816 *masked = isr & ATH9K_INT_COMMON;
2817
2818 if (ahp->ah_intrMitigation) {
2819 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2820 *masked |= ATH9K_INT_RX;
2821 }
2822
2823 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2824 *masked |= ATH9K_INT_RX;
2825 if (isr &
2826 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2827 AR_ISR_TXEOL)) {
2828 u32 s0_s, s1_s;
2829
2830 *masked |= ATH9K_INT_TX;
2831
2832 s0_s = REG_READ(ah, AR_ISR_S0_S);
2833 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2834 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2835
2836 s1_s = REG_READ(ah, AR_ISR_S1_S);
2837 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2838 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2839 }
2840
2841 if (isr & AR_ISR_RXORN) {
2842 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2843 "receive FIFO overrun interrupt\n");
2844 }
2845
2846 if (!AR_SREV_9100(ah)) {
2847 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2848 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2849 if (isr5 & AR_ISR_S5_TIM_TIMER)
2850 *masked |= ATH9K_INT_TIM_TIMER;
2851 }
2852 }
2853
2854 *masked |= mask2;
2855 }
2856
2857 if (AR_SREV_9100(ah))
2858 return true;
2859
2860 if (sync_cause) {
2861 fatal_int =
2862 (sync_cause &
2863 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2864 ? true : false;
2865
2866 if (fatal_int) {
2867 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2868 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2869 "received PCI FATAL interrupt\n");
2870 }
2871 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2872 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2873 "received PCI PERR interrupt\n");
2874 }
2875 }
2876 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2877 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2878 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2879 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2880 REG_WRITE(ah, AR_RC, 0);
2881 *masked |= ATH9K_INT_FATAL;
2882 }
2883 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2884 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2885 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2886 }
2887
2888 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2889 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2890 }
2891
2892 return true;
2893 }
2894
2895 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2896 {
2897 return AH5416(ah)->ah_maskReg;
2898 }
2899
2900 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2901 {
2902 struct ath_hal_5416 *ahp = AH5416(ah);
2903 u32 omask = ahp->ah_maskReg;
2904 u32 mask, mask2;
2905 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2906
2907 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2908
2909 if (omask & ATH9K_INT_GLOBAL) {
2910 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2911 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2912 (void) REG_READ(ah, AR_IER);
2913 if (!AR_SREV_9100(ah)) {
2914 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2915 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2916
2917 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2918 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2919 }
2920 }
2921
2922 mask = ints & ATH9K_INT_COMMON;
2923 mask2 = 0;
2924
2925 if (ints & ATH9K_INT_TX) {
2926 if (ahp->ah_txOkInterruptMask)
2927 mask |= AR_IMR_TXOK;
2928 if (ahp->ah_txDescInterruptMask)
2929 mask |= AR_IMR_TXDESC;
2930 if (ahp->ah_txErrInterruptMask)
2931 mask |= AR_IMR_TXERR;
2932 if (ahp->ah_txEolInterruptMask)
2933 mask |= AR_IMR_TXEOL;
2934 }
2935 if (ints & ATH9K_INT_RX) {
2936 mask |= AR_IMR_RXERR;
2937 if (ahp->ah_intrMitigation)
2938 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2939 else
2940 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2941 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2942 mask |= AR_IMR_GENTMR;
2943 }
2944
2945 if (ints & (ATH9K_INT_BMISC)) {
2946 mask |= AR_IMR_BCNMISC;
2947 if (ints & ATH9K_INT_TIM)
2948 mask2 |= AR_IMR_S2_TIM;
2949 if (ints & ATH9K_INT_DTIM)
2950 mask2 |= AR_IMR_S2_DTIM;
2951 if (ints & ATH9K_INT_DTIMSYNC)
2952 mask2 |= AR_IMR_S2_DTIMSYNC;
2953 if (ints & ATH9K_INT_CABEND)
2954 mask2 |= (AR_IMR_S2_CABEND);
2955 }
2956
2957 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2958 mask |= AR_IMR_BCNMISC;
2959 if (ints & ATH9K_INT_GTT)
2960 mask2 |= AR_IMR_S2_GTT;
2961 if (ints & ATH9K_INT_CST)
2962 mask2 |= AR_IMR_S2_CST;
2963 }
2964
2965 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2966 REG_WRITE(ah, AR_IMR, mask);
2967 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2968 AR_IMR_S2_DTIM |
2969 AR_IMR_S2_DTIMSYNC |
2970 AR_IMR_S2_CABEND |
2971 AR_IMR_S2_CABTO |
2972 AR_IMR_S2_TSFOOR |
2973 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2974 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2975 ahp->ah_maskReg = ints;
2976
2977 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2978 if (ints & ATH9K_INT_TIM_TIMER)
2979 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2980 else
2981 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2982 }
2983
2984 if (ints & ATH9K_INT_GLOBAL) {
2985 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
2986 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2987 if (!AR_SREV_9100(ah)) {
2988 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2989 AR_INTR_MAC_IRQ);
2990 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2991
2992
2993 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2994 AR_INTR_SYNC_DEFAULT);
2995 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2996 AR_INTR_SYNC_DEFAULT);
2997 }
2998 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2999 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3000 }
3001
3002 return omask;
3003 }
3004
3005 /*******************/
3006 /* Beacon Handling */
3007 /*******************/
3008
3009 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3010 {
3011 struct ath_hal_5416 *ahp = AH5416(ah);
3012 int flags = 0;
3013
3014 ahp->ah_beaconInterval = beacon_period;
3015
3016 switch (ah->ah_opmode) {
3017 case NL80211_IFTYPE_STATION:
3018 case NL80211_IFTYPE_MONITOR:
3019 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3020 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3021 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3022 flags |= AR_TBTT_TIMER_EN;
3023 break;
3024 case NL80211_IFTYPE_ADHOC:
3025 REG_SET_BIT(ah, AR_TXCFG,
3026 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3027 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3028 TU_TO_USEC(next_beacon +
3029 (ahp->ah_atimWindow ? ahp->
3030 ah_atimWindow : 1)));
3031 flags |= AR_NDP_TIMER_EN;
3032 case NL80211_IFTYPE_AP:
3033 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3034 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3035 TU_TO_USEC(next_beacon -
3036 ah->ah_config.
3037 dma_beacon_response_time));
3038 REG_WRITE(ah, AR_NEXT_SWBA,
3039 TU_TO_USEC(next_beacon -
3040 ah->ah_config.
3041 sw_beacon_response_time));
3042 flags |=
3043 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3044 break;
3045 default:
3046 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3047 "%s: unsupported opmode: %d\n",
3048 __func__, ah->ah_opmode);
3049 return;
3050 break;
3051 }
3052
3053 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3054 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3055 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3056 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3057
3058 beacon_period &= ~ATH9K_BEACON_ENA;
3059 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3060 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3061 ath9k_hw_reset_tsf(ah);
3062 }
3063
3064 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3065 }
3066
3067 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3068 const struct ath9k_beacon_state *bs)
3069 {
3070 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3071 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3072
3073 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3074
3075 REG_WRITE(ah, AR_BEACON_PERIOD,
3076 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3077 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3078 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3079
3080 REG_RMW_FIELD(ah, AR_RSSI_THR,
3081 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3082
3083 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3084
3085 if (bs->bs_sleepduration > beaconintval)
3086 beaconintval = bs->bs_sleepduration;
3087
3088 dtimperiod = bs->bs_dtimperiod;
3089 if (bs->bs_sleepduration > dtimperiod)
3090 dtimperiod = bs->bs_sleepduration;
3091
3092 if (beaconintval == dtimperiod)
3093 nextTbtt = bs->bs_nextdtim;
3094 else
3095 nextTbtt = bs->bs_nexttbtt;
3096
3097 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3098 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3099 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3100 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3101
3102 REG_WRITE(ah, AR_NEXT_DTIM,
3103 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3104 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3105
3106 REG_WRITE(ah, AR_SLEEP1,
3107 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3108 | AR_SLEEP1_ASSUME_DTIM);
3109
3110 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3111 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3112 else
3113 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3114
3115 REG_WRITE(ah, AR_SLEEP2,
3116 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3117
3118 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3119 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3120
3121 REG_SET_BIT(ah, AR_TIMER_MODE,
3122 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3123 AR_DTIM_TIMER_EN);
3124
3125 }
3126
3127 /*******************/
3128 /* HW Capabilities */
3129 /*******************/
3130
3131 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3132 {
3133 struct ath_hal_5416 *ahp = AH5416(ah);
3134 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3135 u16 capField = 0, eeval;
3136
3137 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3138
3139 ah->ah_currentRD = eeval;
3140
3141 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3142 ah->ah_currentRDExt = eeval;
3143
3144 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3145
3146 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3147 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3148 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3149 ah->ah_currentRD += 5;
3150 else if (ah->ah_currentRD == 0x41)
3151 ah->ah_currentRD = 0x43;
3152 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3153 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3154 }
3155
3156 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3157 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3158
3159 if (eeval & AR5416_OPFLAGS_11A) {
3160 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3161 if (ah->ah_config.ht_enable) {
3162 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3163 set_bit(ATH9K_MODE_11NA_HT20,
3164 pCap->wireless_modes);
3165 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3166 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3167 pCap->wireless_modes);
3168 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3169 pCap->wireless_modes);
3170 }
3171 }
3172 }
3173
3174 if (eeval & AR5416_OPFLAGS_11G) {
3175 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3176 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3177 if (ah->ah_config.ht_enable) {
3178 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3179 set_bit(ATH9K_MODE_11NG_HT20,
3180 pCap->wireless_modes);
3181 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3182 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3183 pCap->wireless_modes);
3184 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3185 pCap->wireless_modes);
3186 }
3187 }
3188 }
3189
3190 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3191 if ((ah->ah_isPciExpress)
3192 || (eeval & AR5416_OPFLAGS_11A)) {
3193 pCap->rx_chainmask =
3194 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3195 } else {
3196 pCap->rx_chainmask =
3197 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3198 }
3199
3200 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3201 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3202
3203 pCap->low_2ghz_chan = 2312;
3204 pCap->high_2ghz_chan = 2732;
3205
3206 pCap->low_5ghz_chan = 4920;
3207 pCap->high_5ghz_chan = 6100;
3208
3209 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3210 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3211 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3212
3213 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3214 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3215 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3216
3217 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3218
3219 if (ah->ah_config.ht_enable)
3220 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3221 else
3222 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3223
3224 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3225 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3226 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3227 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3228
3229 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3230 pCap->total_queues =
3231 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3232 else
3233 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3234
3235 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3236 pCap->keycache_size =
3237 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3238 else
3239 pCap->keycache_size = AR_KEYTABLE_SIZE;
3240
3241 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3242 pCap->num_mr_retries = 4;
3243 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3244
3245 if (AR_SREV_9285_10_OR_LATER(ah))
3246 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3247 else if (AR_SREV_9280_10_OR_LATER(ah))
3248 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3249 else
3250 pCap->num_gpio_pins = AR_NUM_GPIO;
3251
3252 if (AR_SREV_9280_10_OR_LATER(ah)) {
3253 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3254 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3255 } else {
3256 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3257 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3258 }
3259
3260 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3261 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3262 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3263 } else {
3264 pCap->rts_aggr_limit = (8 * 1024);
3265 }
3266
3267 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3268
3269 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3270 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3271 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3272 ah->ah_rfkill_gpio =
3273 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3274 ah->ah_rfkill_polarity =
3275 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3276
3277 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3278 }
3279 #endif
3280
3281 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3282 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3283 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3284 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3285 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3286 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3287 else
3288 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3289
3290 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3291 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3292 else
3293 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3294
3295 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3296 pCap->reg_cap =
3297 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3298 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3299 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3300 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3301 } else {
3302 pCap->reg_cap =
3303 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3304 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3305 }
3306
3307 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3308
3309 pCap->num_antcfg_5ghz =
3310 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3311 pCap->num_antcfg_2ghz =
3312 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3313
3314 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3315 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3316 ah->ah_btactive_gpio = 6;
3317 ah->ah_wlanactive_gpio = 5;
3318 }
3319
3320 return true;
3321 }
3322
3323 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3324 u32 capability, u32 *result)
3325 {
3326 struct ath_hal_5416 *ahp = AH5416(ah);
3327 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3328
3329 switch (type) {
3330 case ATH9K_CAP_CIPHER:
3331 switch (capability) {
3332 case ATH9K_CIPHER_AES_CCM:
3333 case ATH9K_CIPHER_AES_OCB:
3334 case ATH9K_CIPHER_TKIP:
3335 case ATH9K_CIPHER_WEP:
3336 case ATH9K_CIPHER_MIC:
3337 case ATH9K_CIPHER_CLR:
3338 return true;
3339 default:
3340 return false;
3341 }
3342 case ATH9K_CAP_TKIP_MIC:
3343 switch (capability) {
3344 case 0:
3345 return true;
3346 case 1:
3347 return (ahp->ah_staId1Defaults &
3348 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3349 false;
3350 }
3351 case ATH9K_CAP_TKIP_SPLIT:
3352 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3353 false : true;
3354 case ATH9K_CAP_WME_TKIPMIC:
3355 return 0;
3356 case ATH9K_CAP_PHYCOUNTERS:
3357 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3358 case ATH9K_CAP_DIVERSITY:
3359 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3360 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3361 true : false;
3362 case ATH9K_CAP_PHYDIAG:
3363 return true;
3364 case ATH9K_CAP_MCAST_KEYSRCH:
3365 switch (capability) {
3366 case 0:
3367 return true;
3368 case 1:
3369 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3370 return false;
3371 } else {
3372 return (ahp->ah_staId1Defaults &
3373 AR_STA_ID1_MCAST_KSRCH) ? true :
3374 false;
3375 }
3376 }
3377 return false;
3378 case ATH9K_CAP_TSF_ADJUST:
3379 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3380 true : false;
3381 case ATH9K_CAP_RFSILENT:
3382 if (capability == 3)
3383 return false;
3384 case ATH9K_CAP_ANT_CFG_2GHZ:
3385 *result = pCap->num_antcfg_2ghz;
3386 return true;
3387 case ATH9K_CAP_ANT_CFG_5GHZ:
3388 *result = pCap->num_antcfg_5ghz;
3389 return true;
3390 case ATH9K_CAP_TXPOW:
3391 switch (capability) {
3392 case 0:
3393 return 0;
3394 case 1:
3395 *result = ah->ah_powerLimit;
3396 return 0;
3397 case 2:
3398 *result = ah->ah_maxPowerLevel;
3399 return 0;
3400 case 3:
3401 *result = ah->ah_tpScale;
3402 return 0;
3403 }
3404 return false;
3405 default:
3406 return false;
3407 }
3408 }
3409
3410 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3411 u32 capability, u32 setting, int *status)
3412 {
3413 struct ath_hal_5416 *ahp = AH5416(ah);
3414 u32 v;
3415
3416 switch (type) {
3417 case ATH9K_CAP_TKIP_MIC:
3418 if (setting)
3419 ahp->ah_staId1Defaults |=
3420 AR_STA_ID1_CRPT_MIC_ENABLE;
3421 else
3422 ahp->ah_staId1Defaults &=
3423 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3424 return true;
3425 case ATH9K_CAP_DIVERSITY:
3426 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3427 if (setting)
3428 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3429 else
3430 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3431 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3432 return true;
3433 case ATH9K_CAP_MCAST_KEYSRCH:
3434 if (setting)
3435 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3436 else
3437 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3438 return true;
3439 case ATH9K_CAP_TSF_ADJUST:
3440 if (setting)
3441 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3442 else
3443 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3444 return true;
3445 default:
3446 return false;
3447 }
3448 }
3449
3450 /****************************/
3451 /* GPIO / RFKILL / Antennae */
3452 /****************************/
3453
3454 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3455 u32 gpio, u32 type)
3456 {
3457 int addr;
3458 u32 gpio_shift, tmp;
3459
3460 if (gpio > 11)
3461 addr = AR_GPIO_OUTPUT_MUX3;
3462 else if (gpio > 5)
3463 addr = AR_GPIO_OUTPUT_MUX2;
3464 else
3465 addr = AR_GPIO_OUTPUT_MUX1;
3466
3467 gpio_shift = (gpio % 6) * 5;
3468
3469 if (AR_SREV_9280_20_OR_LATER(ah)
3470 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3471 REG_RMW(ah, addr, (type << gpio_shift),
3472 (0x1f << gpio_shift));
3473 } else {
3474 tmp = REG_READ(ah, addr);
3475 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3476 tmp &= ~(0x1f << gpio_shift);
3477 tmp |= (type << gpio_shift);
3478 REG_WRITE(ah, addr, tmp);
3479 }
3480 }
3481
3482 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3483 {
3484 u32 gpio_shift;
3485
3486 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3487
3488 gpio_shift = gpio << 1;
3489
3490 REG_RMW(ah,
3491 AR_GPIO_OE_OUT,
3492 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3493 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3494 }
3495
3496 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3497 {
3498 #define MS_REG_READ(x, y) \
3499 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3500
3501 if (gpio >= ah->ah_caps.num_gpio_pins)
3502 return 0xffffffff;
3503
3504 if (AR_SREV_9285_10_OR_LATER(ah))
3505 return MS_REG_READ(AR9285, gpio) != 0;
3506 else if (AR_SREV_9280_10_OR_LATER(ah))
3507 return MS_REG_READ(AR928X, gpio) != 0;
3508 else
3509 return MS_REG_READ(AR, gpio) != 0;
3510 }
3511
3512 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3513 u32 ah_signal_type)
3514 {
3515 u32 gpio_shift;
3516
3517 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3518
3519 gpio_shift = 2 * gpio;
3520
3521 REG_RMW(ah,
3522 AR_GPIO_OE_OUT,
3523 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3524 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3525 }
3526
3527 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3528 {
3529 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3530 AR_GPIO_BIT(gpio));
3531 }
3532
3533 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3534 void ath9k_enable_rfkill(struct ath_hal *ah)
3535 {
3536 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3537 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3538
3539 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3540 AR_GPIO_INPUT_MUX2_RFSILENT);
3541
3542 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3543 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3544 }
3545 #endif
3546
3547 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3548 {
3549 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3550 }
3551
3552 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3553 {
3554 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3555 }
3556
3557 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3558 enum ath9k_ant_setting settings,
3559 struct ath9k_channel *chan,
3560 u8 *tx_chainmask,
3561 u8 *rx_chainmask,
3562 u8 *antenna_cfgd)
3563 {
3564 struct ath_hal_5416 *ahp = AH5416(ah);
3565 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3566
3567 if (AR_SREV_9280(ah)) {
3568 if (!tx_chainmask_cfg) {
3569
3570 tx_chainmask_cfg = *tx_chainmask;
3571 rx_chainmask_cfg = *rx_chainmask;
3572 }
3573
3574 switch (settings) {
3575 case ATH9K_ANT_FIXED_A:
3576 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3577 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3578 *antenna_cfgd = true;
3579 break;
3580 case ATH9K_ANT_FIXED_B:
3581 if (ah->ah_caps.tx_chainmask >
3582 ATH9K_ANTENNA1_CHAINMASK) {
3583 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3584 }
3585 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3586 *antenna_cfgd = true;
3587 break;
3588 case ATH9K_ANT_VARIABLE:
3589 *tx_chainmask = tx_chainmask_cfg;
3590 *rx_chainmask = rx_chainmask_cfg;
3591 *antenna_cfgd = true;
3592 break;
3593 default:
3594 break;
3595 }
3596 } else {
3597 ahp->ah_diversityControl = settings;
3598 }
3599
3600 return true;
3601 }
3602
3603 /*********************/
3604 /* General Operation */
3605 /*********************/
3606
3607 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3608 {
3609 u32 bits = REG_READ(ah, AR_RX_FILTER);
3610 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3611
3612 if (phybits & AR_PHY_ERR_RADAR)
3613 bits |= ATH9K_RX_FILTER_PHYRADAR;
3614 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3615 bits |= ATH9K_RX_FILTER_PHYERR;
3616
3617 return bits;
3618 }
3619
3620 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3621 {
3622 u32 phybits;
3623
3624 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3625 phybits = 0;
3626 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3627 phybits |= AR_PHY_ERR_RADAR;
3628 if (bits & ATH9K_RX_FILTER_PHYERR)
3629 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3630 REG_WRITE(ah, AR_PHY_ERR, phybits);
3631
3632 if (phybits)
3633 REG_WRITE(ah, AR_RXCFG,
3634 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3635 else
3636 REG_WRITE(ah, AR_RXCFG,
3637 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3638 }
3639
3640 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3641 {
3642 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3643 }
3644
3645 bool ath9k_hw_disable(struct ath_hal *ah)
3646 {
3647 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3648 return false;
3649
3650 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3651 }
3652
3653 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3654 {
3655 struct ath9k_channel *chan = ah->ah_curchan;
3656 struct ieee80211_channel *channel = chan->chan;
3657
3658 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3659
3660 if (ath9k_hw_set_txpower(ah, chan,
3661 ath9k_regd_get_ctl(ah, chan),
3662 channel->max_antenna_gain * 2,
3663 channel->max_power * 2,
3664 min((u32) MAX_RATE_POWER,
3665 (u32) ah->ah_powerLimit)) != 0)
3666 return false;
3667
3668 return true;
3669 }
3670
3671 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3672 {
3673 struct ath_hal_5416 *ahp = AH5416(ah);
3674
3675 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3676 }
3677
3678 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3679 {
3680 struct ath_hal_5416 *ahp = AH5416(ah);
3681
3682 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3683
3684 return true;
3685 }
3686
3687 void ath9k_hw_setopmode(struct ath_hal *ah)
3688 {
3689 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3690 }
3691
3692 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3693 {
3694 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3695 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3696 }
3697
3698 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3699 {
3700 struct ath_hal_5416 *ahp = AH5416(ah);
3701
3702 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3703 }
3704
3705 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3706 {
3707 struct ath_hal_5416 *ahp = AH5416(ah);
3708
3709 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3710
3711 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3712 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3713
3714 return true;
3715 }
3716
3717 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3718 {
3719 struct ath_hal_5416 *ahp = AH5416(ah);
3720
3721 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3722 ahp->ah_assocId = assocId;
3723
3724 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3725 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3726 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3727 }
3728
3729 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3730 {
3731 u64 tsf;
3732
3733 tsf = REG_READ(ah, AR_TSF_U32);
3734 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3735
3736 return tsf;
3737 }
3738
3739 void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64)
3740 {
3741 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3742 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3743 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3744 }
3745
3746 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3747 {
3748 int count;
3749
3750 count = 0;
3751 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3752 count++;
3753 if (count > 10) {
3754 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3755 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3756 break;
3757 }
3758 udelay(10);
3759 }
3760 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3761 }
3762
3763 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3764 {
3765 struct ath_hal_5416 *ahp = AH5416(ah);
3766
3767 if (setting)
3768 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3769 else
3770 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3771
3772 return true;
3773 }
3774
3775 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3776 {
3777 struct ath_hal_5416 *ahp = AH5416(ah);
3778
3779 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3780 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3781 ahp->ah_slottime = (u32) -1;
3782 return false;
3783 } else {
3784 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3785 ahp->ah_slottime = us;
3786 return true;
3787 }
3788 }
3789
3790 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3791 {
3792 u32 macmode;
3793
3794 if (mode == ATH9K_HT_MACMODE_2040 &&
3795 !ah->ah_config.cwm_ignore_extcca)
3796 macmode = AR_2040_JOINED_RX_CLEAR;
3797 else
3798 macmode = 0;
3799
3800 REG_WRITE(ah, AR_2040_MODE, macmode);
3801 }
3802
3803 /***************************/
3804 /* Bluetooth Coexistence */
3805 /***************************/
3806
3807 void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3808 {
3809 /* connect bt_active to baseband */
3810 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3811 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3812 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3813
3814 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3815 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3816
3817 /* Set input mux for bt_active to gpio pin */
3818 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3819 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3820 ah->ah_btactive_gpio);
3821
3822 /* Configure the desired gpio port for input */
3823 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3824
3825 /* Configure the desired GPIO port for TX_FRAME output */
3826 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3827 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3828 }
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