2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/smp_lock.h>
44 #include <linux/bootmem.h>
45 #include <linux/notifier.h>
46 #include <linux/cpu.h>
47 #include <linux/percpu.h>
48 #include <linux/nmi.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
57 #include <asm/genapic.h>
59 #include <mach_apic.h>
60 #include <mach_wakecpu.h>
61 #include <smpboot_hooks.h>
64 /* Set if we find a B stepping CPU */
65 static int __devinitdata smp_b_stepping
;
67 /* Number of siblings per CPU package */
68 int smp_num_siblings
= 1;
69 EXPORT_SYMBOL(smp_num_siblings
);
71 /* Last level cache ID of each logical CPU */
72 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
74 /* representing HT siblings of each logical CPU */
75 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
76 EXPORT_SYMBOL(cpu_sibling_map
);
78 /* representing HT and core siblings of each logical CPU */
79 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
80 EXPORT_SYMBOL(cpu_core_map
);
82 /* bitmap of online cpus */
83 cpumask_t cpu_online_map __read_mostly
;
84 EXPORT_SYMBOL(cpu_online_map
);
86 cpumask_t cpu_callin_map
;
87 cpumask_t cpu_callout_map
;
88 EXPORT_SYMBOL(cpu_callout_map
);
89 cpumask_t cpu_possible_map
;
90 EXPORT_SYMBOL(cpu_possible_map
);
91 static cpumask_t smp_commenced_mask
;
93 /* Per CPU bogomips and other parameters */
94 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
95 EXPORT_SYMBOL(cpu_data
);
97 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
98 { [0 ... NR_CPUS
-1] = 0xff };
99 EXPORT_SYMBOL(x86_cpu_to_apicid
);
101 u8 apicid_2_node
[MAX_APICID
];
104 * Trampoline 80x86 program as an array.
107 extern unsigned char trampoline_data
[];
108 extern unsigned char trampoline_end
[];
109 static unsigned char *trampoline_base
;
110 static int trampoline_exec
;
112 static void map_cpu_to_logical_apicid(void);
114 /* State of each CPU. */
115 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
118 * Currently trivial. Write the real->protected mode
119 * bootstrap into the page concerned. The caller
120 * has made sure it's suitably aligned.
123 static unsigned long __devinit
setup_trampoline(void)
125 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
126 return virt_to_phys(trampoline_base
);
130 * We are called very early to get the low memory for the
131 * SMP bootup trampoline page.
133 void __init
smp_alloc_memory(void)
135 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
137 * Has to be in very low memory so we can execute
140 if (__pa(trampoline_base
) >= 0x9F000)
143 * Make the SMP trampoline executable:
145 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
149 * The bootstrap kernel entry code has set these up. Save them for
153 static void __cpuinit
smp_store_cpu_info(int id
)
155 struct cpuinfo_x86
*c
= cpu_data
+ id
;
161 * Mask B, Pentium, but not Pentium MMX
163 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
165 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
168 * Remember we have B step Pentia with bugs
173 * Certain Athlons might work (for various values of 'work') in SMP
174 * but they are not certified as MP capable.
176 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
178 if (num_possible_cpus() == 1)
181 /* Athlon 660/661 is valid. */
182 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
185 /* Duron 670 is valid */
186 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
190 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
191 * It's worth noting that the A5 stepping (662) of some Athlon XP's
192 * have the MP bit set.
193 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
195 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
196 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
201 /* If we get here, it's not a certified SMP capable AMD system. */
202 add_taint(TAINT_UNSAFE_SMP
);
209 extern void calibrate_delay(void);
211 static atomic_t init_deasserted
;
213 static void __cpuinit
smp_callin(void)
216 unsigned long timeout
;
219 * If waken up by an INIT in an 82489DX configuration
220 * we may get here before an INIT-deassert IPI reaches
221 * our local APIC. We have to wait for the IPI or we'll
222 * lock up on an APIC access.
224 wait_for_init_deassert(&init_deasserted
);
227 * (This works even if the APIC is not enabled.)
229 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
230 cpuid
= smp_processor_id();
231 if (cpu_isset(cpuid
, cpu_callin_map
)) {
232 printk("huh, phys CPU#%d, CPU#%d already present??\n",
236 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
239 * STARTUP IPIs are fragile beasts as they might sometimes
240 * trigger some glue motherboard logic. Complete APIC bus
241 * silence for 1 second, this overestimates the time the
242 * boot CPU is spending to send the up to 2 STARTUP IPIs
243 * by a factor of two. This should be enough.
247 * Waiting 2s total for startup (udelay is not yet working)
249 timeout
= jiffies
+ 2*HZ
;
250 while (time_before(jiffies
, timeout
)) {
252 * Has the boot CPU finished it's STARTUP sequence?
254 if (cpu_isset(cpuid
, cpu_callout_map
))
259 if (!time_before(jiffies
, timeout
)) {
260 printk("BUG: CPU%d started up but did not get a callout!\n",
266 * the boot CPU has finished the init stage and is spinning
267 * on callin_map until we finish. We are free to set up this
268 * CPU, first the APIC. (this is probably redundant on most
272 Dprintk("CALLIN, before setup_local_APIC().\n");
273 smp_callin_clear_local_apic();
275 map_cpu_to_logical_apicid();
281 Dprintk("Stack at about %p\n",&cpuid
);
284 * Save our processor parameters
286 smp_store_cpu_info(cpuid
);
289 * Allow the master to continue.
291 cpu_set(cpuid
, cpu_callin_map
);
296 /* maps the cpu to the sched domain representing multi-core */
297 cpumask_t
cpu_coregroup_map(int cpu
)
299 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
301 * For perf, we return last level cache shared map.
302 * And for power savings, we return cpu_core_map
304 if (sched_mc_power_savings
|| sched_smt_power_savings
)
305 return cpu_core_map
[cpu
];
307 return c
->llc_shared_map
;
310 /* representing cpus for which sibling maps can be computed */
311 static cpumask_t cpu_sibling_setup_map
;
314 set_cpu_sibling_map(int cpu
)
317 struct cpuinfo_x86
*c
= cpu_data
;
319 cpu_set(cpu
, cpu_sibling_setup_map
);
321 if (smp_num_siblings
> 1) {
322 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
323 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
&&
324 c
[cpu
].cpu_core_id
== c
[i
].cpu_core_id
) {
325 cpu_set(i
, cpu_sibling_map
[cpu
]);
326 cpu_set(cpu
, cpu_sibling_map
[i
]);
327 cpu_set(i
, cpu_core_map
[cpu
]);
328 cpu_set(cpu
, cpu_core_map
[i
]);
329 cpu_set(i
, c
[cpu
].llc_shared_map
);
330 cpu_set(cpu
, c
[i
].llc_shared_map
);
334 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
337 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
339 if (current_cpu_data
.x86_max_cores
== 1) {
340 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
341 c
[cpu
].booted_cores
= 1;
345 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
346 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
347 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
348 cpu_set(i
, c
[cpu
].llc_shared_map
);
349 cpu_set(cpu
, c
[i
].llc_shared_map
);
351 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
) {
352 cpu_set(i
, cpu_core_map
[cpu
]);
353 cpu_set(cpu
, cpu_core_map
[i
]);
355 * Does this new cpu bringup a new core?
357 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
359 * for each core in package, increment
360 * the booted_cores for this new cpu
362 if (first_cpu(cpu_sibling_map
[i
]) == i
)
363 c
[cpu
].booted_cores
++;
365 * increment the core count for all
366 * the other cpus in this package
370 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
371 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
377 * Activate a secondary processor.
379 static void __cpuinit
start_secondary(void *unused
)
382 * Don't put *anything* before secondary_cpu_init(), SMP
383 * booting is too fragile that we want to limit the
384 * things done here to the most necessary things.
389 secondary_cpu_init();
392 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
395 * Check TSC synchronization with the BP:
397 check_tsc_sync_target();
399 setup_secondary_clock();
400 if (nmi_watchdog
== NMI_IO_APIC
) {
401 disable_8259A_irq(0);
402 enable_NMI_through_LVT0(NULL
);
406 * low-memory mappings have been cleared, flush them from
407 * the local TLBs too.
411 /* This must be done before setting cpu_online_map */
412 set_cpu_sibling_map(raw_smp_processor_id());
416 * We need to hold call_lock, so there is no inconsistency
417 * between the time smp_call_function() determines number of
418 * IPI receipients, and the time when the determination is made
419 * for which cpus receive the IPI. Holding this
420 * lock helps us to not include this cpu in a currently in progress
421 * smp_call_function().
423 lock_ipi_call_lock();
424 cpu_set(smp_processor_id(), cpu_online_map
);
425 unlock_ipi_call_lock();
426 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
428 /* We can take interrupts now: we're officially "up". */
436 * Everything has been set up for the secondary
437 * CPUs - they just need to reload everything
438 * from the task structure
439 * This function must not return.
441 void __devinit
initialize_secondary(void)
444 * switch to the per CPU GDT we already set up
447 cpu_set_gdt(current_thread_info()->cpu
);
450 * We don't actually need to load the full TSS,
451 * basically just the stack pointer and the eip.
458 :"m" (current
->thread
.esp
),"m" (current
->thread
.eip
));
461 /* Static state in head.S used to set up a CPU */
466 extern struct i386_pda
*start_pda
;
470 /* which logical CPUs are on which nodes */
471 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
472 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
473 EXPORT_SYMBOL(node_2_cpu_mask
);
474 /* which node each logical CPU is on */
475 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
476 EXPORT_SYMBOL(cpu_2_node
);
478 /* set up a mapping between cpu and node. */
479 static inline void map_cpu_to_node(int cpu
, int node
)
481 printk("Mapping cpu %d to node %d\n", cpu
, node
);
482 cpu_set(cpu
, node_2_cpu_mask
[node
]);
483 cpu_2_node
[cpu
] = node
;
486 /* undo a mapping between cpu and node. */
487 static inline void unmap_cpu_to_node(int cpu
)
491 printk("Unmapping cpu %d from all nodes\n", cpu
);
492 for (node
= 0; node
< MAX_NUMNODES
; node
++)
493 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
496 #else /* !CONFIG_NUMA */
498 #define map_cpu_to_node(cpu, node) ({})
499 #define unmap_cpu_to_node(cpu) ({})
501 #endif /* CONFIG_NUMA */
503 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
505 static void map_cpu_to_logical_apicid(void)
507 int cpu
= smp_processor_id();
508 int apicid
= logical_smp_processor_id();
509 int node
= apicid_to_node(apicid
);
511 if (!node_online(node
))
512 node
= first_online_node
;
514 cpu_2_logical_apicid
[cpu
] = apicid
;
515 map_cpu_to_node(cpu
, node
);
518 static void unmap_cpu_to_logical_apicid(int cpu
)
520 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
521 unmap_cpu_to_node(cpu
);
525 static inline void __inquire_remote_apic(int apicid
)
527 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
528 char *names
[] = { "ID", "VERSION", "SPIV" };
531 printk("Inquiring remote APIC #%d...\n", apicid
);
533 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
534 printk("... APIC #%d %s: ", apicid
, names
[i
]);
539 apic_wait_icr_idle();
541 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
542 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
547 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
548 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
551 case APIC_ICR_RR_VALID
:
552 status
= apic_read(APIC_RRR
);
553 printk("%08x\n", status
);
562 #ifdef WAKE_SECONDARY_VIA_NMI
564 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
565 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
566 * won't ... remember to clear down the APIC, etc later.
569 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
571 unsigned long send_status
= 0, accept_status
= 0;
575 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
577 /* Boot on the stack */
578 /* Kick the second */
579 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
581 Dprintk("Waiting for send to finish...\n");
586 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
587 } while (send_status
&& (timeout
++ < 1000));
590 * Give the other CPU some time to accept the IPI.
594 * Due to the Pentium erratum 3AP.
596 maxlvt
= lapic_get_maxlvt();
598 apic_read_around(APIC_SPIV
);
599 apic_write(APIC_ESR
, 0);
601 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
602 Dprintk("NMI sent.\n");
605 printk("APIC never delivered???\n");
607 printk("APIC delivery error (%lx).\n", accept_status
);
609 return (send_status
| accept_status
);
611 #endif /* WAKE_SECONDARY_VIA_NMI */
613 #ifdef WAKE_SECONDARY_VIA_INIT
615 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
617 unsigned long send_status
= 0, accept_status
= 0;
618 int maxlvt
, timeout
, num_starts
, j
;
621 * Be paranoid about clearing APIC errors.
623 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
624 apic_read_around(APIC_SPIV
);
625 apic_write(APIC_ESR
, 0);
629 Dprintk("Asserting INIT.\n");
632 * Turn INIT on target chip
634 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
639 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
642 Dprintk("Waiting for send to finish...\n");
647 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
648 } while (send_status
&& (timeout
++ < 1000));
652 Dprintk("Deasserting INIT.\n");
655 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
658 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
660 Dprintk("Waiting for send to finish...\n");
665 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
666 } while (send_status
&& (timeout
++ < 1000));
668 atomic_set(&init_deasserted
, 1);
671 * Should we send STARTUP IPIs ?
673 * Determine this based on the APIC version.
674 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
676 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
682 * Paravirt / VMI wants a startup IPI hook here to set up the
683 * target processor state.
685 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
686 (unsigned long) stack_start
.esp
);
689 * Run STARTUP IPI loop.
691 Dprintk("#startup loops: %d.\n", num_starts
);
693 maxlvt
= lapic_get_maxlvt();
695 for (j
= 1; j
<= num_starts
; j
++) {
696 Dprintk("Sending STARTUP #%d.\n",j
);
697 apic_read_around(APIC_SPIV
);
698 apic_write(APIC_ESR
, 0);
700 Dprintk("After apic_write.\n");
707 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
709 /* Boot on the stack */
710 /* Kick the second */
711 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
712 | (start_eip
>> 12));
715 * Give the other CPU some time to accept the IPI.
719 Dprintk("Startup point 1.\n");
721 Dprintk("Waiting for send to finish...\n");
726 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
727 } while (send_status
&& (timeout
++ < 1000));
730 * Give the other CPU some time to accept the IPI.
734 * Due to the Pentium erratum 3AP.
737 apic_read_around(APIC_SPIV
);
738 apic_write(APIC_ESR
, 0);
740 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
741 if (send_status
|| accept_status
)
744 Dprintk("After Startup.\n");
747 printk("APIC never delivered???\n");
749 printk("APIC delivery error (%lx).\n", accept_status
);
751 return (send_status
| accept_status
);
753 #endif /* WAKE_SECONDARY_VIA_INIT */
755 extern cpumask_t cpu_initialized
;
756 static inline int alloc_cpu_id(void)
760 cpus_complement(tmp_map
, cpu_present_map
);
761 cpu
= first_cpu(tmp_map
);
767 #ifdef CONFIG_HOTPLUG_CPU
768 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
769 static inline struct task_struct
* alloc_idle_task(int cpu
)
771 struct task_struct
*idle
;
773 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
774 /* initialize thread_struct. we really want to avoid destroy
777 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
778 init_idle(idle
, cpu
);
781 idle
= fork_idle(cpu
);
784 cpu_idle_tasks
[cpu
] = idle
;
788 #define alloc_idle_task(cpu) fork_idle(cpu)
791 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
)
793 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
794 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
795 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
798 struct task_struct
*idle
;
799 unsigned long boot_error
;
801 unsigned long start_eip
;
802 unsigned short nmi_high
= 0, nmi_low
= 0;
805 * We can't use kernel_thread since we must avoid to
806 * reschedule the child.
808 idle
= alloc_idle_task(cpu
);
810 panic("failed fork for CPU %d", cpu
);
812 /* Pre-allocate and initialize the CPU's GDT and PDA so it
813 doesn't have to do any memory allocation during the
814 delicate CPU-bringup phase. */
815 if (!init_gdt(cpu
, idle
)) {
816 printk(KERN_INFO
"Couldn't allocate GDT/PDA for CPU %d\n", cpu
);
820 idle
->thread
.eip
= (unsigned long) start_secondary
;
821 /* start_eip had better be page-aligned! */
822 start_eip
= setup_trampoline();
825 alternatives_smp_switch(1);
827 /* So we see what's up */
828 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
829 /* Stack for startup_32 can be just as for start_secondary onwards */
830 stack_start
.esp
= (void *) idle
->thread
.esp
;
834 x86_cpu_to_apicid
[cpu
] = apicid
;
836 * This grunge runs the startup process for
837 * the targeted processor.
840 atomic_set(&init_deasserted
, 0);
842 Dprintk("Setting warm reset code and vector.\n");
844 store_NMI_vector(&nmi_high
, &nmi_low
);
846 smpboot_setup_warm_reset_vector(start_eip
);
849 * Starting actual IPI sequence...
851 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
855 * allow APs to start initializing.
857 Dprintk("Before Callout %d.\n", cpu
);
858 cpu_set(cpu
, cpu_callout_map
);
859 Dprintk("After Callout %d.\n", cpu
);
862 * Wait 5s total for a response
864 for (timeout
= 0; timeout
< 50000; timeout
++) {
865 if (cpu_isset(cpu
, cpu_callin_map
))
866 break; /* It has booted */
870 if (cpu_isset(cpu
, cpu_callin_map
)) {
871 /* number CPUs logically, starting from 1 (BSP is 0) */
873 printk("CPU%d: ", cpu
);
874 print_cpu_info(&cpu_data
[cpu
]);
875 Dprintk("CPU has booted.\n");
878 if (*((volatile unsigned char *)trampoline_base
)
880 /* trampoline started but...? */
881 printk("Stuck ??\n");
883 /* trampoline code not run */
884 printk("Not responding.\n");
885 inquire_remote_apic(apicid
);
890 /* Try to put things back the way they were before ... */
891 unmap_cpu_to_logical_apicid(cpu
);
892 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
893 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
896 x86_cpu_to_apicid
[cpu
] = apicid
;
897 cpu_set(cpu
, cpu_present_map
);
900 /* mark "stuck" area as not stuck */
901 *((volatile unsigned long *)trampoline_base
) = 0;
906 #ifdef CONFIG_HOTPLUG_CPU
907 void cpu_exit_clear(void)
909 int cpu
= raw_smp_processor_id();
917 cpu_clear(cpu
, cpu_callout_map
);
918 cpu_clear(cpu
, cpu_callin_map
);
920 cpu_clear(cpu
, smp_commenced_mask
);
921 unmap_cpu_to_logical_apicid(cpu
);
924 struct warm_boot_cpu_info
{
925 struct completion
*complete
;
926 struct work_struct task
;
931 static void __cpuinit
do_warm_boot_cpu(struct work_struct
*work
)
933 struct warm_boot_cpu_info
*info
=
934 container_of(work
, struct warm_boot_cpu_info
, task
);
935 do_boot_cpu(info
->apicid
, info
->cpu
);
936 complete(info
->complete
);
939 static int __cpuinit
__smp_prepare_cpu(int cpu
)
941 DECLARE_COMPLETION_ONSTACK(done
);
942 struct warm_boot_cpu_info info
;
944 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
946 apicid
= x86_cpu_to_apicid
[cpu
];
947 if (apicid
== BAD_APICID
) {
953 * the CPU isn't initialized at boot time, allocate gdt table here.
954 * cpu_init will initialize it
956 if (!cpu_gdt_descr
->address
) {
957 cpu_gdt_descr
->address
= get_zeroed_page(GFP_KERNEL
);
958 if (!cpu_gdt_descr
->address
)
959 printk(KERN_CRIT
"CPU%d failed to allocate GDT\n", cpu
);
964 info
.complete
= &done
;
965 info
.apicid
= apicid
;
967 INIT_WORK(&info
.task
, do_warm_boot_cpu
);
969 /* init low mem mapping */
970 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
971 min_t(unsigned long, KERNEL_PGD_PTRS
, USER_PGD_PTRS
));
973 schedule_work(&info
.task
);
974 wait_for_completion(&done
);
983 static void smp_tune_scheduling(void)
985 unsigned long cachesize
; /* kB */
988 cachesize
= boot_cpu_data
.x86_cache_size
;
991 max_cache_size
= cachesize
* 1024;
996 * Cycle through the processors sending APIC IPIs to boot each.
999 static int boot_cpu_logical_apicid
;
1000 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1002 #ifdef CONFIG_X86_NUMAQ
1003 EXPORT_SYMBOL(xquad_portio
);
1006 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1008 int apicid
, cpu
, bit
, kicked
;
1009 unsigned long bogosum
= 0;
1012 * Setup boot CPU information
1014 smp_store_cpu_info(0); /* Final full version of the data */
1015 printk("CPU%d: ", 0);
1016 print_cpu_info(&cpu_data
[0]);
1018 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1019 boot_cpu_logical_apicid
= logical_smp_processor_id();
1020 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1022 current_thread_info()->cpu
= 0;
1023 smp_tune_scheduling();
1025 set_cpu_sibling_map(0);
1028 * If we couldn't find an SMP configuration at boot time,
1029 * get out of here now!
1031 if (!smp_found_config
&& !acpi_lapic
) {
1032 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1033 smpboot_clear_io_apic_irqs();
1034 phys_cpu_present_map
= physid_mask_of_physid(0);
1035 if (APIC_init_uniprocessor())
1036 printk(KERN_NOTICE
"Local APIC not detected."
1037 " Using dummy APIC emulation.\n");
1038 map_cpu_to_logical_apicid();
1039 cpu_set(0, cpu_sibling_map
[0]);
1040 cpu_set(0, cpu_core_map
[0]);
1045 * Should not be necessary because the MP table should list the boot
1046 * CPU too, but we do it for the sake of robustness anyway.
1047 * Makes no sense to do this check in clustered apic mode, so skip it
1049 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1050 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1051 boot_cpu_physical_apicid
);
1052 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1056 * If we couldn't find a local APIC, then get out of here now!
1058 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1059 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1060 boot_cpu_physical_apicid
);
1061 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1062 smpboot_clear_io_apic_irqs();
1063 phys_cpu_present_map
= physid_mask_of_physid(0);
1064 cpu_set(0, cpu_sibling_map
[0]);
1065 cpu_set(0, cpu_core_map
[0]);
1069 verify_local_APIC();
1072 * If SMP should be disabled, then really disable it!
1075 smp_found_config
= 0;
1076 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1077 smpboot_clear_io_apic_irqs();
1078 phys_cpu_present_map
= physid_mask_of_physid(0);
1079 cpu_set(0, cpu_sibling_map
[0]);
1080 cpu_set(0, cpu_core_map
[0]);
1086 map_cpu_to_logical_apicid();
1089 setup_portio_remap();
1092 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1094 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1095 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1096 * clustered apic ID.
1098 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1101 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1102 apicid
= cpu_present_to_apicid(bit
);
1104 * Don't even attempt to start the boot CPU!
1106 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1109 if (!check_apicid_present(bit
))
1111 if (max_cpus
<= cpucount
+1)
1114 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1115 printk("CPU #%d not responding - cannot use it.\n",
1122 * Cleanup possible dangling ends...
1124 smpboot_restore_warm_reset_vector();
1127 * Allow the user to impress friends.
1129 Dprintk("Before bogomips.\n");
1130 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1131 if (cpu_isset(cpu
, cpu_callout_map
))
1132 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1134 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1136 bogosum
/(500000/HZ
),
1137 (bogosum
/(5000/HZ
))%100);
1139 Dprintk("Before bogocount - setting activated=1.\n");
1142 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1145 * Don't taint if we are running SMP kernel on a single non-MP
1148 if (tainted
& TAINT_UNSAFE_SMP
) {
1150 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1152 tainted
&= ~TAINT_UNSAFE_SMP
;
1155 Dprintk("Boot done.\n");
1158 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1161 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1162 cpus_clear(cpu_sibling_map
[cpu
]);
1163 cpus_clear(cpu_core_map
[cpu
]);
1166 cpu_set(0, cpu_sibling_map
[0]);
1167 cpu_set(0, cpu_core_map
[0]);
1169 smpboot_setup_io_apic();
1174 /* These are wrappers to interface to the new boot process. Someone
1175 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1176 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1178 smp_commenced_mask
= cpumask_of_cpu(0);
1179 cpu_callin_map
= cpumask_of_cpu(0);
1181 smp_boot_cpus(max_cpus
);
1184 void __devinit
smp_prepare_boot_cpu(void)
1186 cpu_set(smp_processor_id(), cpu_online_map
);
1187 cpu_set(smp_processor_id(), cpu_callout_map
);
1188 cpu_set(smp_processor_id(), cpu_present_map
);
1189 cpu_set(smp_processor_id(), cpu_possible_map
);
1190 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1193 #ifdef CONFIG_HOTPLUG_CPU
1195 remove_siblinginfo(int cpu
)
1198 struct cpuinfo_x86
*c
= cpu_data
;
1200 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1201 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1203 * last thread sibling in this cpu core going down
1205 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1206 c
[sibling
].booted_cores
--;
1209 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1210 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1211 cpus_clear(cpu_sibling_map
[cpu
]);
1212 cpus_clear(cpu_core_map
[cpu
]);
1213 c
[cpu
].phys_proc_id
= 0;
1214 c
[cpu
].cpu_core_id
= 0;
1215 cpu_clear(cpu
, cpu_sibling_setup_map
);
1218 int __cpu_disable(void)
1220 cpumask_t map
= cpu_online_map
;
1221 int cpu
= smp_processor_id();
1224 * Perhaps use cpufreq to drop frequency, but that could go
1225 * into generic code.
1227 * We won't take down the boot processor on i386 due to some
1228 * interrupts only being able to be serviced by the BSP.
1229 * Especially so if we're not using an IOAPIC -zwane
1233 if (nmi_watchdog
== NMI_LOCAL_APIC
)
1234 stop_apic_nmi_watchdog(NULL
);
1236 /* Allow any queued timer interrupts to get serviced */
1239 local_irq_disable();
1241 remove_siblinginfo(cpu
);
1243 cpu_clear(cpu
, map
);
1245 /* It's now safe to remove this processor from the online map */
1246 cpu_clear(cpu
, cpu_online_map
);
1250 void __cpu_die(unsigned int cpu
)
1252 /* We don't do anything here: idle task is faking death itself. */
1255 for (i
= 0; i
< 10; i
++) {
1256 /* They ack this in play_dead by setting CPU_DEAD */
1257 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1258 printk ("CPU %d is now offline\n", cpu
);
1259 if (1 == num_online_cpus())
1260 alternatives_smp_switch(0);
1265 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1267 #else /* ... !CONFIG_HOTPLUG_CPU */
1268 int __cpu_disable(void)
1273 void __cpu_die(unsigned int cpu
)
1275 /* We said "no" in __cpu_disable */
1278 #endif /* CONFIG_HOTPLUG_CPU */
1280 int __cpuinit
__cpu_up(unsigned int cpu
)
1282 unsigned long flags
;
1283 #ifdef CONFIG_HOTPLUG_CPU
1287 * We do warm boot only on cpus that had booted earlier
1288 * Otherwise cold boot is all handled from smp_boot_cpus().
1289 * cpu_callin_map is set during AP kickstart process. Its reset
1290 * when a cpu is taken offline from cpu_exit_clear().
1292 if (!cpu_isset(cpu
, cpu_callin_map
))
1293 ret
= __smp_prepare_cpu(cpu
);
1299 /* In case one didn't come up */
1300 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1301 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1305 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1306 /* Unleash the CPU! */
1307 cpu_set(cpu
, smp_commenced_mask
);
1310 * Check TSC synchronization with the AP (keep irqs disabled
1313 local_irq_save(flags
);
1314 check_tsc_sync_source(cpu
);
1315 local_irq_restore(flags
);
1317 while (!cpu_isset(cpu
, cpu_online_map
)) {
1319 touch_nmi_watchdog();
1322 #ifdef CONFIG_X86_GENERICARCH
1323 if (num_online_cpus() > 8 && genapic
== &apic_default
)
1324 panic("Default flat APIC routing can't be used with > 8 cpus\n");
1330 void __init
smp_cpus_done(unsigned int max_cpus
)
1332 #ifdef CONFIG_X86_IO_APIC
1333 setup_ioapic_dest();
1336 #ifndef CONFIG_HOTPLUG_CPU
1338 * Disable executability of the SMP trampoline:
1340 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1344 void __init
smp_intr_init(void)
1347 * IRQ0 must be given a fixed assignment and initialized,
1348 * because it's used before the IO-APIC is set up.
1350 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1353 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1354 * IPI, driven by wakeup.
1356 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1358 /* IPI for invalidation */
1359 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1361 /* IPI for generic function call */
1362 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1366 * If the BIOS enumerates physical processors before logical,
1367 * maxcpus=N at enumeration-time can be used to disable HT.
1369 static int __init
parse_maxcpus(char *arg
)
1371 extern unsigned int maxcpus
;
1373 maxcpus
= simple_strtoul(arg
, NULL
, 0);
1376 early_param("maxcpus", parse_maxcpus
);