1 #include <linux/errno.h>
2 #include <linux/signal.h>
3 #include <linux/sched.h>
4 #include <linux/ioport.h>
5 #include <linux/interrupt.h>
6 #include <linux/slab.h>
7 #include <linux/random.h>
8 #include <linux/smp_lock.h>
9 #include <linux/init.h>
10 #include <linux/kernel_stat.h>
11 #include <linux/sysdev.h>
12 #include <linux/bitops.h>
14 #include <asm/8253pit.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
18 #include <asm/timer.h>
19 #include <asm/pgtable.h>
20 #include <asm/delay.h>
23 #include <asm/arch_hooks.h>
24 #include <asm/i8259.h>
29 * This is the 'legacy' 8259A Programmable Interrupt Controller,
30 * present in the majority of PC/AT boxes.
31 * plus some generic x86 specific things if generic specifics makes
33 * this file should become arch/i386/kernel/irq.c when the old irq.c
34 * moves to arch independent land
37 static int i8259A_auto_eoi
;
38 DEFINE_SPINLOCK(i8259A_lock
);
39 static void mask_and_ack_8259A(unsigned int);
41 static struct irq_chip i8259A_chip
= {
43 .mask
= disable_8259A_irq
,
44 .disable
= disable_8259A_irq
,
45 .unmask
= enable_8259A_irq
,
46 .mask_ack
= mask_and_ack_8259A
,
50 * 8259A PIC functions to handle ISA devices:
54 * This contains the irq mask for both 8259A irq controllers,
56 unsigned int cached_irq_mask
= 0xffff;
59 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
60 * boards the timer interrupt is not really connected to any IO-APIC pin,
61 * it's fed to the master 8259A's IR0 line only.
63 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
64 * this 'mixed mode' IRQ handling costs nothing because it's only used
67 unsigned long io_apic_irqs
;
69 void disable_8259A_irq(unsigned int irq
)
71 unsigned int mask
= 1 << irq
;
74 spin_lock_irqsave(&i8259A_lock
, flags
);
75 cached_irq_mask
|= mask
;
77 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
79 outb(cached_master_mask
, PIC_MASTER_IMR
);
80 spin_unlock_irqrestore(&i8259A_lock
, flags
);
83 void enable_8259A_irq(unsigned int irq
)
85 unsigned int mask
= ~(1 << irq
);
88 spin_lock_irqsave(&i8259A_lock
, flags
);
89 cached_irq_mask
&= mask
;
91 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
93 outb(cached_master_mask
, PIC_MASTER_IMR
);
94 spin_unlock_irqrestore(&i8259A_lock
, flags
);
97 int i8259A_irq_pending(unsigned int irq
)
99 unsigned int mask
= 1<<irq
;
103 spin_lock_irqsave(&i8259A_lock
, flags
);
105 ret
= inb(PIC_MASTER_CMD
) & mask
;
107 ret
= inb(PIC_SLAVE_CMD
) & (mask
>> 8);
108 spin_unlock_irqrestore(&i8259A_lock
, flags
);
113 void make_8259A_irq(unsigned int irq
)
115 disable_irq_nosync(irq
);
116 io_apic_irqs
&= ~(1<<irq
);
117 set_irq_chip_and_handler_name(irq
, &i8259A_chip
, handle_level_irq
,
123 * This function assumes to be called rarely. Switching between
124 * 8259A registers is slow.
125 * This has to be protected by the irq controller spinlock
126 * before being called.
128 static inline int i8259A_irq_real(unsigned int irq
)
131 int irqmask
= 1<<irq
;
134 outb(0x0B,PIC_MASTER_CMD
); /* ISR register */
135 value
= inb(PIC_MASTER_CMD
) & irqmask
;
136 outb(0x0A,PIC_MASTER_CMD
); /* back to the IRR register */
139 outb(0x0B,PIC_SLAVE_CMD
); /* ISR register */
140 value
= inb(PIC_SLAVE_CMD
) & (irqmask
>> 8);
141 outb(0x0A,PIC_SLAVE_CMD
); /* back to the IRR register */
146 * Careful! The 8259A is a fragile beast, it pretty
147 * much _has_ to be done exactly like this (mask it
148 * first, _then_ send the EOI, and the order of EOI
149 * to the two 8259s is important!
151 static void mask_and_ack_8259A(unsigned int irq
)
153 unsigned int irqmask
= 1 << irq
;
156 spin_lock_irqsave(&i8259A_lock
, flags
);
158 * Lightweight spurious IRQ detection. We do not want
159 * to overdo spurious IRQ handling - it's usually a sign
160 * of hardware problems, so we only do the checks we can
161 * do without slowing down good hardware unnecessarily.
163 * Note that IRQ7 and IRQ15 (the two spurious IRQs
164 * usually resulting from the 8259A-1|2 PICs) occur
165 * even if the IRQ is masked in the 8259A. Thus we
166 * can check spurious 8259A IRQs without doing the
167 * quite slow i8259A_irq_real() call for every IRQ.
168 * This does not cover 100% of spurious interrupts,
169 * but should be enough to warn the user that there
170 * is something bad going on ...
172 if (cached_irq_mask
& irqmask
)
173 goto spurious_8259A_irq
;
174 cached_irq_mask
|= irqmask
;
178 inb(PIC_SLAVE_IMR
); /* DUMMY - (do we need this?) */
179 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
180 outb(0x60+(irq
&7),PIC_SLAVE_CMD
);/* 'Specific EOI' to slave */
181 outb(0x60+PIC_CASCADE_IR
,PIC_MASTER_CMD
); /* 'Specific EOI' to master-IRQ2 */
183 inb(PIC_MASTER_IMR
); /* DUMMY - (do we need this?) */
184 outb(cached_master_mask
, PIC_MASTER_IMR
);
185 outb(0x60+irq
,PIC_MASTER_CMD
); /* 'Specific EOI to master */
187 spin_unlock_irqrestore(&i8259A_lock
, flags
);
192 * this is the slow path - should happen rarely.
194 if (i8259A_irq_real(irq
))
196 * oops, the IRQ _is_ in service according to the
197 * 8259A - not spurious, go handle it.
199 goto handle_real_irq
;
202 static int spurious_irq_mask
;
204 * At this point we can be sure the IRQ is spurious,
205 * lets ACK and report it. [once per IRQ]
207 if (!(spurious_irq_mask
& irqmask
)) {
208 printk(KERN_DEBUG
"spurious 8259A interrupt: IRQ%d.\n", irq
);
209 spurious_irq_mask
|= irqmask
;
211 atomic_inc(&irq_err_count
);
213 * Theoretically we do not have to handle this IRQ,
214 * but in Linux this does not cause problems and is
217 goto handle_real_irq
;
221 static char irq_trigger
[2];
223 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
225 static void restore_ELCR(char *trigger
)
227 outb(trigger
[0], 0x4d0);
228 outb(trigger
[1], 0x4d1);
231 static void save_ELCR(char *trigger
)
233 /* IRQ 0,1,2,8,13 are marked as reserved */
234 trigger
[0] = inb(0x4d0) & 0xF8;
235 trigger
[1] = inb(0x4d1) & 0xDE;
238 static int i8259A_resume(struct sys_device
*dev
)
240 init_8259A(i8259A_auto_eoi
);
241 restore_ELCR(irq_trigger
);
245 static int i8259A_suspend(struct sys_device
*dev
, pm_message_t state
)
247 save_ELCR(irq_trigger
);
251 static int i8259A_shutdown(struct sys_device
*dev
)
253 /* Put the i8259A into a quiescent state that
254 * the kernel initialization code can get it
257 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
258 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-1 */
262 static struct sysdev_class i8259_sysdev_class
= {
263 set_kset_name("i8259"),
264 .suspend
= i8259A_suspend
,
265 .resume
= i8259A_resume
,
266 .shutdown
= i8259A_shutdown
,
269 static struct sys_device device_i8259A
= {
271 .cls
= &i8259_sysdev_class
,
274 static int __init
i8259A_init_sysfs(void)
276 int error
= sysdev_class_register(&i8259_sysdev_class
);
278 error
= sysdev_register(&device_i8259A
);
282 device_initcall(i8259A_init_sysfs
);
284 void init_8259A(int auto_eoi
)
288 i8259A_auto_eoi
= auto_eoi
;
290 spin_lock_irqsave(&i8259A_lock
, flags
);
292 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
293 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
296 * outb_p - this has to work on a wide range of PC hardware.
298 outb_p(0x11, PIC_MASTER_CMD
); /* ICW1: select 8259A-1 init */
299 outb_p(0x20 + 0, PIC_MASTER_IMR
); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
300 outb_p(1U << PIC_CASCADE_IR
, PIC_MASTER_IMR
); /* 8259A-1 (the master) has a slave on IR2 */
301 if (auto_eoi
) /* master does Auto EOI */
302 outb_p(MASTER_ICW4_DEFAULT
| PIC_ICW4_AEOI
, PIC_MASTER_IMR
);
303 else /* master expects normal EOI */
304 outb_p(MASTER_ICW4_DEFAULT
, PIC_MASTER_IMR
);
306 outb_p(0x11, PIC_SLAVE_CMD
); /* ICW1: select 8259A-2 init */
307 outb_p(0x20 + 8, PIC_SLAVE_IMR
); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
308 outb_p(PIC_CASCADE_IR
, PIC_SLAVE_IMR
); /* 8259A-2 is a slave on master's IR2 */
309 outb_p(SLAVE_ICW4_DEFAULT
, PIC_SLAVE_IMR
); /* (slave's support for AEOI in flat mode is to be investigated) */
312 * In AEOI mode we just have to mask the interrupt
315 i8259A_chip
.mask_ack
= disable_8259A_irq
;
317 i8259A_chip
.mask_ack
= mask_and_ack_8259A
;
319 udelay(100); /* wait for 8259A to initialize */
321 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
322 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
324 spin_unlock_irqrestore(&i8259A_lock
, flags
);
328 * Note that on a 486, we don't want to do a SIGFPE on an irq13
329 * as the irq is unreliable, and exception 16 works correctly
330 * (ie as explained in the intel literature). On a 386, you
331 * can't use exception 16 due to bad IBM design, so we have to
332 * rely on the less exact irq13.
334 * Careful.. Not only is IRQ13 unreliable, but it is also
335 * leads to races. IBM designers who came up with it should
340 static irqreturn_t
math_error_irq(int cpl
, void *dev_id
)
342 extern void math_error(void __user
*);
344 if (ignore_fpu_irq
|| !boot_cpu_data
.hard_math
)
346 math_error((void __user
*)get_irq_regs()->eip
);
351 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
352 * so allow interrupt sharing.
354 static struct irqaction fpu_irq
= { math_error_irq
, 0, CPU_MASK_NONE
, "fpu", NULL
, NULL
};
356 void __init
init_ISA_irqs (void)
360 #ifdef CONFIG_X86_LOCAL_APIC
365 for (i
= 0; i
< NR_IRQS
; i
++) {
366 irq_desc
[i
].status
= IRQ_DISABLED
;
367 irq_desc
[i
].action
= NULL
;
368 irq_desc
[i
].depth
= 1;
372 * 16 old-style INTA-cycle interrupts:
374 set_irq_chip_and_handler_name(i
, &i8259A_chip
,
375 handle_level_irq
, "XT");
378 * 'high' PCI IRQs filled in on demand
380 irq_desc
[i
].chip
= &no_irq_chip
;
385 /* Overridden in paravirt.c */
386 void init_IRQ(void) __attribute__((weak
, alias("native_init_IRQ")));
388 void __init
native_init_IRQ(void)
392 /* all the set up before the call gates are initialised */
393 pre_intr_init_hook();
396 * Cover the whole vector space, no vector can escape
397 * us. (some of these will be overridden and become
398 * 'special' SMP interrupts)
400 for (i
= 0; i
< (NR_VECTORS
- FIRST_EXTERNAL_VECTOR
); i
++) {
401 int vector
= FIRST_EXTERNAL_VECTOR
+ i
;
404 if (vector
!= SYSCALL_VECTOR
)
405 set_intr_gate(vector
, interrupt
[i
]);
408 /* setup after call gates are initialised (usually add in
409 * the architecture specific gates)
414 * External FPU? Set up irq13 if so, for
415 * original braindamaged IBM FERR coupling.
417 if (boot_cpu_data
.hard_math
&& !cpu_has_fpu
)
418 setup_irq(FPU_IRQ
, &fpu_irq
);
420 irq_ctx_init(smp_processor_id());