drivers/net/sfc/tenxpress.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2007-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/seq_file.h>
  12 #include "efx.h"
  13 #include "mdio_10g.h"
  14 #include "falcon.h"
  15 #include "phy.h"
  16 #include "falcon_hwdefs.h"
  17 #include "boards.h"
  18 #include "workarounds.h"
  19 #include "selftest.h"
  20
  21 /* We expect these MMDs to be in the package.  SFT9001 also has a
  22  * clause 22 extension MMD, but since it doesn't have all the generic
  23  * MMD registers it is pointless to include it here.
  24  */
  25 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD        | \
  26                                  MDIO_MMDREG_DEVS_PCS           | \
  27                                  MDIO_MMDREG_DEVS_PHYXS         | \
  28                                  MDIO_MMDREG_DEVS_AN)
  29
  30 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) |      \
  31                            (1 << LOOPBACK_PCS) |        \
  32                            (1 << LOOPBACK_PMAPMD) |     \
  33                            (1 << LOOPBACK_NETWORK))
  34
  35 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) |       \
  36                            (1 << LOOPBACK_PHYXS) |      \
  37                            (1 << LOOPBACK_PCS) |        \
  38                            (1 << LOOPBACK_PMAPMD) |     \
  39                            (1 << LOOPBACK_NETWORK))
  40
  41 /* We complain if we fail to see the link partner as 10G capable this many
  42  * times in a row (must be > 1 as sampling the autoneg. registers is racy)
  43  */
  44 #define MAX_BAD_LP_TRIES        (5)
  45
  46 /* LASI Control */
  47 #define PMA_PMD_LASI_CTRL       36866
  48 #define PMA_PMD_LASI_STATUS     36869
  49 #define PMA_PMD_LS_ALARM_LBN    0
  50 #define PMA_PMD_LS_ALARM_WIDTH  1
  51 #define PMA_PMD_TX_ALARM_LBN    1
  52 #define PMA_PMD_TX_ALARM_WIDTH  1
  53 #define PMA_PMD_RX_ALARM_LBN    2
  54 #define PMA_PMD_RX_ALARM_WIDTH  1
  55 #define PMA_PMD_AN_ALARM_LBN    3
  56 #define PMA_PMD_AN_ALARM_WIDTH  1
  57
  58 /* Extended control register */
  59 #define PMA_PMD_XCONTROL_REG    49152
  60 #define PMA_PMD_EXT_GMII_EN_LBN 1
  61 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
  62 #define PMA_PMD_EXT_CLK_OUT_LBN 2
  63 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
  64 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8   /* SFX7101 only */
  65 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
  66 #define PMA_PMD_EXT_CLK312_LBN  8       /* SFT9001 only */
  67 #define PMA_PMD_EXT_CLK312_WIDTH 1
  68 #define PMA_PMD_EXT_LPOWER_LBN  12
  69 #define PMA_PMD_EXT_LPOWER_WIDTH 1
  70 #define PMA_PMD_EXT_SSR_LBN     15
  71 #define PMA_PMD_EXT_SSR_WIDTH   1
  72
  73 /* extended status register */
  74 #define PMA_PMD_XSTATUS_REG     49153
  75 #define PMA_PMD_XSTAT_FLP_LBN   (12)
  76
  77 /* LED control register */
  78 #define PMA_PMD_LED_CTRL_REG    49159
  79 #define PMA_PMA_LED_ACTIVITY_LBN        (3)
  80
  81 /* LED function override register */
  82 #define PMA_PMD_LED_OVERR_REG   49161
  83 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
  84 #define PMA_PMD_LED_LINK_LBN    (0)
  85 #define PMA_PMD_LED_SPEED_LBN   (2)
  86 #define PMA_PMD_LED_TX_LBN      (4)
  87 #define PMA_PMD_LED_RX_LBN      (6)
  88 /* Override settings */
  89 #define PMA_PMD_LED_AUTO        (0)     /* H/W control */
  90 #define PMA_PMD_LED_ON          (1)
  91 #define PMA_PMD_LED_OFF         (2)
  92 #define PMA_PMD_LED_FLASH       (3)
  93 #define PMA_PMD_LED_MASK        3
  94 /* All LEDs under hardware control */
  95 #define PMA_PMD_LED_FULL_AUTO   (0)
  96 /* Green and Amber under hardware control, Red off */
  97 #define PMA_PMD_LED_DEFAULT     (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
  98
  99 #define PMA_PMD_SPEED_ENABLE_REG 49192
 100 #define PMA_PMD_100TX_ADV_LBN    1
 101 #define PMA_PMD_100TX_ADV_WIDTH  1
 102 #define PMA_PMD_1000T_ADV_LBN    2
 103 #define PMA_PMD_1000T_ADV_WIDTH  1
 104 #define PMA_PMD_10000T_ADV_LBN   3
 105 #define PMA_PMD_10000T_ADV_WIDTH 1
 106 #define PMA_PMD_SPEED_LBN        4
 107 #define PMA_PMD_SPEED_WIDTH      4
 108
 109 /* Serdes control registers - SFT9001 only */
 110 #define PMA_PMD_CSERDES_CTRL_REG 64258
 111 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
 112 #define PMA_PMD_CSERDES_DEFAULT 0x000f
 113
 114 /* Misc register defines - SFX7101 only */
 115 #define PCS_CLOCK_CTRL_REG      55297
 116 #define PLL312_RST_N_LBN 2
 117
 118 #define PCS_SOFT_RST2_REG       55302
 119 #define SERDES_RST_N_LBN 13
 120 #define XGXS_RST_N_LBN 12
 121
 122 #define PCS_TEST_SELECT_REG     55303   /* PRM 10.5.8 */
 123 #define CLK312_EN_LBN 3
 124
 125 /* PHYXS registers */
 126 #define PHYXS_XCONTROL_REG      49152
 127 #define PHYXS_RESET_LBN         15
 128 #define PHYXS_RESET_WIDTH       1
 129
 130 #define PHYXS_TEST1         (49162)
 131 #define LOOPBACK_NEAR_LBN   (8)
 132 #define LOOPBACK_NEAR_WIDTH (1)
 133
 134 #define PCS_10GBASET_STAT1       32
 135 #define PCS_10GBASET_BLKLK_LBN   0
 136 #define PCS_10GBASET_BLKLK_WIDTH 1
 137
 138 /* Boot status register */
 139 #define PCS_BOOT_STATUS_REG     53248
 140 #define PCS_BOOT_FATAL_ERR_LBN  (0)
 141 #define PCS_BOOT_PROGRESS_LBN   (1)
 142 #define PCS_BOOT_PROGRESS_WIDTH (2)
 143 #define PCS_BOOT_COMPLETE_LBN   (3)
 144
 145 #define PCS_BOOT_MAX_DELAY      (100)
 146 #define PCS_BOOT_POLL_DELAY     (10)
 147
 148 /* 100M/1G PHY registers */
 149 #define GPHY_XCONTROL_REG       49152
 150 #define GPHY_ISOLATE_LBN        10
 151 #define GPHY_ISOLATE_WIDTH      1
 152 #define GPHY_DUPLEX_LBN         8
 153 #define GPHY_DUPLEX_WIDTH       1
 154 #define GPHY_LOOPBACK_NEAR_LBN  14
 155 #define GPHY_LOOPBACK_NEAR_WIDTH 1
 156
 157 #define C22EXT_STATUS_REG       49153
 158 #define C22EXT_STATUS_LINK_LBN  2
 159 #define C22EXT_STATUS_LINK_WIDTH 1
 160
 161 #define C22EXT_MSTSLV_REG       49162
 162 #define C22EXT_MSTSLV_1000_HD_LBN 10
 163 #define C22EXT_MSTSLV_1000_HD_WIDTH 1
 164 #define C22EXT_MSTSLV_1000_FD_LBN 11
 165 #define C22EXT_MSTSLV_1000_FD_WIDTH 1
 166
 167 /* Time to wait between powering down the LNPGA and turning off the power
 168  * rails */
 169 #define LNPGA_PDOWN_WAIT        (HZ / 5)
 170
 171 static int crc_error_reset_threshold = 100;
 172 module_param(crc_error_reset_threshold, int, 0644);
 173 MODULE_PARM_DESC(crc_error_reset_threshold,
 174                  "Max number of CRC errors before XAUI reset");
 175
 176 struct tenxpress_phy_data {
 177         enum efx_loopback_mode loopback_mode;
 178         atomic_t bad_crc_count;
 179         enum efx_phy_mode phy_mode;
 180         int bad_lp_tries;
 181 };
 182
 183 void tenxpress_crc_err(struct efx_nic *efx)
 184 {
 185         struct tenxpress_phy_data *phy_data = efx->phy_data;
 186         if (phy_data != NULL)
 187                 atomic_inc(&phy_data->bad_crc_count);
 188 }
 189
 190 static ssize_t show_phy_short_reach(struct device *dev,
 191                                     struct device_attribute *attr, char *buf)
 192 {
 193         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 194         int reg;
 195
 196         reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 197                                  MDIO_PMAPMD_10GBT_TXPWR);
 198         return sprintf(buf, "%d\n",
 199                        !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
 200 }
 201
 202 static ssize_t set_phy_short_reach(struct device *dev,
 203                                    struct device_attribute *attr,
 204                                    const char *buf, size_t count)
 205 {
 206         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 207
 208         rtnl_lock();
 209         mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 210                                MDIO_PMAPMD_10GBT_TXPWR,
 211                                MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
 212                                count != 0 && *buf != '0');
 213         efx_reconfigure_port(efx);
 214         rtnl_unlock();
 215
 216         return count;
 217 }
 218
 219 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
 220                    set_phy_short_reach);
 221
 222 /* Check that the C166 has booted successfully */
 223 static int tenxpress_phy_check(struct efx_nic *efx)
 224 {
 225         int phy_id = efx->mii.phy_id;
 226         int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
 227         int boot_stat;
 228
 229         /* Wait for the boot to complete (or not) */
 230         while (count) {
 231                 boot_stat = mdio_clause45_read(efx, phy_id,
 232                                                MDIO_MMD_PCS,
 233                                                PCS_BOOT_STATUS_REG);
 234                 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
 235                         break;
 236                 count--;
 237                 udelay(PCS_BOOT_POLL_DELAY);
 238         }
 239
 240         if (!count) {
 241                 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
 242                         "%x\n", __func__,
 243                         (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
 244                         ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
 245                 return -ETIMEDOUT;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static int tenxpress_init(struct efx_nic *efx)
 252 {
 253         int phy_id = efx->mii.phy_id;
 254         int reg;
 255         int rc;
 256
 257         if (efx->phy_type == PHY_TYPE_SFX7101) {
 258                 /* Enable 312.5 MHz clock */
 259                 mdio_clause45_write(efx, phy_id,
 260                                     MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
 261                                     1 << CLK312_EN_LBN);
 262         } else {
 263                 /* Enable 312.5 MHz clock and GMII */
 264                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 265                                          PMA_PMD_XCONTROL_REG);
 266                 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
 267                         (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
 268                         (1 << PMA_PMD_EXT_CLK312_LBN));
 269                 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
 270                                     PMA_PMD_XCONTROL_REG, reg);
 271                 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
 272                                        GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
 273                                        false);
 274         }
 275
 276         rc = tenxpress_phy_check(efx);
 277         if (rc < 0)
 278                 return rc;
 279
 280         /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
 281         if (efx->phy_type == PHY_TYPE_SFX7101) {
 282                 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
 283                                        PMA_PMD_LED_CTRL_REG,
 284                                        PMA_PMA_LED_ACTIVITY_LBN,
 285                                        true);
 286                 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
 287                                     PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
 288         }
 289
 290         return rc;
 291 }
 292
 293 static int tenxpress_phy_init(struct efx_nic *efx)
 294 {
 295         struct tenxpress_phy_data *phy_data;
 296         int rc = 0;
 297
 298         phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
 299         if (!phy_data)
 300                 return -ENOMEM;
 301         efx->phy_data = phy_data;
 302         phy_data->phy_mode = efx->phy_mode;
 303
 304         if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
 305                 if (efx->phy_type == PHY_TYPE_SFT9001A) {
 306                         int reg;
 307                         reg = mdio_clause45_read(efx, efx->mii.phy_id,
 308                                                  MDIO_MMD_PMAPMD,
 309                                                  PMA_PMD_XCONTROL_REG);
 310                         reg |= (1 << PMA_PMD_EXT_SSR_LBN);
 311                         mdio_clause45_write(efx, efx->mii.phy_id,
 312                                             MDIO_MMD_PMAPMD,
 313                                             PMA_PMD_XCONTROL_REG, reg);
 314                         mdelay(200);
 315                 }
 316
 317                 rc = mdio_clause45_wait_reset_mmds(efx,
 318                                                    TENXPRESS_REQUIRED_DEVS);
 319                 if (rc < 0)
 320                         goto fail;
 321
 322                 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
 323                 if (rc < 0)
 324                         goto fail;
 325         }
 326
 327         rc = tenxpress_init(efx);
 328         if (rc < 0)
 329                 goto fail;
 330
 331         if (efx->phy_type == PHY_TYPE_SFT9001B) {
 332                 rc = device_create_file(&efx->pci_dev->dev,
 333                                         &dev_attr_phy_short_reach);
 334                 if (rc)
 335                         goto fail;
 336         }
 337
 338         schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
 339
 340         /* Let XGXS and SerDes out of reset */
 341         falcon_reset_xaui(efx);
 342
 343         return 0;
 344
 345  fail:
 346         kfree(efx->phy_data);
 347         efx->phy_data = NULL;
 348         return rc;
 349 }
 350
 351 /* Perform a "special software reset" on the PHY. The caller is
 352  * responsible for saving and restoring the PHY hardware registers
 353  * properly, and masking/unmasking LASI */
 354 static int tenxpress_special_reset(struct efx_nic *efx)
 355 {
 356         int rc, reg;
 357
 358         /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
 359          * a special software reset can glitch the XGMAC sufficiently for stats
 360          * requests to fail. Since we don't often special_reset, just lock. */
 361         spin_lock(&efx->stats_lock);
 362
 363         /* Initiate reset */
 364         reg = mdio_clause45_read(efx, efx->mii.phy_id,
 365                                  MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
 366         reg |= (1 << PMA_PMD_EXT_SSR_LBN);
 367         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 368                             PMA_PMD_XCONTROL_REG, reg);
 369
 370         mdelay(200);
 371
 372         /* Wait for the blocks to come out of reset */
 373         rc = mdio_clause45_wait_reset_mmds(efx,
 374                                            TENXPRESS_REQUIRED_DEVS);
 375         if (rc < 0)
 376                 goto unlock;
 377
 378         /* Try and reconfigure the device */
 379         rc = tenxpress_init(efx);
 380         if (rc < 0)
 381                 goto unlock;
 382
 383         /* Wait for the XGXS state machine to churn */
 384         mdelay(10);
 385 unlock:
 386         spin_unlock(&efx->stats_lock);
 387         return rc;
 388 }
 389
 390 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
 391 {
 392         struct tenxpress_phy_data *pd = efx->phy_data;
 393         int phy_id = efx->mii.phy_id;
 394         bool bad_lp;
 395         int reg;
 396
 397         if (link_ok) {
 398                 bad_lp = false;
 399         } else {
 400                 /* Check that AN has started but not completed. */
 401                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 402                                          MDIO_AN_STATUS);
 403                 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
 404                         return; /* LP status is unknown */
 405                 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
 406                 if (bad_lp)
 407                         pd->bad_lp_tries++;
 408         }
 409
 410         /* Nothing to do if all is well and was previously so. */
 411         if (!pd->bad_lp_tries)
 412                 return;
 413
 414         /* Use the RX (red) LED as an error indicator once we've seen AN
 415          * failure several times in a row, and also log a message. */
 416         if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
 417                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 418                                          PMA_PMD_LED_OVERR_REG);
 419                 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
 420                 if (!bad_lp) {
 421                         reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
 422                 } else {
 423                         reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
 424                         EFX_ERR(efx, "appears to be plugged into a port"
 425                                 " that is not 10GBASE-T capable. The PHY"
 426                                 " supports 10GBASE-T ONLY, so no link can"
 427                                 " be established\n");
 428                 }
 429                 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
 430                                     PMA_PMD_LED_OVERR_REG, reg);
 431                 pd->bad_lp_tries = bad_lp;
 432         }
 433 }
 434
 435 static bool sfx7101_link_ok(struct efx_nic *efx)
 436 {
 437         return mdio_clause45_links_ok(efx,
 438                                       MDIO_MMDREG_DEVS_PMAPMD |
 439                                       MDIO_MMDREG_DEVS_PCS |
 440                                       MDIO_MMDREG_DEVS_PHYXS);
 441 }
 442
 443 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 444 {
 445         int phy_id = efx->mii.phy_id;
 446         u32 reg;
 447
 448         if (efx_phy_mode_disabled(efx->phy_mode))
 449                 return false;
 450         else if (efx->loopback_mode == LOOPBACK_GPHY)
 451                 return true;
 452         else if (efx->loopback_mode)
 453                 return mdio_clause45_links_ok(efx,
 454                                               MDIO_MMDREG_DEVS_PMAPMD |
 455                                               MDIO_MMDREG_DEVS_PHYXS);
 456
 457         /* We must use the same definition of link state as LASI,
 458          * otherwise we can miss a link state transition
 459          */
 460         if (ecmd->speed == 10000) {
 461                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
 462                                          PCS_10GBASET_STAT1);
 463                 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
 464         } else {
 465                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
 466                                          C22EXT_STATUS_REG);
 467                 return reg & (1 << C22EXT_STATUS_LINK_LBN);
 468         }
 469 }
 470
 471 static void tenxpress_ext_loopback(struct efx_nic *efx)
 472 {
 473         int phy_id = efx->mii.phy_id;
 474
 475         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
 476                                PHYXS_TEST1, LOOPBACK_NEAR_LBN,
 477                                efx->loopback_mode == LOOPBACK_PHYXS);
 478         if (efx->phy_type != PHY_TYPE_SFX7101)
 479                 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
 480                                        GPHY_XCONTROL_REG,
 481                                        GPHY_LOOPBACK_NEAR_LBN,
 482                                        efx->loopback_mode == LOOPBACK_GPHY);
 483 }
 484
 485 static void tenxpress_low_power(struct efx_nic *efx)
 486 {
 487         int phy_id = efx->mii.phy_id;
 488
 489         if (efx->phy_type == PHY_TYPE_SFX7101)
 490                 mdio_clause45_set_mmds_lpower(
 491                         efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
 492                         TENXPRESS_REQUIRED_DEVS);
 493         else
 494                 mdio_clause45_set_flag(
 495                         efx, phy_id, MDIO_MMD_PMAPMD,
 496                         PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
 497                         !!(efx->phy_mode & PHY_MODE_LOW_POWER));
 498 }
 499
 500 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
 501 {
 502         struct tenxpress_phy_data *phy_data = efx->phy_data;
 503         struct ethtool_cmd ecmd;
 504         bool phy_mode_change, loop_reset, loop_toggle, loopback;
 505
 506         if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
 507                 phy_data->phy_mode = efx->phy_mode;
 508                 return;
 509         }
 510
 511         tenxpress_low_power(efx);
 512
 513         phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
 514                            phy_data->phy_mode != PHY_MODE_NORMAL);
 515         loopback = LOOPBACK_MASK(efx) & efx->phy_op->loopbacks;
 516         loop_toggle = LOOPBACK_CHANGED(phy_data, efx, efx->phy_op->loopbacks);
 517         loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
 518                       LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
 519
 520         if (loop_reset || loop_toggle || loopback || phy_mode_change) {
 521                 int rc;
 522
 523                 efx->phy_op->get_settings(efx, &ecmd);
 524
 525                 if (loop_reset || phy_mode_change) {
 526                         tenxpress_special_reset(efx);
 527
 528                         /* Reset XAUI if we were in 10G, and are staying
 529                          * in 10G. If we're moving into and out of 10G
 530                          * then xaui will be reset anyway */
 531                         if (EFX_IS10G(efx))
 532                                 falcon_reset_xaui(efx);
 533                 }
 534
 535                 if (efx->phy_type != PHY_TYPE_SFX7101) {
 536                         /* Only change autoneg once, on coming out or
 537                          * going into loopback */
 538                         if (loop_toggle)
 539                                 ecmd.autoneg = !loopback;
 540                         if (loopback) {
 541                                 ecmd.duplex = DUPLEX_FULL;
 542                                 if (efx->loopback_mode == LOOPBACK_GPHY)
 543                                         ecmd.speed = SPEED_1000;
 544                                 else
 545                                         ecmd.speed = SPEED_10000;
 546                         }
 547                 }
 548
 549                 rc = efx->phy_op->set_settings(efx, &ecmd);
 550                 WARN_ON(rc);
 551         }
 552
 553         mdio_clause45_transmit_disable(efx);
 554         mdio_clause45_phy_reconfigure(efx);
 555         tenxpress_ext_loopback(efx);
 556
 557         phy_data->loopback_mode = efx->loopback_mode;
 558         phy_data->phy_mode = efx->phy_mode;
 559
 560         if (efx->phy_type == PHY_TYPE_SFX7101) {
 561                 efx->link_speed = 10000;
 562                 efx->link_fd = true;
 563                 efx->link_up = sfx7101_link_ok(efx);
 564         } else {
 565                 efx->phy_op->get_settings(efx, &ecmd);
 566                 efx->link_speed = ecmd.speed;
 567                 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
 568                 efx->link_up = sft9001_link_ok(efx, &ecmd);
 569         }
 570         efx->link_fc = mdio_clause45_get_pause(efx);
 571 }
 572
 573 /* Poll PHY for interrupt */
 574 static void tenxpress_phy_poll(struct efx_nic *efx)
 575 {
 576         struct tenxpress_phy_data *phy_data = efx->phy_data;
 577         bool change = false, link_ok;
 578         unsigned link_fc;
 579
 580         if (efx->phy_type == PHY_TYPE_SFX7101) {
 581                 link_ok = sfx7101_link_ok(efx);
 582                 if (link_ok != efx->link_up) {
 583                         change = true;
 584                 } else {
 585                         link_fc = mdio_clause45_get_pause(efx);
 586                         if (link_fc != efx->link_fc)
 587                                 change = true;
 588                 }
 589                 sfx7101_check_bad_lp(efx, link_ok);
 590         } else if (efx->loopback_mode) {
 591                 bool link_ok = sft9001_link_ok(efx, NULL);
 592                 if (link_ok != efx->link_up)
 593                         change = true;
 594         } else {
 595                 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
 596                                                 MDIO_MMD_PMAPMD,
 597                                                 PMA_PMD_LASI_STATUS);
 598                 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
 599                         change = true;
 600         }
 601
 602         if (change)
 603                 falcon_sim_phy_event(efx);
 604
 605         if (phy_data->phy_mode != PHY_MODE_NORMAL)
 606                 return;
 607
 608         if (EFX_WORKAROUND_10750(efx) &&
 609             atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
 610                 EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
 611                 falcon_reset_xaui(efx);
 612                 atomic_set(&phy_data->bad_crc_count, 0);
 613         }
 614 }
 615
 616 static void tenxpress_phy_fini(struct efx_nic *efx)
 617 {
 618         int reg;
 619
 620         if (efx->phy_type == PHY_TYPE_SFT9001B) {
 621                 device_remove_file(&efx->pci_dev->dev,
 622                                    &dev_attr_phy_short_reach);
 623         } else {
 624                 /* Power down the LNPGA */
 625                 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
 626                 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 627                                     PMA_PMD_XCONTROL_REG, reg);
 628
 629                 /* Waiting here ensures that the board fini, which can turn
 630                  * off the power to the PHY, won't get run until the LNPGA
 631                  * powerdown has been given long enough to complete. */
 632                 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
 633         }
 634
 635         kfree(efx->phy_data);
 636         efx->phy_data = NULL;
 637 }
 638
 639
 640 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
 641  * (which probably aren't wired anyway) are left in AUTO mode */
 642 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
 643 {
 644         int reg;
 645
 646         if (blink)
 647                 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
 648                         (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
 649                         (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
 650         else
 651                 reg = PMA_PMD_LED_DEFAULT;
 652
 653         mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 654                             PMA_PMD_LED_OVERR_REG, reg);
 655 }
 656
 657 static int tenxpress_phy_test(struct efx_nic *efx)
 658 {
 659         /* BIST is automatically run after a special software reset */
 660         return tenxpress_special_reset(efx);
 661 }
 662
 663 static u32 tenxpress_get_xnp_lpa(struct efx_nic *efx)
 664 {
 665         int phy = efx->mii.phy_id;
 666         u32 lpa = 0;
 667         int reg;
 668
 669         if (efx->phy_type != PHY_TYPE_SFX7101) {
 670                 reg = mdio_clause45_read(efx, phy, MDIO_MMD_C22EXT,
 671                                          C22EXT_MSTSLV_REG);
 672                 if (reg & (1 << C22EXT_MSTSLV_1000_HD_LBN))
 673                         lpa |= ADVERTISED_1000baseT_Half;
 674                 if (reg & (1 << C22EXT_MSTSLV_1000_FD_LBN))
 675                         lpa |= ADVERTISED_1000baseT_Full;
 676         }
 677         reg = mdio_clause45_read(efx, phy, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS);
 678         if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
 679                 lpa |= ADVERTISED_10000baseT_Full;
 680         return lpa;
 681 }
 682
 683 static void sfx7101_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 684 {
 685         mdio_clause45_get_settings_ext(efx, ecmd, ADVERTISED_10000baseT_Full,
 686                                        tenxpress_get_xnp_lpa(efx));
 687         ecmd->supported |= SUPPORTED_10000baseT_Full;
 688         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 689 }
 690
 691 static void sft9001_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 692 {
 693         int phy_id = efx->mii.phy_id;
 694         u32 xnp_adv = 0;
 695         int reg;
 696
 697         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 698                                  PMA_PMD_SPEED_ENABLE_REG);
 699         if (EFX_WORKAROUND_13204(efx) && (reg & (1 << PMA_PMD_100TX_ADV_LBN)))
 700                 xnp_adv |= ADVERTISED_100baseT_Full;
 701         if (reg & (1 << PMA_PMD_1000T_ADV_LBN))
 702                 xnp_adv |= ADVERTISED_1000baseT_Full;
 703         if (reg & (1 << PMA_PMD_10000T_ADV_LBN))
 704                 xnp_adv |= ADVERTISED_10000baseT_Full;
 705
 706         mdio_clause45_get_settings_ext(efx, ecmd, xnp_adv,
 707                                        tenxpress_get_xnp_lpa(efx));
 708
 709         ecmd->supported |= (SUPPORTED_100baseT_Half |
 710                             SUPPORTED_100baseT_Full |
 711                             SUPPORTED_1000baseT_Full);
 712
 713         /* Use the vendor defined C22ext register for duplex settings */
 714         if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) {
 715                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
 716                                          GPHY_XCONTROL_REG);
 717                 ecmd->duplex = (reg & (1 << GPHY_DUPLEX_LBN) ?
 718                                 DUPLEX_FULL : DUPLEX_HALF);
 719         }
 720 }
 721
 722 static int sft9001_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 723 {
 724         int phy_id = efx->mii.phy_id;
 725         int rc;
 726
 727         rc = mdio_clause45_set_settings(efx, ecmd);
 728         if (rc)
 729                 return rc;
 730
 731         if (ecmd->speed != SPEED_10000 && !ecmd->autoneg)
 732                 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
 733                                        GPHY_XCONTROL_REG, GPHY_DUPLEX_LBN,
 734                                        ecmd->duplex == DUPLEX_FULL);
 735
 736         return rc;
 737 }
 738
 739 static bool sft9001_set_xnp_advertise(struct efx_nic *efx, u32 advertising)
 740 {
 741         int phy = efx->mii.phy_id;
 742         int reg = mdio_clause45_read(efx, phy, MDIO_MMD_PMAPMD,
 743                                      PMA_PMD_SPEED_ENABLE_REG);
 744         bool enabled;
 745
 746         reg &= ~((1 << 2) | (1 << 3));
 747         if (EFX_WORKAROUND_13204(efx) &&
 748             (advertising & ADVERTISED_100baseT_Full))
 749                 reg |= 1 << PMA_PMD_100TX_ADV_LBN;
 750         if (advertising & ADVERTISED_1000baseT_Full)
 751                 reg |= 1 << PMA_PMD_1000T_ADV_LBN;
 752         if (advertising & ADVERTISED_10000baseT_Full)
 753                 reg |= 1 << PMA_PMD_10000T_ADV_LBN;
 754         mdio_clause45_write(efx, phy, MDIO_MMD_PMAPMD,
 755                             PMA_PMD_SPEED_ENABLE_REG, reg);
 756
 757         enabled = (advertising &
 758                    (ADVERTISED_1000baseT_Half |
 759                     ADVERTISED_1000baseT_Full |
 760                     ADVERTISED_10000baseT_Full));
 761         if (EFX_WORKAROUND_13204(efx))
 762                 enabled |= (advertising & ADVERTISED_100baseT_Full);
 763         return enabled;
 764 }
 765
 766 struct efx_phy_operations falcon_sfx7101_phy_ops = {
 767         .macs             = EFX_XMAC,
 768         .init             = tenxpress_phy_init,
 769         .reconfigure      = tenxpress_phy_reconfigure,
 770         .poll             = tenxpress_phy_poll,
 771         .fini             = tenxpress_phy_fini,
 772         .clear_interrupt  = efx_port_dummy_op_void,
 773         .test             = tenxpress_phy_test,
 774         .get_settings     = sfx7101_get_settings,
 775         .set_settings     = mdio_clause45_set_settings,
 776         .mmds             = TENXPRESS_REQUIRED_DEVS,
 777         .loopbacks        = SFX7101_LOOPBACKS,
 778 };
 779
 780 struct efx_phy_operations falcon_sft9001_phy_ops = {
 781         .macs             = EFX_GMAC | EFX_XMAC,
 782         .init             = tenxpress_phy_init,
 783         .reconfigure      = tenxpress_phy_reconfigure,
 784         .poll             = tenxpress_phy_poll,
 785         .fini             = tenxpress_phy_fini,
 786         .clear_interrupt  = efx_port_dummy_op_void,
 787         .test             = tenxpress_phy_test,
 788         .get_settings     = sft9001_get_settings,
 789         .set_settings     = sft9001_set_settings,
 790         .set_xnp_advertise = sft9001_set_xnp_advertise,
 791         .mmds             = TENXPRESS_REQUIRED_DEVS,
 792         .loopbacks        = SFT9001_LOOPBACKS,
 793 };