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KVM: use proper hrtimer function to retrieve expiration time
[linux-2.6/verdex.git] / arch / x86 / kvm / lapic.c
blob9a65123b798e7ec9c7111f01b610c5e9bd3e2afb
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
30 #include <asm/msr.h>
31 #include <asm/page.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
36 #include "irq.h"
37
38 #ifndef CONFIG_X86_64
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40 #else
41 #define mod_64(x, y) ((x) % (y))
42 #endif
43
44 #define PRId64 "d"
45 #define PRIx64 "llx"
46 #define PRIu64 "u"
47 #define PRIo64 "o"
48
49 #define APIC_BUS_CYCLE_NS 1
50
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
53
54 #define APIC_LVT_NUM 6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
63
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
66
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
68 {
69 return *((u32 *) (apic->regs + reg_off));
70 }
71
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
73 {
74 *((u32 *) (apic->regs + reg_off)) = val;
75 }
76
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
78 {
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
80 }
81
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
83 {
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85 }
86
87 static inline void apic_set_vector(int vec, void *bitmap)
88 {
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90 }
91
92 static inline void apic_clear_vector(int vec, void *bitmap)
93 {
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95 }
96
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
98 {
99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
100 }
101
102 static inline int apic_sw_enabled(struct kvm_lapic *apic)
103 {
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
105 }
106
107 static inline int apic_enabled(struct kvm_lapic *apic)
108 {
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
110 }
111
112 #define LVT_MASK \
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
114
115 #define LINT_MASK \
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
118
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
120 {
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
122 }
123
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
125 {
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
127 }
128
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
130 {
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
132 }
133
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
135 {
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
137 }
138
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
140 {
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
142 }
143
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
150 };
151
152 static int find_highest_vector(void *bitmap)
153 {
154 u32 *word = bitmap;
155 int word_offset = MAX_APIC_VECTOR >> 5;
156
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
158 continue;
159
160 if (likely(!word_offset && !word[0]))
161 return -1;
162 else
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
164 }
165
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
167 {
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
169 }
170
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
172 {
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
174 }
175
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
177 {
178 int result;
179
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
182
183 return result;
184 }
185
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
187 {
188 struct kvm_lapic *apic = vcpu->arch.apic;
189 int highest_irr;
190
191 if (!apic)
192 return 0;
193 highest_irr = apic_find_highest_irr(apic);
194
195 return highest_irr;
196 }
197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
198
199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
200 int vector, int level, int trig_mode);
201
202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
203 {
204 struct kvm_lapic *apic = vcpu->arch.apic;
205
206 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
207 irq->level, irq->trig_mode);
208 }
209
210 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
211 {
212 int result;
213
214 result = find_highest_vector(apic->regs + APIC_ISR);
215 ASSERT(result == -1 || result >= 16);
216
217 return result;
218 }
219
220 static void apic_update_ppr(struct kvm_lapic *apic)
221 {
222 u32 tpr, isrv, ppr;
223 int isr;
224
225 tpr = apic_get_reg(apic, APIC_TASKPRI);
226 isr = apic_find_highest_isr(apic);
227 isrv = (isr != -1) ? isr : 0;
228
229 if ((tpr & 0xf0) >= (isrv & 0xf0))
230 ppr = tpr & 0xff;
231 else
232 ppr = isrv & 0xf0;
233
234 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
235 apic, ppr, isr, isrv);
236
237 apic_set_reg(apic, APIC_PROCPRI, ppr);
238 }
239
240 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
241 {
242 apic_set_reg(apic, APIC_TASKPRI, tpr);
243 apic_update_ppr(apic);
244 }
245
246 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
247 {
248 return dest == 0xff || kvm_apic_id(apic) == dest;
249 }
250
251 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
252 {
253 int result = 0;
254 u8 logical_id;
255
256 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
257
258 switch (apic_get_reg(apic, APIC_DFR)) {
259 case APIC_DFR_FLAT:
260 if (logical_id & mda)
261 result = 1;
262 break;
263 case APIC_DFR_CLUSTER:
264 if (((logical_id >> 4) == (mda >> 0x4))
265 && (logical_id & mda & 0xf))
266 result = 1;
267 break;
268 default:
269 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
270 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
271 break;
272 }
273
274 return result;
275 }
276
277 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
278 int short_hand, int dest, int dest_mode)
279 {
280 int result = 0;
281 struct kvm_lapic *target = vcpu->arch.apic;
282
283 apic_debug("target %p, source %p, dest 0x%x, "
284 "dest_mode 0x%x, short_hand 0x%x\n",
285 target, source, dest, dest_mode, short_hand);
286
287 ASSERT(!target);
288 switch (short_hand) {
289 case APIC_DEST_NOSHORT:
290 if (dest_mode == 0)
291 /* Physical mode. */
292 result = kvm_apic_match_physical_addr(target, dest);
293 else
294 /* Logical mode. */
295 result = kvm_apic_match_logical_addr(target, dest);
296 break;
297 case APIC_DEST_SELF:
298 result = (target == source);
299 break;
300 case APIC_DEST_ALLINC:
301 result = 1;
302 break;
303 case APIC_DEST_ALLBUT:
304 result = (target != source);
305 break;
306 default:
307 printk(KERN_WARNING "Bad dest shorthand value %x\n",
308 short_hand);
309 break;
310 }
311
312 return result;
313 }
314
315 /*
316 * Add a pending IRQ into lapic.
317 * Return 1 if successfully added and 0 if discarded.
318 */
319 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
320 int vector, int level, int trig_mode)
321 {
322 int result = 0;
323 struct kvm_vcpu *vcpu = apic->vcpu;
324
325 switch (delivery_mode) {
326 case APIC_DM_LOWEST:
327 vcpu->arch.apic_arb_prio++;
328 case APIC_DM_FIXED:
329 /* FIXME add logic for vcpu on reset */
330 if (unlikely(!apic_enabled(apic)))
331 break;
332
333 result = !apic_test_and_set_irr(vector, apic);
334 if (!result) {
335 if (trig_mode)
336 apic_debug("level trig mode repeatedly for "
337 "vector %d", vector);
338 break;
339 }
340
341 if (trig_mode) {
342 apic_debug("level trig mode for vector %d", vector);
343 apic_set_vector(vector, apic->regs + APIC_TMR);
344 } else
345 apic_clear_vector(vector, apic->regs + APIC_TMR);
346 kvm_vcpu_kick(vcpu);
347 break;
348
349 case APIC_DM_REMRD:
350 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
351 break;
352
353 case APIC_DM_SMI:
354 printk(KERN_DEBUG "Ignoring guest SMI\n");
355 break;
356
357 case APIC_DM_NMI:
358 result = 1;
359 kvm_inject_nmi(vcpu);
360 kvm_vcpu_kick(vcpu);
361 break;
362
363 case APIC_DM_INIT:
364 if (level) {
365 result = 1;
366 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
367 printk(KERN_DEBUG
368 "INIT on a runnable vcpu %d\n",
369 vcpu->vcpu_id);
370 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
371 kvm_vcpu_kick(vcpu);
372 } else {
373 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
374 vcpu->vcpu_id);
375 }
376 break;
377
378 case APIC_DM_STARTUP:
379 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
380 vcpu->vcpu_id, vector);
381 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
382 result = 1;
383 vcpu->arch.sipi_vector = vector;
384 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
385 kvm_vcpu_kick(vcpu);
386 }
387 break;
388
389 case APIC_DM_EXTINT:
390 /*
391 * Should only be called by kvm_apic_local_deliver() with LVT0,
392 * before NMI watchdog was enabled. Already handled by
393 * kvm_apic_accept_pic_intr().
394 */
395 break;
396
397 default:
398 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
399 delivery_mode);
400 break;
401 }
402 return result;
403 }
404
405 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
406 {
407 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
408 }
409
410 static void apic_set_eoi(struct kvm_lapic *apic)
411 {
412 int vector = apic_find_highest_isr(apic);
413 int trigger_mode;
414 /*
415 * Not every write EOI will has corresponding ISR,
416 * one example is when Kernel check timer on setup_IO_APIC
417 */
418 if (vector == -1)
419 return;
420
421 apic_clear_vector(vector, apic->regs + APIC_ISR);
422 apic_update_ppr(apic);
423
424 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
425 trigger_mode = IOAPIC_LEVEL_TRIG;
426 else
427 trigger_mode = IOAPIC_EDGE_TRIG;
428 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
429 }
430
431 static void apic_send_ipi(struct kvm_lapic *apic)
432 {
433 u32 icr_low = apic_get_reg(apic, APIC_ICR);
434 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
435 struct kvm_lapic_irq irq;
436
437 irq.vector = icr_low & APIC_VECTOR_MASK;
438 irq.delivery_mode = icr_low & APIC_MODE_MASK;
439 irq.dest_mode = icr_low & APIC_DEST_MASK;
440 irq.level = icr_low & APIC_INT_ASSERT;
441 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
442 irq.shorthand = icr_low & APIC_SHORT_MASK;
443 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
444
445 apic_debug("icr_high 0x%x, icr_low 0x%x, "
446 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
447 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
448 icr_high, icr_low, irq.shorthand, irq.dest_id,
449 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
450 irq.vector);
451
452 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
453 }
454
455 static u32 apic_get_tmcct(struct kvm_lapic *apic)
456 {
457 ktime_t remaining;
458 s64 ns;
459 u32 tmcct;
460
461 ASSERT(apic != NULL);
462
463 /* if initial count is 0, current count should also be 0 */
464 if (apic_get_reg(apic, APIC_TMICT) == 0)
465 return 0;
466
467 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
468 if (ktime_to_ns(remaining) < 0)
469 remaining = ktime_set(0, 0);
470
471 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
472 tmcct = div64_u64(ns,
473 (APIC_BUS_CYCLE_NS * apic->divide_count));
474
475 return tmcct;
476 }
477
478 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
479 {
480 struct kvm_vcpu *vcpu = apic->vcpu;
481 struct kvm_run *run = vcpu->run;
482
483 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
484 run->tpr_access.rip = kvm_rip_read(vcpu);
485 run->tpr_access.is_write = write;
486 }
487
488 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
489 {
490 if (apic->vcpu->arch.tpr_access_reporting)
491 __report_tpr_access(apic, write);
492 }
493
494 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
495 {
496 u32 val = 0;
497
498 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
499
500 if (offset >= LAPIC_MMIO_LENGTH)
501 return 0;
502
503 switch (offset) {
504 case APIC_ARBPRI:
505 printk(KERN_WARNING "Access APIC ARBPRI register "
506 "which is for P6\n");
507 break;
508
509 case APIC_TMCCT: /* Timer CCR */
510 val = apic_get_tmcct(apic);
511 break;
512
513 case APIC_TASKPRI:
514 report_tpr_access(apic, false);
515 /* fall thru */
516 default:
517 apic_update_ppr(apic);
518 val = apic_get_reg(apic, offset);
519 break;
520 }
521
522 return val;
523 }
524
525 static void apic_mmio_read(struct kvm_io_device *this,
526 gpa_t address, int len, void *data)
527 {
528 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
529 unsigned int offset = address - apic->base_address;
530 unsigned char alignment = offset & 0xf;
531 u32 result;
532
533 if ((alignment + len) > 4) {
534 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
535 (unsigned long)address, len);
536 return;
537 }
538 result = __apic_read(apic, offset & ~0xf);
539
540 switch (len) {
541 case 1:
542 case 2:
543 case 4:
544 memcpy(data, (char *)&result + alignment, len);
545 break;
546 default:
547 printk(KERN_ERR "Local APIC read with len = %x, "
548 "should be 1,2, or 4 instead\n", len);
549 break;
550 }
551 }
552
553 static void update_divide_count(struct kvm_lapic *apic)
554 {
555 u32 tmp1, tmp2, tdcr;
556
557 tdcr = apic_get_reg(apic, APIC_TDCR);
558 tmp1 = tdcr & 0xf;
559 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
560 apic->divide_count = 0x1 << (tmp2 & 0x7);
561
562 apic_debug("timer divide count is 0x%x\n",
563 apic->divide_count);
564 }
565
566 static void start_apic_timer(struct kvm_lapic *apic)
567 {
568 ktime_t now = apic->lapic_timer.timer.base->get_time();
569
570 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
571 APIC_BUS_CYCLE_NS * apic->divide_count;
572 atomic_set(&apic->lapic_timer.pending, 0);
573
574 if (!apic->lapic_timer.period)
575 return;
576 /*
577 * Do not allow the guest to program periodic timers with small
578 * interval, since the hrtimers are not throttled by the host
579 * scheduler.
580 */
581 if (apic_lvtt_period(apic)) {
582 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
583 apic->lapic_timer.period = NSEC_PER_MSEC/2;
584 }
585
586 hrtimer_start(&apic->lapic_timer.timer,
587 ktime_add_ns(now, apic->lapic_timer.period),
588 HRTIMER_MODE_ABS);
589
590 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
591 PRIx64 ", "
592 "timer initial count 0x%x, period %lldns, "
593 "expire @ 0x%016" PRIx64 ".\n", __func__,
594 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
595 apic_get_reg(apic, APIC_TMICT),
596 apic->lapic_timer.period,
597 ktime_to_ns(ktime_add_ns(now,
598 apic->lapic_timer.period)));
599 }
600
601 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
602 {
603 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
604
605 if (apic_lvt_nmi_mode(lvt0_val)) {
606 if (!nmi_wd_enabled) {
607 apic_debug("Receive NMI setting on APIC_LVT0 "
608 "for cpu %d\n", apic->vcpu->vcpu_id);
609 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
610 }
611 } else if (nmi_wd_enabled)
612 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
613 }
614
615 static void apic_mmio_write(struct kvm_io_device *this,
616 gpa_t address, int len, const void *data)
617 {
618 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
619 unsigned int offset = address - apic->base_address;
620 unsigned char alignment = offset & 0xf;
621 u32 val;
622
623 /*
624 * APIC register must be aligned on 128-bits boundary.
625 * 32/64/128 bits registers must be accessed thru 32 bits.
626 * Refer SDM 8.4.1
627 */
628 if (len != 4 || alignment) {
629 /* Don't shout loud, $infamous_os would cause only noise. */
630 apic_debug("apic write: bad size=%d %lx\n",
631 len, (long)address);
632 return;
633 }
634
635 val = *(u32 *) data;
636
637 /* too common printing */
638 if (offset != APIC_EOI)
639 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
640 "0x%x\n", __func__, offset, len, val);
641
642 offset &= 0xff0;
643
644 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
645
646 switch (offset) {
647 case APIC_ID: /* Local APIC ID */
648 apic_set_reg(apic, APIC_ID, val);
649 break;
650
651 case APIC_TASKPRI:
652 report_tpr_access(apic, true);
653 apic_set_tpr(apic, val & 0xff);
654 break;
655
656 case APIC_EOI:
657 apic_set_eoi(apic);
658 break;
659
660 case APIC_LDR:
661 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
662 break;
663
664 case APIC_DFR:
665 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
666 break;
667
668 case APIC_SPIV:
669 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
670 if (!(val & APIC_SPIV_APIC_ENABLED)) {
671 int i;
672 u32 lvt_val;
673
674 for (i = 0; i < APIC_LVT_NUM; i++) {
675 lvt_val = apic_get_reg(apic,
676 APIC_LVTT + 0x10 * i);
677 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
678 lvt_val | APIC_LVT_MASKED);
679 }
680 atomic_set(&apic->lapic_timer.pending, 0);
681
682 }
683 break;
684
685 case APIC_ICR:
686 /* No delay here, so we always clear the pending bit */
687 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
688 apic_send_ipi(apic);
689 break;
690
691 case APIC_ICR2:
692 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
693 break;
694
695 case APIC_LVT0:
696 apic_manage_nmi_watchdog(apic, val);
697 case APIC_LVTT:
698 case APIC_LVTTHMR:
699 case APIC_LVTPC:
700 case APIC_LVT1:
701 case APIC_LVTERR:
702 /* TODO: Check vector */
703 if (!apic_sw_enabled(apic))
704 val |= APIC_LVT_MASKED;
705
706 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
707 apic_set_reg(apic, offset, val);
708
709 break;
710
711 case APIC_TMICT:
712 hrtimer_cancel(&apic->lapic_timer.timer);
713 apic_set_reg(apic, APIC_TMICT, val);
714 start_apic_timer(apic);
715 return;
716
717 case APIC_TDCR:
718 if (val & 4)
719 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
720 apic_set_reg(apic, APIC_TDCR, val);
721 update_divide_count(apic);
722 break;
723
724 default:
725 apic_debug("Local APIC Write to read-only register %x\n",
726 offset);
727 break;
728 }
729
730 }
731
732 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
733 int len, int size)
734 {
735 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
736 int ret = 0;
737
738
739 if (apic_hw_enabled(apic) &&
740 (addr >= apic->base_address) &&
741 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
742 ret = 1;
743
744 return ret;
745 }
746
747 void kvm_free_lapic(struct kvm_vcpu *vcpu)
748 {
749 if (!vcpu->arch.apic)
750 return;
751
752 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
753
754 if (vcpu->arch.apic->regs_page)
755 __free_page(vcpu->arch.apic->regs_page);
756
757 kfree(vcpu->arch.apic);
758 }
759
760 /*
761 *----------------------------------------------------------------------
762 * LAPIC interface
763 *----------------------------------------------------------------------
764 */
765
766 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
767 {
768 struct kvm_lapic *apic = vcpu->arch.apic;
769
770 if (!apic)
771 return;
772 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
773 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
774 }
775 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
776
777 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
778 {
779 struct kvm_lapic *apic = vcpu->arch.apic;
780 u64 tpr;
781
782 if (!apic)
783 return 0;
784 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
785
786 return (tpr & 0xf0) >> 4;
787 }
788 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
789
790 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
791 {
792 struct kvm_lapic *apic = vcpu->arch.apic;
793
794 if (!apic) {
795 value |= MSR_IA32_APICBASE_BSP;
796 vcpu->arch.apic_base = value;
797 return;
798 }
799 if (apic->vcpu->vcpu_id)
800 value &= ~MSR_IA32_APICBASE_BSP;
801
802 vcpu->arch.apic_base = value;
803 apic->base_address = apic->vcpu->arch.apic_base &
804 MSR_IA32_APICBASE_BASE;
805
806 /* with FSB delivery interrupt, we can restart APIC functionality */
807 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
808 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
809
810 }
811
812 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
813 {
814 return vcpu->arch.apic_base;
815 }
816 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
817
818 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
819 {
820 struct kvm_lapic *apic;
821 int i;
822
823 apic_debug("%s\n", __func__);
824
825 ASSERT(vcpu);
826 apic = vcpu->arch.apic;
827 ASSERT(apic != NULL);
828
829 /* Stop the timer in case it's a reset to an active apic */
830 hrtimer_cancel(&apic->lapic_timer.timer);
831
832 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
833 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
834
835 for (i = 0; i < APIC_LVT_NUM; i++)
836 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
837 apic_set_reg(apic, APIC_LVT0,
838 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
839
840 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
841 apic_set_reg(apic, APIC_SPIV, 0xff);
842 apic_set_reg(apic, APIC_TASKPRI, 0);
843 apic_set_reg(apic, APIC_LDR, 0);
844 apic_set_reg(apic, APIC_ESR, 0);
845 apic_set_reg(apic, APIC_ICR, 0);
846 apic_set_reg(apic, APIC_ICR2, 0);
847 apic_set_reg(apic, APIC_TDCR, 0);
848 apic_set_reg(apic, APIC_TMICT, 0);
849 for (i = 0; i < 8; i++) {
850 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
851 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
852 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
853 }
854 update_divide_count(apic);
855 atomic_set(&apic->lapic_timer.pending, 0);
856 if (vcpu->vcpu_id == 0)
857 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
858 apic_update_ppr(apic);
859
860 vcpu->arch.apic_arb_prio = 0;
861
862 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
863 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
864 vcpu, kvm_apic_id(apic),
865 vcpu->arch.apic_base, apic->base_address);
866 }
867 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
868
869 bool kvm_apic_present(struct kvm_vcpu *vcpu)
870 {
871 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
872 }
873
874 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
875 {
876 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
877 }
878 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
879
880 /*
881 *----------------------------------------------------------------------
882 * timer interface
883 *----------------------------------------------------------------------
884 */
885
886 static bool lapic_is_periodic(struct kvm_timer *ktimer)
887 {
888 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
889 lapic_timer);
890 return apic_lvtt_period(apic);
891 }
892
893 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
894 {
895 struct kvm_lapic *lapic = vcpu->arch.apic;
896
897 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
898 return atomic_read(&lapic->lapic_timer.pending);
899
900 return 0;
901 }
902
903 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
904 {
905 u32 reg = apic_get_reg(apic, lvt_type);
906 int vector, mode, trig_mode;
907
908 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
909 vector = reg & APIC_VECTOR_MASK;
910 mode = reg & APIC_MODE_MASK;
911 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
912 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
913 }
914 return 0;
915 }
916
917 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
918 {
919 struct kvm_lapic *apic = vcpu->arch.apic;
920
921 if (apic)
922 kvm_apic_local_deliver(apic, APIC_LVT0);
923 }
924
925 static struct kvm_timer_ops lapic_timer_ops = {
926 .is_periodic = lapic_is_periodic,
927 };
928
929 int kvm_create_lapic(struct kvm_vcpu *vcpu)
930 {
931 struct kvm_lapic *apic;
932
933 ASSERT(vcpu != NULL);
934 apic_debug("apic_init %d\n", vcpu->vcpu_id);
935
936 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
937 if (!apic)
938 goto nomem;
939
940 vcpu->arch.apic = apic;
941
942 apic->regs_page = alloc_page(GFP_KERNEL);
943 if (apic->regs_page == NULL) {
944 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
945 vcpu->vcpu_id);
946 goto nomem_free_apic;
947 }
948 apic->regs = page_address(apic->regs_page);
949 memset(apic->regs, 0, PAGE_SIZE);
950 apic->vcpu = vcpu;
951
952 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
953 HRTIMER_MODE_ABS);
954 apic->lapic_timer.timer.function = kvm_timer_fn;
955 apic->lapic_timer.t_ops = &lapic_timer_ops;
956 apic->lapic_timer.kvm = vcpu->kvm;
957 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
958
959 apic->base_address = APIC_DEFAULT_PHYS_BASE;
960 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
961
962 kvm_lapic_reset(vcpu);
963 apic->dev.read = apic_mmio_read;
964 apic->dev.write = apic_mmio_write;
965 apic->dev.in_range = apic_mmio_range;
966 apic->dev.private = apic;
967
968 return 0;
969 nomem_free_apic:
970 kfree(apic);
971 nomem:
972 return -ENOMEM;
973 }
974 EXPORT_SYMBOL_GPL(kvm_create_lapic);
975
976 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
977 {
978 struct kvm_lapic *apic = vcpu->arch.apic;
979 int highest_irr;
980
981 if (!apic || !apic_enabled(apic))
982 return -1;
983
984 apic_update_ppr(apic);
985 highest_irr = apic_find_highest_irr(apic);
986 if ((highest_irr == -1) ||
987 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
988 return -1;
989 return highest_irr;
990 }
991
992 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
993 {
994 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
995 int r = 0;
996
997 if (vcpu->vcpu_id == 0) {
998 if (!apic_hw_enabled(vcpu->arch.apic))
999 r = 1;
1000 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1001 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1002 r = 1;
1003 }
1004 return r;
1005 }
1006
1007 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1008 {
1009 struct kvm_lapic *apic = vcpu->arch.apic;
1010
1011 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1012 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1013 atomic_dec(&apic->lapic_timer.pending);
1014 }
1015 }
1016
1017 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1018 {
1019 int vector = kvm_apic_has_interrupt(vcpu);
1020 struct kvm_lapic *apic = vcpu->arch.apic;
1021
1022 if (vector == -1)
1023 return -1;
1024
1025 apic_set_vector(vector, apic->regs + APIC_ISR);
1026 apic_update_ppr(apic);
1027 apic_clear_irr(vector, apic);
1028 return vector;
1029 }
1030
1031 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1032 {
1033 struct kvm_lapic *apic = vcpu->arch.apic;
1034
1035 apic->base_address = vcpu->arch.apic_base &
1036 MSR_IA32_APICBASE_BASE;
1037 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1038 apic_update_ppr(apic);
1039 hrtimer_cancel(&apic->lapic_timer.timer);
1040 update_divide_count(apic);
1041 start_apic_timer(apic);
1042 }
1043
1044 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1045 {
1046 struct kvm_lapic *apic = vcpu->arch.apic;
1047 struct hrtimer *timer;
1048
1049 if (!apic)
1050 return;
1051
1052 timer = &apic->lapic_timer.timer;
1053 if (hrtimer_cancel(timer))
1054 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1055 }
1056
1057 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1058 {
1059 u32 data;
1060 void *vapic;
1061
1062 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1063 return;
1064
1065 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1066 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1067 kunmap_atomic(vapic, KM_USER0);
1068
1069 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1070 }
1071
1072 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1073 {
1074 u32 data, tpr;
1075 int max_irr, max_isr;
1076 struct kvm_lapic *apic;
1077 void *vapic;
1078
1079 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1080 return;
1081
1082 apic = vcpu->arch.apic;
1083 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1084 max_irr = apic_find_highest_irr(apic);
1085 if (max_irr < 0)
1086 max_irr = 0;
1087 max_isr = apic_find_highest_isr(apic);
1088 if (max_isr < 0)
1089 max_isr = 0;
1090 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1091
1092 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1093 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1094 kunmap_atomic(vapic, KM_USER0);
1095 }
1096
1097 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1098 {
1099 if (!irqchip_in_kernel(vcpu->kvm))
1100 return;
1101
1102 vcpu->arch.apic->vapic_addr = vapic_addr;
1103 }
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