2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
27 #include <asm/amd_iommu_types.h>
29 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
31 #define to_pages(addr, size) \
32 (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
40 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
41 struct unity_map_entry
*e
);
43 static int iommu_has_npcache(struct amd_iommu
*iommu
)
45 return iommu
->cap
& IOMMU_CAP_NPCACHE
;
48 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct command
*cmd
)
53 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
54 target
= (iommu
->cmd_buf
+ tail
);
55 memcpy_toio(target
, cmd
, sizeof(*cmd
));
56 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
57 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
60 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
65 static int iommu_queue_command(struct amd_iommu
*iommu
, struct command
*cmd
)
70 spin_lock_irqsave(&iommu
->lock
, flags
);
71 ret
= __iommu_queue_command(iommu
, cmd
);
72 spin_unlock_irqrestore(&iommu
->lock
, flags
);
77 static int iommu_completion_wait(struct amd_iommu
*iommu
)
81 volatile u64 ready
= 0;
82 unsigned long ready_phys
= virt_to_phys(&ready
);
84 memset(&cmd
, 0, sizeof(cmd
));
85 cmd
.data
[0] = LOW_U32(ready_phys
) | CMD_COMPL_WAIT_STORE_MASK
;
86 cmd
.data
[1] = HIGH_U32(ready_phys
);
87 cmd
.data
[2] = 1; /* value written to 'ready' */
88 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
92 ret
= iommu_queue_command(iommu
, &cmd
);
103 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
107 BUG_ON(iommu
== NULL
);
109 memset(&cmd
, 0, sizeof(cmd
));
110 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
113 iommu
->need_sync
= 1;
115 return iommu_queue_command(iommu
, &cmd
);
118 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
119 u64 address
, u16 domid
, int pde
, int s
)
123 memset(&cmd
, 0, sizeof(cmd
));
124 address
&= PAGE_MASK
;
125 CMD_SET_TYPE(&cmd
, CMD_INV_IOMMU_PAGES
);
126 cmd
.data
[1] |= domid
;
127 cmd
.data
[2] = LOW_U32(address
);
128 cmd
.data
[3] = HIGH_U32(address
);
130 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
132 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
134 iommu
->need_sync
= 1;
136 return iommu_queue_command(iommu
, &cmd
);
139 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
140 u64 address
, size_t size
)
143 unsigned pages
= to_pages(address
, size
);
145 address
&= PAGE_MASK
;
147 for (i
= 0; i
< pages
; ++i
) {
148 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, 0);
149 address
+= PAGE_SIZE
;
155 static int iommu_map(struct protection_domain
*dom
,
156 unsigned long bus_addr
,
157 unsigned long phys_addr
,
160 u64 __pte
, *pte
, *page
;
162 bus_addr
= PAGE_ALIGN(bus_addr
);
163 phys_addr
= PAGE_ALIGN(bus_addr
);
165 /* only support 512GB address spaces for now */
166 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
169 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
171 if (!IOMMU_PTE_PRESENT(*pte
)) {
172 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
175 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
178 pte
= IOMMU_PTE_PAGE(*pte
);
179 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
181 if (!IOMMU_PTE_PRESENT(*pte
)) {
182 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
185 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
188 pte
= IOMMU_PTE_PAGE(*pte
);
189 pte
= &pte
[IOMMU_PTE_L0_INDEX(bus_addr
)];
191 if (IOMMU_PTE_PRESENT(*pte
))
194 __pte
= phys_addr
| IOMMU_PTE_P
;
195 if (prot
& IOMMU_PROT_IR
)
196 __pte
|= IOMMU_PTE_IR
;
197 if (prot
& IOMMU_PROT_IW
)
198 __pte
|= IOMMU_PTE_IW
;
205 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
206 struct unity_map_entry
*entry
)
210 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
211 bdf
= amd_iommu_alias_table
[i
];
212 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
219 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
221 struct unity_map_entry
*entry
;
224 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
225 if (!iommu_for_unity_map(iommu
, entry
))
227 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
235 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
236 struct unity_map_entry
*e
)
241 for (addr
= e
->address_start
; addr
< e
->address_end
;
243 ret
= iommu_map(&dma_dom
->domain
, addr
, addr
, e
->prot
);
247 * if unity mapping is in aperture range mark the page
248 * as allocated in the aperture
250 if (addr
< dma_dom
->aperture_size
)
251 __set_bit(addr
>> PAGE_SHIFT
, dma_dom
->bitmap
);
257 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
260 struct unity_map_entry
*e
;
263 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
264 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
266 ret
= dma_ops_unity_map(dma_dom
, e
);
274 static unsigned long dma_mask_to_pages(unsigned long mask
)
276 return (mask
>> PAGE_SHIFT
) +
277 (PAGE_ALIGN(mask
& ~PAGE_MASK
) >> PAGE_SHIFT
);
280 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
281 struct dma_ops_domain
*dom
,
284 unsigned long limit
= dma_mask_to_pages(*dev
->dma_mask
);
285 unsigned long address
;
286 unsigned long size
= dom
->aperture_size
>> PAGE_SHIFT
;
287 unsigned long boundary_size
;
289 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
290 PAGE_SIZE
) >> PAGE_SHIFT
;
291 limit
= limit
< size
? limit
: size
;
293 if (dom
->next_bit
>= limit
)
296 address
= iommu_area_alloc(dom
->bitmap
, limit
, dom
->next_bit
, pages
,
297 0 , boundary_size
, 0);
299 address
= iommu_area_alloc(dom
->bitmap
, limit
, 0, pages
,
300 0, boundary_size
, 0);
302 if (likely(address
!= -1)) {
303 set_bit_string(dom
->bitmap
, address
, pages
);
304 dom
->next_bit
= address
+ pages
;
305 address
<<= PAGE_SHIFT
;
307 address
= bad_dma_address
;
309 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
314 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
315 unsigned long address
,
318 address
>>= PAGE_SHIFT
;
319 iommu_area_free(dom
->bitmap
, address
, pages
);
322 static u16
domain_id_alloc(void)
327 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
328 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
330 if (id
> 0 && id
< MAX_DOMAIN_ID
)
331 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
334 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
339 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
340 unsigned long start_page
,
343 unsigned int last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
345 if (start_page
+ pages
> last_page
)
346 pages
= last_page
- start_page
;
348 set_bit_string(dom
->bitmap
, start_page
, pages
);
351 static void dma_ops_free_pagetable(struct dma_ops_domain
*dma_dom
)
356 p1
= dma_dom
->domain
.pt_root
;
361 for (i
= 0; i
< 512; ++i
) {
362 if (!IOMMU_PTE_PRESENT(p1
[i
]))
365 p2
= IOMMU_PTE_PAGE(p1
[i
]);
366 for (j
= 0; j
< 512; ++i
) {
367 if (!IOMMU_PTE_PRESENT(p2
[j
]))
369 p3
= IOMMU_PTE_PAGE(p2
[j
]);
370 free_page((unsigned long)p3
);
373 free_page((unsigned long)p2
);
376 free_page((unsigned long)p1
);
379 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
384 dma_ops_free_pagetable(dom
);
386 kfree(dom
->pte_pages
);
393 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
,
396 struct dma_ops_domain
*dma_dom
;
397 unsigned i
, num_pte_pages
;
402 * Currently the DMA aperture must be between 32 MB and 1GB in size
404 if ((order
< 25) || (order
> 30))
407 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
411 spin_lock_init(&dma_dom
->domain
.lock
);
413 dma_dom
->domain
.id
= domain_id_alloc();
414 if (dma_dom
->domain
.id
== 0)
416 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
417 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
418 dma_dom
->domain
.priv
= dma_dom
;
419 if (!dma_dom
->domain
.pt_root
)
421 dma_dom
->aperture_size
= (1ULL << order
);
422 dma_dom
->bitmap
= kzalloc(dma_dom
->aperture_size
/ (PAGE_SIZE
* 8),
424 if (!dma_dom
->bitmap
)
427 * mark the first page as allocated so we never return 0 as
428 * a valid dma-address. So we can use 0 as error value
430 dma_dom
->bitmap
[0] = 1;
431 dma_dom
->next_bit
= 0;
433 if (iommu
->exclusion_start
&&
434 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
435 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
436 int pages
= to_pages(iommu
->exclusion_start
,
437 iommu
->exclusion_length
);
438 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
441 num_pte_pages
= dma_dom
->aperture_size
/ (PAGE_SIZE
* 512);
442 dma_dom
->pte_pages
= kzalloc(num_pte_pages
* sizeof(void *),
444 if (!dma_dom
->pte_pages
)
447 l2_pde
= (u64
*)get_zeroed_page(GFP_KERNEL
);
451 dma_dom
->domain
.pt_root
[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde
));
453 for (i
= 0; i
< num_pte_pages
; ++i
) {
454 dma_dom
->pte_pages
[i
] = (u64
*)get_zeroed_page(GFP_KERNEL
);
455 if (!dma_dom
->pte_pages
[i
])
457 address
= virt_to_phys(dma_dom
->pte_pages
[i
]);
458 l2_pde
[i
] = IOMMU_L1_PDE(address
);
464 dma_ops_domain_free(dma_dom
);
469 static struct protection_domain
*domain_for_device(u16 devid
)
471 struct protection_domain
*dom
;
474 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
475 dom
= amd_iommu_pd_table
[devid
];
476 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
481 static void set_device_domain(struct amd_iommu
*iommu
,
482 struct protection_domain
*domain
,
487 u64 pte_root
= virt_to_phys(domain
->pt_root
);
489 pte_root
|= (domain
->mode
& 0x07) << 9;
490 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| 2;
492 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
493 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
494 amd_iommu_dev_table
[devid
].data
[1] = pte_root
>> 32;
495 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
497 amd_iommu_pd_table
[devid
] = domain
;
498 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
500 iommu_queue_inv_dev_entry(iommu
, devid
);
502 iommu
->need_sync
= 1;
505 static int get_device_resources(struct device
*dev
,
506 struct amd_iommu
**iommu
,
507 struct protection_domain
**domain
,
510 struct dma_ops_domain
*dma_dom
;
511 struct pci_dev
*pcidev
;
514 BUG_ON(!dev
|| dev
->bus
!= &pci_bus_type
|| !dev
->dma_mask
);
516 pcidev
= to_pci_dev(dev
);
517 _bdf
= (pcidev
->bus
->number
<< 8) | pcidev
->devfn
;
519 if (_bdf
>= amd_iommu_last_bdf
) {
526 *bdf
= amd_iommu_alias_table
[_bdf
];
528 *iommu
= amd_iommu_rlookup_table
[*bdf
];
531 dma_dom
= (*iommu
)->default_dom
;
532 *domain
= domain_for_device(*bdf
);
533 if (*domain
== NULL
) {
534 *domain
= &dma_dom
->domain
;
535 set_device_domain(*iommu
, *domain
, *bdf
);
536 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
537 "device ", (*domain
)->id
);
538 print_devid(_bdf
, 1);
544 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
545 struct dma_ops_domain
*dom
,
546 unsigned long address
,
552 WARN_ON(address
> dom
->aperture_size
);
556 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
557 pte
+= IOMMU_PTE_L0_INDEX(address
);
559 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
561 if (direction
== DMA_TO_DEVICE
)
562 __pte
|= IOMMU_PTE_IR
;
563 else if (direction
== DMA_FROM_DEVICE
)
564 __pte
|= IOMMU_PTE_IW
;
565 else if (direction
== DMA_BIDIRECTIONAL
)
566 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
572 return (dma_addr_t
)address
;
575 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
576 struct dma_ops_domain
*dom
,
577 unsigned long address
)
581 if (address
>= dom
->aperture_size
)
584 WARN_ON(address
& 0xfffULL
|| address
> dom
->aperture_size
);
586 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
587 pte
+= IOMMU_PTE_L0_INDEX(address
);
594 static dma_addr_t
__map_single(struct device
*dev
,
595 struct amd_iommu
*iommu
,
596 struct dma_ops_domain
*dma_dom
,
601 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
602 dma_addr_t address
, start
;
606 pages
= to_pages(paddr
, size
);
609 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
);
610 if (unlikely(address
== bad_dma_address
))
614 for (i
= 0; i
< pages
; ++i
) {
615 dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
625 static void __unmap_single(struct amd_iommu
*iommu
,
626 struct dma_ops_domain
*dma_dom
,
634 if ((dma_addr
== 0) || (dma_addr
+ size
> dma_dom
->aperture_size
))
637 pages
= to_pages(dma_addr
, size
);
638 dma_addr
&= PAGE_MASK
;
641 for (i
= 0; i
< pages
; ++i
) {
642 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
646 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
649 static dma_addr_t
map_single(struct device
*dev
, phys_addr_t paddr
,
650 size_t size
, int dir
)
653 struct amd_iommu
*iommu
;
654 struct protection_domain
*domain
;
658 get_device_resources(dev
, &iommu
, &domain
, &devid
);
660 if (iommu
== NULL
|| domain
== NULL
)
661 return (dma_addr_t
)paddr
;
663 spin_lock_irqsave(&domain
->lock
, flags
);
664 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
);
665 if (addr
== bad_dma_address
)
668 if (iommu_has_npcache(iommu
))
669 iommu_flush_pages(iommu
, domain
->id
, addr
, size
);
671 if (iommu
->need_sync
)
672 iommu_completion_wait(iommu
);
675 spin_unlock_irqrestore(&domain
->lock
, flags
);
680 static void unmap_single(struct device
*dev
, dma_addr_t dma_addr
,
681 size_t size
, int dir
)
684 struct amd_iommu
*iommu
;
685 struct protection_domain
*domain
;
688 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
691 spin_lock_irqsave(&domain
->lock
, flags
);
693 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
695 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
697 if (iommu
->need_sync
)
698 iommu_completion_wait(iommu
);
700 spin_unlock_irqrestore(&domain
->lock
, flags
);
703 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
706 struct scatterlist
*s
;
709 for_each_sg(sglist
, s
, nelems
, i
) {
710 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
711 s
->dma_length
= s
->length
;
717 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
721 struct amd_iommu
*iommu
;
722 struct protection_domain
*domain
;
725 struct scatterlist
*s
;
727 int mapped_elems
= 0;
729 get_device_resources(dev
, &iommu
, &domain
, &devid
);
731 if (!iommu
|| !domain
)
732 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
734 spin_lock_irqsave(&domain
->lock
, flags
);
736 for_each_sg(sglist
, s
, nelems
, i
) {
739 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
740 paddr
, s
->length
, dir
);
742 if (s
->dma_address
) {
743 s
->dma_length
= s
->length
;
747 if (iommu_has_npcache(iommu
))
748 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
752 if (iommu
->need_sync
)
753 iommu_completion_wait(iommu
);
756 spin_unlock_irqrestore(&domain
->lock
, flags
);
760 for_each_sg(sglist
, s
, mapped_elems
, i
) {
762 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
764 s
->dma_address
= s
->dma_length
= 0;
772 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
776 struct amd_iommu
*iommu
;
777 struct protection_domain
*domain
;
778 struct scatterlist
*s
;
782 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
785 spin_lock_irqsave(&domain
->lock
, flags
);
787 for_each_sg(sglist
, s
, nelems
, i
) {
788 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
790 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
792 s
->dma_address
= s
->dma_length
= 0;
795 if (iommu
->need_sync
)
796 iommu_completion_wait(iommu
);
798 spin_unlock_irqrestore(&domain
->lock
, flags
);
801 static void *alloc_coherent(struct device
*dev
, size_t size
,
802 dma_addr_t
*dma_addr
, gfp_t flag
)
806 struct amd_iommu
*iommu
;
807 struct protection_domain
*domain
;
811 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
815 memset(virt_addr
, 0, size
);
816 paddr
= virt_to_phys(virt_addr
);
818 get_device_resources(dev
, &iommu
, &domain
, &devid
);
820 if (!iommu
|| !domain
) {
821 *dma_addr
= (dma_addr_t
)paddr
;
825 spin_lock_irqsave(&domain
->lock
, flags
);
827 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
828 size
, DMA_BIDIRECTIONAL
);
830 if (*dma_addr
== bad_dma_address
) {
831 free_pages((unsigned long)virt_addr
, get_order(size
));
836 if (iommu_has_npcache(iommu
))
837 iommu_flush_pages(iommu
, domain
->id
, *dma_addr
, size
);
839 if (iommu
->need_sync
)
840 iommu_completion_wait(iommu
);
843 spin_unlock_irqrestore(&domain
->lock
, flags
);
848 static void free_coherent(struct device
*dev
, size_t size
,
849 void *virt_addr
, dma_addr_t dma_addr
)
852 struct amd_iommu
*iommu
;
853 struct protection_domain
*domain
;
856 get_device_resources(dev
, &iommu
, &domain
, &devid
);
858 if (!iommu
|| !domain
)
861 spin_lock_irqsave(&domain
->lock
, flags
);
863 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
864 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
866 if (iommu
->need_sync
)
867 iommu_completion_wait(iommu
);
869 spin_unlock_irqrestore(&domain
->lock
, flags
);
872 free_pages((unsigned long)virt_addr
, get_order(size
));
876 * If the driver core informs the DMA layer if a driver grabs a device
877 * we don't need to preallocate the protection domains anymore.
878 * For now we have to.
880 void prealloc_protection_domains(void)
882 struct pci_dev
*dev
= NULL
;
883 struct dma_ops_domain
*dma_dom
;
884 struct amd_iommu
*iommu
;
885 int order
= amd_iommu_aperture_order
;
888 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
889 devid
= (dev
->bus
->number
<< 8) | dev
->devfn
;
890 if (devid
>= amd_iommu_last_bdf
)
892 devid
= amd_iommu_alias_table
[devid
];
893 if (domain_for_device(devid
))
895 iommu
= amd_iommu_rlookup_table
[devid
];
898 dma_dom
= dma_ops_domain_alloc(iommu
, order
);
901 init_unity_mappings_for_device(dma_dom
, devid
);
902 set_device_domain(iommu
, &dma_dom
->domain
, devid
);
903 printk(KERN_INFO
"AMD IOMMU: Allocated domain %d for device ",
905 print_devid(devid
, 1);