2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
64 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
65 struct list_head
*head
)
67 struct ath_hal
*ah
= sc
->sc_ah
;
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
78 bf
= list_first_entry(head
, struct ath_buf
, list
);
80 list_splice_tail_init(head
, &txq
->axq_q
);
82 txq
->axq_totalqueued
++;
83 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
85 DPRINTF(sc
, ATH_DBG_QUEUE
,
86 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
88 if (txq
->axq_link
== NULL
) {
89 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
90 DPRINTF(sc
, ATH_DBG_XMIT
,
91 "%s: TXDP[%u] = %llx (%p)\n",
92 __func__
, txq
->axq_qnum
,
93 ito64(bf
->bf_daddr
), bf
->bf_desc
);
95 *txq
->axq_link
= bf
->bf_daddr
;
96 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
98 txq
->axq_qnum
, txq
->axq_link
,
99 ito64(bf
->bf_daddr
), bf
->bf_desc
);
101 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
102 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
105 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
106 struct ath_xmit_status
*tx_status
)
108 struct ieee80211_hw
*hw
= sc
->hw
;
109 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
110 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
112 DPRINTF(sc
, ATH_DBG_XMIT
,
113 "%s: TX complete: skb: %p\n", __func__
, skb
);
115 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
||
116 tx_info
->flags
& IEEE80211_TX_STAT_TX_FILTERED
) {
118 tx_info
->rate_driver_data
[0] = NULL
;
121 if (tx_status
->flags
& ATH_TX_BAR
) {
122 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
123 tx_status
->flags
&= ~ATH_TX_BAR
;
126 if (!(tx_status
->flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
127 /* Frame was ACKed */
128 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
131 tx_info
->status
.rates
[0].count
= tx_status
->retries
+ 1;
133 ieee80211_tx_status(hw
, skb
);
136 /* Check if it's okay to send out aggregates */
138 static int ath_aggr_query(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
140 struct ath_atx_tid
*tid
;
141 tid
= ATH_AN_2_TID(an
, tidno
);
143 if (tid
->state
& AGGR_ADDBA_COMPLETE
||
144 tid
->state
& AGGR_ADDBA_PROGRESS
)
150 /* Calculate Atheros packet type from IEEE80211 packet header */
152 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
154 struct ieee80211_hdr
*hdr
;
155 enum ath9k_pkt_type htype
;
158 hdr
= (struct ieee80211_hdr
*)skb
->data
;
159 fc
= hdr
->frame_control
;
161 if (ieee80211_is_beacon(fc
))
162 htype
= ATH9K_PKT_TYPE_BEACON
;
163 else if (ieee80211_is_probe_resp(fc
))
164 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
165 else if (ieee80211_is_atim(fc
))
166 htype
= ATH9K_PKT_TYPE_ATIM
;
167 else if (ieee80211_is_pspoll(fc
))
168 htype
= ATH9K_PKT_TYPE_PSPOLL
;
170 htype
= ATH9K_PKT_TYPE_NORMAL
;
175 static bool is_pae(struct sk_buff
*skb
)
177 struct ieee80211_hdr
*hdr
;
180 hdr
= (struct ieee80211_hdr
*)skb
->data
;
181 fc
= hdr
->frame_control
;
183 if (ieee80211_is_data(fc
)) {
184 if (ieee80211_is_nullfunc(fc
) ||
185 /* Port Access Entity (IEEE 802.1X) */
186 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
194 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
196 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
198 if (tx_info
->control
.hw_key
) {
199 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
200 return ATH9K_KEY_TYPE_WEP
;
201 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
202 return ATH9K_KEY_TYPE_TKIP
;
203 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
204 return ATH9K_KEY_TYPE_AES
;
207 return ATH9K_KEY_TYPE_CLEAR
;
210 /* Called only when tx aggregation is enabled and HT is supported */
212 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
215 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
216 struct ieee80211_hdr
*hdr
;
218 struct ath_atx_tid
*tid
;
222 if (!tx_info
->control
.sta
)
225 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
226 hdr
= (struct ieee80211_hdr
*)skb
->data
;
227 fc
= hdr
->frame_control
;
231 if (ieee80211_is_data_qos(fc
)) {
232 qc
= ieee80211_get_qos_ctl(hdr
);
233 bf
->bf_tidno
= qc
[0] & 0xf;
238 if (ieee80211_is_data(fc
) && !is_pae(skb
)) {
239 /* For HT capable stations, we save tidno for later use.
240 * We also override seqno set by upper layer with the one
241 * in tx aggregation state.
243 * If fragmentation is on, the sequence number is
244 * not overridden, since it has been
245 * incremented by the fragmentation routine.
247 * FIXME: check if the fragmentation threshold exceeds
250 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
251 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
252 IEEE80211_SEQ_SEQ_SHIFT
);
253 bf
->bf_seqno
= tid
->seq_next
;
254 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
258 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
261 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
264 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
265 flags
|= ATH9K_TXDESC_INTREQ
;
267 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
268 flags
|= ATH9K_TXDESC_NOACK
;
269 if (tx_info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
270 flags
|= ATH9K_TXDESC_RTSENA
;
275 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
277 struct ath_buf
*bf
= NULL
;
279 spin_lock_bh(&sc
->sc_txbuflock
);
281 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
282 spin_unlock_bh(&sc
->sc_txbuflock
);
286 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
289 spin_unlock_bh(&sc
->sc_txbuflock
);
294 /* To complete a chain of buffers associated a frame */
296 static void ath_tx_complete_buf(struct ath_softc
*sc
,
298 struct list_head
*bf_q
,
299 int txok
, int sendbar
)
301 struct sk_buff
*skb
= bf
->bf_mpdu
;
302 struct ath_xmit_status tx_status
;
305 * Set retry information.
306 * NB: Don't use the information in the descriptor, because the frame
307 * could be software retried.
309 tx_status
.retries
= bf
->bf_retries
;
313 tx_status
.flags
= ATH_TX_BAR
;
316 tx_status
.flags
|= ATH_TX_ERROR
;
318 if (bf_isxretried(bf
))
319 tx_status
.flags
|= ATH_TX_XRETRY
;
322 /* Unmap this frame */
323 pci_unmap_single(sc
->pdev
,
327 /* complete this frame */
328 ath_tx_complete(sc
, skb
, &tx_status
);
331 * Return the list of ath_buf of this mpdu to free queue
333 spin_lock_bh(&sc
->sc_txbuflock
);
334 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
335 spin_unlock_bh(&sc
->sc_txbuflock
);
339 * queue up a dest/ac pair for tx scheduling
340 * NB: must be called with txq lock held
343 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
345 struct ath_atx_ac
*ac
= tid
->ac
;
348 * if tid is paused, hold off
354 * add tid to ac atmost once
360 list_add_tail(&tid
->list
, &ac
->tid_q
);
363 * add node ac to txq atmost once
369 list_add_tail(&ac
->list
, &txq
->axq_acq
);
374 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
376 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
378 spin_lock_bh(&txq
->axq_lock
);
382 spin_unlock_bh(&txq
->axq_lock
);
385 /* resume a tid and schedule aggregate */
387 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
389 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
391 ASSERT(tid
->paused
> 0);
392 spin_lock_bh(&txq
->axq_lock
);
399 if (list_empty(&tid
->buf_q
))
403 * Add this TID to scheduler and try to send out aggregates
405 ath_tx_queue_tid(txq
, tid
);
406 ath_txq_schedule(sc
, txq
);
408 spin_unlock_bh(&txq
->axq_lock
);
411 /* Compute the number of bad frames */
413 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
416 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
417 struct ath_desc
*ds
= bf_last
->bf_desc
;
419 u32 ba
[WME_BA_BMP_SIZE
>> 5];
424 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
427 isaggr
= bf_isaggr(bf
);
429 seq_st
= ATH_DS_BA_SEQ(ds
);
430 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
434 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
435 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
444 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
447 struct ieee80211_hdr
*hdr
;
449 bf
->bf_state
.bf_type
|= BUF_RETRY
;
453 hdr
= (struct ieee80211_hdr
*)skb
->data
;
454 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
457 /* Update block ack window */
459 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
464 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
465 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
467 tid
->tx_buf
[cindex
] = NULL
;
469 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
470 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
471 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
476 * ath_pkt_dur - compute packet duration (NB: not NAV)
479 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
480 * width - 0 for 20 MHz, 1 for 40 MHz
481 * half_gi - to use 4us v/s 3.6 us for symbol time
483 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
484 int width
, int half_gi
, bool shortPreamble
)
486 struct ath_rate_table
*rate_table
= sc
->hw_rate_table
[sc
->sc_curmode
];
487 u32 nbits
, nsymbits
, duration
, nsymbols
;
491 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
492 rc
= rate_table
->info
[rix
].ratecode
;
494 /* for legacy rates, use old function to compute packet duration */
496 return ath9k_hw_computetxtime(sc
->sc_ah
, rate_table
, pktlen
,
499 /* find number of symbols: PLCP + data */
500 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
501 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
502 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
505 duration
= SYMBOL_TIME(nsymbols
);
507 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
509 /* addup duration for legacy/ht training and signal fields */
510 streams
= HT_RC_2_STREAMS(rc
);
511 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
516 /* Rate module function to set rate related fields in tx descriptor */
518 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
520 struct ath_hal
*ah
= sc
->sc_ah
;
521 struct ath_rate_table
*rt
;
522 struct ath_desc
*ds
= bf
->bf_desc
;
523 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
524 struct ath9k_11n_rate_series series
[4];
525 struct ath_node
*an
= NULL
;
527 struct ieee80211_tx_info
*tx_info
;
528 struct ieee80211_tx_rate
*rates
;
529 struct ieee80211_hdr
*hdr
;
530 int i
, flags
, rtsctsena
= 0;
532 u8 rix
= 0, cix
, ctsrate
= 0;
535 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
537 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
538 hdr
= (struct ieee80211_hdr
*)skb
->data
;
539 fc
= hdr
->frame_control
;
540 tx_info
= IEEE80211_SKB_CB(skb
);
541 rates
= tx_info
->control
.rates
;
543 if (tx_info
->control
.sta
)
544 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
546 if (ieee80211_has_morefrags(fc
) ||
547 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
548 rates
[1].count
= rates
[2].count
= rates
[3].count
= 0;
549 rates
[1].idx
= rates
[2].idx
= rates
[3].idx
= 0;
550 rates
[0].count
= ATH_TXMAXTRY
;
553 /* get the cix for the lowest valid rix */
554 rt
= sc
->hw_rate_table
[sc
->sc_curmode
];
555 for (i
= 3; i
>= 0; i
--) {
556 if (rates
[i
].count
&& (rates
[i
].idx
>= 0)) {
562 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
563 cix
= rt
->info
[rix
].ctrl_rate
;
566 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
567 * just CTS. Note that this is only done for OFDM/HT unicast frames.
569 if (sc
->sc_protmode
!= PROT_M_NONE
&& !(bf
->bf_flags
& ATH9K_TXDESC_NOACK
)
570 && (rt
->info
[rix
].phy
== WLAN_RC_PHY_OFDM
||
571 WLAN_RC_PHY_HT(rt
->info
[rix
].phy
))) {
572 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
573 flags
= ATH9K_TXDESC_RTSENA
;
574 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
575 flags
= ATH9K_TXDESC_CTSENA
;
577 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
581 /* For 11n, the default behavior is to enable RTS for hw retried frames.
582 * We enable the global flag here and let rate series flags determine
583 * which rates will actually use RTS.
585 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
586 /* 802.11g protection not needed, use our default behavior */
588 flags
= ATH9K_TXDESC_RTSENA
;
591 /* Set protection if aggregate protection on */
592 if (sc
->sc_config
.ath_aggr_prot
&&
593 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
594 flags
= ATH9K_TXDESC_RTSENA
;
595 cix
= rt
->info
[sc
->sc_protrix
].ctrl_rate
;
599 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
600 if (bf_isaggr(bf
) && (bf
->bf_al
> ah
->ah_caps
.rts_aggr_limit
))
601 flags
&= ~(ATH9K_TXDESC_RTSENA
);
604 * CTS transmit rate is derived from the transmit rate by looking in the
605 * h/w rate table. We must also factor in whether or not a short
606 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
608 ctsrate
= rt
->info
[cix
].ratecode
|
609 (bf_isshpreamble(bf
) ? rt
->info
[cix
].short_preamble
: 0);
611 for (i
= 0; i
< 4; i
++) {
612 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
617 series
[i
].Rate
= rt
->info
[rix
].ratecode
|
618 (bf_isshpreamble(bf
) ? rt
->info
[rix
].short_preamble
: 0);
620 series
[i
].Tries
= rates
[i
].count
;
622 series
[i
].RateFlags
= (
623 (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ?
624 ATH9K_RATESERIES_RTS_CTS
: 0) |
625 ((rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ?
626 ATH9K_RATESERIES_2040
: 0) |
627 ((rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
) ?
628 ATH9K_RATESERIES_HALFGI
: 0);
630 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
631 (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) != 0,
632 (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
),
633 bf_isshpreamble(bf
));
635 if (bf_isht(bf
) && an
)
636 series
[i
].ChSel
= ath_chainmask_sel_logic(sc
, an
);
638 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
641 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
644 /* set dur_update_en for l-sig computation except for PS-Poll frames */
645 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
, !bf_ispspoll(bf
),
646 ctsrate
, ctsduration
,
649 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
650 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
654 * Function to send a normal HT (non-AMPDU) frame
655 * NB: must be called with txq lock held
657 static int ath_tx_send_normal(struct ath_softc
*sc
,
659 struct ath_atx_tid
*tid
,
660 struct list_head
*bf_head
)
664 BUG_ON(list_empty(bf_head
));
666 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
667 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
669 /* update starting sequence number for subsequent ADDBA request */
670 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
672 /* Queue to h/w without aggregation */
674 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
675 ath_buf_set_rate(sc
, bf
);
676 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
681 /* flush tid's software queue and send frames as non-ampdu's */
683 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
685 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
687 struct list_head bf_head
;
688 INIT_LIST_HEAD(&bf_head
);
690 ASSERT(tid
->paused
> 0);
691 spin_lock_bh(&txq
->axq_lock
);
695 if (tid
->paused
> 0) {
696 spin_unlock_bh(&txq
->axq_lock
);
700 while (!list_empty(&tid
->buf_q
)) {
701 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
702 ASSERT(!bf_isretried(bf
));
703 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
704 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
707 spin_unlock_bh(&txq
->axq_lock
);
710 /* Completion routine of an aggregate */
712 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
715 struct list_head
*bf_q
,
718 struct ath_node
*an
= NULL
;
720 struct ieee80211_tx_info
*tx_info
;
721 struct ath_atx_tid
*tid
= NULL
;
722 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
723 struct ath_desc
*ds
= bf_last
->bf_desc
;
724 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
725 struct list_head bf_head
, bf_pending
;
727 u32 ba
[WME_BA_BMP_SIZE
>> 5];
728 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
730 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
731 tx_info
= IEEE80211_SKB_CB(skb
);
733 if (tx_info
->control
.sta
) {
734 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
735 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
738 isaggr
= bf_isaggr(bf
);
741 if (ATH_DS_TX_BA(ds
)) {
743 * extract starting sequence and
746 seq_st
= ATH_DS_BA_SEQ(ds
);
748 ATH_DS_BA_BITMAP(ds
),
749 WME_BA_BMP_SIZE
>> 3);
751 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
754 * AR5416 can become deaf/mute when BA
755 * issue happens. Chip needs to be reset.
756 * But AP code may have sychronization issues
757 * when perform internal reset in this routine.
758 * Only enable reset in STA mode for now.
760 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
764 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
768 INIT_LIST_HEAD(&bf_pending
);
769 INIT_LIST_HEAD(&bf_head
);
772 txfail
= txpending
= 0;
773 bf_next
= bf
->bf_next
;
775 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
776 /* transmit completion, subframe is
777 * acked by block ack */
778 } else if (!isaggr
&& txok
) {
779 /* transmit completion */
782 if (!(tid
->state
& AGGR_CLEANUP
) &&
783 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
784 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
785 ath_tx_set_retry(sc
, bf
);
788 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
794 * cleanup in progress, just fail
795 * the un-acked sub-frames
801 * Remove ath_buf's of this sub-frame from aggregate queue.
803 if (bf_next
== NULL
) { /* last subframe in the aggregate */
804 ASSERT(bf
->bf_lastfrm
== bf_last
);
807 * The last descriptor of the last sub frame could be
808 * a holding descriptor for h/w. If that's the case,
809 * bf->bf_lastfrm won't be in the bf_q.
810 * Make sure we handle bf_q properly here.
813 if (!list_empty(bf_q
)) {
814 bf_lastq
= list_entry(bf_q
->prev
,
815 struct ath_buf
, list
);
816 list_cut_position(&bf_head
,
817 bf_q
, &bf_lastq
->list
);
820 * XXX: if the last subframe only has one
821 * descriptor which is also being used as
822 * a holding descriptor. Then the ath_buf
823 * is not in the bf_q at all.
825 INIT_LIST_HEAD(&bf_head
);
828 ASSERT(!list_empty(bf_q
));
829 list_cut_position(&bf_head
,
830 bf_q
, &bf
->bf_lastfrm
->list
);
835 * complete the acked-ones/xretried ones; update
838 spin_lock_bh(&txq
->axq_lock
);
839 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
840 spin_unlock_bh(&txq
->axq_lock
);
842 /* complete this sub-frame */
843 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
846 * retry the un-acked ones
849 * XXX: if the last descriptor is holding descriptor,
850 * in order to requeue the frame to software queue, we
851 * need to allocate a new descriptor and
852 * copy the content of holding descriptor to it.
854 if (bf
->bf_next
== NULL
&&
855 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
858 /* allocate new descriptor */
859 spin_lock_bh(&sc
->sc_txbuflock
);
860 ASSERT(!list_empty((&sc
->sc_txbuf
)));
861 tbf
= list_first_entry(&sc
->sc_txbuf
,
862 struct ath_buf
, list
);
863 list_del(&tbf
->list
);
864 spin_unlock_bh(&sc
->sc_txbuflock
);
866 ATH_TXBUF_RESET(tbf
);
868 /* copy descriptor content */
869 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
870 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
871 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
873 /* link it to the frame */
875 bf_lastq
->bf_desc
->ds_link
=
877 bf
->bf_lastfrm
= tbf
;
878 ath9k_hw_cleartxdesc(sc
->sc_ah
,
879 bf
->bf_lastfrm
->bf_desc
);
881 tbf
->bf_state
= bf_last
->bf_state
;
882 tbf
->bf_lastfrm
= tbf
;
883 ath9k_hw_cleartxdesc(sc
->sc_ah
,
884 tbf
->bf_lastfrm
->bf_desc
);
886 /* copy the DMA context */
888 bf_last
->bf_dmacontext
;
890 list_add_tail(&tbf
->list
, &bf_head
);
893 * Clear descriptor status words for
896 ath9k_hw_cleartxdesc(sc
->sc_ah
,
897 bf
->bf_lastfrm
->bf_desc
);
901 * Put this buffer to the temporary pending
902 * queue to retain ordering
904 list_splice_tail_init(&bf_head
, &bf_pending
);
910 if (tid
->state
& AGGR_CLEANUP
) {
911 /* check to see if we're done with cleaning the h/w queue */
912 spin_lock_bh(&txq
->axq_lock
);
914 if (tid
->baw_head
== tid
->baw_tail
) {
915 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
916 tid
->addba_exchangeattempts
= 0;
917 spin_unlock_bh(&txq
->axq_lock
);
919 tid
->state
&= ~AGGR_CLEANUP
;
921 /* send buffered frames as singles */
922 ath_tx_flush_tid(sc
, tid
);
924 spin_unlock_bh(&txq
->axq_lock
);
930 * prepend un-acked frames to the beginning of the pending frame queue
932 if (!list_empty(&bf_pending
)) {
933 spin_lock_bh(&txq
->axq_lock
);
934 /* Note: we _prepend_, we _do_not_ at to
935 * the end of the queue ! */
936 list_splice(&bf_pending
, &tid
->buf_q
);
937 ath_tx_queue_tid(txq
, tid
);
938 spin_unlock_bh(&txq
->axq_lock
);
942 ath_reset(sc
, false);
947 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
, int nbad
)
949 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
950 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
951 struct ath_tx_info_priv
*tx_info_priv
= ATH_TX_INFO_PRIV(tx_info
);
953 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
954 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
956 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
957 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
959 memcpy(&tx_info_priv
->tx
, &ds
->ds_txstat
,
960 sizeof(tx_info_priv
->tx
));
961 tx_info_priv
->n_frames
= bf
->bf_nframes
;
962 tx_info_priv
->n_bad_frames
= nbad
;
967 /* Process completed xmit descriptors from the specified queue */
969 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
971 struct ath_hal
*ah
= sc
->sc_ah
;
972 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
973 struct list_head bf_head
;
978 DPRINTF(sc
, ATH_DBG_QUEUE
,
979 "%s: tx queue %d (%x), link %p\n", __func__
,
980 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
984 spin_lock_bh(&txq
->axq_lock
);
985 if (list_empty(&txq
->axq_q
)) {
986 txq
->axq_link
= NULL
;
987 txq
->axq_linkbuf
= NULL
;
988 spin_unlock_bh(&txq
->axq_lock
);
991 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
994 * There is a race condition that a BH gets scheduled
995 * after sw writes TxE and before hw re-load the last
996 * descriptor to get the newly chained one.
997 * Software must keep the last DONE descriptor as a
998 * holding descriptor - software does so by marking
999 * it with the STALE flag.
1002 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1004 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1006 * The holding descriptor is the last
1007 * descriptor in queue. It's safe to remove
1008 * the last holding descriptor in BH context.
1010 spin_unlock_bh(&txq
->axq_lock
);
1013 /* Lets work with the next buffer now */
1014 bf
= list_entry(bf_held
->list
.next
,
1015 struct ath_buf
, list
);
1019 lastbf
= bf
->bf_lastbf
;
1020 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1022 status
= ath9k_hw_txprocdesc(ah
, ds
);
1023 if (status
== -EINPROGRESS
) {
1024 spin_unlock_bh(&txq
->axq_lock
);
1027 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1028 txq
->axq_lastdsWithCTS
= NULL
;
1029 if (ds
== txq
->axq_gatingds
)
1030 txq
->axq_gatingds
= NULL
;
1033 * Remove ath_buf's of the same transmit unit from txq,
1034 * however leave the last descriptor back as the holding
1035 * descriptor for hw.
1037 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1038 INIT_LIST_HEAD(&bf_head
);
1040 if (!list_is_singular(&lastbf
->list
))
1041 list_cut_position(&bf_head
,
1042 &txq
->axq_q
, lastbf
->list
.prev
);
1047 txq
->axq_aggr_depth
--;
1049 txok
= (ds
->ds_txstat
.ts_status
== 0);
1051 spin_unlock_bh(&txq
->axq_lock
);
1054 list_del(&bf_held
->list
);
1055 spin_lock_bh(&sc
->sc_txbuflock
);
1056 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1057 spin_unlock_bh(&sc
->sc_txbuflock
);
1060 if (!bf_isampdu(bf
)) {
1062 * This frame is sent out as a single frame.
1063 * Use hardware retry status for this frame.
1065 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1066 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1067 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1070 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1073 ath_tx_rc_status(bf
, ds
, nbad
);
1076 * Complete this transmit unit
1079 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1081 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1083 /* Wake up mac80211 queue */
1085 spin_lock_bh(&txq
->axq_lock
);
1086 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1089 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1091 ieee80211_wake_queue(sc
->hw
, qnum
);
1098 * schedule any pending packets if aggregation is enabled
1100 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1101 ath_txq_schedule(sc
, txq
);
1102 spin_unlock_bh(&txq
->axq_lock
);
1106 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1108 struct ath_hal
*ah
= sc
->sc_ah
;
1110 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1111 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1112 __func__
, txq
->axq_qnum
,
1113 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1116 /* Drain only the data queues */
1118 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1120 struct ath_hal
*ah
= sc
->sc_ah
;
1121 int i
, status
, npend
= 0;
1123 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1124 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1125 if (ATH_TXQ_SETUP(sc
, i
)) {
1126 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1127 /* The TxDMA may not really be stopped.
1128 * Double check the hal tx pending count */
1129 npend
+= ath9k_hw_numtxpending(ah
,
1130 sc
->sc_txq
[i
].axq_qnum
);
1136 /* TxDMA not stopped, reset the hal */
1137 DPRINTF(sc
, ATH_DBG_XMIT
,
1138 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1140 spin_lock_bh(&sc
->sc_resetlock
);
1141 if (!ath9k_hw_reset(ah
,
1142 sc
->sc_ah
->ah_curchan
,
1143 sc
->sc_ht_info
.tx_chan_width
,
1144 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1145 sc
->sc_ht_extprotspacing
, true, &status
)) {
1147 DPRINTF(sc
, ATH_DBG_FATAL
,
1148 "%s: unable to reset hardware; hal status %u\n",
1152 spin_unlock_bh(&sc
->sc_resetlock
);
1155 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1156 if (ATH_TXQ_SETUP(sc
, i
))
1157 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1161 /* Add a sub-frame to block ack window */
1163 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1164 struct ath_atx_tid
*tid
,
1169 if (bf_isretried(bf
))
1172 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1173 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1175 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1176 tid
->tx_buf
[cindex
] = bf
;
1178 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1179 (ATH_TID_MAX_BUFS
- 1))) {
1180 tid
->baw_tail
= cindex
;
1181 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1186 * Function to send an A-MPDU
1187 * NB: must be called with txq lock held
1190 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1191 struct ath_atx_tid
*tid
,
1192 struct list_head
*bf_head
,
1193 struct ath_tx_control
*txctl
)
1197 BUG_ON(list_empty(bf_head
));
1199 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1200 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1203 * Do not queue to h/w when any of the following conditions is true:
1204 * - there are pending frames in software queue
1205 * - the TID is currently paused for ADDBA/BAR request
1206 * - seqno is not within block-ack window
1207 * - h/w queue depth exceeds low water mark
1209 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1210 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1211 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1213 * Add this frame to software queue for scheduling later
1216 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1217 ath_tx_queue_tid(txctl
->txq
, tid
);
1221 /* Add sub-frame to BAW */
1222 ath_tx_addto_baw(sc
, tid
, bf
);
1224 /* Queue to h/w without aggregation */
1226 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1227 ath_buf_set_rate(sc
, bf
);
1228 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1235 * returns aggr limit based on lowest of the rates
1238 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1240 struct ath_atx_tid
*tid
)
1242 struct ath_rate_table
*rate_table
= sc
->hw_rate_table
[sc
->sc_curmode
];
1243 struct sk_buff
*skb
;
1244 struct ieee80211_tx_info
*tx_info
;
1245 struct ieee80211_tx_rate
*rates
;
1246 struct ath_tx_info_priv
*tx_info_priv
;
1247 u32 max_4ms_framelen
, frame_length
;
1248 u16 aggr_limit
, legacy
= 0, maxampdu
;
1251 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1252 tx_info
= IEEE80211_SKB_CB(skb
);
1253 rates
= tx_info
->control
.rates
;
1255 (struct ath_tx_info_priv
*)tx_info
->rate_driver_data
[0];
1258 * Find the lowest frame length among the rate series that will have a
1259 * 4ms transmit duration.
1260 * TODO - TXOP limit needs to be considered.
1262 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1264 for (i
= 0; i
< 4; i
++) {
1265 if (rates
[i
].count
) {
1266 if (!WLAN_RC_PHY_HT(rate_table
->info
[rates
[i
].idx
].phy
)) {
1272 rate_table
->info
[rates
[i
].idx
].max_4ms_framelen
;
1273 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1278 * limit aggregate size by the minimum rate if rate selected is
1279 * not a probe rate, if rate selected is a probe rate then
1280 * avoid aggregation of this packet.
1282 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1285 aggr_limit
= min(max_4ms_framelen
,
1286 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1289 * h/w can accept aggregates upto 16 bit lengths (65535).
1290 * The IE, however can hold upto 65536, which shows up here
1291 * as zero. Ignore 65536 since we are constrained by hw.
1293 maxampdu
= tid
->an
->maxampdu
;
1295 aggr_limit
= min(aggr_limit
, maxampdu
);
1301 * returns the number of delimiters to be added to
1302 * meet the minimum required mpdudensity.
1303 * caller should make sure that the rate is HT rate .
1306 static int ath_compute_num_delims(struct ath_softc
*sc
,
1307 struct ath_atx_tid
*tid
,
1311 struct ath_rate_table
*rt
= sc
->hw_rate_table
[sc
->sc_curmode
];
1312 struct sk_buff
*skb
= bf
->bf_mpdu
;
1313 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1314 u32 nsymbits
, nsymbols
, mpdudensity
;
1317 int width
, half_gi
, ndelim
, mindelim
;
1319 /* Select standard number of delimiters based on frame length alone */
1320 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1323 * If encryption enabled, hardware requires some more padding between
1325 * TODO - this could be improved to be dependent on the rate.
1326 * The hardware can keep up at lower rates, but not higher rates
1328 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1329 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1332 * Convert desired mpdu density from microeconds to bytes based
1333 * on highest rate in rate series (i.e. first rate) to determine
1334 * required minimum length for subframe. Take into account
1335 * whether high rate is 20 or 40Mhz and half or full GI.
1337 mpdudensity
= tid
->an
->mpdudensity
;
1340 * If there is no mpdu density restriction, no further calculation
1343 if (mpdudensity
== 0)
1346 rix
= tx_info
->control
.rates
[0].idx
;
1347 flags
= tx_info
->control
.rates
[0].flags
;
1348 rc
= rt
->info
[rix
].ratecode
;
1349 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
1350 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
1353 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1355 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1360 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1361 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1363 /* Is frame shorter than required minimum length? */
1364 if (frmlen
< minlen
) {
1365 /* Get the minimum number of delimiters required. */
1366 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1367 ndelim
= max(mindelim
, ndelim
);
1374 * For aggregation from software buffer queue.
1375 * NB: must be called with txq lock held
1378 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1379 struct ath_atx_tid
*tid
,
1380 struct list_head
*bf_q
,
1381 struct ath_buf
**bf_last
,
1382 struct aggr_rifs_param
*param
,
1385 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1386 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1387 struct list_head bf_head
;
1388 int rl
= 0, nframes
= 0, ndelim
;
1389 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1390 al_delta
, h_baw
= tid
->baw_size
/ 2;
1391 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1393 INIT_LIST_HEAD(&bf_head
);
1395 BUG_ON(list_empty(&tid
->buf_q
));
1397 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1400 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1403 * do not step over block-ack window
1405 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1406 status
= ATH_AGGR_BAW_CLOSED
;
1411 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1416 * do not exceed aggregation limit
1418 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1420 if (nframes
&& (aggr_limit
<
1421 (al
+ bpad
+ al_delta
+ prev_al
))) {
1422 status
= ATH_AGGR_LIMITED
;
1427 * do not exceed subframe limit
1429 if ((nframes
+ *prev_frames
) >=
1430 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1431 status
= ATH_AGGR_LIMITED
;
1436 * add padding for previous frame to aggregation length
1438 al
+= bpad
+ al_delta
;
1441 * Get the delimiters needed to meet the MPDU
1442 * density for this node.
1444 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1446 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1449 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1452 * this packet is part of an aggregate
1453 * - remove all descriptors belonging to this frame from
1455 * - add it to block ack window
1456 * - set up descriptors for aggregation
1458 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1459 ath_tx_addto_baw(sc
, tid
, bf
);
1461 list_for_each_entry(tbf
, &bf_head
, list
) {
1462 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1463 tbf
->bf_desc
, ndelim
);
1467 * link buffers of this frame to the aggregate
1469 list_splice_tail_init(&bf_head
, bf_q
);
1473 bf_prev
->bf_next
= bf
;
1474 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1480 * terminate aggregation on a small packet boundary
1482 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1483 status
= ATH_AGGR_SHORTPKT
;
1487 } while (!list_empty(&tid
->buf_q
));
1489 bf_first
->bf_al
= al
;
1490 bf_first
->bf_nframes
= nframes
;
1497 * process pending frames possibly doing a-mpdu aggregation
1498 * NB: must be called with txq lock held
1501 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1502 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1504 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1505 enum ATH_AGGR_STATUS status
;
1506 struct list_head bf_q
;
1507 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1508 int prev_frames
= 0;
1511 if (list_empty(&tid
->buf_q
))
1514 INIT_LIST_HEAD(&bf_q
);
1516 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1520 * no frames picked up to be aggregated; block-ack
1521 * window is not open
1523 if (list_empty(&bf_q
))
1526 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1527 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1528 bf
->bf_lastbf
= bf_last
;
1531 * if only one frame, send as non-aggregate
1533 if (bf
->bf_nframes
== 1) {
1534 ASSERT(bf
->bf_lastfrm
== bf_last
);
1536 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1538 * clear aggr bits for every descriptor
1539 * XXX TODO: is there a way to optimize it?
1541 list_for_each_entry(tbf
, &bf_q
, list
) {
1542 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1545 ath_buf_set_rate(sc
, bf
);
1546 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1551 * setup first desc with rate and aggr info
1553 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1554 ath_buf_set_rate(sc
, bf
);
1555 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1558 * anchor last frame of aggregate correctly
1560 ASSERT(bf_lastaggr
);
1561 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1563 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1565 /* XXX: We don't enter into this loop, consider removing this */
1566 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1567 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1568 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1571 txq
->axq_aggr_depth
++;
1574 * Normal aggregate, queue to hardware
1576 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1578 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1579 status
!= ATH_AGGR_BAW_CLOSED
);
1582 /* Called with txq lock held */
1584 static void ath_tid_drain(struct ath_softc
*sc
,
1585 struct ath_txq
*txq
,
1586 struct ath_atx_tid
*tid
)
1590 struct list_head bf_head
;
1591 INIT_LIST_HEAD(&bf_head
);
1594 if (list_empty(&tid
->buf_q
))
1596 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1598 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1600 /* update baw for software retried frame */
1601 if (bf_isretried(bf
))
1602 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1605 * do not indicate packets while holding txq spinlock.
1606 * unlock is intentional here
1608 spin_unlock(&txq
->axq_lock
);
1610 /* complete this sub-frame */
1611 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1613 spin_lock(&txq
->axq_lock
);
1617 * TODO: For frame(s) that are in the retry state, we will reuse the
1618 * sequence number(s) without setting the retry bit. The
1619 * alternative is to give up on these and BAR the receiver's window
1622 tid
->seq_next
= tid
->seq_start
;
1623 tid
->baw_tail
= tid
->baw_head
;
1627 * Drain all pending buffers
1628 * NB: must be called with txq lock held
1631 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1632 struct ath_txq
*txq
)
1634 struct ath_atx_ac
*ac
, *ac_tmp
;
1635 struct ath_atx_tid
*tid
, *tid_tmp
;
1637 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1638 list_del(&ac
->list
);
1640 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1641 list_del(&tid
->list
);
1643 ath_tid_drain(sc
, txq
, tid
);
1648 static void ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1649 struct sk_buff
*skb
, struct scatterlist
*sg
,
1650 struct ath_tx_control
*txctl
)
1652 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1653 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1654 struct ath_tx_info_priv
*tx_info_priv
;
1658 tx_info_priv
= kzalloc(sizeof(*tx_info_priv
), GFP_KERNEL
);
1659 tx_info
->rate_driver_data
[0] = tx_info_priv
;
1660 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1661 fc
= hdr
->frame_control
;
1663 ATH_TXBUF_RESET(bf
);
1667 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1669 ieee80211_is_data(fc
) ?
1670 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1671 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1672 ieee80211_is_back_req(fc
) ?
1673 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1674 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1675 ieee80211_is_pspoll(fc
) ?
1676 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1677 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1678 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1679 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1680 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1681 (sc
->hw
->conf
.ht
.enabled
&& !is_pae(skb
) &&
1682 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) ?
1683 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1684 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1686 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1690 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1692 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1693 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1694 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1696 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1699 /* Assign seqno, tidno */
1701 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1702 assign_aggr_tid_seqno(skb
, bf
);
1707 bf
->bf_dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
1708 skb
->len
, PCI_DMA_TODEVICE
);
1709 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1712 /* FIXME: tx power */
1713 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1714 struct scatterlist
*sg
, u32 n_sg
,
1715 struct ath_tx_control
*txctl
)
1717 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1718 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1719 struct ath_node
*an
= NULL
;
1720 struct list_head bf_head
;
1721 struct ath_desc
*ds
;
1722 struct ath_atx_tid
*tid
;
1723 struct ath_hal
*ah
= sc
->sc_ah
;
1726 frm_type
= get_hw_packet_type(skb
);
1728 INIT_LIST_HEAD(&bf_head
);
1729 list_add_tail(&bf
->list
, &bf_head
);
1731 /* setup descriptor */
1735 ds
->ds_data
= bf
->bf_buf_addr
;
1737 /* Formulate first tx descriptor with tx controls */
1739 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1740 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1742 ath9k_hw_filltxdesc(ah
, ds
,
1743 sg_dma_len(sg
), /* segment length */
1744 true, /* first segment */
1745 (n_sg
== 1) ? true : false, /* last segment */
1746 ds
); /* first descriptor */
1748 bf
->bf_lastfrm
= bf
;
1750 spin_lock_bh(&txctl
->txq
->axq_lock
);
1752 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1753 tx_info
->control
.sta
) {
1754 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1755 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1757 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1759 * Try aggregation if it's a unicast data frame
1760 * and the destination is HT capable.
1762 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1765 * Send this frame as regular when ADDBA
1766 * exchange is neither complete nor pending.
1768 ath_tx_send_normal(sc
, txctl
->txq
,
1775 ath_buf_set_rate(sc
, bf
);
1776 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1779 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1782 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1783 struct ath_tx_control
*txctl
)
1786 struct scatterlist sg
;
1788 /* Check if a tx buffer is available */
1790 bf
= ath_tx_get_buffer(sc
);
1792 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX buffers are full\n",
1797 ath_tx_setup_buffer(sc
, bf
, skb
, &sg
, txctl
);
1801 memset(&sg
, 0, sizeof(struct scatterlist
));
1802 sg_dma_address(&sg
) = bf
->bf_dmacontext
;
1803 sg_dma_len(&sg
) = skb
->len
;
1805 ath_tx_start_dma(sc
, bf
, &sg
, 1, txctl
);
1810 /* Initialize TX queue and h/w */
1812 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
1817 spin_lock_init(&sc
->sc_txbuflock
);
1819 /* Setup tx descriptors */
1820 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
1823 DPRINTF(sc
, ATH_DBG_FATAL
,
1824 "%s: failed to allocate tx descriptors: %d\n",
1829 /* XXX allocate beacon state together with vap */
1830 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
1831 "beacon", ATH_BCBUF
, 1);
1833 DPRINTF(sc
, ATH_DBG_FATAL
,
1834 "%s: failed to allocate "
1835 "beacon descripotrs: %d\n",
1848 /* Reclaim all tx queue resources */
1850 int ath_tx_cleanup(struct ath_softc
*sc
)
1852 /* cleanup beacon descriptors */
1853 if (sc
->sc_bdma
.dd_desc_len
!= 0)
1854 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
1856 /* cleanup tx descriptors */
1857 if (sc
->sc_txdma
.dd_desc_len
!= 0)
1858 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
1863 /* Setup a h/w transmit queue */
1865 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1867 struct ath_hal
*ah
= sc
->sc_ah
;
1868 struct ath9k_tx_queue_info qi
;
1871 memset(&qi
, 0, sizeof(qi
));
1872 qi
.tqi_subtype
= subtype
;
1873 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1874 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1875 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1876 qi
.tqi_physCompBuf
= 0;
1879 * Enable interrupts only for EOL and DESC conditions.
1880 * We mark tx descriptors to receive a DESC interrupt
1881 * when a tx queue gets deep; otherwise waiting for the
1882 * EOL to reap descriptors. Note that this is done to
1883 * reduce interrupt load and this only defers reaping
1884 * descriptors, never transmitting frames. Aside from
1885 * reducing interrupts this also permits more concurrency.
1886 * The only potential downside is if the tx queue backs
1887 * up in which case the top half of the kernel may backup
1888 * due to a lack of tx descriptors.
1890 * The UAPSD queue is an exception, since we take a desc-
1891 * based intr on the EOSP frames.
1893 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1894 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1896 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1897 TXQ_FLAG_TXDESCINT_ENABLE
;
1898 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1901 * NB: don't print a message, this happens
1902 * normally on parts with too few tx queues
1906 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
1907 DPRINTF(sc
, ATH_DBG_FATAL
,
1908 "%s: hal qnum %u out of range, max %u!\n",
1909 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
1910 ath9k_hw_releasetxqueue(ah
, qnum
);
1913 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
1914 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
1916 txq
->axq_qnum
= qnum
;
1917 txq
->axq_link
= NULL
;
1918 INIT_LIST_HEAD(&txq
->axq_q
);
1919 INIT_LIST_HEAD(&txq
->axq_acq
);
1920 spin_lock_init(&txq
->axq_lock
);
1922 txq
->axq_aggr_depth
= 0;
1923 txq
->axq_totalqueued
= 0;
1924 txq
->axq_linkbuf
= NULL
;
1925 sc
->sc_txqsetup
|= 1<<qnum
;
1927 return &sc
->sc_txq
[qnum
];
1930 /* Reclaim resources for a setup queue */
1932 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1934 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1935 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
1939 * Setup a hardware data transmit queue for the specified
1940 * access control. The hal may not support all requested
1941 * queues in which case it will return a reference to a
1942 * previously setup queue. We record the mapping from ac's
1943 * to h/w queues for use by ath_tx_start and also track
1944 * the set of h/w queues being used to optimize work in the
1945 * transmit interrupt handler and related routines.
1948 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1950 struct ath_txq
*txq
;
1952 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
1953 DPRINTF(sc
, ATH_DBG_FATAL
,
1954 "%s: HAL AC %u out of range, max %zu!\n",
1955 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
1958 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1960 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
1966 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
1971 case ATH9K_TX_QUEUE_DATA
:
1972 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
1973 DPRINTF(sc
, ATH_DBG_FATAL
,
1974 "%s: HAL AC %u out of range, max %zu!\n",
1976 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
1979 qnum
= sc
->sc_haltype2q
[haltype
];
1981 case ATH9K_TX_QUEUE_BEACON
:
1982 qnum
= sc
->sc_bhalq
;
1984 case ATH9K_TX_QUEUE_CAB
:
1985 qnum
= sc
->sc_cabq
->axq_qnum
;
1993 /* Get a transmit queue, if available */
1995 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
1997 struct ath_txq
*txq
= NULL
;
2000 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
2001 txq
= &sc
->sc_txq
[qnum
];
2003 spin_lock_bh(&txq
->axq_lock
);
2005 /* Try to avoid running out of descriptors */
2006 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
2007 DPRINTF(sc
, ATH_DBG_FATAL
,
2008 "%s: TX queue: %d is full, depth: %d\n",
2009 __func__
, qnum
, txq
->axq_depth
);
2010 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
2012 spin_unlock_bh(&txq
->axq_lock
);
2016 spin_unlock_bh(&txq
->axq_lock
);
2021 /* Update parameters for a transmit queue */
2023 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2024 struct ath9k_tx_queue_info
*qinfo
)
2026 struct ath_hal
*ah
= sc
->sc_ah
;
2028 struct ath9k_tx_queue_info qi
;
2030 if (qnum
== sc
->sc_bhalq
) {
2032 * XXX: for beacon queue, we just save the parameter.
2033 * It will be picked up by ath_beaconq_config when
2036 sc
->sc_beacon_qi
= *qinfo
;
2040 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2042 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2043 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2044 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2045 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2046 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2047 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2049 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2050 DPRINTF(sc
, ATH_DBG_FATAL
,
2051 "%s: unable to update hardware queue %u!\n",
2055 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2061 int ath_cabq_update(struct ath_softc
*sc
)
2063 struct ath9k_tx_queue_info qi
;
2064 int qnum
= sc
->sc_cabq
->axq_qnum
;
2065 struct ath_beacon_config conf
;
2067 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2069 * Ensure the readytime % is within the bounds.
2071 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2072 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2073 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2074 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2076 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2078 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2079 ath_txq_update(sc
, qnum
, &qi
);
2084 /* Deferred processing of transmit interrupt */
2086 void ath_tx_tasklet(struct ath_softc
*sc
)
2089 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2091 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2094 * Process each active queue.
2096 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2097 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2098 ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2102 void ath_tx_draintxq(struct ath_softc
*sc
,
2103 struct ath_txq
*txq
, bool retry_tx
)
2105 struct ath_buf
*bf
, *lastbf
;
2106 struct list_head bf_head
;
2108 INIT_LIST_HEAD(&bf_head
);
2111 * NB: this assumes output has been stopped and
2112 * we do not need to block ath_tx_tasklet
2115 spin_lock_bh(&txq
->axq_lock
);
2117 if (list_empty(&txq
->axq_q
)) {
2118 txq
->axq_link
= NULL
;
2119 txq
->axq_linkbuf
= NULL
;
2120 spin_unlock_bh(&txq
->axq_lock
);
2124 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2126 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2127 list_del(&bf
->list
);
2128 spin_unlock_bh(&txq
->axq_lock
);
2130 spin_lock_bh(&sc
->sc_txbuflock
);
2131 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2132 spin_unlock_bh(&sc
->sc_txbuflock
);
2136 lastbf
= bf
->bf_lastbf
;
2138 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2139 ATH9K_TX_SW_ABORTED
;
2141 /* remove ath_buf's of the same mpdu from txq */
2142 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2145 spin_unlock_bh(&txq
->axq_lock
);
2148 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2150 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2153 /* flush any pending frames if aggregation is enabled */
2154 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2156 spin_lock_bh(&txq
->axq_lock
);
2157 ath_txq_drain_pending_buffers(sc
, txq
);
2158 spin_unlock_bh(&txq
->axq_lock
);
2163 /* Drain the transmit queues and reclaim resources */
2165 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2167 /* stop beacon queue. The beacon will be freed when
2168 * we go to INIT state */
2169 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2170 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2171 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2172 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2175 ath_drain_txdataq(sc
, retry_tx
);
2178 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2180 return sc
->sc_txq
[qnum
].axq_depth
;
2183 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2185 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2188 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
2190 struct ath_atx_tid
*txtid
;
2192 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2195 txtid
= ATH_AN_2_TID(an
, tidno
);
2197 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2198 if (!(txtid
->state
& AGGR_ADDBA_PROGRESS
) &&
2199 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2200 txtid
->addba_exchangeattempts
++;
2208 /* Start TX aggregation */
2210 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
2213 struct ath_atx_tid
*txtid
;
2214 struct ath_node
*an
;
2216 an
= (struct ath_node
*)sta
->drv_priv
;
2218 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2219 txtid
= ATH_AN_2_TID(an
, tid
);
2220 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
2221 ath_tx_pause_tid(sc
, txtid
);
2227 /* Stop tx aggregation */
2229 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2231 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
2233 ath_tx_aggr_teardown(sc
, an
, tid
);
2237 /* Resume tx aggregation */
2239 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2241 struct ath_atx_tid
*txtid
;
2242 struct ath_node
*an
;
2244 an
= (struct ath_node
*)sta
->drv_priv
;
2246 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2247 txtid
= ATH_AN_2_TID(an
, tid
);
2249 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
2250 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
2251 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2252 ath_tx_resume_tid(sc
, txtid
);
2257 * Performs transmit side cleanup when TID changes from aggregated to
2259 * - Pause the TID and mark cleanup in progress
2260 * - Discard all retry frames from the s/w queue.
2263 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tid
)
2265 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2266 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2268 struct list_head bf_head
;
2269 INIT_LIST_HEAD(&bf_head
);
2271 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2273 if (txtid
->state
& AGGR_CLEANUP
) /* cleanup is in progress */
2276 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2277 txtid
->addba_exchangeattempts
= 0;
2281 /* TID must be paused first */
2282 ath_tx_pause_tid(sc
, txtid
);
2284 /* drop all software retried frames and mark this TID */
2285 spin_lock_bh(&txq
->axq_lock
);
2286 while (!list_empty(&txtid
->buf_q
)) {
2287 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2288 if (!bf_isretried(bf
)) {
2290 * NB: it's based on the assumption that
2291 * software retried frame will always stay
2292 * at the head of software queue.
2296 list_cut_position(&bf_head
,
2297 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2298 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2300 /* complete this sub-frame */
2301 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2304 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2305 spin_unlock_bh(&txq
->axq_lock
);
2306 txtid
->state
|= AGGR_CLEANUP
;
2308 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2309 txtid
->addba_exchangeattempts
= 0;
2310 spin_unlock_bh(&txq
->axq_lock
);
2311 ath_tx_flush_tid(sc
, txtid
);
2316 * Tx scheduling logic
2317 * NB: must be called with txq lock held
2320 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2322 struct ath_atx_ac
*ac
;
2323 struct ath_atx_tid
*tid
;
2325 /* nothing to schedule */
2326 if (list_empty(&txq
->axq_acq
))
2329 * get the first node/ac pair on the queue
2331 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2332 list_del(&ac
->list
);
2336 * process a single tid per destination
2339 /* nothing to schedule */
2340 if (list_empty(&ac
->tid_q
))
2343 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2344 list_del(&tid
->list
);
2347 if (tid
->paused
) /* check next tid to keep h/w busy */
2350 if ((txq
->axq_depth
% 2) == 0)
2351 ath_tx_sched_aggr(sc
, txq
, tid
);
2354 * add tid to round-robin queue if more frames
2355 * are pending for the tid
2357 if (!list_empty(&tid
->buf_q
))
2358 ath_tx_queue_tid(txq
, tid
);
2360 /* only schedule one TID at a time */
2362 } while (!list_empty(&ac
->tid_q
));
2365 * schedule AC if more TIDs need processing
2367 if (!list_empty(&ac
->tid_q
)) {
2369 * add dest ac to txq if not already added
2373 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2378 /* Initialize per-node transmit state */
2380 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2382 struct ath_atx_tid
*tid
;
2383 struct ath_atx_ac
*ac
;
2387 * Init per tid tx state
2389 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2390 tidno
< WME_NUM_TID
;
2394 tid
->seq_start
= tid
->seq_next
= 0;
2395 tid
->baw_size
= WME_MAX_BA
;
2396 tid
->baw_head
= tid
->baw_tail
= 0;
2398 tid
->paused
= false;
2399 tid
->state
&= ~AGGR_CLEANUP
;
2400 INIT_LIST_HEAD(&tid
->buf_q
);
2402 acno
= TID_TO_WME_AC(tidno
);
2403 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2406 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2407 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2408 tid
->addba_exchangeattempts
= 0;
2412 * Init per ac tx state
2414 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2415 acno
< WME_NUM_AC
; acno
++, ac
++) {
2417 INIT_LIST_HEAD(&ac
->tid_q
);
2421 ac
->qnum
= ath_tx_get_qnum(sc
,
2422 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2425 ac
->qnum
= ath_tx_get_qnum(sc
,
2426 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2429 ac
->qnum
= ath_tx_get_qnum(sc
,
2430 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2433 ac
->qnum
= ath_tx_get_qnum(sc
,
2434 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2440 /* Cleanupthe pending buffers for the node. */
2442 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2445 struct ath_atx_ac
*ac
, *ac_tmp
;
2446 struct ath_atx_tid
*tid
, *tid_tmp
;
2447 struct ath_txq
*txq
;
2448 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2449 if (ATH_TXQ_SETUP(sc
, i
)) {
2450 txq
= &sc
->sc_txq
[i
];
2452 spin_lock(&txq
->axq_lock
);
2454 list_for_each_entry_safe(ac
,
2455 ac_tmp
, &txq
->axq_acq
, list
) {
2456 tid
= list_first_entry(&ac
->tid_q
,
2457 struct ath_atx_tid
, list
);
2458 if (tid
&& tid
->an
!= an
)
2460 list_del(&ac
->list
);
2463 list_for_each_entry_safe(tid
,
2464 tid_tmp
, &ac
->tid_q
, list
) {
2465 list_del(&tid
->list
);
2467 ath_tid_drain(sc
, txq
, tid
);
2468 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2469 tid
->addba_exchangeattempts
= 0;
2470 tid
->state
&= ~AGGR_CLEANUP
;
2474 spin_unlock(&txq
->axq_lock
);
2479 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2481 int hdrlen
, padsize
;
2482 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2483 struct ath_tx_control txctl
;
2485 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2488 * As a temporary workaround, assign seq# here; this will likely need
2489 * to be cleaned up to work better with Beacon transmission and virtual
2492 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2493 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2494 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2496 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2497 hdr
->seq_ctrl
|= cpu_to_le16(sc
->seq_no
);
2500 /* Add the padding after the header if this is not already done */
2501 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2503 padsize
= hdrlen
% 4;
2504 if (skb_headroom(skb
) < padsize
) {
2505 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ padding "
2506 "failed\n", __func__
);
2507 dev_kfree_skb_any(skb
);
2510 skb_push(skb
, padsize
);
2511 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2514 txctl
.txq
= sc
->sc_cabq
;
2516 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: transmitting CABQ packet, skb: %p\n",
2520 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2521 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX failed\n", __func__
);
2527 dev_kfree_skb_any(skb
);