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ath9k: Move TX completion routine to xmit.c
[linux-2.6/verdex.git] / drivers / net / wireless / ath9k / main.c
blob54d89abce478feeaac3454872f4d2ee5b019e5c6
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /* mac80211 and PCI callbacks */
18
19 #include <linux/nl80211.h>
20 #include "core.h"
21 #include "reg.h"
22
23 #define ATH_PCI_VERSION "0.1"
24
25 static char *dev_info = "ath9k";
26
27 MODULE_AUTHOR("Atheros Communications");
28 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
29 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
30 MODULE_LICENSE("Dual BSD/GPL");
31
32 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
33 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
34 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
35 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
37 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
38 { 0 }
39 };
40
41 static void ath_detach(struct ath_softc *sc);
42
43 static int ath_get_channel(struct ath_softc *sc,
44 struct ieee80211_channel *chan)
45 {
46 int i;
47
48 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
49 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
50 return i;
51 }
52
53 return -1;
54 }
55
56 static u32 ath_get_extchanmode(struct ath_softc *sc,
57 struct ieee80211_channel *chan)
58 {
59 u32 chanmode = 0;
60 u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
61 enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
62
63 switch (chan->band) {
64 case IEEE80211_BAND_2GHZ:
65 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
66 (tx_chan_width == ATH9K_HT_MACMODE_20))
67 chanmode = CHANNEL_G_HT20;
68 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
69 (tx_chan_width == ATH9K_HT_MACMODE_2040))
70 chanmode = CHANNEL_G_HT40PLUS;
71 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
72 (tx_chan_width == ATH9K_HT_MACMODE_2040))
73 chanmode = CHANNEL_G_HT40MINUS;
74 break;
75 case IEEE80211_BAND_5GHZ:
76 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
77 (tx_chan_width == ATH9K_HT_MACMODE_20))
78 chanmode = CHANNEL_A_HT20;
79 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
80 (tx_chan_width == ATH9K_HT_MACMODE_2040))
81 chanmode = CHANNEL_A_HT40PLUS;
82 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
83 (tx_chan_width == ATH9K_HT_MACMODE_2040))
84 chanmode = CHANNEL_A_HT40MINUS;
85 break;
86 default:
87 break;
88 }
89
90 return chanmode;
91 }
92
93
94 static int ath_setkey_tkip(struct ath_softc *sc,
95 struct ieee80211_key_conf *key,
96 struct ath9k_keyval *hk,
97 const u8 *addr)
98 {
99 u8 *key_rxmic = NULL;
100 u8 *key_txmic = NULL;
101
102 key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
103 key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
104
105 if (addr == NULL) {
106 /* Group key installation */
107 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
108 return ath_keyset(sc, key->keyidx, hk, addr);
109 }
110 if (!sc->sc_splitmic) {
111 /*
112 * data key goes at first index,
113 * the hal handles the MIC keys at index+64.
114 */
115 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
116 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
117 return ath_keyset(sc, key->keyidx, hk, addr);
118 }
119 /*
120 * TX key goes at first index, RX key at +32.
121 * The hal handles the MIC keys at index+64.
122 */
123 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
124 if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
125 /* Txmic entry failed. No need to proceed further */
126 DPRINTF(sc, ATH_DBG_KEYCACHE,
127 "%s Setting TX MIC Key Failed\n", __func__);
128 return 0;
129 }
130
131 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
132 /* XXX delete tx key on failure? */
133 return ath_keyset(sc, key->keyidx+32, hk, addr);
134 }
135
136 static int ath_key_config(struct ath_softc *sc,
137 const u8 *addr,
138 struct ieee80211_key_conf *key)
139 {
140 struct ieee80211_vif *vif;
141 struct ath9k_keyval hk;
142 const u8 *mac = NULL;
143 int ret = 0;
144 enum nl80211_iftype opmode;
145
146 memset(&hk, 0, sizeof(hk));
147
148 switch (key->alg) {
149 case ALG_WEP:
150 hk.kv_type = ATH9K_CIPHER_WEP;
151 break;
152 case ALG_TKIP:
153 hk.kv_type = ATH9K_CIPHER_TKIP;
154 break;
155 case ALG_CCMP:
156 hk.kv_type = ATH9K_CIPHER_AES_CCM;
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 hk.kv_len = key->keylen;
163 memcpy(hk.kv_val, key->key, key->keylen);
164
165 if (!sc->sc_vaps[0])
166 return -EIO;
167
168 vif = sc->sc_vaps[0];
169 opmode = vif->type;
170
171 /*
172 * Strategy:
173 * For _M_STA mc tx, we will not setup a key at all since we never
174 * tx mc.
175 * _M_STA mc rx, we will use the keyID.
176 * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
177 * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
178 * peer node. BUT we will plumb a cleartext key so that we can do
179 * perSta default key table lookup in software.
180 */
181 if (is_broadcast_ether_addr(addr)) {
182 switch (opmode) {
183 case NL80211_IFTYPE_STATION:
184 /* default key: could be group WPA key
185 * or could be static WEP key */
186 mac = NULL;
187 break;
188 case NL80211_IFTYPE_ADHOC:
189 break;
190 case NL80211_IFTYPE_AP:
191 break;
192 default:
193 ASSERT(0);
194 break;
195 }
196 } else {
197 mac = addr;
198 }
199
200 if (key->alg == ALG_TKIP)
201 ret = ath_setkey_tkip(sc, key, &hk, mac);
202 else
203 ret = ath_keyset(sc, key->keyidx, &hk, mac);
204
205 if (!ret)
206 return -EIO;
207
208 return 0;
209 }
210
211 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
212 {
213 int freeslot;
214
215 freeslot = (key->keyidx >= 4) ? 1 : 0;
216 ath_key_reset(sc, key->keyidx, freeslot);
217 }
218
219 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
220 {
221 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
222 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
223
224 ht_info->ht_supported = true;
225 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
226 IEEE80211_HT_CAP_SM_PS |
227 IEEE80211_HT_CAP_SGI_40 |
228 IEEE80211_HT_CAP_DSSSCCK40;
229
230 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
231 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
232 /* set up supported mcs set */
233 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
234 ht_info->mcs.rx_mask[0] = 0xff;
235 ht_info->mcs.rx_mask[1] = 0xff;
236 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
237 }
238
239 static void ath9k_ht_conf(struct ath_softc *sc,
240 struct ieee80211_bss_conf *bss_conf)
241 {
242 struct ath_ht_info *ht_info = &sc->sc_ht_info;
243
244 if (sc->hw->conf.ht.enabled) {
245 ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
246
247 if (bss_conf->ht.width_40_ok)
248 ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
249 else
250 ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
251
252 ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
253 }
254 }
255
256 static void ath9k_bss_assoc_info(struct ath_softc *sc,
257 struct ieee80211_vif *vif,
258 struct ieee80211_bss_conf *bss_conf)
259 {
260 struct ieee80211_hw *hw = sc->hw;
261 struct ieee80211_channel *curchan = hw->conf.channel;
262 struct ath_vap *avp = (void *)vif->drv_priv;
263 int pos;
264
265 if (bss_conf->assoc) {
266 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
267 __func__,
268 bss_conf->aid);
269
270 /* New association, store aid */
271 if (avp->av_opmode == ATH9K_M_STA) {
272 sc->sc_curaid = bss_conf->aid;
273 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
274 sc->sc_curaid);
275 }
276
277 /* Configure the beacon */
278 ath_beacon_config(sc, 0);
279 sc->sc_flags |= SC_OP_BEACONS;
280
281 /* Reset rssi stats */
282 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
283 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
284 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
285 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
286
287 /* Update chainmask */
288 ath_update_chainmask(sc, hw->conf.ht.enabled);
289
290 DPRINTF(sc, ATH_DBG_CONFIG,
291 "%s: bssid %pM aid 0x%x\n",
292 __func__,
293 sc->sc_curbssid, sc->sc_curaid);
294
295 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
296 __func__,
297 curchan->center_freq);
298
299 pos = ath_get_channel(sc, curchan);
300 if (pos == -1) {
301 DPRINTF(sc, ATH_DBG_FATAL,
302 "%s: Invalid channel\n", __func__);
303 return;
304 }
305
306 if (hw->conf.ht.enabled)
307 sc->sc_ah->ah_channels[pos].chanmode =
308 ath_get_extchanmode(sc, curchan);
309 else
310 sc->sc_ah->ah_channels[pos].chanmode =
311 (curchan->band == IEEE80211_BAND_2GHZ) ?
312 CHANNEL_G : CHANNEL_A;
313
314 /* set h/w channel */
315 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
316 DPRINTF(sc, ATH_DBG_FATAL,
317 "%s: Unable to set channel\n",
318 __func__);
319 /* Start ANI */
320 mod_timer(&sc->sc_ani.timer,
321 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
322
323 } else {
324 DPRINTF(sc, ATH_DBG_CONFIG,
325 "%s: Bss Info DISSOC\n", __func__);
326 sc->sc_curaid = 0;
327 }
328 }
329
330 void ath_get_beaconconfig(struct ath_softc *sc,
331 int if_id,
332 struct ath_beacon_config *conf)
333 {
334 struct ieee80211_hw *hw = sc->hw;
335
336 /* fill in beacon config data */
337
338 conf->beacon_interval = hw->conf.beacon_int;
339 conf->listen_interval = 100;
340 conf->dtim_count = 1;
341 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
342 }
343
344 /********************************/
345 /* LED functions */
346 /********************************/
347
348 static void ath_led_brightness(struct led_classdev *led_cdev,
349 enum led_brightness brightness)
350 {
351 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
352 struct ath_softc *sc = led->sc;
353
354 switch (brightness) {
355 case LED_OFF:
356 if (led->led_type == ATH_LED_ASSOC ||
357 led->led_type == ATH_LED_RADIO)
358 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
359 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
360 (led->led_type == ATH_LED_RADIO) ? 1 :
361 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
362 break;
363 case LED_FULL:
364 if (led->led_type == ATH_LED_ASSOC)
365 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
366 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
367 break;
368 default:
369 break;
370 }
371 }
372
373 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
374 char *trigger)
375 {
376 int ret;
377
378 led->sc = sc;
379 led->led_cdev.name = led->name;
380 led->led_cdev.default_trigger = trigger;
381 led->led_cdev.brightness_set = ath_led_brightness;
382
383 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
384 if (ret)
385 DPRINTF(sc, ATH_DBG_FATAL,
386 "Failed to register led:%s", led->name);
387 else
388 led->registered = 1;
389 return ret;
390 }
391
392 static void ath_unregister_led(struct ath_led *led)
393 {
394 if (led->registered) {
395 led_classdev_unregister(&led->led_cdev);
396 led->registered = 0;
397 }
398 }
399
400 static void ath_deinit_leds(struct ath_softc *sc)
401 {
402 ath_unregister_led(&sc->assoc_led);
403 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
404 ath_unregister_led(&sc->tx_led);
405 ath_unregister_led(&sc->rx_led);
406 ath_unregister_led(&sc->radio_led);
407 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
408 }
409
410 static void ath_init_leds(struct ath_softc *sc)
411 {
412 char *trigger;
413 int ret;
414
415 /* Configure gpio 1 for output */
416 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
417 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
418 /* LED off, active low */
419 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
420
421 trigger = ieee80211_get_radio_led_name(sc->hw);
422 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
423 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
424 ret = ath_register_led(sc, &sc->radio_led, trigger);
425 sc->radio_led.led_type = ATH_LED_RADIO;
426 if (ret)
427 goto fail;
428
429 trigger = ieee80211_get_assoc_led_name(sc->hw);
430 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
431 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
432 ret = ath_register_led(sc, &sc->assoc_led, trigger);
433 sc->assoc_led.led_type = ATH_LED_ASSOC;
434 if (ret)
435 goto fail;
436
437 trigger = ieee80211_get_tx_led_name(sc->hw);
438 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
439 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
440 ret = ath_register_led(sc, &sc->tx_led, trigger);
441 sc->tx_led.led_type = ATH_LED_TX;
442 if (ret)
443 goto fail;
444
445 trigger = ieee80211_get_rx_led_name(sc->hw);
446 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
447 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
448 ret = ath_register_led(sc, &sc->rx_led, trigger);
449 sc->rx_led.led_type = ATH_LED_RX;
450 if (ret)
451 goto fail;
452
453 return;
454
455 fail:
456 ath_deinit_leds(sc);
457 }
458
459 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
460
461 /*******************/
462 /* Rfkill */
463 /*******************/
464
465 static void ath_radio_enable(struct ath_softc *sc)
466 {
467 struct ath_hal *ah = sc->sc_ah;
468 int status;
469
470 spin_lock_bh(&sc->sc_resetlock);
471 if (!ath9k_hw_reset(ah, ah->ah_curchan,
472 sc->sc_ht_info.tx_chan_width,
473 sc->sc_tx_chainmask,
474 sc->sc_rx_chainmask,
475 sc->sc_ht_extprotspacing,
476 false, &status)) {
477 DPRINTF(sc, ATH_DBG_FATAL,
478 "%s: unable to reset channel %u (%uMhz) "
479 "flags 0x%x hal status %u\n", __func__,
480 ath9k_hw_mhz2ieee(ah,
481 ah->ah_curchan->channel,
482 ah->ah_curchan->channelFlags),
483 ah->ah_curchan->channel,
484 ah->ah_curchan->channelFlags, status);
485 }
486 spin_unlock_bh(&sc->sc_resetlock);
487
488 ath_update_txpow(sc);
489 if (ath_startrecv(sc) != 0) {
490 DPRINTF(sc, ATH_DBG_FATAL,
491 "%s: unable to restart recv logic\n", __func__);
492 return;
493 }
494
495 if (sc->sc_flags & SC_OP_BEACONS)
496 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
497
498 /* Re-Enable interrupts */
499 ath9k_hw_set_interrupts(ah, sc->sc_imask);
500
501 /* Enable LED */
502 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
503 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
504 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
505
506 ieee80211_wake_queues(sc->hw);
507 }
508
509 static void ath_radio_disable(struct ath_softc *sc)
510 {
511 struct ath_hal *ah = sc->sc_ah;
512 int status;
513
514
515 ieee80211_stop_queues(sc->hw);
516
517 /* Disable LED */
518 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
519 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
520
521 /* Disable interrupts */
522 ath9k_hw_set_interrupts(ah, 0);
523
524 ath_draintxq(sc, false); /* clear pending tx frames */
525 ath_stoprecv(sc); /* turn off frame recv */
526 ath_flushrecv(sc); /* flush recv queue */
527
528 spin_lock_bh(&sc->sc_resetlock);
529 if (!ath9k_hw_reset(ah, ah->ah_curchan,
530 sc->sc_ht_info.tx_chan_width,
531 sc->sc_tx_chainmask,
532 sc->sc_rx_chainmask,
533 sc->sc_ht_extprotspacing,
534 false, &status)) {
535 DPRINTF(sc, ATH_DBG_FATAL,
536 "%s: unable to reset channel %u (%uMhz) "
537 "flags 0x%x hal status %u\n", __func__,
538 ath9k_hw_mhz2ieee(ah,
539 ah->ah_curchan->channel,
540 ah->ah_curchan->channelFlags),
541 ah->ah_curchan->channel,
542 ah->ah_curchan->channelFlags, status);
543 }
544 spin_unlock_bh(&sc->sc_resetlock);
545
546 ath9k_hw_phy_disable(ah);
547 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
548 }
549
550 static bool ath_is_rfkill_set(struct ath_softc *sc)
551 {
552 struct ath_hal *ah = sc->sc_ah;
553
554 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
555 ah->ah_rfkill_polarity;
556 }
557
558 /* h/w rfkill poll function */
559 static void ath_rfkill_poll(struct work_struct *work)
560 {
561 struct ath_softc *sc = container_of(work, struct ath_softc,
562 rf_kill.rfkill_poll.work);
563 bool radio_on;
564
565 if (sc->sc_flags & SC_OP_INVALID)
566 return;
567
568 radio_on = !ath_is_rfkill_set(sc);
569
570 /*
571 * enable/disable radio only when there is a
572 * state change in RF switch
573 */
574 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
575 enum rfkill_state state;
576
577 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
578 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
579 : RFKILL_STATE_HARD_BLOCKED;
580 } else if (radio_on) {
581 ath_radio_enable(sc);
582 state = RFKILL_STATE_UNBLOCKED;
583 } else {
584 ath_radio_disable(sc);
585 state = RFKILL_STATE_HARD_BLOCKED;
586 }
587
588 if (state == RFKILL_STATE_HARD_BLOCKED)
589 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
590 else
591 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
592
593 rfkill_force_state(sc->rf_kill.rfkill, state);
594 }
595
596 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
597 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
598 }
599
600 /* s/w rfkill handler */
601 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
602 {
603 struct ath_softc *sc = data;
604
605 switch (state) {
606 case RFKILL_STATE_SOFT_BLOCKED:
607 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
608 SC_OP_RFKILL_SW_BLOCKED)))
609 ath_radio_disable(sc);
610 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
611 return 0;
612 case RFKILL_STATE_UNBLOCKED:
613 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
614 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
615 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
616 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
617 "radio as it is disabled by h/w \n");
618 return -EPERM;
619 }
620 ath_radio_enable(sc);
621 }
622 return 0;
623 default:
624 return -EINVAL;
625 }
626 }
627
628 /* Init s/w rfkill */
629 static int ath_init_sw_rfkill(struct ath_softc *sc)
630 {
631 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
632 RFKILL_TYPE_WLAN);
633 if (!sc->rf_kill.rfkill) {
634 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
635 return -ENOMEM;
636 }
637
638 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
639 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
640 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
641 sc->rf_kill.rfkill->data = sc;
642 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
643 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
644 sc->rf_kill.rfkill->user_claim_unsupported = 1;
645
646 return 0;
647 }
648
649 /* Deinitialize rfkill */
650 static void ath_deinit_rfkill(struct ath_softc *sc)
651 {
652 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
653 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
654
655 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
656 rfkill_unregister(sc->rf_kill.rfkill);
657 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
658 sc->rf_kill.rfkill = NULL;
659 }
660 }
661
662 static int ath_start_rfkill_poll(struct ath_softc *sc)
663 {
664 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
665 queue_delayed_work(sc->hw->workqueue,
666 &sc->rf_kill.rfkill_poll, 0);
667
668 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
669 if (rfkill_register(sc->rf_kill.rfkill)) {
670 DPRINTF(sc, ATH_DBG_FATAL,
671 "Unable to register rfkill\n");
672 rfkill_free(sc->rf_kill.rfkill);
673
674 /* Deinitialize the device */
675 ath_detach(sc);
676 if (sc->pdev->irq)
677 free_irq(sc->pdev->irq, sc);
678 pci_iounmap(sc->pdev, sc->mem);
679 pci_release_region(sc->pdev, 0);
680 pci_disable_device(sc->pdev);
681 ieee80211_free_hw(sc->hw);
682 return -EIO;
683 } else {
684 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
685 }
686 }
687
688 return 0;
689 }
690 #endif /* CONFIG_RFKILL */
691
692 static void ath_detach(struct ath_softc *sc)
693 {
694 struct ieee80211_hw *hw = sc->hw;
695 int i = 0;
696
697 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
698
699 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
700 ath_deinit_rfkill(sc);
701 #endif
702 ath_deinit_leds(sc);
703
704 ieee80211_unregister_hw(hw);
705
706 ath_rate_control_unregister();
707
708 ath_rx_cleanup(sc);
709 ath_tx_cleanup(sc);
710
711 tasklet_kill(&sc->intr_tq);
712 tasklet_kill(&sc->bcon_tasklet);
713
714 if (!(sc->sc_flags & SC_OP_INVALID))
715 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
716
717 /* cleanup tx queues */
718 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
719 if (ATH_TXQ_SETUP(sc, i))
720 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
721
722 ath9k_hw_detach(sc->sc_ah);
723 }
724
725 static int ath_attach(u16 devid, struct ath_softc *sc)
726 {
727 struct ieee80211_hw *hw = sc->hw;
728 int error = 0;
729
730 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
731
732 error = ath_init(devid, sc);
733 if (error != 0)
734 return error;
735
736 /* get mac address from hardware and set in mac80211 */
737
738 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
739
740 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
741 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
742 IEEE80211_HW_SIGNAL_DBM |
743 IEEE80211_HW_AMPDU_AGGREGATION;
744
745 hw->wiphy->interface_modes =
746 BIT(NL80211_IFTYPE_AP) |
747 BIT(NL80211_IFTYPE_STATION) |
748 BIT(NL80211_IFTYPE_ADHOC);
749
750 hw->queues = 4;
751 hw->max_rates = 4;
752 hw->max_rate_tries = ATH_11N_TXMAXTRY;
753 hw->sta_data_size = sizeof(struct ath_node);
754 hw->vif_data_size = sizeof(struct ath_vap);
755
756 /* Register rate control */
757 hw->rate_control_algorithm = "ath9k_rate_control";
758 error = ath_rate_control_register();
759 if (error != 0) {
760 DPRINTF(sc, ATH_DBG_FATAL,
761 "%s: Unable to register rate control "
762 "algorithm:%d\n", __func__, error);
763 ath_rate_control_unregister();
764 goto bad;
765 }
766
767 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
768 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
769 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
770 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
771 }
772
773 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
774 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
775 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
776 &sc->sbands[IEEE80211_BAND_5GHZ];
777
778 /* initialize tx/rx engine */
779 error = ath_tx_init(sc, ATH_TXBUF);
780 if (error != 0)
781 goto detach;
782
783 error = ath_rx_init(sc, ATH_RXBUF);
784 if (error != 0)
785 goto detach;
786
787 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
788 /* Initialze h/w Rfkill */
789 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
790 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
791
792 /* Initialize s/w rfkill */
793 if (ath_init_sw_rfkill(sc))
794 goto detach;
795 #endif
796
797 error = ieee80211_register_hw(hw);
798 if (error != 0) {
799 ath_rate_control_unregister();
800 goto bad;
801 }
802
803 /* Initialize LED control */
804 ath_init_leds(sc);
805
806 return 0;
807 detach:
808 ath_detach(sc);
809 bad:
810 return error;
811 }
812
813 static int ath9k_start(struct ieee80211_hw *hw)
814 {
815 struct ath_softc *sc = hw->priv;
816 struct ieee80211_channel *curchan = hw->conf.channel;
817 int error = 0, pos;
818
819 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
820 "initial channel: %d MHz\n", __func__, curchan->center_freq);
821
822 memset(&sc->sc_ht_info, 0, sizeof(struct ath_ht_info));
823
824 /* setup initial channel */
825
826 pos = ath_get_channel(sc, curchan);
827 if (pos == -1) {
828 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
829 error = -EINVAL;
830 goto exit;
831 }
832
833 sc->sc_ah->ah_channels[pos].chanmode =
834 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
835
836 error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
837 if (error) {
838 DPRINTF(sc, ATH_DBG_FATAL,
839 "%s: Unable to complete ath_open\n", __func__);
840 goto exit;
841 }
842
843 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
844 error = ath_start_rfkill_poll(sc);
845 #endif
846
847 exit:
848 return error;
849 }
850
851 static int ath9k_tx(struct ieee80211_hw *hw,
852 struct sk_buff *skb)
853 {
854 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
855 struct ath_softc *sc = hw->priv;
856 struct ath_tx_control txctl;
857 int hdrlen, padsize;
858
859 memset(&txctl, 0, sizeof(struct ath_tx_control));
860
861 /*
862 * As a temporary workaround, assign seq# here; this will likely need
863 * to be cleaned up to work better with Beacon transmission and virtual
864 * BSSes.
865 */
866 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
867 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
868 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
869 sc->seq_no += 0x10;
870 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
871 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
872 }
873
874 /* Add the padding after the header if this is not already done */
875 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
876 if (hdrlen & 3) {
877 padsize = hdrlen % 4;
878 if (skb_headroom(skb) < padsize)
879 return -1;
880 skb_push(skb, padsize);
881 memmove(skb->data, skb->data + padsize, hdrlen);
882 }
883
884 /* Check if a tx queue is available */
885
886 txctl.txq = ath_test_get_txq(sc, skb);
887 if (!txctl.txq)
888 goto exit;
889
890 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
891 __func__,
892 skb);
893
894 if (ath_tx_start(sc, skb, &txctl) != 0) {
895 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
896 goto exit;
897 }
898
899 return 0;
900 exit:
901 dev_kfree_skb_any(skb);
902 return 0;
903 }
904
905 static void ath9k_stop(struct ieee80211_hw *hw)
906 {
907 struct ath_softc *sc = hw->priv;
908
909 if (sc->sc_flags & SC_OP_INVALID) {
910 DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
911 return;
912 }
913
914 ath_stop(sc);
915
916 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
917 }
918
919 static int ath9k_add_interface(struct ieee80211_hw *hw,
920 struct ieee80211_if_init_conf *conf)
921 {
922 struct ath_softc *sc = hw->priv;
923 struct ath_vap *avp = (void *)conf->vif->drv_priv;
924 int ic_opmode = 0;
925
926 /* Support only vap for now */
927
928 if (sc->sc_nvaps)
929 return -ENOBUFS;
930
931 switch (conf->type) {
932 case NL80211_IFTYPE_STATION:
933 ic_opmode = ATH9K_M_STA;
934 break;
935 case NL80211_IFTYPE_ADHOC:
936 ic_opmode = ATH9K_M_IBSS;
937 break;
938 case NL80211_IFTYPE_AP:
939 ic_opmode = ATH9K_M_HOSTAP;
940 break;
941 default:
942 DPRINTF(sc, ATH_DBG_FATAL,
943 "%s: Interface type %d not yet supported\n",
944 __func__, conf->type);
945 return -EOPNOTSUPP;
946 }
947
948 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
949 __func__,
950 ic_opmode);
951
952 /* Set the VAP opmode */
953 avp->av_opmode = ic_opmode;
954 avp->av_bslot = -1;
955
956 if (ic_opmode == ATH9K_M_HOSTAP)
957 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
958
959 sc->sc_vaps[0] = conf->vif;
960 sc->sc_nvaps++;
961
962 /* Set the device opmode */
963 sc->sc_ah->ah_opmode = ic_opmode;
964
965 if (conf->type == NL80211_IFTYPE_AP) {
966 /* TODO: is this a suitable place to start ANI for AP mode? */
967 /* Start ANI */
968 mod_timer(&sc->sc_ani.timer,
969 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
970 }
971
972 return 0;
973 }
974
975 static void ath9k_remove_interface(struct ieee80211_hw *hw,
976 struct ieee80211_if_init_conf *conf)
977 {
978 struct ath_softc *sc = hw->priv;
979 struct ath_vap *avp = (void *)conf->vif->drv_priv;
980
981 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
982
983 #ifdef CONFIG_SLOW_ANT_DIV
984 ath_slow_ant_div_stop(&sc->sc_antdiv);
985 #endif
986 /* Stop ANI */
987 del_timer_sync(&sc->sc_ani.timer);
988
989 /* Reclaim beacon resources */
990 if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
991 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
992 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
993 ath_beacon_return(sc, avp);
994 }
995
996 sc->sc_flags &= ~SC_OP_BEACONS;
997
998 sc->sc_vaps[0] = NULL;
999 sc->sc_nvaps--;
1000 }
1001
1002 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1003 {
1004 struct ath_softc *sc = hw->priv;
1005 struct ieee80211_channel *curchan = hw->conf.channel;
1006 struct ieee80211_conf *conf = &hw->conf;
1007 int pos;
1008
1009 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
1010 __func__,
1011 curchan->center_freq);
1012
1013 /* Update chainmask */
1014 ath_update_chainmask(sc, conf->ht.enabled);
1015
1016 pos = ath_get_channel(sc, curchan);
1017 if (pos == -1) {
1018 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1019 return -EINVAL;
1020 }
1021
1022 sc->sc_ah->ah_channels[pos].chanmode =
1023 (curchan->band == IEEE80211_BAND_2GHZ) ?
1024 CHANNEL_G : CHANNEL_A;
1025
1026 if (sc->sc_curaid && hw->conf.ht.enabled)
1027 sc->sc_ah->ah_channels[pos].chanmode =
1028 ath_get_extchanmode(sc, curchan);
1029
1030 if (changed & IEEE80211_CONF_CHANGE_POWER)
1031 sc->sc_config.txpowlimit = 2 * conf->power_level;
1032
1033 /* set h/w channel */
1034 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
1035 DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
1036 __func__);
1037
1038 return 0;
1039 }
1040
1041 static int ath9k_config_interface(struct ieee80211_hw *hw,
1042 struct ieee80211_vif *vif,
1043 struct ieee80211_if_conf *conf)
1044 {
1045 struct ath_softc *sc = hw->priv;
1046 struct ath_hal *ah = sc->sc_ah;
1047 struct ath_vap *avp = (void *)vif->drv_priv;
1048 u32 rfilt = 0;
1049 int error, i;
1050
1051 /* TODO: Need to decide which hw opmode to use for multi-interface
1052 * cases */
1053 if (vif->type == NL80211_IFTYPE_AP &&
1054 ah->ah_opmode != ATH9K_M_HOSTAP) {
1055 ah->ah_opmode = ATH9K_M_HOSTAP;
1056 ath9k_hw_setopmode(ah);
1057 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
1058 /* Request full reset to get hw opmode changed properly */
1059 sc->sc_flags |= SC_OP_FULL_RESET;
1060 }
1061
1062 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
1063 !is_zero_ether_addr(conf->bssid)) {
1064 switch (vif->type) {
1065 case NL80211_IFTYPE_STATION:
1066 case NL80211_IFTYPE_ADHOC:
1067 /* Set BSSID */
1068 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
1069 sc->sc_curaid = 0;
1070 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
1071 sc->sc_curaid);
1072
1073 /* Set aggregation protection mode parameters */
1074 sc->sc_config.ath_aggr_prot = 0;
1075
1076 DPRINTF(sc, ATH_DBG_CONFIG,
1077 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
1078 __func__, rfilt,
1079 sc->sc_curbssid, sc->sc_curaid);
1080
1081 /* need to reconfigure the beacon */
1082 sc->sc_flags &= ~SC_OP_BEACONS ;
1083
1084 break;
1085 default:
1086 break;
1087 }
1088 }
1089
1090 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
1091 ((vif->type == NL80211_IFTYPE_ADHOC) ||
1092 (vif->type == NL80211_IFTYPE_AP))) {
1093 /*
1094 * Allocate and setup the beacon frame.
1095 *
1096 * Stop any previous beacon DMA. This may be
1097 * necessary, for example, when an ibss merge
1098 * causes reconfiguration; we may be called
1099 * with beacon transmission active.
1100 */
1101 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
1102
1103 error = ath_beacon_alloc(sc, 0);
1104 if (error != 0)
1105 return error;
1106
1107 ath_beacon_sync(sc, 0);
1108 }
1109
1110 /* Check for WLAN_CAPABILITY_PRIVACY ? */
1111 if ((avp->av_opmode != ATH9K_M_STA)) {
1112 for (i = 0; i < IEEE80211_WEP_NKID; i++)
1113 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
1114 ath9k_hw_keysetmac(sc->sc_ah,
1115 (u16)i,
1116 sc->sc_curbssid);
1117 }
1118
1119 /* Only legacy IBSS for now */
1120 if (vif->type == NL80211_IFTYPE_ADHOC)
1121 ath_update_chainmask(sc, 0);
1122
1123 return 0;
1124 }
1125
1126 #define SUPPORTED_FILTERS \
1127 (FIF_PROMISC_IN_BSS | \
1128 FIF_ALLMULTI | \
1129 FIF_CONTROL | \
1130 FIF_OTHER_BSS | \
1131 FIF_BCN_PRBRESP_PROMISC | \
1132 FIF_FCSFAIL)
1133
1134 /* FIXME: sc->sc_full_reset ? */
1135 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1136 unsigned int changed_flags,
1137 unsigned int *total_flags,
1138 int mc_count,
1139 struct dev_mc_list *mclist)
1140 {
1141 struct ath_softc *sc = hw->priv;
1142 u32 rfilt;
1143
1144 changed_flags &= SUPPORTED_FILTERS;
1145 *total_flags &= SUPPORTED_FILTERS;
1146
1147 sc->rx_filter = *total_flags;
1148 rfilt = ath_calcrxfilter(sc);
1149 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1150
1151 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1152 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1153 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
1154 }
1155
1156 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
1157 __func__, sc->rx_filter);
1158 }
1159
1160 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1161 struct ieee80211_vif *vif,
1162 enum sta_notify_cmd cmd,
1163 struct ieee80211_sta *sta)
1164 {
1165 struct ath_softc *sc = hw->priv;
1166
1167 switch (cmd) {
1168 case STA_NOTIFY_ADD:
1169 ath_node_attach(sc, sta);
1170 break;
1171 case STA_NOTIFY_REMOVE:
1172 ath_node_detach(sc, sta);
1173 break;
1174 default:
1175 break;
1176 }
1177 }
1178
1179 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1180 u16 queue,
1181 const struct ieee80211_tx_queue_params *params)
1182 {
1183 struct ath_softc *sc = hw->priv;
1184 struct ath9k_tx_queue_info qi;
1185 int ret = 0, qnum;
1186
1187 if (queue >= WME_NUM_AC)
1188 return 0;
1189
1190 qi.tqi_aifs = params->aifs;
1191 qi.tqi_cwmin = params->cw_min;
1192 qi.tqi_cwmax = params->cw_max;
1193 qi.tqi_burstTime = params->txop;
1194 qnum = ath_get_hal_qnum(queue, sc);
1195
1196 DPRINTF(sc, ATH_DBG_CONFIG,
1197 "%s: Configure tx [queue/halq] [%d/%d], "
1198 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1199 __func__,
1200 queue,
1201 qnum,
1202 params->aifs,
1203 params->cw_min,
1204 params->cw_max,
1205 params->txop);
1206
1207 ret = ath_txq_update(sc, qnum, &qi);
1208 if (ret)
1209 DPRINTF(sc, ATH_DBG_FATAL,
1210 "%s: TXQ Update failed\n", __func__);
1211
1212 return ret;
1213 }
1214
1215 static int ath9k_set_key(struct ieee80211_hw *hw,
1216 enum set_key_cmd cmd,
1217 const u8 *local_addr,
1218 const u8 *addr,
1219 struct ieee80211_key_conf *key)
1220 {
1221 struct ath_softc *sc = hw->priv;
1222 int ret = 0;
1223
1224 DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
1225
1226 switch (cmd) {
1227 case SET_KEY:
1228 ret = ath_key_config(sc, addr, key);
1229 if (!ret) {
1230 set_bit(key->keyidx, sc->sc_keymap);
1231 key->hw_key_idx = key->keyidx;
1232 /* push IV and Michael MIC generation to stack */
1233 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1234 if (key->alg == ALG_TKIP)
1235 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1236 }
1237 break;
1238 case DISABLE_KEY:
1239 ath_key_delete(sc, key);
1240 clear_bit(key->keyidx, sc->sc_keymap);
1241 break;
1242 default:
1243 ret = -EINVAL;
1244 }
1245
1246 return ret;
1247 }
1248
1249 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1250 struct ieee80211_vif *vif,
1251 struct ieee80211_bss_conf *bss_conf,
1252 u32 changed)
1253 {
1254 struct ath_softc *sc = hw->priv;
1255
1256 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1257 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
1258 __func__,
1259 bss_conf->use_short_preamble);
1260 if (bss_conf->use_short_preamble)
1261 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1262 else
1263 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1264 }
1265
1266 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1267 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
1268 __func__,
1269 bss_conf->use_cts_prot);
1270 if (bss_conf->use_cts_prot &&
1271 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1272 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1273 else
1274 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1275 }
1276
1277 if (changed & BSS_CHANGED_HT) {
1278 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
1279 __func__);
1280 ath9k_ht_conf(sc, bss_conf);
1281 }
1282
1283 if (changed & BSS_CHANGED_ASSOC) {
1284 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
1285 __func__,
1286 bss_conf->assoc);
1287 ath9k_bss_assoc_info(sc, vif, bss_conf);
1288 }
1289 }
1290
1291 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1292 {
1293 u64 tsf;
1294 struct ath_softc *sc = hw->priv;
1295 struct ath_hal *ah = sc->sc_ah;
1296
1297 tsf = ath9k_hw_gettsf64(ah);
1298
1299 return tsf;
1300 }
1301
1302 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1303 {
1304 struct ath_softc *sc = hw->priv;
1305 struct ath_hal *ah = sc->sc_ah;
1306
1307 ath9k_hw_reset_tsf(ah);
1308 }
1309
1310 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1311 enum ieee80211_ampdu_mlme_action action,
1312 struct ieee80211_sta *sta,
1313 u16 tid, u16 *ssn)
1314 {
1315 struct ath_softc *sc = hw->priv;
1316 int ret = 0;
1317
1318 switch (action) {
1319 case IEEE80211_AMPDU_RX_START:
1320 if (!(sc->sc_flags & SC_OP_RXAGGR))
1321 ret = -ENOTSUPP;
1322 break;
1323 case IEEE80211_AMPDU_RX_STOP:
1324 break;
1325 case IEEE80211_AMPDU_TX_START:
1326 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1327 if (ret < 0)
1328 DPRINTF(sc, ATH_DBG_FATAL,
1329 "%s: Unable to start TX aggregation\n",
1330 __func__);
1331 else
1332 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
1333 break;
1334 case IEEE80211_AMPDU_TX_STOP:
1335 ret = ath_tx_aggr_stop(sc, sta, tid);
1336 if (ret < 0)
1337 DPRINTF(sc, ATH_DBG_FATAL,
1338 "%s: Unable to stop TX aggregation\n",
1339 __func__);
1340
1341 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
1342 break;
1343 case IEEE80211_AMPDU_TX_RESUME:
1344 ath_tx_aggr_resume(sc, sta, tid);
1345 break;
1346 default:
1347 DPRINTF(sc, ATH_DBG_FATAL,
1348 "%s: Unknown AMPDU action\n", __func__);
1349 }
1350
1351 return ret;
1352 }
1353
1354 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
1355 {
1356 return -EOPNOTSUPP;
1357 }
1358
1359 static struct ieee80211_ops ath9k_ops = {
1360 .tx = ath9k_tx,
1361 .start = ath9k_start,
1362 .stop = ath9k_stop,
1363 .add_interface = ath9k_add_interface,
1364 .remove_interface = ath9k_remove_interface,
1365 .config = ath9k_config,
1366 .config_interface = ath9k_config_interface,
1367 .configure_filter = ath9k_configure_filter,
1368 .sta_notify = ath9k_sta_notify,
1369 .conf_tx = ath9k_conf_tx,
1370 .bss_info_changed = ath9k_bss_info_changed,
1371 .set_key = ath9k_set_key,
1372 .get_tsf = ath9k_get_tsf,
1373 .reset_tsf = ath9k_reset_tsf,
1374 .ampdu_action = ath9k_ampdu_action,
1375 .set_frag_threshold = ath9k_no_fragmentation,
1376 };
1377
1378 static struct {
1379 u32 version;
1380 const char * name;
1381 } ath_mac_bb_names[] = {
1382 { AR_SREV_VERSION_5416_PCI, "5416" },
1383 { AR_SREV_VERSION_5416_PCIE, "5418" },
1384 { AR_SREV_VERSION_9100, "9100" },
1385 { AR_SREV_VERSION_9160, "9160" },
1386 { AR_SREV_VERSION_9280, "9280" },
1387 { AR_SREV_VERSION_9285, "9285" }
1388 };
1389
1390 static struct {
1391 u16 version;
1392 const char * name;
1393 } ath_rf_names[] = {
1394 { 0, "5133" },
1395 { AR_RAD5133_SREV_MAJOR, "5133" },
1396 { AR_RAD5122_SREV_MAJOR, "5122" },
1397 { AR_RAD2133_SREV_MAJOR, "2133" },
1398 { AR_RAD2122_SREV_MAJOR, "2122" }
1399 };
1400
1401 /*
1402 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
1403 */
1404
1405 static const char *
1406 ath_mac_bb_name(u32 mac_bb_version)
1407 {
1408 int i;
1409
1410 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
1411 if (ath_mac_bb_names[i].version == mac_bb_version) {
1412 return ath_mac_bb_names[i].name;
1413 }
1414 }
1415
1416 return "????";
1417 }
1418
1419 /*
1420 * Return the RF name. "????" is returned if the RF is unknown.
1421 */
1422
1423 static const char *
1424 ath_rf_name(u16 rf_version)
1425 {
1426 int i;
1427
1428 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
1429 if (ath_rf_names[i].version == rf_version) {
1430 return ath_rf_names[i].name;
1431 }
1432 }
1433
1434 return "????";
1435 }
1436
1437 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1438 {
1439 void __iomem *mem;
1440 struct ath_softc *sc;
1441 struct ieee80211_hw *hw;
1442 u8 csz;
1443 u32 val;
1444 int ret = 0;
1445 struct ath_hal *ah;
1446
1447 if (pci_enable_device(pdev))
1448 return -EIO;
1449
1450 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1451
1452 if (ret) {
1453 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
1454 goto bad;
1455 }
1456
1457 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1458
1459 if (ret) {
1460 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
1461 "DMA enable faled\n");
1462 goto bad;
1463 }
1464
1465 /*
1466 * Cache line size is used to size and align various
1467 * structures used to communicate with the hardware.
1468 */
1469 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
1470 if (csz == 0) {
1471 /*
1472 * Linux 2.4.18 (at least) writes the cache line size
1473 * register as a 16-bit wide register which is wrong.
1474 * We must have this setup properly for rx buffer
1475 * DMA to work so force a reasonable value here if it
1476 * comes up zero.
1477 */
1478 csz = L1_CACHE_BYTES / sizeof(u32);
1479 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
1480 }
1481 /*
1482 * The default setting of latency timer yields poor results,
1483 * set it to the value used by other systems. It may be worth
1484 * tweaking this setting more.
1485 */
1486 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
1487
1488 pci_set_master(pdev);
1489
1490 /*
1491 * Disable the RETRY_TIMEOUT register (0x41) to keep
1492 * PCI Tx retries from interfering with C3 CPU state.
1493 */
1494 pci_read_config_dword(pdev, 0x40, &val);
1495 if ((val & 0x0000ff00) != 0)
1496 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1497
1498 ret = pci_request_region(pdev, 0, "ath9k");
1499 if (ret) {
1500 dev_err(&pdev->dev, "PCI memory region reserve error\n");
1501 ret = -ENODEV;
1502 goto bad;
1503 }
1504
1505 mem = pci_iomap(pdev, 0, 0);
1506 if (!mem) {
1507 printk(KERN_ERR "PCI memory map error\n") ;
1508 ret = -EIO;
1509 goto bad1;
1510 }
1511
1512 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
1513 if (hw == NULL) {
1514 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
1515 goto bad2;
1516 }
1517
1518 SET_IEEE80211_DEV(hw, &pdev->dev);
1519 pci_set_drvdata(pdev, hw);
1520
1521 sc = hw->priv;
1522 sc->hw = hw;
1523 sc->pdev = pdev;
1524 sc->mem = mem;
1525
1526 if (ath_attach(id->device, sc) != 0) {
1527 ret = -ENODEV;
1528 goto bad3;
1529 }
1530
1531 /* setup interrupt service routine */
1532
1533 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
1534 printk(KERN_ERR "%s: request_irq failed\n",
1535 wiphy_name(hw->wiphy));
1536 ret = -EIO;
1537 goto bad4;
1538 }
1539
1540 ah = sc->sc_ah;
1541 printk(KERN_INFO
1542 "%s: Atheros AR%s MAC/BB Rev:%x "
1543 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
1544 wiphy_name(hw->wiphy),
1545 ath_mac_bb_name(ah->ah_macVersion),
1546 ah->ah_macRev,
1547 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
1548 ah->ah_phyRev,
1549 (unsigned long)mem, pdev->irq);
1550
1551 return 0;
1552 bad4:
1553 ath_detach(sc);
1554 bad3:
1555 ieee80211_free_hw(hw);
1556 bad2:
1557 pci_iounmap(pdev, mem);
1558 bad1:
1559 pci_release_region(pdev, 0);
1560 bad:
1561 pci_disable_device(pdev);
1562 return ret;
1563 }
1564
1565 static void ath_pci_remove(struct pci_dev *pdev)
1566 {
1567 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1568 struct ath_softc *sc = hw->priv;
1569
1570 ath_detach(sc);
1571 if (pdev->irq)
1572 free_irq(pdev->irq, sc);
1573 pci_iounmap(pdev, sc->mem);
1574 pci_release_region(pdev, 0);
1575 pci_disable_device(pdev);
1576 ieee80211_free_hw(hw);
1577 }
1578
1579 #ifdef CONFIG_PM
1580
1581 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1582 {
1583 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1584 struct ath_softc *sc = hw->priv;
1585
1586 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1587
1588 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1589 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1590 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1591 #endif
1592
1593 pci_save_state(pdev);
1594 pci_disable_device(pdev);
1595 pci_set_power_state(pdev, 3);
1596
1597 return 0;
1598 }
1599
1600 static int ath_pci_resume(struct pci_dev *pdev)
1601 {
1602 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1603 struct ath_softc *sc = hw->priv;
1604 u32 val;
1605 int err;
1606
1607 err = pci_enable_device(pdev);
1608 if (err)
1609 return err;
1610 pci_restore_state(pdev);
1611 /*
1612 * Suspend/Resume resets the PCI configuration space, so we have to
1613 * re-disable the RETRY_TIMEOUT register (0x41) to keep
1614 * PCI Tx retries from interfering with C3 CPU state
1615 */
1616 pci_read_config_dword(pdev, 0x40, &val);
1617 if ((val & 0x0000ff00) != 0)
1618 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1619
1620 /* Enable LED */
1621 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1622 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1623 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1624
1625 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1626 /*
1627 * check the h/w rfkill state on resume
1628 * and start the rfkill poll timer
1629 */
1630 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1631 queue_delayed_work(sc->hw->workqueue,
1632 &sc->rf_kill.rfkill_poll, 0);
1633 #endif
1634
1635 return 0;
1636 }
1637
1638 #endif /* CONFIG_PM */
1639
1640 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
1641
1642 static struct pci_driver ath_pci_driver = {
1643 .name = "ath9k",
1644 .id_table = ath_pci_id_table,
1645 .probe = ath_pci_probe,
1646 .remove = ath_pci_remove,
1647 #ifdef CONFIG_PM
1648 .suspend = ath_pci_suspend,
1649 .resume = ath_pci_resume,
1650 #endif /* CONFIG_PM */
1651 };
1652
1653 static int __init init_ath_pci(void)
1654 {
1655 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
1656
1657 if (pci_register_driver(&ath_pci_driver) < 0) {
1658 printk(KERN_ERR
1659 "ath_pci: No devices found, driver not installed.\n");
1660 pci_unregister_driver(&ath_pci_driver);
1661 return -ENODEV;
1662 }
1663
1664 return 0;
1665 }
1666 module_init(init_ath_pci);
1667
1668 static void __exit exit_ath_pci(void)
1669 {
1670 pci_unregister_driver(&ath_pci_driver);
1671 printk(KERN_INFO "%s: driver unloaded\n", dev_info);
1672 }
1673 module_exit(exit_ath_pci);
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