2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu
21 * Technically, updating td->status here is a race, but it's not really a
22 * problem. The worst that can happen is that we set the IOC bit again
23 * generating a spurious interrupt. We could fix this by creating another
24 * QH and leaving the IOC bit always set, but then we would have to play
25 * games with the FSBR code to make sure we get the correct order in all
26 * the cases. I don't think it's worth the effort
28 static void uhci_set_next_interrupt(struct uhci_hcd
*uhci
)
31 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
32 uhci
->term_td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
35 static inline void uhci_clear_next_interrupt(struct uhci_hcd
*uhci
)
37 uhci
->term_td
->status
&= ~cpu_to_le32(TD_CTRL_IOC
);
42 * Full-Speed Bandwidth Reclamation (FSBR).
43 * We turn on FSBR whenever a queue that wants it is advancing,
44 * and leave it on for a short time thereafter.
46 static void uhci_fsbr_on(struct uhci_hcd
*uhci
)
49 uhci
->skel_term_qh
->link
= cpu_to_le32(
50 uhci
->skel_fs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
53 static void uhci_fsbr_off(struct uhci_hcd
*uhci
)
56 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;
59 static void uhci_add_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
61 struct urb_priv
*urbp
= urb
->hcpriv
;
63 if (!(urb
->transfer_flags
& URB_NO_FSBR
))
67 static void uhci_urbp_wants_fsbr(struct uhci_hcd
*uhci
, struct urb_priv
*urbp
)
70 uhci
->fsbr_is_wanted
= 1;
71 if (!uhci
->fsbr_is_on
)
73 else if (uhci
->fsbr_expiring
) {
74 uhci
->fsbr_expiring
= 0;
75 del_timer(&uhci
->fsbr_timer
);
80 static void uhci_fsbr_timeout(unsigned long _uhci
)
82 struct uhci_hcd
*uhci
= (struct uhci_hcd
*) _uhci
;
85 spin_lock_irqsave(&uhci
->lock
, flags
);
86 if (uhci
->fsbr_expiring
) {
87 uhci
->fsbr_expiring
= 0;
90 spin_unlock_irqrestore(&uhci
->lock
, flags
);
94 static struct uhci_td
*uhci_alloc_td(struct uhci_hcd
*uhci
)
96 dma_addr_t dma_handle
;
99 td
= dma_pool_alloc(uhci
->td_pool
, GFP_ATOMIC
, &dma_handle
);
103 td
->dma_handle
= dma_handle
;
106 INIT_LIST_HEAD(&td
->list
);
107 INIT_LIST_HEAD(&td
->fl_list
);
112 static void uhci_free_td(struct uhci_hcd
*uhci
, struct uhci_td
*td
)
114 if (!list_empty(&td
->list
))
115 dev_warn(uhci_dev(uhci
), "td %p still in list!\n", td
);
116 if (!list_empty(&td
->fl_list
))
117 dev_warn(uhci_dev(uhci
), "td %p still in fl_list!\n", td
);
119 dma_pool_free(uhci
->td_pool
, td
, td
->dma_handle
);
122 static inline void uhci_fill_td(struct uhci_td
*td
, u32 status
,
123 u32 token
, u32 buffer
)
125 td
->status
= cpu_to_le32(status
);
126 td
->token
= cpu_to_le32(token
);
127 td
->buffer
= cpu_to_le32(buffer
);
130 static void uhci_add_td_to_urbp(struct uhci_td
*td
, struct urb_priv
*urbp
)
132 list_add_tail(&td
->list
, &urbp
->td_list
);
135 static void uhci_remove_td_from_urbp(struct uhci_td
*td
)
137 list_del_init(&td
->list
);
141 * We insert Isochronous URBs directly into the frame list at the beginning
143 static inline void uhci_insert_td_in_frame_list(struct uhci_hcd
*uhci
,
144 struct uhci_td
*td
, unsigned framenum
)
146 framenum
&= (UHCI_NUMFRAMES
- 1);
148 td
->frame
= framenum
;
150 /* Is there a TD already mapped there? */
151 if (uhci
->frame_cpu
[framenum
]) {
152 struct uhci_td
*ftd
, *ltd
;
154 ftd
= uhci
->frame_cpu
[framenum
];
155 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
157 list_add_tail(&td
->fl_list
, &ftd
->fl_list
);
159 td
->link
= ltd
->link
;
161 ltd
->link
= cpu_to_le32(td
->dma_handle
);
163 td
->link
= uhci
->frame
[framenum
];
165 uhci
->frame
[framenum
] = cpu_to_le32(td
->dma_handle
);
166 uhci
->frame_cpu
[framenum
] = td
;
170 static inline void uhci_remove_td_from_frame_list(struct uhci_hcd
*uhci
,
173 /* If it's not inserted, don't remove it */
174 if (td
->frame
== -1) {
175 WARN_ON(!list_empty(&td
->fl_list
));
179 if (uhci
->frame_cpu
[td
->frame
] == td
) {
180 if (list_empty(&td
->fl_list
)) {
181 uhci
->frame
[td
->frame
] = td
->link
;
182 uhci
->frame_cpu
[td
->frame
] = NULL
;
186 ntd
= list_entry(td
->fl_list
.next
, struct uhci_td
, fl_list
);
187 uhci
->frame
[td
->frame
] = cpu_to_le32(ntd
->dma_handle
);
188 uhci
->frame_cpu
[td
->frame
] = ntd
;
193 ptd
= list_entry(td
->fl_list
.prev
, struct uhci_td
, fl_list
);
194 ptd
->link
= td
->link
;
197 list_del_init(&td
->fl_list
);
201 static inline void uhci_remove_tds_from_frame(struct uhci_hcd
*uhci
,
202 unsigned int framenum
)
204 struct uhci_td
*ftd
, *ltd
;
206 framenum
&= (UHCI_NUMFRAMES
- 1);
208 ftd
= uhci
->frame_cpu
[framenum
];
210 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
211 uhci
->frame
[framenum
] = ltd
->link
;
212 uhci
->frame_cpu
[framenum
] = NULL
;
214 while (!list_empty(&ftd
->fl_list
))
215 list_del_init(ftd
->fl_list
.prev
);
220 * Remove all the TDs for an Isochronous URB from the frame list
222 static void uhci_unlink_isochronous_tds(struct uhci_hcd
*uhci
, struct urb
*urb
)
224 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
227 list_for_each_entry(td
, &urbp
->td_list
, list
)
228 uhci_remove_td_from_frame_list(uhci
, td
);
231 static struct uhci_qh
*uhci_alloc_qh(struct uhci_hcd
*uhci
,
232 struct usb_device
*udev
, struct usb_host_endpoint
*hep
)
234 dma_addr_t dma_handle
;
237 qh
= dma_pool_alloc(uhci
->qh_pool
, GFP_ATOMIC
, &dma_handle
);
241 memset(qh
, 0, sizeof(*qh
));
242 qh
->dma_handle
= dma_handle
;
244 qh
->element
= UHCI_PTR_TERM
;
245 qh
->link
= UHCI_PTR_TERM
;
247 INIT_LIST_HEAD(&qh
->queue
);
248 INIT_LIST_HEAD(&qh
->node
);
250 if (udev
) { /* Normal QH */
251 qh
->type
= hep
->desc
.bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
;
252 if (qh
->type
!= USB_ENDPOINT_XFER_ISOC
) {
253 qh
->dummy_td
= uhci_alloc_td(uhci
);
255 dma_pool_free(uhci
->qh_pool
, qh
, dma_handle
);
259 qh
->state
= QH_STATE_IDLE
;
264 if (qh
->type
== USB_ENDPOINT_XFER_INT
||
265 qh
->type
== USB_ENDPOINT_XFER_ISOC
)
266 qh
->load
= usb_calc_bus_time(udev
->speed
,
267 usb_endpoint_dir_in(&hep
->desc
),
268 qh
->type
== USB_ENDPOINT_XFER_ISOC
,
269 le16_to_cpu(hep
->desc
.wMaxPacketSize
))
272 } else { /* Skeleton QH */
273 qh
->state
= QH_STATE_ACTIVE
;
279 static void uhci_free_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
281 WARN_ON(qh
->state
!= QH_STATE_IDLE
&& qh
->udev
);
282 if (!list_empty(&qh
->queue
))
283 dev_warn(uhci_dev(uhci
), "qh %p list not empty!\n", qh
);
287 qh
->hep
->hcpriv
= NULL
;
289 uhci_free_td(uhci
, qh
->dummy_td
);
291 dma_pool_free(uhci
->qh_pool
, qh
, qh
->dma_handle
);
295 * When a queue is stopped and a dequeued URB is given back, adjust
296 * the previous TD link (if the URB isn't first on the queue) or
297 * save its toggle value (if it is first and is currently executing).
299 * Returns 0 if the URB should not yet be given back, 1 otherwise.
301 static int uhci_cleanup_queue(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
304 struct urb_priv
*urbp
= urb
->hcpriv
;
308 /* Isochronous pipes don't use toggles and their TD link pointers
309 * get adjusted during uhci_urb_dequeue(). But since their queues
310 * cannot truly be stopped, we have to watch out for dequeues
311 * occurring after the nominal unlink frame. */
312 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
) {
313 ret
= (uhci
->frame_number
+ uhci
->is_stopped
!=
318 /* If the URB isn't first on its queue, adjust the link pointer
319 * of the last TD in the previous URB. The toggle doesn't need
320 * to be saved since this URB can't be executing yet. */
321 if (qh
->queue
.next
!= &urbp
->node
) {
322 struct urb_priv
*purbp
;
325 purbp
= list_entry(urbp
->node
.prev
, struct urb_priv
, node
);
326 WARN_ON(list_empty(&purbp
->td_list
));
327 ptd
= list_entry(purbp
->td_list
.prev
, struct uhci_td
,
329 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
,
331 ptd
->link
= td
->link
;
335 /* If the QH element pointer is UHCI_PTR_TERM then then currently
336 * executing URB has already been unlinked, so this one isn't it. */
337 if (qh_element(qh
) == UHCI_PTR_TERM
)
339 qh
->element
= UHCI_PTR_TERM
;
341 /* Control pipes don't have to worry about toggles */
342 if (qh
->type
== USB_ENDPOINT_XFER_CONTROL
)
345 /* Save the next toggle value */
346 WARN_ON(list_empty(&urbp
->td_list
));
347 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
349 qh
->initial_toggle
= uhci_toggle(td_token(td
));
356 * Fix up the data toggles for URBs in a queue, when one of them
357 * terminates early (short transfer, error, or dequeued).
359 static void uhci_fixup_toggles(struct uhci_qh
*qh
, int skip_first
)
361 struct urb_priv
*urbp
= NULL
;
363 unsigned int toggle
= qh
->initial_toggle
;
366 /* Fixups for a short transfer start with the second URB in the
367 * queue (the short URB is the first). */
369 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
371 /* When starting with the first URB, if the QH element pointer is
372 * still valid then we know the URB's toggles are okay. */
373 else if (qh_element(qh
) != UHCI_PTR_TERM
)
376 /* Fix up the toggle for the URBs in the queue. Normally this
377 * loop won't run more than once: When an error or short transfer
378 * occurs, the queue usually gets emptied. */
379 urbp
= list_prepare_entry(urbp
, &qh
->queue
, node
);
380 list_for_each_entry_continue(urbp
, &qh
->queue
, node
) {
382 /* If the first TD has the right toggle value, we don't
383 * need to change any toggles in this URB */
384 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
385 if (toggle
> 1 || uhci_toggle(td_token(td
)) == toggle
) {
386 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
,
388 toggle
= uhci_toggle(td_token(td
)) ^ 1;
390 /* Otherwise all the toggles in the URB have to be switched */
392 list_for_each_entry(td
, &urbp
->td_list
, list
) {
393 td
->token
^= __constant_cpu_to_le32(
401 pipe
= list_entry(qh
->queue
.next
, struct urb_priv
, node
)->urb
->pipe
;
402 usb_settoggle(qh
->udev
, usb_pipeendpoint(pipe
),
403 usb_pipeout(pipe
), toggle
);
408 * Put a QH on the schedule in both hardware and software
410 static void uhci_activate_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
414 WARN_ON(list_empty(&qh
->queue
));
416 /* Set the element pointer if it isn't set already.
417 * This isn't needed for Isochronous queues, but it doesn't hurt. */
418 if (qh_element(qh
) == UHCI_PTR_TERM
) {
419 struct urb_priv
*urbp
= list_entry(qh
->queue
.next
,
420 struct urb_priv
, node
);
421 struct uhci_td
*td
= list_entry(urbp
->td_list
.next
,
422 struct uhci_td
, list
);
424 qh
->element
= cpu_to_le32(td
->dma_handle
);
427 /* Treat the queue as if it has just advanced */
428 qh
->wait_expired
= 0;
429 qh
->advance_jiffies
= jiffies
;
431 if (qh
->state
== QH_STATE_ACTIVE
)
433 qh
->state
= QH_STATE_ACTIVE
;
435 /* Move the QH from its old list to the end of the appropriate
437 if (qh
== uhci
->next_qh
)
438 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
440 list_move_tail(&qh
->node
, &qh
->skel
->node
);
442 /* Link it into the schedule */
443 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
444 qh
->link
= pqh
->link
;
446 pqh
->link
= UHCI_PTR_QH
| cpu_to_le32(qh
->dma_handle
);
450 * Take a QH off the hardware schedule
452 static void uhci_unlink_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
456 if (qh
->state
== QH_STATE_UNLINKING
)
458 WARN_ON(qh
->state
!= QH_STATE_ACTIVE
|| !qh
->udev
);
459 qh
->state
= QH_STATE_UNLINKING
;
461 /* Unlink the QH from the schedule and record when we did it */
462 pqh
= list_entry(qh
->node
.prev
, struct uhci_qh
, node
);
463 pqh
->link
= qh
->link
;
466 uhci_get_current_frame_number(uhci
);
467 qh
->unlink_frame
= uhci
->frame_number
;
469 /* Force an interrupt so we know when the QH is fully unlinked */
470 if (list_empty(&uhci
->skel_unlink_qh
->node
))
471 uhci_set_next_interrupt(uhci
);
473 /* Move the QH from its old list to the end of the unlinking list */
474 if (qh
== uhci
->next_qh
)
475 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
477 list_move_tail(&qh
->node
, &uhci
->skel_unlink_qh
->node
);
481 * When we and the controller are through with a QH, it becomes IDLE.
482 * This happens when a QH has been off the schedule (on the unlinking
483 * list) for more than one frame, or when an error occurs while adding
484 * the first URB onto a new QH.
486 static void uhci_make_qh_idle(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
488 WARN_ON(qh
->state
== QH_STATE_ACTIVE
);
490 if (qh
== uhci
->next_qh
)
491 uhci
->next_qh
= list_entry(qh
->node
.next
, struct uhci_qh
,
493 list_move(&qh
->node
, &uhci
->idle_qh_list
);
494 qh
->state
= QH_STATE_IDLE
;
496 /* Now that the QH is idle, its post_td isn't being used */
498 uhci_free_td(uhci
, qh
->post_td
);
502 /* If anyone is waiting for a QH to become idle, wake them up */
503 if (uhci
->num_waiting
)
504 wake_up_all(&uhci
->waitqh
);
508 * Find the highest existing bandwidth load for a given phase and period.
510 static int uhci_highest_load(struct uhci_hcd
*uhci
, int phase
, int period
)
512 int highest_load
= uhci
->load
[phase
];
514 for (phase
+= period
; phase
< MAX_PHASE
; phase
+= period
)
515 highest_load
= max_t(int, highest_load
, uhci
->load
[phase
]);
520 * Set qh->phase to the optimal phase for a periodic transfer and
521 * check whether the bandwidth requirement is acceptable.
523 static int uhci_check_bandwidth(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
527 /* Find the optimal phase (unless it is already set) and get
530 minimax_load
= uhci_highest_load(uhci
, qh
->phase
, qh
->period
);
533 int max_phase
= min_t(int, MAX_PHASE
, qh
->period
);
536 minimax_load
= uhci_highest_load(uhci
, qh
->phase
, qh
->period
);
537 for (phase
= 1; phase
< max_phase
; ++phase
) {
538 load
= uhci_highest_load(uhci
, phase
, qh
->period
);
539 if (load
< minimax_load
) {
546 /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
547 if (minimax_load
+ qh
->load
> 900) {
548 dev_dbg(uhci_dev(uhci
), "bandwidth allocation failed: "
549 "period %d, phase %d, %d + %d us\n",
550 qh
->period
, qh
->phase
, minimax_load
, qh
->load
);
557 * Reserve a periodic QH's bandwidth in the schedule
559 static void uhci_reserve_bandwidth(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
565 for (i
= qh
->phase
; i
< MAX_PHASE
; i
+= qh
->period
) {
566 uhci
->load
[i
] += load
;
567 uhci
->total_load
+= load
;
569 uhci_to_hcd(uhci
)->self
.bandwidth_allocated
=
570 uhci
->total_load
/ MAX_PHASE
;
572 case USB_ENDPOINT_XFER_INT
:
573 ++uhci_to_hcd(uhci
)->self
.bandwidth_int_reqs
;
576 case USB_ENDPOINT_XFER_ISOC
:
577 ++uhci_to_hcd(uhci
)->self
.bandwidth_isoc_reqs
;
581 qh
->bandwidth_reserved
= 1;
582 dev_dbg(uhci_dev(uhci
),
583 "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
584 "reserve", qh
->udev
->devnum
,
585 qh
->hep
->desc
.bEndpointAddress
, p
,
586 qh
->period
, qh
->phase
, load
);
590 * Release a periodic QH's bandwidth reservation
592 static void uhci_release_bandwidth(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
598 for (i
= qh
->phase
; i
< MAX_PHASE
; i
+= qh
->period
) {
599 uhci
->load
[i
] -= load
;
600 uhci
->total_load
-= load
;
602 uhci_to_hcd(uhci
)->self
.bandwidth_allocated
=
603 uhci
->total_load
/ MAX_PHASE
;
605 case USB_ENDPOINT_XFER_INT
:
606 --uhci_to_hcd(uhci
)->self
.bandwidth_int_reqs
;
609 case USB_ENDPOINT_XFER_ISOC
:
610 --uhci_to_hcd(uhci
)->self
.bandwidth_isoc_reqs
;
614 qh
->bandwidth_reserved
= 0;
615 dev_dbg(uhci_dev(uhci
),
616 "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
617 "release", qh
->udev
->devnum
,
618 qh
->hep
->desc
.bEndpointAddress
, p
,
619 qh
->period
, qh
->phase
, load
);
622 static inline struct urb_priv
*uhci_alloc_urb_priv(struct uhci_hcd
*uhci
,
625 struct urb_priv
*urbp
;
627 urbp
= kmem_cache_zalloc(uhci_up_cachep
, GFP_ATOMIC
);
634 INIT_LIST_HEAD(&urbp
->node
);
635 INIT_LIST_HEAD(&urbp
->td_list
);
640 static void uhci_free_urb_priv(struct uhci_hcd
*uhci
,
641 struct urb_priv
*urbp
)
643 struct uhci_td
*td
, *tmp
;
645 if (!list_empty(&urbp
->node
))
646 dev_warn(uhci_dev(uhci
), "urb %p still on QH's list!\n",
649 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
650 uhci_remove_td_from_urbp(td
);
651 uhci_free_td(uhci
, td
);
654 urbp
->urb
->hcpriv
= NULL
;
655 kmem_cache_free(uhci_up_cachep
, urbp
);
659 * Map status to standard result codes
661 * <status> is (td_status(td) & 0xF60000), a.k.a.
662 * uhci_status_bits(td_status(td)).
663 * Note: <status> does not include the TD_CTRL_NAK bit.
664 * <dir_out> is True for output TDs and False for input TDs.
666 static int uhci_map_status(int status
, int dir_out
)
670 if (status
& TD_CTRL_BITSTUFF
) /* Bitstuff error */
672 if (status
& TD_CTRL_CRCTIMEO
) { /* CRC/Timeout */
678 if (status
& TD_CTRL_BABBLE
) /* Babble */
680 if (status
& TD_CTRL_DBUFERR
) /* Buffer error */
682 if (status
& TD_CTRL_STALLED
) /* Stalled */
690 static int uhci_submit_control(struct uhci_hcd
*uhci
, struct urb
*urb
,
694 unsigned long destination
, status
;
695 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
696 int len
= urb
->transfer_buffer_length
;
697 dma_addr_t data
= urb
->transfer_dma
;
699 struct urb_priv
*urbp
= urb
->hcpriv
;
701 /* The "pipe" thing contains the destination in bits 8--18 */
702 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | USB_PID_SETUP
;
704 /* 3 errors, dummy TD remains inactive */
705 status
= uhci_maxerr(3);
706 if (urb
->dev
->speed
== USB_SPEED_LOW
)
707 status
|= TD_CTRL_LS
;
710 * Build the TD for the control request setup packet
713 uhci_add_td_to_urbp(td
, urbp
);
714 uhci_fill_td(td
, status
, destination
| uhci_explen(8),
717 status
|= TD_CTRL_ACTIVE
;
720 * If direction is "send", change the packet ID from SETUP (0x2D)
721 * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
722 * set Short Packet Detect (SPD) for all data packets.
724 if (usb_pipeout(urb
->pipe
))
725 destination
^= (USB_PID_SETUP
^ USB_PID_OUT
);
727 destination
^= (USB_PID_SETUP
^ USB_PID_IN
);
728 status
|= TD_CTRL_SPD
;
735 int pktsze
= min(len
, maxsze
);
737 td
= uhci_alloc_td(uhci
);
740 *plink
= cpu_to_le32(td
->dma_handle
);
742 /* Alternate Data0/1 (start with Data1) */
743 destination
^= TD_TOKEN_TOGGLE
;
745 uhci_add_td_to_urbp(td
, urbp
);
746 uhci_fill_td(td
, status
, destination
| uhci_explen(pktsze
),
755 * Build the final TD for control status
757 td
= uhci_alloc_td(uhci
);
760 *plink
= cpu_to_le32(td
->dma_handle
);
763 * It's IN if the pipe is an output pipe or we're not expecting
766 destination
&= ~TD_TOKEN_PID_MASK
;
767 if (usb_pipeout(urb
->pipe
) || !urb
->transfer_buffer_length
)
768 destination
|= USB_PID_IN
;
770 destination
|= USB_PID_OUT
;
772 destination
|= TD_TOKEN_TOGGLE
; /* End in Data1 */
774 status
&= ~TD_CTRL_SPD
;
776 uhci_add_td_to_urbp(td
, urbp
);
777 uhci_fill_td(td
, status
| TD_CTRL_IOC
,
778 destination
| uhci_explen(0), 0);
782 * Build the new dummy TD and activate the old one
784 td
= uhci_alloc_td(uhci
);
787 *plink
= cpu_to_le32(td
->dma_handle
);
789 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
791 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
794 /* Low-speed transfers get a different queue, and won't hog the bus.
795 * Also, some devices enumerate better without FSBR; the easiest way
796 * to do that is to put URBs on the low-speed queue while the device
797 * isn't in the CONFIGURED state. */
798 if (urb
->dev
->speed
== USB_SPEED_LOW
||
799 urb
->dev
->state
!= USB_STATE_CONFIGURED
)
800 qh
->skel
= uhci
->skel_ls_control_qh
;
802 qh
->skel
= uhci
->skel_fs_control_qh
;
803 uhci_add_fsbr(uhci
, urb
);
806 urb
->actual_length
= -8; /* Account for the SETUP packet */
810 /* Remove the dummy TD from the td_list so it doesn't get freed */
811 uhci_remove_td_from_urbp(qh
->dummy_td
);
816 * Common submit for bulk and interrupt
818 static int uhci_submit_common(struct uhci_hcd
*uhci
, struct urb
*urb
,
822 unsigned long destination
, status
;
823 int maxsze
= le16_to_cpu(qh
->hep
->desc
.wMaxPacketSize
);
824 int len
= urb
->transfer_buffer_length
;
825 dma_addr_t data
= urb
->transfer_dma
;
827 struct urb_priv
*urbp
= urb
->hcpriv
;
833 /* The "pipe" thing contains the destination in bits 8--18 */
834 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
835 toggle
= usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
836 usb_pipeout(urb
->pipe
));
838 /* 3 errors, dummy TD remains inactive */
839 status
= uhci_maxerr(3);
840 if (urb
->dev
->speed
== USB_SPEED_LOW
)
841 status
|= TD_CTRL_LS
;
842 if (usb_pipein(urb
->pipe
))
843 status
|= TD_CTRL_SPD
;
850 do { /* Allow zero length packets */
853 if (len
<= pktsze
) { /* The last packet */
855 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
856 status
&= ~TD_CTRL_SPD
;
860 td
= uhci_alloc_td(uhci
);
863 *plink
= cpu_to_le32(td
->dma_handle
);
865 uhci_add_td_to_urbp(td
, urbp
);
866 uhci_fill_td(td
, status
,
867 destination
| uhci_explen(pktsze
) |
868 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
871 status
|= TD_CTRL_ACTIVE
;
879 * URB_ZERO_PACKET means adding a 0-length packet, if direction
880 * is OUT and the transfer_length was an exact multiple of maxsze,
881 * hence (len = transfer_length - N * maxsze) == 0
882 * however, if transfer_length == 0, the zero packet was already
885 if ((urb
->transfer_flags
& URB_ZERO_PACKET
) &&
886 usb_pipeout(urb
->pipe
) && len
== 0 &&
887 urb
->transfer_buffer_length
> 0) {
888 td
= uhci_alloc_td(uhci
);
891 *plink
= cpu_to_le32(td
->dma_handle
);
893 uhci_add_td_to_urbp(td
, urbp
);
894 uhci_fill_td(td
, status
,
895 destination
| uhci_explen(0) |
896 (toggle
<< TD_TOKEN_TOGGLE_SHIFT
),
903 /* Set the interrupt-on-completion flag on the last packet.
904 * A more-or-less typical 4 KB URB (= size of one memory page)
905 * will require about 3 ms to transfer; that's a little on the
906 * fast side but not enough to justify delaying an interrupt
907 * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
909 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
912 * Build the new dummy TD and activate the old one
914 td
= uhci_alloc_td(uhci
);
917 *plink
= cpu_to_le32(td
->dma_handle
);
919 uhci_fill_td(td
, 0, USB_PID_OUT
| uhci_explen(0), 0);
921 qh
->dummy_td
->status
|= __constant_cpu_to_le32(TD_CTRL_ACTIVE
);
924 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
925 usb_pipeout(urb
->pipe
), toggle
);
929 /* Remove the dummy TD from the td_list so it doesn't get freed */
930 uhci_remove_td_from_urbp(qh
->dummy_td
);
934 static inline int uhci_submit_bulk(struct uhci_hcd
*uhci
, struct urb
*urb
,
939 /* Can't have low-speed bulk transfers */
940 if (urb
->dev
->speed
== USB_SPEED_LOW
)
943 qh
->skel
= uhci
->skel_bulk_qh
;
944 ret
= uhci_submit_common(uhci
, urb
, qh
);
946 uhci_add_fsbr(uhci
, urb
);
950 static int uhci_submit_interrupt(struct uhci_hcd
*uhci
, struct urb
*urb
,
955 /* USB 1.1 interrupt transfers only involve one packet per interval.
956 * Drivers can submit URBs of any length, but longer ones will need
957 * multiple intervals to complete.
960 if (!qh
->bandwidth_reserved
) {
963 /* Figure out which power-of-two queue to use */
964 for (exponent
= 7; exponent
>= 0; --exponent
) {
965 if ((1 << exponent
) <= urb
->interval
)
970 qh
->period
= 1 << exponent
;
971 qh
->skel
= uhci
->skelqh
[UHCI_SKEL_INDEX(exponent
)];
973 /* For now, interrupt phase is fixed by the layout
974 * of the QH lists. */
975 qh
->phase
= (qh
->period
/ 2) & (MAX_PHASE
- 1);
976 ret
= uhci_check_bandwidth(uhci
, qh
);
979 } else if (qh
->period
> urb
->interval
)
980 return -EINVAL
; /* Can't decrease the period */
982 ret
= uhci_submit_common(uhci
, urb
, qh
);
984 urb
->interval
= qh
->period
;
985 if (!qh
->bandwidth_reserved
)
986 uhci_reserve_bandwidth(uhci
, qh
);
992 * Fix up the data structures following a short transfer
994 static int uhci_fixup_short_transfer(struct uhci_hcd
*uhci
,
995 struct uhci_qh
*qh
, struct urb_priv
*urbp
)
998 struct list_head
*tmp
;
1001 td
= list_entry(urbp
->td_list
.prev
, struct uhci_td
, list
);
1002 if (qh
->type
== USB_ENDPOINT_XFER_CONTROL
) {
1004 /* When a control transfer is short, we have to restart
1005 * the queue at the status stage transaction, which is
1007 WARN_ON(list_empty(&urbp
->td_list
));
1008 qh
->element
= cpu_to_le32(td
->dma_handle
);
1009 tmp
= td
->list
.prev
;
1014 /* When a bulk/interrupt transfer is short, we have to
1015 * fix up the toggles of the following URBs on the queue
1016 * before restarting the queue at the next URB. */
1017 qh
->initial_toggle
= uhci_toggle(td_token(qh
->post_td
)) ^ 1;
1018 uhci_fixup_toggles(qh
, 1);
1020 if (list_empty(&urbp
->td_list
))
1022 qh
->element
= td
->link
;
1023 tmp
= urbp
->td_list
.prev
;
1027 /* Remove all the TDs we skipped over, from tmp back to the start */
1028 while (tmp
!= &urbp
->td_list
) {
1029 td
= list_entry(tmp
, struct uhci_td
, list
);
1032 uhci_remove_td_from_urbp(td
);
1033 uhci_free_td(uhci
, td
);
1039 * Common result for control, bulk, and interrupt
1041 static int uhci_result_common(struct uhci_hcd
*uhci
, struct urb
*urb
)
1043 struct urb_priv
*urbp
= urb
->hcpriv
;
1044 struct uhci_qh
*qh
= urbp
->qh
;
1045 struct uhci_td
*td
, *tmp
;
1049 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
1050 unsigned int ctrlstat
;
1053 ctrlstat
= td_status(td
);
1054 status
= uhci_status_bits(ctrlstat
);
1055 if (status
& TD_CTRL_ACTIVE
)
1056 return -EINPROGRESS
;
1058 len
= uhci_actual_length(ctrlstat
);
1059 urb
->actual_length
+= len
;
1062 ret
= uhci_map_status(status
,
1063 uhci_packetout(td_token(td
)));
1064 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
1065 /* Some debugging code */
1066 dev_dbg(&urb
->dev
->dev
,
1067 "%s: failed with status %x\n",
1068 __FUNCTION__
, status
);
1070 if (debug
> 1 && errbuf
) {
1071 /* Print the chain for debugging */
1072 uhci_show_qh(urbp
->qh
, errbuf
,
1078 } else if (len
< uhci_expected_length(td_token(td
))) {
1080 /* We received a short packet */
1081 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1084 /* Fixup needed only if this isn't the URB's last TD */
1085 else if (&td
->list
!= urbp
->td_list
.prev
)
1089 uhci_remove_td_from_urbp(td
);
1091 uhci_free_td(uhci
, qh
->post_td
);
1101 /* In case a control transfer gets an error
1102 * during the setup stage */
1103 urb
->actual_length
= max(urb
->actual_length
, 0);
1105 /* Note that the queue has stopped and save
1106 * the next toggle value */
1107 qh
->element
= UHCI_PTR_TERM
;
1109 qh
->needs_fixup
= (qh
->type
!= USB_ENDPOINT_XFER_CONTROL
);
1110 qh
->initial_toggle
= uhci_toggle(td_token(td
)) ^
1111 (ret
== -EREMOTEIO
);
1113 } else /* Short packet received */
1114 ret
= uhci_fixup_short_transfer(uhci
, qh
, urbp
);
1119 * Isochronous transfers
1121 static int uhci_submit_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
,
1124 struct uhci_td
*td
= NULL
; /* Since urb->number_of_packets > 0 */
1126 unsigned long destination
, status
;
1127 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
1129 /* Values must not be too big (could overflow below) */
1130 if (urb
->interval
>= UHCI_NUMFRAMES
||
1131 urb
->number_of_packets
>= UHCI_NUMFRAMES
)
1134 /* Check the period and figure out the starting frame number */
1135 if (!qh
->bandwidth_reserved
) {
1136 qh
->period
= urb
->interval
;
1137 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
1138 qh
->phase
= -1; /* Find the best phase */
1139 i
= uhci_check_bandwidth(uhci
, qh
);
1143 /* Allow a little time to allocate the TDs */
1144 uhci_get_current_frame_number(uhci
);
1145 frame
= uhci
->frame_number
+ 10;
1147 /* Move forward to the first frame having the
1149 urb
->start_frame
= frame
+ ((qh
->phase
- frame
) &
1152 i
= urb
->start_frame
- uhci
->last_iso_frame
;
1153 if (i
<= 0 || i
>= UHCI_NUMFRAMES
)
1155 qh
->phase
= urb
->start_frame
& (qh
->period
- 1);
1156 i
= uhci_check_bandwidth(uhci
, qh
);
1161 } else if (qh
->period
!= urb
->interval
) {
1162 return -EINVAL
; /* Can't change the period */
1164 } else { /* Pick up where the last URB leaves off */
1165 if (list_empty(&qh
->queue
)) {
1166 frame
= qh
->iso_frame
;
1170 lurb
= list_entry(qh
->queue
.prev
,
1171 struct urb_priv
, node
)->urb
;
1172 frame
= lurb
->start_frame
+
1173 lurb
->number_of_packets
*
1176 if (urb
->transfer_flags
& URB_ISO_ASAP
)
1177 urb
->start_frame
= frame
;
1178 else if (urb
->start_frame
!= frame
)
1182 /* Make sure we won't have to go too far into the future */
1183 if (uhci_frame_before_eq(uhci
->last_iso_frame
+ UHCI_NUMFRAMES
,
1184 urb
->start_frame
+ urb
->number_of_packets
*
1188 status
= TD_CTRL_ACTIVE
| TD_CTRL_IOS
;
1189 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
1191 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1192 td
= uhci_alloc_td(uhci
);
1196 uhci_add_td_to_urbp(td
, urbp
);
1197 uhci_fill_td(td
, status
, destination
|
1198 uhci_explen(urb
->iso_frame_desc
[i
].length
),
1200 urb
->iso_frame_desc
[i
].offset
);
1203 /* Set the interrupt-on-completion flag on the last packet. */
1204 td
->status
|= __constant_cpu_to_le32(TD_CTRL_IOC
);
1206 /* Add the TDs to the frame list */
1207 frame
= urb
->start_frame
;
1208 list_for_each_entry(td
, &urbp
->td_list
, list
) {
1209 uhci_insert_td_in_frame_list(uhci
, td
, frame
);
1210 frame
+= qh
->period
;
1213 if (list_empty(&qh
->queue
)) {
1214 qh
->iso_packet_desc
= &urb
->iso_frame_desc
[0];
1215 qh
->iso_frame
= urb
->start_frame
;
1219 qh
->skel
= uhci
->skel_iso_qh
;
1220 if (!qh
->bandwidth_reserved
)
1221 uhci_reserve_bandwidth(uhci
, qh
);
1225 static int uhci_result_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
)
1227 struct uhci_td
*td
, *tmp
;
1228 struct urb_priv
*urbp
= urb
->hcpriv
;
1229 struct uhci_qh
*qh
= urbp
->qh
;
1231 list_for_each_entry_safe(td
, tmp
, &urbp
->td_list
, list
) {
1232 unsigned int ctrlstat
;
1236 if (uhci_frame_before_eq(uhci
->cur_iso_frame
, qh
->iso_frame
))
1237 return -EINPROGRESS
;
1239 uhci_remove_tds_from_frame(uhci
, qh
->iso_frame
);
1241 ctrlstat
= td_status(td
);
1242 if (ctrlstat
& TD_CTRL_ACTIVE
) {
1243 status
= -EXDEV
; /* TD was added too late? */
1245 status
= uhci_map_status(uhci_status_bits(ctrlstat
),
1246 usb_pipeout(urb
->pipe
));
1247 actlength
= uhci_actual_length(ctrlstat
);
1249 urb
->actual_length
+= actlength
;
1250 qh
->iso_packet_desc
->actual_length
= actlength
;
1251 qh
->iso_packet_desc
->status
= status
;
1256 qh
->iso_status
= status
;
1259 uhci_remove_td_from_urbp(td
);
1260 uhci_free_td(uhci
, td
);
1261 qh
->iso_frame
+= qh
->period
;
1262 ++qh
->iso_packet_desc
;
1264 return qh
->iso_status
;
1267 static int uhci_urb_enqueue(struct usb_hcd
*hcd
,
1268 struct usb_host_endpoint
*hep
,
1269 struct urb
*urb
, gfp_t mem_flags
)
1272 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1273 unsigned long flags
;
1274 struct urb_priv
*urbp
;
1277 spin_lock_irqsave(&uhci
->lock
, flags
);
1280 if (ret
!= -EINPROGRESS
) /* URB already unlinked! */
1284 urbp
= uhci_alloc_urb_priv(uhci
, urb
);
1289 qh
= (struct uhci_qh
*) hep
->hcpriv
;
1291 qh
= uhci_alloc_qh(uhci
, urb
->dev
, hep
);
1298 case USB_ENDPOINT_XFER_CONTROL
:
1299 ret
= uhci_submit_control(uhci
, urb
, qh
);
1301 case USB_ENDPOINT_XFER_BULK
:
1302 ret
= uhci_submit_bulk(uhci
, urb
, qh
);
1304 case USB_ENDPOINT_XFER_INT
:
1305 ret
= uhci_submit_interrupt(uhci
, urb
, qh
);
1307 case USB_ENDPOINT_XFER_ISOC
:
1308 urb
->error_count
= 0;
1309 ret
= uhci_submit_isochronous(uhci
, urb
, qh
);
1313 goto err_submit_failed
;
1315 /* Add this URB to the QH */
1317 list_add_tail(&urbp
->node
, &qh
->queue
);
1319 /* If the new URB is the first and only one on this QH then either
1320 * the QH is new and idle or else it's unlinked and waiting to
1321 * become idle, so we can activate it right away. But only if the
1322 * queue isn't stopped. */
1323 if (qh
->queue
.next
== &urbp
->node
&& !qh
->is_stopped
) {
1324 uhci_activate_qh(uhci
, qh
);
1325 uhci_urbp_wants_fsbr(uhci
, urbp
);
1330 if (qh
->state
== QH_STATE_IDLE
)
1331 uhci_make_qh_idle(uhci
, qh
); /* Reclaim unused QH */
1334 uhci_free_urb_priv(uhci
, urbp
);
1337 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1341 static int uhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
)
1343 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1344 unsigned long flags
;
1345 struct urb_priv
*urbp
;
1348 spin_lock_irqsave(&uhci
->lock
, flags
);
1350 if (!urbp
) /* URB was never linked! */
1354 /* Remove Isochronous TDs from the frame list ASAP */
1355 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
) {
1356 uhci_unlink_isochronous_tds(uhci
, urb
);
1359 /* If the URB has already started, update the QH unlink time */
1360 uhci_get_current_frame_number(uhci
);
1361 if (uhci_frame_before_eq(urb
->start_frame
, uhci
->frame_number
))
1362 qh
->unlink_frame
= uhci
->frame_number
;
1365 uhci_unlink_qh(uhci
, qh
);
1368 spin_unlock_irqrestore(&uhci
->lock
, flags
);
1373 * Finish unlinking an URB and give it back
1375 static void uhci_giveback_urb(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
,
1377 __releases(uhci
->lock
)
1378 __acquires(uhci
->lock
)
1380 struct urb_priv
*urbp
= (struct urb_priv
*) urb
->hcpriv
;
1382 /* When giving back the first URB in an Isochronous queue,
1383 * reinitialize the QH's iso-related members for the next URB. */
1384 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
&&
1385 urbp
->node
.prev
== &qh
->queue
&&
1386 urbp
->node
.next
!= &qh
->queue
) {
1387 struct urb
*nurb
= list_entry(urbp
->node
.next
,
1388 struct urb_priv
, node
)->urb
;
1390 qh
->iso_packet_desc
= &nurb
->iso_frame_desc
[0];
1391 qh
->iso_frame
= nurb
->start_frame
;
1395 /* Take the URB off the QH's queue. If the queue is now empty,
1396 * this is a perfect time for a toggle fixup. */
1397 list_del_init(&urbp
->node
);
1398 if (list_empty(&qh
->queue
) && qh
->needs_fixup
) {
1399 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1400 usb_pipeout(urb
->pipe
), qh
->initial_toggle
);
1401 qh
->needs_fixup
= 0;
1404 uhci_free_urb_priv(uhci
, urbp
);
1406 spin_unlock(&uhci
->lock
);
1407 usb_hcd_giveback_urb(uhci_to_hcd(uhci
), urb
);
1408 spin_lock(&uhci
->lock
);
1410 /* If the queue is now empty, we can unlink the QH and give up its
1411 * reserved bandwidth. */
1412 if (list_empty(&qh
->queue
)) {
1413 uhci_unlink_qh(uhci
, qh
);
1414 if (qh
->bandwidth_reserved
)
1415 uhci_release_bandwidth(uhci
, qh
);
1420 * Scan the URBs in a QH's queue
1422 #define QH_FINISHED_UNLINKING(qh) \
1423 (qh->state == QH_STATE_UNLINKING && \
1424 uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
1426 static void uhci_scan_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
1428 struct urb_priv
*urbp
;
1432 while (!list_empty(&qh
->queue
)) {
1433 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1436 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
)
1437 status
= uhci_result_isochronous(uhci
, urb
);
1439 status
= uhci_result_common(uhci
, urb
);
1440 if (status
== -EINPROGRESS
)
1443 spin_lock(&urb
->lock
);
1444 if (urb
->status
== -EINPROGRESS
) /* Not dequeued */
1445 urb
->status
= status
;
1447 status
= ECONNRESET
; /* Not -ECONNRESET */
1448 spin_unlock(&urb
->lock
);
1450 /* Dequeued but completed URBs can't be given back unless
1451 * the QH is stopped or has finished unlinking. */
1452 if (status
== ECONNRESET
) {
1453 if (QH_FINISHED_UNLINKING(qh
))
1455 else if (!qh
->is_stopped
)
1459 uhci_giveback_urb(uhci
, qh
, urb
);
1460 if (status
< 0 && qh
->type
!= USB_ENDPOINT_XFER_ISOC
)
1464 /* If the QH is neither stopped nor finished unlinking (normal case),
1465 * our work here is done. */
1466 if (QH_FINISHED_UNLINKING(qh
))
1468 else if (!qh
->is_stopped
)
1471 /* Otherwise give back each of the dequeued URBs */
1473 list_for_each_entry(urbp
, &qh
->queue
, node
) {
1475 if (urb
->status
!= -EINPROGRESS
) {
1477 /* Fix up the TD links and save the toggles for
1478 * non-Isochronous queues. For Isochronous queues,
1479 * test for too-recent dequeues. */
1480 if (!uhci_cleanup_queue(uhci
, qh
, urb
)) {
1484 uhci_giveback_urb(uhci
, qh
, urb
);
1490 /* There are no more dequeued URBs. If there are still URBs on the
1491 * queue, the QH can now be re-activated. */
1492 if (!list_empty(&qh
->queue
)) {
1493 if (qh
->needs_fixup
)
1494 uhci_fixup_toggles(qh
, 0);
1496 /* If the first URB on the queue wants FSBR but its time
1497 * limit has expired, set the next TD to interrupt on
1498 * completion before reactivating the QH. */
1499 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1500 if (urbp
->fsbr
&& qh
->wait_expired
) {
1501 struct uhci_td
*td
= list_entry(urbp
->td_list
.next
,
1502 struct uhci_td
, list
);
1504 td
->status
|= __cpu_to_le32(TD_CTRL_IOC
);
1507 uhci_activate_qh(uhci
, qh
);
1510 /* The queue is empty. The QH can become idle if it is fully
1512 else if (QH_FINISHED_UNLINKING(qh
))
1513 uhci_make_qh_idle(uhci
, qh
);
1517 * Check for queues that have made some forward progress.
1518 * Returns 0 if the queue is not Isochronous, is ACTIVE, and
1519 * has not advanced since last examined; 1 otherwise.
1521 * Early Intel controllers have a bug which causes qh->element sometimes
1522 * not to advance when a TD completes successfully. The queue remains
1523 * stuck on the inactive completed TD. We detect such cases and advance
1524 * the element pointer by hand.
1526 static int uhci_advance_check(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
1528 struct urb_priv
*urbp
= NULL
;
1533 if (qh
->type
== USB_ENDPOINT_XFER_ISOC
)
1536 /* Treat an UNLINKING queue as though it hasn't advanced.
1537 * This is okay because reactivation will treat it as though
1538 * it has advanced, and if it is going to become IDLE then
1539 * this doesn't matter anyway. Furthermore it's possible
1540 * for an UNLINKING queue not to have any URBs at all, or
1541 * for its first URB not to have any TDs (if it was dequeued
1542 * just as it completed). So it's not easy in any case to
1543 * test whether such queues have advanced. */
1544 if (qh
->state
!= QH_STATE_ACTIVE
) {
1549 urbp
= list_entry(qh
->queue
.next
, struct urb_priv
, node
);
1550 td
= list_entry(urbp
->td_list
.next
, struct uhci_td
, list
);
1551 status
= td_status(td
);
1552 if (!(status
& TD_CTRL_ACTIVE
)) {
1554 /* We're okay, the queue has advanced */
1555 qh
->wait_expired
= 0;
1556 qh
->advance_jiffies
= jiffies
;
1562 /* The queue hasn't advanced; check for timeout */
1563 if (qh
->wait_expired
)
1566 if (time_after(jiffies
, qh
->advance_jiffies
+ QH_WAIT_TIMEOUT
)) {
1568 /* Detect the Intel bug and work around it */
1569 if (qh
->post_td
&& qh_element(qh
) ==
1570 cpu_to_le32(qh
->post_td
->dma_handle
)) {
1571 qh
->element
= qh
->post_td
->link
;
1572 qh
->advance_jiffies
= jiffies
;
1577 qh
->wait_expired
= 1;
1579 /* If the current URB wants FSBR, unlink it temporarily
1580 * so that we can safely set the next TD to interrupt on
1581 * completion. That way we'll know as soon as the queue
1582 * starts moving again. */
1583 if (urbp
&& urbp
->fsbr
&& !(status
& TD_CTRL_IOC
))
1584 uhci_unlink_qh(uhci
, qh
);
1587 /* Unmoving but not-yet-expired queues keep FSBR alive */
1589 uhci_urbp_wants_fsbr(uhci
, urbp
);
1597 * Process events in the schedule, but only in one thread at a time
1599 static void uhci_scan_schedule(struct uhci_hcd
*uhci
)
1604 /* Don't allow re-entrant calls */
1605 if (uhci
->scan_in_progress
) {
1606 uhci
->need_rescan
= 1;
1609 uhci
->scan_in_progress
= 1;
1611 uhci
->need_rescan
= 0;
1612 uhci
->fsbr_is_wanted
= 0;
1614 uhci_clear_next_interrupt(uhci
);
1615 uhci_get_current_frame_number(uhci
);
1616 uhci
->cur_iso_frame
= uhci
->frame_number
;
1618 /* Go through all the QH queues and process the URBs in each one */
1619 for (i
= 0; i
< UHCI_NUM_SKELQH
- 1; ++i
) {
1620 uhci
->next_qh
= list_entry(uhci
->skelqh
[i
]->node
.next
,
1621 struct uhci_qh
, node
);
1622 while ((qh
= uhci
->next_qh
) != uhci
->skelqh
[i
]) {
1623 uhci
->next_qh
= list_entry(qh
->node
.next
,
1624 struct uhci_qh
, node
);
1626 if (uhci_advance_check(uhci
, qh
)) {
1627 uhci_scan_qh(uhci
, qh
);
1628 if (qh
->state
== QH_STATE_ACTIVE
) {
1629 uhci_urbp_wants_fsbr(uhci
,
1630 list_entry(qh
->queue
.next
, struct urb_priv
, node
));
1636 uhci
->last_iso_frame
= uhci
->cur_iso_frame
;
1637 if (uhci
->need_rescan
)
1639 uhci
->scan_in_progress
= 0;
1641 if (uhci
->fsbr_is_on
&& !uhci
->fsbr_is_wanted
&&
1642 !uhci
->fsbr_expiring
) {
1643 uhci
->fsbr_expiring
= 1;
1644 mod_timer(&uhci
->fsbr_timer
, jiffies
+ FSBR_OFF_DELAY
);
1647 if (list_empty(&uhci
->skel_unlink_qh
->node
))
1648 uhci_clear_next_interrupt(uhci
);
1650 uhci_set_next_interrupt(uhci
);