include/asm-ppc/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  */
   4
   5 #ifdef __KERNEL__
   6 #ifndef _PPC_MMU_H_
   7 #define _PPC_MMU_H_
   8
   9
  10 #ifndef __ASSEMBLY__
  11
  12 /*
  13  * Define physical address type.  Machines using split size
  14  * virtual/physical addressing like 32-bit virtual / 36-bit
  15  * physical need a larger than native word size type. -Matt
  16  */
  17 #ifndef CONFIG_PHYS_64BIT
  18 typedef unsigned long phys_addr_t;
  19 #define PHYS_FMT        "%.8lx"
  20 #else
  21 typedef unsigned long long phys_addr_t;
  22 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
  23 #define PHYS_FMT        "%16Lx"
  24 #endif
  25
  26 typedef struct {
  27         unsigned long id;
  28         unsigned long vdso_base;
  29 } mm_context_t;
  30
  31 /* Hardware Page Table Entry */
  32 typedef struct _PTE {
  33         unsigned long v:1;      /* Entry is valid */
  34         unsigned long vsid:24;  /* Virtual segment identifier */
  35         unsigned long h:1;      /* Hash algorithm indicator */
  36         unsigned long api:6;    /* Abbreviated page index */
  37         unsigned long rpn:20;   /* Real (physical) page number */
  38         unsigned long    :3;    /* Unused */
  39         unsigned long r:1;      /* Referenced */
  40         unsigned long c:1;      /* Changed */
  41         unsigned long w:1;      /* Write-thru cache mode */
  42         unsigned long i:1;      /* Cache inhibited */
  43         unsigned long m:1;      /* Memory coherence */
  44         unsigned long g:1;      /* Guarded */
  45         unsigned long  :1;      /* Unused */
  46         unsigned long pp:2;     /* Page protection */
  47 } PTE;
  48
  49 /* Values for PP (assumes Ks=0, Kp=1) */
  50 #define PP_RWXX 0       /* Supervisor read/write, User none */
  51 #define PP_RWRX 1       /* Supervisor read/write, User read */
  52 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  53 #define PP_RXRX 3       /* Supervisor read,       User read */
  54
  55 /* Segment Register */
  56 typedef struct _SEGREG {
  57         unsigned long t:1;      /* Normal or I/O  type */
  58         unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
  59         unsigned long kp:1;     /* User 'key' (normally 1) */
  60         unsigned long n:1;      /* No-execute */
  61         unsigned long :4;       /* Unused */
  62         unsigned long vsid:24;  /* Virtual Segment Identifier */
  63 } SEGREG;
  64
  65 /* Block Address Translation (BAT) Registers */
  66 typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
  67         unsigned long bepi:15;  /* Effective page index (virtual address) */
  68         unsigned long :8;       /* unused */
  69         unsigned long w:1;
  70         unsigned long i:1;      /* Cache inhibit */
  71         unsigned long m:1;      /* Memory coherence */
  72         unsigned long ks:1;     /* Supervisor key (normally 0) */
  73         unsigned long kp:1;     /* User key (normally 1) */
  74         unsigned long pp:2;     /* Page access protections */
  75 } P601_BATU;
  76
  77 typedef struct _BATU {          /* Upper part of BAT (all except 601) */
  78         unsigned long bepi:15;  /* Effective page index (virtual address) */
  79         unsigned long :4;       /* Unused */
  80         unsigned long bl:11;    /* Block size mask */
  81         unsigned long vs:1;     /* Supervisor valid */
  82         unsigned long vp:1;     /* User valid */
  83 } BATU;
  84
  85 typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
  86         unsigned long brpn:15;  /* Real page index (physical address) */
  87         unsigned long :10;      /* Unused */
  88         unsigned long v:1;      /* Valid bit */
  89         unsigned long bl:6;     /* Block size mask */
  90 } P601_BATL;
  91
  92 typedef struct _BATL {          /* Lower part of BAT (all except 601) */
  93         unsigned long brpn:15;  /* Real page index (physical address) */
  94         unsigned long :10;      /* Unused */
  95         unsigned long w:1;      /* Write-thru cache */
  96         unsigned long i:1;      /* Cache inhibit */
  97         unsigned long m:1;      /* Memory coherence */
  98         unsigned long g:1;      /* Guarded (MBZ in IBAT) */
  99         unsigned long :1;       /* Unused */
 100         unsigned long pp:2;     /* Page access protections */
 101 } BATL;
 102
 103 typedef struct _BAT {
 104         BATU batu;              /* Upper register */
 105         BATL batl;              /* Lower register */
 106 } BAT;
 107
 108 typedef struct _P601_BAT {
 109         P601_BATU batu;         /* Upper register */
 110         P601_BATL batl;         /* Lower register */
 111 } P601_BAT;
 112
 113 #endif /* __ASSEMBLY__ */
 114
 115 /* Block size masks */
 116 #define BL_128K 0x000
 117 #define BL_256K 0x001
 118 #define BL_512K 0x003
 119 #define BL_1M   0x007
 120 #define BL_2M   0x00F
 121 #define BL_4M   0x01F
 122 #define BL_8M   0x03F
 123 #define BL_16M  0x07F
 124 #define BL_32M  0x0FF
 125 #define BL_64M  0x1FF
 126 #define BL_128M 0x3FF
 127 #define BL_256M 0x7FF
 128
 129 /* BAT Access Protection */
 130 #define BPP_XX  0x00            /* No access */
 131 #define BPP_RX  0x01            /* Read only */
 132 #define BPP_RW  0x02            /* Read/write */
 133
 134 /* Control/status registers for the MPC8xx.
 135  * A write operation to these registers causes serialized access.
 136  * During software tablewalk, the registers used perform mask/shift-add
 137  * operations when written/read.  A TLB entry is created when the Mx_RPN
 138  * is written, and the contents of several registers are used to
 139  * create the entry.
 140  */
 141 #define SPRN_MI_CTR     784     /* Instruction TLB control register */
 142 #define MI_GPM          0x80000000      /* Set domain manager mode */
 143 #define MI_PPM          0x40000000      /* Set subpage protection */
 144 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 145 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 146 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 147 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
 148 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
 149
 150 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 151  * Ks = 0, Kp = 1.
 152  */
 153 #define SPRN_MI_AP      786
 154 #define MI_Ks           0x80000000      /* Should not be set */
 155 #define MI_Kp           0x40000000      /* Should always be set */
 156
 157 /* The effective page number register.  When read, contains the information
 158  * about the last instruction TLB miss.  When MI_RPN is written, bits in
 159  * this register are used to create the TLB entry.
 160  */
 161 #define SPRN_MI_EPN     787
 162 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
 163 #define MI_EVALID       0x00000200      /* Entry is valid */
 164 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
 165                                         /* Reset value is undefined */
 166
 167 /* A "level 1" or "segment" or whatever you want to call it register.
 168  * For the instruction TLB, it contains bits that get loaded into the
 169  * TLB entry when the MI_RPN is written.
 170  */
 171 #define SPRN_MI_TWC     789
 172 #define MI_APG          0x000001e0      /* Access protection group (0) */
 173 #define MI_GUARDED      0x00000010      /* Guarded storage */
 174 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
 175 #define MI_PS8MEG       0x0000000c      /* 8M page size */
 176 #define MI_PS512K       0x00000004      /* 512K page size */
 177 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
 178 #define MI_SVALID       0x00000001      /* Segment entry is valid */
 179                                         /* Reset value is undefined */
 180
 181 /* Real page number.  Defined by the pte.  Writing this register
 182  * causes a TLB entry to be created for the instruction TLB, using
 183  * additional information from the MI_EPN, and MI_TWC registers.
 184  */
 185 #define SPRN_MI_RPN     790
 186
 187 /* Define an RPN value for mapping kernel memory to large virtual
 188  * pages for boot initialization.  This has real page number of 0,
 189  * large page size, shared page, cache enabled, and valid.
 190  * Also mark all subpages valid and write access.
 191  */
 192 #define MI_BOOTINIT     0x000001fd
 193
 194 #define SPRN_MD_CTR     792     /* Data TLB control register */
 195 #define MD_GPM          0x80000000      /* Set domain manager mode */
 196 #define MD_PPM          0x40000000      /* Set subpage protection */
 197 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 198 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
 199 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 200 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
 201 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 202 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
 203 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 204
 205 #define SPRN_M_CASID    793     /* Address space ID (context) to match */
 206 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 207
 208
 209 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 210  * Ks = 0, Kp = 1.
 211  */
 212 #define SPRN_MD_AP      794
 213 #define MD_Ks           0x80000000      /* Should not be set */
 214 #define MD_Kp           0x40000000      /* Should always be set */
 215
 216 /* The effective page number register.  When read, contains the information
 217  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 218  * this register are used to create the TLB entry.
 219  */
 220 #define SPRN_MD_EPN     795
 221 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 222 #define MD_EVALID       0x00000200      /* Entry is valid */
 223 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 224                                         /* Reset value is undefined */
 225
 226 /* The pointer to the base address of the first level page table.
 227  * During a software tablewalk, reading this register provides the address
 228  * of the entry associated with MD_EPN.
 229  */
 230 #define SPRN_M_TWB      796
 231 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 232 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 233                                         /* Reset value is undefined */
 234
 235 /* A "level 1" or "segment" or whatever you want to call it register.
 236  * For the data TLB, it contains bits that get loaded into the TLB entry
 237  * when the MD_RPN is written.  It is also provides the hardware assist
 238  * for finding the PTE address during software tablewalk.
 239  */
 240 #define SPRN_MD_TWC     797
 241 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 242 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 243 #define MD_APG          0x000001e0      /* Access protection group (0) */
 244 #define MD_GUARDED      0x00000010      /* Guarded storage */
 245 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 246 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 247 #define MD_PS512K       0x00000004      /* 512K page size */
 248 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 249 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 250 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 251                                         /* Reset value is undefined */
 252
 253
 254 /* Real page number.  Defined by the pte.  Writing this register
 255  * causes a TLB entry to be created for the data TLB, using
 256  * additional information from the MD_EPN, and MD_TWC registers.
 257  */
 258 #define SPRN_MD_RPN     798
 259
 260 /* This is a temporary storage register that could be used to save
 261  * a processor working register during a tablewalk.
 262  */
 263 #define SPRN_M_TW       799
 264
 265 /*
 266  * At present, all PowerPC 400-class processors share a similar TLB
 267  * architecture. The instruction and data sides share a unified,
 268  * 64-entry, fully-associative TLB which is maintained totally under
 269  * software control. In addition, the instruction side has a
 270  * hardware-managed, 4-entry, fully- associative TLB which serves as a
 271  * first level to the shared TLB. These two TLBs are known as the UTLB
 272  * and ITLB, respectively.
 273  */
 274
 275 #define        PPC4XX_TLB_SIZE 64
 276
 277 /*
 278  * TLB entries are defined by a "high" tag portion and a "low" data
 279  * portion.  On all architectures, the data portion is 32-bits.
 280  *
 281  * TLB entries are managed entirely under software control by reading,
 282  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 283  * instructions.
 284  */
 285
 286 #define TLB_LO          1
 287 #define TLB_HI          0
 288
 289 #define TLB_DATA        TLB_LO
 290 #define TLB_TAG         TLB_HI
 291
 292 /* Tag portion */
 293
 294 #define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
 295 #define TLB_PAGESZ_MASK 0x00000380
 296 #define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
 297 #define   PAGESZ_1K             0
 298 #define   PAGESZ_4K             1
 299 #define   PAGESZ_16K            2
 300 #define   PAGESZ_64K            3
 301 #define   PAGESZ_256K           4
 302 #define   PAGESZ_1M             5
 303 #define   PAGESZ_4M             6
 304 #define   PAGESZ_16M            7
 305 #define TLB_VALID       0x00000040      /* Entry is valid */
 306
 307 /* Data portion */
 308
 309 #define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
 310 #define TLB_PERM_MASK   0x00000300
 311 #define TLB_EX          0x00000200      /* Instruction execution allowed */
 312 #define TLB_WR          0x00000100      /* Writes permitted */
 313 #define TLB_ZSEL_MASK   0x000000F0
 314 #define TLB_ZSEL(x)     (((x) & 0xF) << 4)
 315 #define TLB_ATTR_MASK   0x0000000F
 316 #define TLB_W           0x00000008      /* Caching is write-through */
 317 #define TLB_I           0x00000004      /* Caching is inhibited */
 318 #define TLB_M           0x00000002      /* Memory is coherent */
 319 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
 320
 321 /*
 322  * PPC440 support
 323  */
 324 #define PPC44x_MMUCR_TID        0x000000ff
 325 #define PPC44x_MMUCR_STS        0x00010000
 326
 327 #define PPC44x_TLB_PAGEID       0
 328 #define PPC44x_TLB_XLAT         1
 329 #define PPC44x_TLB_ATTRIB       2
 330
 331 /* Page identification fields */
 332 #define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
 333 #define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
 334 #define PPC44x_TLB_TS           0x00000100      /* Translation address space */
 335 #define PPC44x_TLB_1K           0x00000000      /* Page sizes */
 336 #define PPC44x_TLB_4K           0x00000010
 337 #define PPC44x_TLB_16K          0x00000020
 338 #define PPC44x_TLB_64K          0x00000030
 339 #define PPC44x_TLB_256K         0x00000040
 340 #define PPC44x_TLB_1M           0x00000050
 341 #define PPC44x_TLB_16M          0x00000070
 342 #define PPC44x_TLB_256M         0x00000090
 343
 344 /* Translation fields */
 345 #define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
 346 #define PPC44x_TLB_ERPN_MASK    0x0000000f
 347
 348 /* Storage attribute and access control fields */
 349 #define PPC44x_TLB_ATTR_MASK    0x0000ff80
 350 #define PPC44x_TLB_U0           0x00008000      /* User 0 */
 351 #define PPC44x_TLB_U1           0x00004000      /* User 1 */
 352 #define PPC44x_TLB_U2           0x00002000      /* User 2 */
 353 #define PPC44x_TLB_U3           0x00001000      /* User 3 */
 354 #define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
 355 #define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
 356 #define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
 357 #define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
 358 #define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
 359
 360 #define PPC44x_TLB_PERM_MASK    0x0000003f
 361 #define PPC44x_TLB_UX           0x00000020      /* User execution */
 362 #define PPC44x_TLB_UW           0x00000010      /* User write */
 363 #define PPC44x_TLB_UR           0x00000008      /* User read */
 364 #define PPC44x_TLB_SX           0x00000004      /* Super execution */
 365 #define PPC44x_TLB_SW           0x00000002      /* Super write */
 366 #define PPC44x_TLB_SR           0x00000001      /* Super read */
 367
 368 /* Book-E defined page sizes */
 369 #define BOOKE_PAGESZ_1K         0
 370 #define BOOKE_PAGESZ_4K         1
 371 #define BOOKE_PAGESZ_16K        2
 372 #define BOOKE_PAGESZ_64K        3
 373 #define BOOKE_PAGESZ_256K       4
 374 #define BOOKE_PAGESZ_1M         5
 375 #define BOOKE_PAGESZ_4M         6
 376 #define BOOKE_PAGESZ_16M        7
 377 #define BOOKE_PAGESZ_64M        8
 378 #define BOOKE_PAGESZ_256M       9
 379 #define BOOKE_PAGESZ_1GB        10
 380 #define BOOKE_PAGESZ_4GB        11
 381 #define BOOKE_PAGESZ_16GB       12
 382 #define BOOKE_PAGESZ_64GB       13
 383 #define BOOKE_PAGESZ_256GB      14
 384 #define BOOKE_PAGESZ_1TB        15
 385
 386 #ifndef CONFIG_SERIAL_TEXT_DEBUG
 387 #define PPC44x_EARLY_TLBS       1
 388 #else
 389 #define PPC44x_EARLY_TLBS       2
 390 #endif
 391
 392 /*
 393  * Freescale Book-E MMU support
 394  */
 395
 396 #define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
 397 #define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
 398 #define MAS0_NV(x)      ((x) & 0x00000FFF)
 399
 400 #define MAS1_VALID      0x80000000
 401 #define MAS1_IPROT      0x40000000
 402 #define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
 403 #define MAS1_TS         0x00001000
 404 #define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
 405
 406 #define MAS2_EPN        0xFFFFF000
 407 #define MAS2_X0         0x00000040
 408 #define MAS2_X1         0x00000020
 409 #define MAS2_W          0x00000010
 410 #define MAS2_I          0x00000008
 411 #define MAS2_M          0x00000004
 412 #define MAS2_G          0x00000002
 413 #define MAS2_E          0x00000001
 414
 415 #define MAS3_RPN        0xFFFFF000
 416 #define MAS3_U0         0x00000200
 417 #define MAS3_U1         0x00000100
 418 #define MAS3_U2         0x00000080
 419 #define MAS3_U3         0x00000040
 420 #define MAS3_UX         0x00000020
 421 #define MAS3_SX         0x00000010
 422 #define MAS3_UW         0x00000008
 423 #define MAS3_SW         0x00000004
 424 #define MAS3_UR         0x00000002
 425 #define MAS3_SR         0x00000001
 426
 427 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
 428 #define MAS4_TIDDSEL    0x000F0000
 429 #define MAS4_TSIZED(x)  MAS1_TSIZE(x)
 430 #define MAS4_X0D        0x00000040
 431 #define MAS4_X1D        0x00000020
 432 #define MAS4_WD         0x00000010
 433 #define MAS4_ID         0x00000008
 434 #define MAS4_MD         0x00000004
 435 #define MAS4_GD         0x00000002
 436 #define MAS4_ED         0x00000001
 437
 438 #define MAS6_SPID0      0x3FFF0000
 439 #define MAS6_SPID1      0x00007FFE
 440 #define MAS6_SAS        0x00000001
 441 #define MAS6_SPID       MAS6_SPID0
 442
 443 #define MAS7_RPN        0xFFFFFFFF
 444
 445 #endif /* _PPC_MMU_H_ */
 446 #endif /* __KERNEL__ */