2 * FarSync WAN driver for Linux (2.6.x kernel version)
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
25 #include <linux/hdlc.h>
27 #include <asm/uaccess.h>
34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36 MODULE_LICENSE("GPL");
38 /* Driver configuration and global parameters
39 * ==========================================
42 /* Number of ports (per card) and cards supported
44 #define FST_MAX_PORTS 4
45 #define FST_MAX_CARDS 32
47 /* Default parameters for the link
49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
51 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
52 * of frames on the way down to the card
53 * so that we can keep the card busy
54 * and maximise throughput
56 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
58 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
59 * control from network layer */
60 #define FST_MAX_MTU 8000 /* Huge but possible */
61 #define FST_DEF_MTU 1500 /* Common sane value */
63 #define FST_TX_TIMEOUT (2*HZ)
66 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
68 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
72 * Modules parameters and associated varaibles
74 static int fst_txq_low
= FST_LOW_WATER_MARK
;
75 static int fst_txq_high
= FST_HIGH_WATER_MARK
;
76 static int fst_max_reads
= 7;
77 static int fst_excluded_cards
= 0;
78 static int fst_excluded_list
[FST_MAX_CARDS
];
80 module_param(fst_txq_low
, int, 0);
81 module_param(fst_txq_high
, int, 0);
82 module_param(fst_max_reads
, int, 0);
83 module_param(fst_excluded_cards
, int, 0);
84 module_param_array(fst_excluded_list
, int, NULL
, 0);
86 /* Card shared memory layout
87 * =========================
91 /* This information is derived in part from the FarSite FarSync Smc.h
92 * file. Unfortunately various name clashes and the non-portability of the
93 * bit field declarations in that file have meant that I have chosen to
94 * recreate the information here.
96 * The SMC (Shared Memory Configuration) has a version number that is
97 * incremented every time there is a significant change. This number can
98 * be used to check that we have not got out of step with the firmware
99 * contained in the .CDE files.
101 #define SMC_VERSION 24
103 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
105 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
106 * configuration structure */
107 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
110 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
111 #define LEN_RX_BUFFER 8192
113 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
114 #define LEN_SMALL_RX_BUFFER 256
116 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
117 #define NUM_RX_BUFFER 8
119 /* Interrupt retry time in milliseconds */
120 #define INT_RETRY_TIME 2
122 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
123 * of buffer descriptors. The structure is almost identical to that used
124 * in the LANCE Ethernet controllers. Details available as PDF from the
125 * AMD web site: http://www.amd.com/products/epd/processors/\
126 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
128 struct txdesc
{ /* Transmit descriptor */
129 volatile u16 ladr
; /* Low order address of packet. This is a
130 * linear address in the Am186 memory space
132 volatile u8 hadr
; /* High order address. Low 4 bits only, high 4
135 volatile u8 bits
; /* Status and config */
136 volatile u16 bcnt
; /* 2s complement of packet size in low 15 bits.
137 * Transmit terminal count interrupt enable in
140 u16 unused
; /* Not used in Tx */
143 struct rxdesc
{ /* Receive descriptor */
144 volatile u16 ladr
; /* Low order address of packet */
145 volatile u8 hadr
; /* High order address */
146 volatile u8 bits
; /* Status and config */
147 volatile u16 bcnt
; /* 2s complement of buffer size in low 15 bits.
148 * Receive terminal count interrupt enable in
151 volatile u16 mcnt
; /* Message byte count (15 bits) */
154 /* Convert a length into the 15 bit 2's complement */
155 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
156 /* Since we need to set the high bit to enable the completion interrupt this
157 * can be made a lot simpler
159 #define cnv_bcnt(len) (-(len))
161 /* Status and config bits for the above */
162 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
163 #define TX_STP 0x02 /* Tx: start of packet */
164 #define TX_ENP 0x01 /* Tx: end of packet */
165 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
166 #define RX_FRAM 0x20 /* Rx: framing error */
167 #define RX_OFLO 0x10 /* Rx: overflow error */
168 #define RX_CRC 0x08 /* Rx: CRC error */
169 #define RX_HBUF 0x04 /* Rx: buffer error */
170 #define RX_STP 0x02 /* Rx: start of packet */
171 #define RX_ENP 0x01 /* Rx: end of packet */
173 /* Interrupts from the card are caused by various events which are presented
174 * in a circular buffer as several events may be processed on one physical int
176 #define MAX_CIRBUFF 32
179 u8 rdindex
; /* read, then increment and wrap */
180 u8 wrindex
; /* write, then increment and wrap */
181 u8 evntbuff
[MAX_CIRBUFF
];
184 /* Interrupt event codes.
185 * Where appropriate the two low order bits indicate the port number
187 #define CTLA_CHG 0x18 /* Control signal changed */
188 #define CTLB_CHG 0x19
189 #define CTLC_CHG 0x1A
190 #define CTLD_CHG 0x1B
192 #define INIT_CPLT 0x20 /* Initialisation complete */
193 #define INIT_FAIL 0x21 /* Initialisation failed */
195 #define ABTA_SENT 0x24 /* Abort sent */
196 #define ABTB_SENT 0x25
197 #define ABTC_SENT 0x26
198 #define ABTD_SENT 0x27
200 #define TXA_UNDF 0x28 /* Transmission underflow */
201 #define TXB_UNDF 0x29
202 #define TXC_UNDF 0x2A
203 #define TXD_UNDF 0x2B
208 #define TE1_ALMA 0x30
210 /* Port physical configuration. See farsync.h for field values */
212 u16 lineInterface
; /* Physical interface type */
213 u8 x25op
; /* Unused at present */
214 u8 internalClock
; /* 1 => internal clock, 0 => external */
215 u8 transparentMode
; /* 1 => on, 0 => off */
216 u8 invertClock
; /* 0 => normal, 1 => inverted */
217 u8 padBytes
[6]; /* Padding */
218 u32 lineSpeed
; /* Speed in bps */
221 /* TE1 port physical configuration */
245 u32 receiveBufferDelay
;
246 u32 framingErrorCount
;
247 u32 codeViolationCount
;
252 u8 receiveRemoteAlarm
;
253 u8 alarmIndicationSignal
;
257 /* Finally sling all the above together into the shared memory structure.
258 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
259 * evolving under NT for some time so I guess we're stuck with it.
260 * The structure starts at offset SMC_BASE.
261 * See farsync.h for some field values.
264 /* DMA descriptor rings */
265 struct rxdesc rxDescrRing
[FST_MAX_PORTS
][NUM_RX_BUFFER
];
266 struct txdesc txDescrRing
[FST_MAX_PORTS
][NUM_TX_BUFFER
];
268 /* Obsolete small buffers */
269 u8 smallRxBuffer
[FST_MAX_PORTS
][NUM_RX_BUFFER
][LEN_SMALL_RX_BUFFER
];
270 u8 smallTxBuffer
[FST_MAX_PORTS
][NUM_TX_BUFFER
][LEN_SMALL_TX_BUFFER
];
272 u8 taskStatus
; /* 0x00 => initialising, 0x01 => running,
276 u8 interruptHandshake
; /* Set to 0x01 by adapter to signal interrupt,
277 * set to 0xEE by host to acknowledge interrupt
280 u16 smcVersion
; /* Must match SMC_VERSION */
282 u32 smcFirmwareVersion
; /* 0xIIVVRRBB where II = product ID, VV = major
283 * version, RR = revision and BB = build
286 u16 txa_done
; /* Obsolete completion flags */
295 u16 mailbox
[4]; /* Diagnostics mailbox. Not used */
297 struct cirbuff interruptEvent
; /* interrupt causes */
299 u32 v24IpSts
[FST_MAX_PORTS
]; /* V.24 control input status */
300 u32 v24OpSts
[FST_MAX_PORTS
]; /* V.24 control output status */
302 struct port_cfg portConfig
[FST_MAX_PORTS
];
304 u16 clockStatus
[FST_MAX_PORTS
]; /* lsb: 0=> present, 1=> absent */
306 u16 cableStatus
; /* lsb: 0=> present, 1=> absent */
308 u16 txDescrIndex
[FST_MAX_PORTS
]; /* transmit descriptor ring index */
309 u16 rxDescrIndex
[FST_MAX_PORTS
]; /* receive descriptor ring index */
311 u16 portMailbox
[FST_MAX_PORTS
][2]; /* command, modifier */
312 u16 cardMailbox
[4]; /* Not used */
314 /* Number of times the card thinks the host has
315 * missed an interrupt by not acknowledging
316 * within 2mS (I guess NT has problems)
318 u32 interruptRetryCount
;
320 /* Driver private data used as an ID. We'll not
321 * use this as I'd rather keep such things
322 * in main memory rather than on the PCI bus
324 u32 portHandle
[FST_MAX_PORTS
];
326 /* Count of Tx underflows for stats */
327 u32 transmitBufferUnderflow
[FST_MAX_PORTS
];
329 /* Debounced V.24 control input status */
330 u32 v24DebouncedSts
[FST_MAX_PORTS
];
332 /* Adapter debounce timers. Don't touch */
333 u32 ctsTimer
[FST_MAX_PORTS
];
334 u32 ctsTimerRun
[FST_MAX_PORTS
];
335 u32 dcdTimer
[FST_MAX_PORTS
];
336 u32 dcdTimerRun
[FST_MAX_PORTS
];
338 u32 numberOfPorts
; /* Number of ports detected at startup */
342 u16 cardMode
; /* Bit-mask to enable features:
343 * Bit 0: 1 enables LED identify mode
346 u16 portScheduleOffset
;
348 struct su_config suConfig
; /* TE1 Bits */
349 struct su_status suStatus
;
351 u32 endOfSmcSignature
; /* endOfSmcSignature MUST be the last member of
352 * the structure and marks the end of shared
353 * memory. Adapter code initializes it as
358 /* endOfSmcSignature value */
359 #define END_SIG 0x12345678
361 /* Mailbox values. (portMailbox) */
362 #define NOP 0 /* No operation */
363 #define ACK 1 /* Positive acknowledgement to PC driver */
364 #define NAK 2 /* Negative acknowledgement to PC driver */
365 #define STARTPORT 3 /* Start an HDLC port */
366 #define STOPPORT 4 /* Stop an HDLC port */
367 #define ABORTTX 5 /* Abort the transmitter for a port */
368 #define SETV24O 6 /* Set V24 outputs */
370 /* PLX Chip Register Offsets */
371 #define CNTRL_9052 0x50 /* Control Register */
372 #define CNTRL_9054 0x6c /* Control Register */
374 #define INTCSR_9052 0x4c /* Interrupt control/status register */
375 #define INTCSR_9054 0x68 /* Interrupt control/status register */
377 /* 9054 DMA Registers */
379 * Note that we will be using DMA Channel 0 for copying rx data
380 * and Channel 1 for copying tx data
382 #define DMAMODE0 0x80
383 #define DMAPADR0 0x84
384 #define DMALADR0 0x88
387 #define DMAMODE1 0x94
388 #define DMAPADR1 0x98
389 #define DMALADR1 0x9c
398 #define DMAMARBR 0xac
400 #define FST_MIN_DMA_LEN 64
401 #define FST_RX_DMA_INT 0x01
402 #define FST_TX_DMA_INT 0x02
403 #define FST_CARD_INT 0x04
405 /* Larger buffers are positioned in memory at offset BFM_BASE */
407 u8 txBuffer
[FST_MAX_PORTS
][NUM_TX_BUFFER
][LEN_TX_BUFFER
];
408 u8 rxBuffer
[FST_MAX_PORTS
][NUM_RX_BUFFER
][LEN_RX_BUFFER
];
411 /* Calculate offset of a buffer object within the shared memory window */
412 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
416 /* Device driver private information
417 * =================================
419 /* Per port (line or channel) information
421 struct fst_port_info
{
422 struct net_device
*dev
; /* Device struct - must be first */
423 struct fst_card_info
*card
; /* Card we're associated with */
424 int index
; /* Port index on the card */
425 int hwif
; /* Line hardware (lineInterface copy) */
426 int run
; /* Port is running */
427 int mode
; /* Normal or FarSync raw */
428 int rxpos
; /* Next Rx buffer to use */
429 int txpos
; /* Next Tx buffer to use */
430 int txipos
; /* Next Tx buffer to check for free */
431 int start
; /* Indication of start/stop to network */
433 * A sixteen entry transmit queue
435 int txqs
; /* index to get next buffer to tx */
436 int txqe
; /* index to queue next packet */
437 struct sk_buff
*txq
[FST_TXQ_DEPTH
]; /* The queue */
441 /* Per card information
443 struct fst_card_info
{
444 char __iomem
*mem
; /* Card memory mapped to kernel space */
445 char __iomem
*ctlmem
; /* Control memory for PCI cards */
446 unsigned int phys_mem
; /* Physical memory window address */
447 unsigned int phys_ctlmem
; /* Physical control memory address */
448 unsigned int irq
; /* Interrupt request line number */
449 unsigned int nports
; /* Number of serial ports */
450 unsigned int type
; /* Type index of card */
451 unsigned int state
; /* State of card */
452 spinlock_t card_lock
; /* Lock for SMP access */
453 unsigned short pci_conf
; /* PCI card config in I/O space */
455 struct fst_port_info ports
[FST_MAX_PORTS
];
456 struct pci_dev
*device
; /* Information about the pci device */
457 int card_no
; /* Inst of the card on the system */
458 int family
; /* TxP or TxU */
459 int dmarx_in_progress
;
460 int dmatx_in_progress
;
461 unsigned long int_count
;
462 unsigned long int_time_ave
;
463 void *rx_dma_handle_host
;
464 dma_addr_t rx_dma_handle_card
;
465 void *tx_dma_handle_host
;
466 dma_addr_t tx_dma_handle_card
;
467 struct sk_buff
*dma_skb_rx
;
468 struct fst_port_info
*dma_port_rx
;
469 struct fst_port_info
*dma_port_tx
;
476 /* Convert an HDLC device pointer into a port info pointer and similar */
477 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
478 #define port_to_dev(P) ((P)->dev)
482 * Shared memory window access macros
484 * We have a nice memory based structure above, which could be directly
485 * mapped on i386 but might not work on other architectures unless we use
486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
487 * physical offsets so we have to convert. The only saving grace is that
488 * this should all collapse back to a simple indirection eventually.
490 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
492 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
493 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
494 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
496 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
497 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
498 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
505 static int fst_debug_mask
= { FST_DEBUG
};
507 /* Most common debug activity is to print something if the corresponding bit
508 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
509 * support variable numbers of macro parameters. The inverted if prevents us
510 * eating someone else's else clause.
512 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
515 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
518 #define dbg(X...) /* NOP */
521 /* Printing short cuts
523 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
524 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
525 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
528 * PCI ID lookup table
530 static struct pci_device_id fst_pci_dev_id
[] __devinitdata
= {
531 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T2P
, PCI_ANY_ID
,
532 PCI_ANY_ID
, 0, 0, FST_TYPE_T2P
},
534 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T4P
, PCI_ANY_ID
,
535 PCI_ANY_ID
, 0, 0, FST_TYPE_T4P
},
537 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T1U
, PCI_ANY_ID
,
538 PCI_ANY_ID
, 0, 0, FST_TYPE_T1U
},
540 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T2U
, PCI_ANY_ID
,
541 PCI_ANY_ID
, 0, 0, FST_TYPE_T2U
},
543 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T4U
, PCI_ANY_ID
,
544 PCI_ANY_ID
, 0, 0, FST_TYPE_T4U
},
546 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_TE1
, PCI_ANY_ID
,
547 PCI_ANY_ID
, 0, 0, FST_TYPE_TE1
},
549 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_TE1C
, PCI_ANY_ID
,
550 PCI_ANY_ID
, 0, 0, FST_TYPE_TE1
},
554 MODULE_DEVICE_TABLE(pci
, fst_pci_dev_id
);
557 * Device Driver Work Queues
559 * So that we don't spend too much time processing events in the
560 * Interrupt Service routine, we will declare a work queue per Card
561 * and make the ISR schedule a task in the queue for later execution.
562 * In the 2.4 Kernel we used to use the immediate queue for BH's
563 * Now that they are gone, tasklets seem to be much better than work
567 static void do_bottom_half_tx(struct fst_card_info
*card
);
568 static void do_bottom_half_rx(struct fst_card_info
*card
);
569 static void fst_process_tx_work_q(unsigned long work_q
);
570 static void fst_process_int_work_q(unsigned long work_q
);
572 static DECLARE_TASKLET(fst_tx_task
, fst_process_tx_work_q
, 0);
573 static DECLARE_TASKLET(fst_int_task
, fst_process_int_work_q
, 0);
575 static struct fst_card_info
*fst_card_array
[FST_MAX_CARDS
];
576 static spinlock_t fst_work_q_lock
;
577 static u64 fst_work_txq
;
578 static u64 fst_work_intq
;
581 fst_q_work_item(u64
* queue
, int card_index
)
587 * Grab the queue exclusively
589 spin_lock_irqsave(&fst_work_q_lock
, flags
);
592 * Making an entry in the queue is simply a matter of setting
593 * a bit for the card indicating that there is work to do in the
594 * bottom half for the card. Note the limitation of 64 cards.
595 * That ought to be enough
597 mask
= 1 << card_index
;
599 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
603 fst_process_tx_work_q(unsigned long /*void **/work_q
)
610 * Grab the queue exclusively
612 dbg(DBG_TX
, "fst_process_tx_work_q\n");
613 spin_lock_irqsave(&fst_work_q_lock
, flags
);
614 work_txq
= fst_work_txq
;
616 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
619 * Call the bottom half for each card with work waiting
621 for (i
= 0; i
< FST_MAX_CARDS
; i
++) {
622 if (work_txq
& 0x01) {
623 if (fst_card_array
[i
] != NULL
) {
624 dbg(DBG_TX
, "Calling tx bh for card %d\n", i
);
625 do_bottom_half_tx(fst_card_array
[i
]);
628 work_txq
= work_txq
>> 1;
633 fst_process_int_work_q(unsigned long /*void **/work_q
)
640 * Grab the queue exclusively
642 dbg(DBG_INTR
, "fst_process_int_work_q\n");
643 spin_lock_irqsave(&fst_work_q_lock
, flags
);
644 work_intq
= fst_work_intq
;
646 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
649 * Call the bottom half for each card with work waiting
651 for (i
= 0; i
< FST_MAX_CARDS
; i
++) {
652 if (work_intq
& 0x01) {
653 if (fst_card_array
[i
] != NULL
) {
655 "Calling rx & tx bh for card %d\n", i
);
656 do_bottom_half_rx(fst_card_array
[i
]);
657 do_bottom_half_tx(fst_card_array
[i
]);
660 work_intq
= work_intq
>> 1;
664 /* Card control functions
665 * ======================
667 /* Place the processor in reset state
669 * Used to be a simple write to card control space but a glitch in the latest
670 * AMD Am186CH processor means that we now have to do it by asserting and de-
671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
672 * at offset 9052_CNTRL. Note the updates for the TXU.
675 fst_cpureset(struct fst_card_info
*card
)
677 unsigned char interrupt_line_register
;
678 unsigned long j
= jiffies
+ 1;
681 if (card
->family
== FST_FAMILY_TXU
) {
682 if (pci_read_config_byte
683 (card
->device
, PCI_INTERRUPT_LINE
, &interrupt_line_register
)) {
685 "Error in reading interrupt line register\n");
688 * Assert PLX software reset and Am186 hardware reset
689 * and then deassert the PLX software reset but 186 still in reset
691 outw(0x440f, card
->pci_conf
+ CNTRL_9054
+ 2);
692 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
694 * We are delaying here to allow the 9054 to reset itself
699 outw(0x240f, card
->pci_conf
+ CNTRL_9054
+ 2);
701 * We are delaying here to allow the 9054 to reload its eeprom
706 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
708 if (pci_write_config_byte
709 (card
->device
, PCI_INTERRUPT_LINE
, interrupt_line_register
)) {
711 "Error in writing interrupt line register\n");
715 regval
= inl(card
->pci_conf
+ CNTRL_9052
);
717 outl(regval
| 0x40000000, card
->pci_conf
+ CNTRL_9052
);
718 outl(regval
& ~0x40000000, card
->pci_conf
+ CNTRL_9052
);
722 /* Release the processor from reset
725 fst_cpurelease(struct fst_card_info
*card
)
727 if (card
->family
== FST_FAMILY_TXU
) {
729 * Force posted writes to complete
731 (void) readb(card
->mem
);
734 * Release LRESET DO = 1
735 * Then release Local Hold, DO = 1
737 outw(0x040e, card
->pci_conf
+ CNTRL_9054
+ 2);
738 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
740 (void) readb(card
->ctlmem
);
744 /* Clear the cards interrupt flag
747 fst_clear_intr(struct fst_card_info
*card
)
749 if (card
->family
== FST_FAMILY_TXU
) {
750 (void) readb(card
->ctlmem
);
752 /* Poke the appropriate PLX chip register (same as enabling interrupts)
754 outw(0x0543, card
->pci_conf
+ INTCSR_9052
);
758 /* Enable card interrupts
761 fst_enable_intr(struct fst_card_info
*card
)
763 if (card
->family
== FST_FAMILY_TXU
) {
764 outl(0x0f0c0900, card
->pci_conf
+ INTCSR_9054
);
766 outw(0x0543, card
->pci_conf
+ INTCSR_9052
);
770 /* Disable card interrupts
773 fst_disable_intr(struct fst_card_info
*card
)
775 if (card
->family
== FST_FAMILY_TXU
) {
776 outl(0x00000000, card
->pci_conf
+ INTCSR_9054
);
778 outw(0x0000, card
->pci_conf
+ INTCSR_9052
);
782 /* Process the result of trying to pass a received frame up the stack
785 fst_process_rx_status(int rx_status
, char *name
)
798 dbg(DBG_ASS
, "%s: Receive Low Congestion\n", name
);
804 dbg(DBG_ASS
, "%s: Receive Moderate Congestion\n", name
);
810 dbg(DBG_ASS
, "%s: Receive High Congestion\n", name
);
816 dbg(DBG_ASS
, "%s: Received packet dropped\n", name
);
822 /* Initilaise DMA for PLX 9054
825 fst_init_dma(struct fst_card_info
*card
)
828 * This is only required for the PLX 9054
830 if (card
->family
== FST_FAMILY_TXU
) {
831 pci_set_master(card
->device
);
832 outl(0x00020441, card
->pci_conf
+ DMAMODE0
);
833 outl(0x00020441, card
->pci_conf
+ DMAMODE1
);
834 outl(0x0, card
->pci_conf
+ DMATHR
);
838 /* Tx dma complete interrupt
841 fst_tx_dma_complete(struct fst_card_info
*card
, struct fst_port_info
*port
,
844 struct net_device
*dev
= port_to_dev(port
);
847 * Everything is now set, just tell the card to go
849 dbg(DBG_TX
, "fst_tx_dma_complete\n");
850 FST_WRB(card
, txDescrRing
[port
->index
][txpos
].bits
,
851 DMA_OWN
| TX_STP
| TX_ENP
);
852 dev
->stats
.tx_packets
++;
853 dev
->stats
.tx_bytes
+= len
;
854 dev
->trans_start
= jiffies
;
858 * Mark it for our own raw sockets interface
860 static __be16
farsync_type_trans(struct sk_buff
*skb
, struct net_device
*dev
)
863 skb_reset_mac_header(skb
);
864 skb
->pkt_type
= PACKET_HOST
;
865 return htons(ETH_P_CUST
);
868 /* Rx dma complete interrupt
871 fst_rx_dma_complete(struct fst_card_info
*card
, struct fst_port_info
*port
,
872 int len
, struct sk_buff
*skb
, int rxp
)
874 struct net_device
*dev
= port_to_dev(port
);
878 dbg(DBG_TX
, "fst_rx_dma_complete\n");
880 memcpy(skb_put(skb
, len
), card
->rx_dma_handle_host
, len
);
882 /* Reset buffer descriptor */
883 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
886 dev
->stats
.rx_packets
++;
887 dev
->stats
.rx_bytes
+= len
;
890 dbg(DBG_RX
, "Pushing the frame up the stack\n");
891 if (port
->mode
== FST_RAW
)
892 skb
->protocol
= farsync_type_trans(skb
, dev
);
894 skb
->protocol
= hdlc_type_trans(skb
, dev
);
895 rx_status
= netif_rx(skb
);
896 fst_process_rx_status(rx_status
, port_to_dev(port
)->name
);
897 if (rx_status
== NET_RX_DROP
)
898 dev
->stats
.rx_dropped
++;
902 * Receive a frame through the DMA
905 fst_rx_dma(struct fst_card_info
*card
, unsigned char *skb
,
906 unsigned char *mem
, int len
)
909 * This routine will setup the DMA and start it
912 dbg(DBG_RX
, "In fst_rx_dma %p %p %d\n", skb
, mem
, len
);
913 if (card
->dmarx_in_progress
) {
914 dbg(DBG_ASS
, "In fst_rx_dma while dma in progress\n");
917 outl((unsigned long) skb
, card
->pci_conf
+ DMAPADR0
); /* Copy to here */
918 outl((unsigned long) mem
, card
->pci_conf
+ DMALADR0
); /* from here */
919 outl(len
, card
->pci_conf
+ DMASIZ0
); /* for this length */
920 outl(0x00000000c, card
->pci_conf
+ DMADPR0
); /* In this direction */
923 * We use the dmarx_in_progress flag to flag the channel as busy
925 card
->dmarx_in_progress
= 1;
926 outb(0x03, card
->pci_conf
+ DMACSR0
); /* Start the transfer */
930 * Send a frame through the DMA
933 fst_tx_dma(struct fst_card_info
*card
, unsigned char *skb
,
934 unsigned char *mem
, int len
)
937 * This routine will setup the DMA and start it.
940 dbg(DBG_TX
, "In fst_tx_dma %p %p %d\n", skb
, mem
, len
);
941 if (card
->dmatx_in_progress
) {
942 dbg(DBG_ASS
, "In fst_tx_dma while dma in progress\n");
945 outl((unsigned long) skb
, card
->pci_conf
+ DMAPADR1
); /* Copy from here */
946 outl((unsigned long) mem
, card
->pci_conf
+ DMALADR1
); /* to here */
947 outl(len
, card
->pci_conf
+ DMASIZ1
); /* for this length */
948 outl(0x000000004, card
->pci_conf
+ DMADPR1
); /* In this direction */
951 * We use the dmatx_in_progress to flag the channel as busy
953 card
->dmatx_in_progress
= 1;
954 outb(0x03, card
->pci_conf
+ DMACSR1
); /* Start the transfer */
957 /* Issue a Mailbox command for a port.
958 * Note we issue them on a fire and forget basis, not expecting to see an
959 * error and not waiting for completion.
962 fst_issue_cmd(struct fst_port_info
*port
, unsigned short cmd
)
964 struct fst_card_info
*card
;
965 unsigned short mbval
;
970 spin_lock_irqsave(&card
->card_lock
, flags
);
971 mbval
= FST_RDW(card
, portMailbox
[port
->index
][0]);
974 /* Wait for any previous command to complete */
975 while (mbval
> NAK
) {
976 spin_unlock_irqrestore(&card
->card_lock
, flags
);
977 schedule_timeout_uninterruptible(1);
978 spin_lock_irqsave(&card
->card_lock
, flags
);
980 if (++safety
> 2000) {
981 printk_err("Mailbox safety timeout\n");
985 mbval
= FST_RDW(card
, portMailbox
[port
->index
][0]);
988 dbg(DBG_CMD
, "Mailbox clear after %d jiffies\n", safety
);
991 dbg(DBG_CMD
, "issue_cmd: previous command was NAK'd\n");
994 FST_WRW(card
, portMailbox
[port
->index
][0], cmd
);
996 if (cmd
== ABORTTX
|| cmd
== STARTPORT
) {
1002 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1005 /* Port output signals control
1008 fst_op_raise(struct fst_port_info
*port
, unsigned int outputs
)
1010 outputs
|= FST_RDL(port
->card
, v24OpSts
[port
->index
]);
1011 FST_WRL(port
->card
, v24OpSts
[port
->index
], outputs
);
1014 fst_issue_cmd(port
, SETV24O
);
1018 fst_op_lower(struct fst_port_info
*port
, unsigned int outputs
)
1020 outputs
= ~outputs
& FST_RDL(port
->card
, v24OpSts
[port
->index
]);
1021 FST_WRL(port
->card
, v24OpSts
[port
->index
], outputs
);
1024 fst_issue_cmd(port
, SETV24O
);
1028 * Setup port Rx buffers
1031 fst_rx_config(struct fst_port_info
*port
)
1035 unsigned int offset
;
1036 unsigned long flags
;
1037 struct fst_card_info
*card
;
1041 spin_lock_irqsave(&card
->card_lock
, flags
);
1042 for (i
= 0; i
< NUM_RX_BUFFER
; i
++) {
1043 offset
= BUF_OFFSET(rxBuffer
[pi
][i
][0]);
1045 FST_WRW(card
, rxDescrRing
[pi
][i
].ladr
, (u16
) offset
);
1046 FST_WRB(card
, rxDescrRing
[pi
][i
].hadr
, (u8
) (offset
>> 16));
1047 FST_WRW(card
, rxDescrRing
[pi
][i
].bcnt
, cnv_bcnt(LEN_RX_BUFFER
));
1048 FST_WRW(card
, rxDescrRing
[pi
][i
].mcnt
, LEN_RX_BUFFER
);
1049 FST_WRB(card
, rxDescrRing
[pi
][i
].bits
, DMA_OWN
);
1052 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1056 * Setup port Tx buffers
1059 fst_tx_config(struct fst_port_info
*port
)
1063 unsigned int offset
;
1064 unsigned long flags
;
1065 struct fst_card_info
*card
;
1069 spin_lock_irqsave(&card
->card_lock
, flags
);
1070 for (i
= 0; i
< NUM_TX_BUFFER
; i
++) {
1071 offset
= BUF_OFFSET(txBuffer
[pi
][i
][0]);
1073 FST_WRW(card
, txDescrRing
[pi
][i
].ladr
, (u16
) offset
);
1074 FST_WRB(card
, txDescrRing
[pi
][i
].hadr
, (u8
) (offset
>> 16));
1075 FST_WRW(card
, txDescrRing
[pi
][i
].bcnt
, 0);
1076 FST_WRB(card
, txDescrRing
[pi
][i
].bits
, 0);
1081 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1084 /* TE1 Alarm change interrupt event
1087 fst_intr_te1_alarm(struct fst_card_info
*card
, struct fst_port_info
*port
)
1093 los
= FST_RDB(card
, suStatus
.lossOfSignal
);
1094 rra
= FST_RDB(card
, suStatus
.receiveRemoteAlarm
);
1095 ais
= FST_RDB(card
, suStatus
.alarmIndicationSignal
);
1101 if (netif_carrier_ok(port_to_dev(port
))) {
1102 dbg(DBG_INTR
, "Net carrier off\n");
1103 netif_carrier_off(port_to_dev(port
));
1109 if (!netif_carrier_ok(port_to_dev(port
))) {
1110 dbg(DBG_INTR
, "Net carrier on\n");
1111 netif_carrier_on(port_to_dev(port
));
1116 dbg(DBG_INTR
, "Assert LOS Alarm\n");
1118 dbg(DBG_INTR
, "De-assert LOS Alarm\n");
1120 dbg(DBG_INTR
, "Assert RRA Alarm\n");
1122 dbg(DBG_INTR
, "De-assert RRA Alarm\n");
1125 dbg(DBG_INTR
, "Assert AIS Alarm\n");
1127 dbg(DBG_INTR
, "De-assert AIS Alarm\n");
1130 /* Control signal change interrupt event
1133 fst_intr_ctlchg(struct fst_card_info
*card
, struct fst_port_info
*port
)
1137 signals
= FST_RDL(card
, v24DebouncedSts
[port
->index
]);
1139 if (signals
& (((port
->hwif
== X21
) || (port
->hwif
== X21D
))
1140 ? IPSTS_INDICATE
: IPSTS_DCD
)) {
1141 if (!netif_carrier_ok(port_to_dev(port
))) {
1142 dbg(DBG_INTR
, "DCD active\n");
1143 netif_carrier_on(port_to_dev(port
));
1146 if (netif_carrier_ok(port_to_dev(port
))) {
1147 dbg(DBG_INTR
, "DCD lost\n");
1148 netif_carrier_off(port_to_dev(port
));
1156 fst_log_rx_error(struct fst_card_info
*card
, struct fst_port_info
*port
,
1157 unsigned char dmabits
, int rxp
, unsigned short len
)
1159 struct net_device
*dev
= port_to_dev(port
);
1162 * Increment the appropriate error counter
1164 dev
->stats
.rx_errors
++;
1165 if (dmabits
& RX_OFLO
) {
1166 dev
->stats
.rx_fifo_errors
++;
1167 dbg(DBG_ASS
, "Rx fifo error on card %d port %d buffer %d\n",
1168 card
->card_no
, port
->index
, rxp
);
1170 if (dmabits
& RX_CRC
) {
1171 dev
->stats
.rx_crc_errors
++;
1172 dbg(DBG_ASS
, "Rx crc error on card %d port %d\n",
1173 card
->card_no
, port
->index
);
1175 if (dmabits
& RX_FRAM
) {
1176 dev
->stats
.rx_frame_errors
++;
1177 dbg(DBG_ASS
, "Rx frame error on card %d port %d\n",
1178 card
->card_no
, port
->index
);
1180 if (dmabits
== (RX_STP
| RX_ENP
)) {
1181 dev
->stats
.rx_length_errors
++;
1182 dbg(DBG_ASS
, "Rx length error (%d) on card %d port %d\n",
1183 len
, card
->card_no
, port
->index
);
1187 /* Rx Error Recovery
1190 fst_recover_rx_error(struct fst_card_info
*card
, struct fst_port_info
*port
,
1191 unsigned char dmabits
, int rxp
, unsigned short len
)
1198 * Discard buffer descriptors until we see the start of the
1199 * next frame. Note that for long frames this could be in
1200 * a subsequent interrupt.
1203 while ((dmabits
& (DMA_OWN
| RX_STP
)) == 0) {
1204 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1205 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1206 if (++i
> NUM_RX_BUFFER
) {
1207 dbg(DBG_ASS
, "intr_rx: Discarding more bufs"
1211 dmabits
= FST_RDB(card
, rxDescrRing
[pi
][rxp
].bits
);
1212 dbg(DBG_ASS
, "DMA Bits of next buffer was %x\n", dmabits
);
1214 dbg(DBG_ASS
, "There were %d subsequent buffers in error\n", i
);
1216 /* Discard the terminal buffer */
1217 if (!(dmabits
& DMA_OWN
)) {
1218 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1219 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1226 /* Rx complete interrupt
1229 fst_intr_rx(struct fst_card_info
*card
, struct fst_port_info
*port
)
1231 unsigned char dmabits
;
1236 struct sk_buff
*skb
;
1237 struct net_device
*dev
= port_to_dev(port
);
1239 /* Check we have a buffer to process */
1242 dmabits
= FST_RDB(card
, rxDescrRing
[pi
][rxp
].bits
);
1243 if (dmabits
& DMA_OWN
) {
1244 dbg(DBG_RX
| DBG_INTR
, "intr_rx: No buffer port %d pos %d\n",
1248 if (card
->dmarx_in_progress
) {
1252 /* Get buffer length */
1253 len
= FST_RDW(card
, rxDescrRing
[pi
][rxp
].mcnt
);
1254 /* Discard the CRC */
1258 * This seems to happen on the TE1 interface sometimes
1259 * so throw the frame away and log the event.
1261 printk_err("Frame received with 0 length. Card %d Port %d\n",
1262 card
->card_no
, port
->index
);
1263 /* Return descriptor to card */
1264 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1266 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1271 /* Check buffer length and for other errors. We insist on one packet
1272 * in one buffer. This simplifies things greatly and since we've
1273 * allocated 8K it shouldn't be a real world limitation
1275 dbg(DBG_RX
, "intr_rx: %d,%d: flags %x len %d\n", pi
, rxp
, dmabits
, len
);
1276 if (dmabits
!= (RX_STP
| RX_ENP
) || len
> LEN_RX_BUFFER
- 2) {
1277 fst_log_rx_error(card
, port
, dmabits
, rxp
, len
);
1278 fst_recover_rx_error(card
, port
, dmabits
, rxp
, len
);
1283 if ((skb
= dev_alloc_skb(len
)) == NULL
) {
1284 dbg(DBG_RX
, "intr_rx: can't allocate buffer\n");
1286 dev
->stats
.rx_dropped
++;
1288 /* Return descriptor to card */
1289 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1291 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1297 * We know the length we need to receive, len.
1298 * It's not worth using the DMA for reads of less than
1302 if ((len
< FST_MIN_DMA_LEN
) || (card
->family
== FST_FAMILY_TXP
)) {
1303 memcpy_fromio(skb_put(skb
, len
),
1304 card
->mem
+ BUF_OFFSET(rxBuffer
[pi
][rxp
][0]),
1307 /* Reset buffer descriptor */
1308 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1311 dev
->stats
.rx_packets
++;
1312 dev
->stats
.rx_bytes
+= len
;
1315 dbg(DBG_RX
, "Pushing frame up the stack\n");
1316 if (port
->mode
== FST_RAW
)
1317 skb
->protocol
= farsync_type_trans(skb
, dev
);
1319 skb
->protocol
= hdlc_type_trans(skb
, dev
);
1320 rx_status
= netif_rx(skb
);
1321 fst_process_rx_status(rx_status
, port_to_dev(port
)->name
);
1322 if (rx_status
== NET_RX_DROP
)
1323 dev
->stats
.rx_dropped
++;
1325 card
->dma_skb_rx
= skb
;
1326 card
->dma_port_rx
= port
;
1327 card
->dma_len_rx
= len
;
1328 card
->dma_rxpos
= rxp
;
1329 fst_rx_dma(card
, (char *) card
->rx_dma_handle_card
,
1330 (char *) BUF_OFFSET(rxBuffer
[pi
][rxp
][0]), len
);
1332 if (rxp
!= port
->rxpos
) {
1333 dbg(DBG_ASS
, "About to increment rxpos by more than 1\n");
1334 dbg(DBG_ASS
, "rxp = %d rxpos = %d\n", rxp
, port
->rxpos
);
1336 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1341 * The bottom halfs to the ISR
1346 do_bottom_half_tx(struct fst_card_info
*card
)
1348 struct fst_port_info
*port
;
1351 struct sk_buff
*skb
;
1352 unsigned long flags
;
1353 struct net_device
*dev
;
1356 * Find a free buffer for the transmit
1357 * Step through each port on this card
1360 dbg(DBG_TX
, "do_bottom_half_tx\n");
1361 for (pi
= 0, port
= card
->ports
; pi
< card
->nports
; pi
++, port
++) {
1365 dev
= port_to_dev(port
);
1366 while (!(FST_RDB(card
, txDescrRing
[pi
][port
->txpos
].bits
) &
1368 && !(card
->dmatx_in_progress
)) {
1370 * There doesn't seem to be a txdone event per-se
1371 * We seem to have to deduce it, by checking the DMA_OWN
1372 * bit on the next buffer we think we can use
1374 spin_lock_irqsave(&card
->card_lock
, flags
);
1375 if ((txq_length
= port
->txqe
- port
->txqs
) < 0) {
1377 * This is the case where one has wrapped and the
1378 * maths gives us a negative number
1380 txq_length
= txq_length
+ FST_TXQ_DEPTH
;
1382 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1383 if (txq_length
> 0) {
1385 * There is something to send
1387 spin_lock_irqsave(&card
->card_lock
, flags
);
1388 skb
= port
->txq
[port
->txqs
];
1390 if (port
->txqs
== FST_TXQ_DEPTH
) {
1393 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1395 * copy the data and set the required indicators on the
1398 FST_WRW(card
, txDescrRing
[pi
][port
->txpos
].bcnt
,
1399 cnv_bcnt(skb
->len
));
1400 if ((skb
->len
< FST_MIN_DMA_LEN
)
1401 || (card
->family
== FST_FAMILY_TXP
)) {
1402 /* Enqueue the packet with normal io */
1403 memcpy_toio(card
->mem
+
1404 BUF_OFFSET(txBuffer
[pi
]
1407 skb
->data
, skb
->len
);
1409 txDescrRing
[pi
][port
->txpos
].
1411 DMA_OWN
| TX_STP
| TX_ENP
);
1412 dev
->stats
.tx_packets
++;
1413 dev
->stats
.tx_bytes
+= skb
->len
;
1414 dev
->trans_start
= jiffies
;
1416 /* Or do it through dma */
1417 memcpy(card
->tx_dma_handle_host
,
1418 skb
->data
, skb
->len
);
1419 card
->dma_port_tx
= port
;
1420 card
->dma_len_tx
= skb
->len
;
1421 card
->dma_txpos
= port
->txpos
;
1426 BUF_OFFSET(txBuffer
[pi
]
1430 if (++port
->txpos
>= NUM_TX_BUFFER
)
1433 * If we have flow control on, can we now release it?
1436 if (txq_length
< fst_txq_low
) {
1437 netif_wake_queue(port_to_dev
1445 * Nothing to send so break out of the while loop
1454 do_bottom_half_rx(struct fst_card_info
*card
)
1456 struct fst_port_info
*port
;
1460 /* Check for rx completions on all ports on this card */
1461 dbg(DBG_RX
, "do_bottom_half_rx\n");
1462 for (pi
= 0, port
= card
->ports
; pi
< card
->nports
; pi
++, port
++) {
1466 while (!(FST_RDB(card
, rxDescrRing
[pi
][port
->rxpos
].bits
)
1467 & DMA_OWN
) && !(card
->dmarx_in_progress
)) {
1468 if (rx_count
> fst_max_reads
) {
1470 * Don't spend forever in receive processing
1471 * Schedule another event
1473 fst_q_work_item(&fst_work_intq
, card
->card_no
);
1474 tasklet_schedule(&fst_int_task
);
1475 break; /* Leave the loop */
1477 fst_intr_rx(card
, port
);
1484 * The interrupt service routine
1485 * Dev_id is our fst_card_info pointer
1488 fst_intr(int dummy
, void *dev_id
)
1490 struct fst_card_info
*card
= dev_id
;
1491 struct fst_port_info
*port
;
1492 int rdidx
; /* Event buffer indices */
1494 int event
; /* Actual event for processing */
1495 unsigned int dma_intcsr
= 0;
1496 unsigned int do_card_interrupt
;
1497 unsigned int int_retry_count
;
1500 * Check to see if the interrupt was for this card
1502 * Note that the call to clear the interrupt is important
1504 dbg(DBG_INTR
, "intr: %d %p\n", card
->irq
, card
);
1505 if (card
->state
!= FST_RUNNING
) {
1507 ("Interrupt received for card %d in a non running state (%d)\n",
1508 card
->card_no
, card
->state
);
1511 * It is possible to really be running, i.e. we have re-loaded
1513 * Clear and reprime the interrupt source
1515 fst_clear_intr(card
);
1519 /* Clear and reprime the interrupt source */
1520 fst_clear_intr(card
);
1523 * Is the interrupt for this card (handshake == 1)
1525 do_card_interrupt
= 0;
1526 if (FST_RDB(card
, interruptHandshake
) == 1) {
1527 do_card_interrupt
+= FST_CARD_INT
;
1528 /* Set the software acknowledge */
1529 FST_WRB(card
, interruptHandshake
, 0xEE);
1531 if (card
->family
== FST_FAMILY_TXU
) {
1533 * Is it a DMA Interrupt
1535 dma_intcsr
= inl(card
->pci_conf
+ INTCSR_9054
);
1536 if (dma_intcsr
& 0x00200000) {
1538 * DMA Channel 0 (Rx transfer complete)
1540 dbg(DBG_RX
, "DMA Rx xfer complete\n");
1541 outb(0x8, card
->pci_conf
+ DMACSR0
);
1542 fst_rx_dma_complete(card
, card
->dma_port_rx
,
1543 card
->dma_len_rx
, card
->dma_skb_rx
,
1545 card
->dmarx_in_progress
= 0;
1546 do_card_interrupt
+= FST_RX_DMA_INT
;
1548 if (dma_intcsr
& 0x00400000) {
1550 * DMA Channel 1 (Tx transfer complete)
1552 dbg(DBG_TX
, "DMA Tx xfer complete\n");
1553 outb(0x8, card
->pci_conf
+ DMACSR1
);
1554 fst_tx_dma_complete(card
, card
->dma_port_tx
,
1555 card
->dma_len_tx
, card
->dma_txpos
);
1556 card
->dmatx_in_progress
= 0;
1557 do_card_interrupt
+= FST_TX_DMA_INT
;
1562 * Have we been missing Interrupts
1564 int_retry_count
= FST_RDL(card
, interruptRetryCount
);
1565 if (int_retry_count
) {
1566 dbg(DBG_ASS
, "Card %d int_retry_count is %d\n",
1567 card
->card_no
, int_retry_count
);
1568 FST_WRL(card
, interruptRetryCount
, 0);
1571 if (!do_card_interrupt
) {
1575 /* Scehdule the bottom half of the ISR */
1576 fst_q_work_item(&fst_work_intq
, card
->card_no
);
1577 tasklet_schedule(&fst_int_task
);
1579 /* Drain the event queue */
1580 rdidx
= FST_RDB(card
, interruptEvent
.rdindex
) & 0x1f;
1581 wridx
= FST_RDB(card
, interruptEvent
.wrindex
) & 0x1f;
1582 while (rdidx
!= wridx
) {
1583 event
= FST_RDB(card
, interruptEvent
.evntbuff
[rdidx
]);
1584 port
= &card
->ports
[event
& 0x03];
1586 dbg(DBG_INTR
, "Processing Interrupt event: %x\n", event
);
1590 dbg(DBG_INTR
, "TE1 Alarm intr\n");
1592 fst_intr_te1_alarm(card
, port
);
1600 fst_intr_ctlchg(card
, port
);
1607 dbg(DBG_TX
, "Abort complete port %d\n", port
->index
);
1614 /* Difficult to see how we'd get this given that we
1615 * always load up the entire packet for DMA.
1617 dbg(DBG_TX
, "Tx underflow port %d\n", port
->index
);
1618 port_to_dev(port
)->stats
.tx_errors
++;
1619 port_to_dev(port
)->stats
.tx_fifo_errors
++;
1620 dbg(DBG_ASS
, "Tx underflow on card %d port %d\n",
1621 card
->card_no
, port
->index
);
1625 dbg(DBG_INIT
, "Card init OK intr\n");
1629 dbg(DBG_INIT
, "Card init FAILED intr\n");
1630 card
->state
= FST_IFAILED
;
1634 printk_err("intr: unknown card event %d. ignored\n",
1639 /* Bump and wrap the index */
1640 if (++rdidx
>= MAX_CIRBUFF
)
1643 FST_WRB(card
, interruptEvent
.rdindex
, rdidx
);
1647 /* Check that the shared memory configuration is one that we can handle
1648 * and that some basic parameters are correct
1651 check_started_ok(struct fst_card_info
*card
)
1655 /* Check structure version and end marker */
1656 if (FST_RDW(card
, smcVersion
) != SMC_VERSION
) {
1657 printk_err("Bad shared memory version %d expected %d\n",
1658 FST_RDW(card
, smcVersion
), SMC_VERSION
);
1659 card
->state
= FST_BADVERSION
;
1662 if (FST_RDL(card
, endOfSmcSignature
) != END_SIG
) {
1663 printk_err("Missing shared memory signature\n");
1664 card
->state
= FST_BADVERSION
;
1667 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1668 if ((i
= FST_RDB(card
, taskStatus
)) == 0x01) {
1669 card
->state
= FST_RUNNING
;
1670 } else if (i
== 0xFF) {
1671 printk_err("Firmware initialisation failed. Card halted\n");
1672 card
->state
= FST_HALTED
;
1674 } else if (i
!= 0x00) {
1675 printk_err("Unknown firmware status 0x%x\n", i
);
1676 card
->state
= FST_HALTED
;
1680 /* Finally check the number of ports reported by firmware against the
1681 * number we assumed at card detection. Should never happen with
1682 * existing firmware etc so we just report it for the moment.
1684 if (FST_RDL(card
, numberOfPorts
) != card
->nports
) {
1685 printk_warn("Port count mismatch on card %d."
1686 " Firmware thinks %d we say %d\n", card
->card_no
,
1687 FST_RDL(card
, numberOfPorts
), card
->nports
);
1692 set_conf_from_info(struct fst_card_info
*card
, struct fst_port_info
*port
,
1693 struct fstioc_info
*info
)
1696 unsigned char my_framing
;
1698 /* Set things according to the user set valid flags
1699 * Several of the old options have been invalidated/replaced by the
1700 * generic hdlc package.
1703 if (info
->valid
& FSTVAL_PROTO
) {
1704 if (info
->proto
== FST_RAW
)
1705 port
->mode
= FST_RAW
;
1707 port
->mode
= FST_GEN_HDLC
;
1710 if (info
->valid
& FSTVAL_CABLE
)
1713 if (info
->valid
& FSTVAL_SPEED
)
1716 if (info
->valid
& FSTVAL_PHASE
)
1717 FST_WRB(card
, portConfig
[port
->index
].invertClock
,
1719 if (info
->valid
& FSTVAL_MODE
)
1720 FST_WRW(card
, cardMode
, info
->cardMode
);
1721 if (info
->valid
& FSTVAL_TE1
) {
1722 FST_WRL(card
, suConfig
.dataRate
, info
->lineSpeed
);
1723 FST_WRB(card
, suConfig
.clocking
, info
->clockSource
);
1724 my_framing
= FRAMING_E1
;
1725 if (info
->framing
== E1
)
1726 my_framing
= FRAMING_E1
;
1727 if (info
->framing
== T1
)
1728 my_framing
= FRAMING_T1
;
1729 if (info
->framing
== J1
)
1730 my_framing
= FRAMING_J1
;
1731 FST_WRB(card
, suConfig
.framing
, my_framing
);
1732 FST_WRB(card
, suConfig
.structure
, info
->structure
);
1733 FST_WRB(card
, suConfig
.interface
, info
->interface
);
1734 FST_WRB(card
, suConfig
.coding
, info
->coding
);
1735 FST_WRB(card
, suConfig
.lineBuildOut
, info
->lineBuildOut
);
1736 FST_WRB(card
, suConfig
.equalizer
, info
->equalizer
);
1737 FST_WRB(card
, suConfig
.transparentMode
, info
->transparentMode
);
1738 FST_WRB(card
, suConfig
.loopMode
, info
->loopMode
);
1739 FST_WRB(card
, suConfig
.range
, info
->range
);
1740 FST_WRB(card
, suConfig
.txBufferMode
, info
->txBufferMode
);
1741 FST_WRB(card
, suConfig
.rxBufferMode
, info
->rxBufferMode
);
1742 FST_WRB(card
, suConfig
.startingSlot
, info
->startingSlot
);
1743 FST_WRB(card
, suConfig
.losThreshold
, info
->losThreshold
);
1745 FST_WRB(card
, suConfig
.enableIdleCode
, 1);
1747 FST_WRB(card
, suConfig
.enableIdleCode
, 0);
1748 FST_WRB(card
, suConfig
.idleCode
, info
->idleCode
);
1750 if (info
->valid
& FSTVAL_TE1
) {
1751 printk("Setting TE1 data\n");
1752 printk("Line Speed = %d\n", info
->lineSpeed
);
1753 printk("Start slot = %d\n", info
->startingSlot
);
1754 printk("Clock source = %d\n", info
->clockSource
);
1755 printk("Framing = %d\n", my_framing
);
1756 printk("Structure = %d\n", info
->structure
);
1757 printk("interface = %d\n", info
->interface
);
1758 printk("Coding = %d\n", info
->coding
);
1759 printk("Line build out = %d\n", info
->lineBuildOut
);
1760 printk("Equaliser = %d\n", info
->equalizer
);
1761 printk("Transparent mode = %d\n",
1762 info
->transparentMode
);
1763 printk("Loop mode = %d\n", info
->loopMode
);
1764 printk("Range = %d\n", info
->range
);
1765 printk("Tx Buffer mode = %d\n", info
->txBufferMode
);
1766 printk("Rx Buffer mode = %d\n", info
->rxBufferMode
);
1767 printk("LOS Threshold = %d\n", info
->losThreshold
);
1768 printk("Idle Code = %d\n", info
->idleCode
);
1773 if (info
->valid
& FSTVAL_DEBUG
) {
1774 fst_debug_mask
= info
->debug
;
1782 gather_conf_info(struct fst_card_info
*card
, struct fst_port_info
*port
,
1783 struct fstioc_info
*info
)
1787 memset(info
, 0, sizeof (struct fstioc_info
));
1790 info
->kernelVersion
= LINUX_VERSION_CODE
;
1791 info
->nports
= card
->nports
;
1792 info
->type
= card
->type
;
1793 info
->state
= card
->state
;
1794 info
->proto
= FST_GEN_HDLC
;
1797 info
->debug
= fst_debug_mask
;
1800 /* Only mark information as valid if card is running.
1801 * Copy the data anyway in case it is useful for diagnostics
1803 info
->valid
= ((card
->state
== FST_RUNNING
) ? FSTVAL_ALL
: FSTVAL_CARD
)
1809 info
->lineInterface
= FST_RDW(card
, portConfig
[i
].lineInterface
);
1810 info
->internalClock
= FST_RDB(card
, portConfig
[i
].internalClock
);
1811 info
->lineSpeed
= FST_RDL(card
, portConfig
[i
].lineSpeed
);
1812 info
->invertClock
= FST_RDB(card
, portConfig
[i
].invertClock
);
1813 info
->v24IpSts
= FST_RDL(card
, v24IpSts
[i
]);
1814 info
->v24OpSts
= FST_RDL(card
, v24OpSts
[i
]);
1815 info
->clockStatus
= FST_RDW(card
, clockStatus
[i
]);
1816 info
->cableStatus
= FST_RDW(card
, cableStatus
);
1817 info
->cardMode
= FST_RDW(card
, cardMode
);
1818 info
->smcFirmwareVersion
= FST_RDL(card
, smcFirmwareVersion
);
1821 * The T2U can report cable presence for both A or B
1822 * in bits 0 and 1 of cableStatus. See which port we are and
1825 if (card
->family
== FST_FAMILY_TXU
) {
1826 if (port
->index
== 0) {
1830 info
->cableStatus
= info
->cableStatus
& 1;
1835 info
->cableStatus
= info
->cableStatus
>> 1;
1836 info
->cableStatus
= info
->cableStatus
& 1;
1840 * Some additional bits if we are TE1
1842 if (card
->type
== FST_TYPE_TE1
) {
1843 info
->lineSpeed
= FST_RDL(card
, suConfig
.dataRate
);
1844 info
->clockSource
= FST_RDB(card
, suConfig
.clocking
);
1845 info
->framing
= FST_RDB(card
, suConfig
.framing
);
1846 info
->structure
= FST_RDB(card
, suConfig
.structure
);
1847 info
->interface
= FST_RDB(card
, suConfig
.interface
);
1848 info
->coding
= FST_RDB(card
, suConfig
.coding
);
1849 info
->lineBuildOut
= FST_RDB(card
, suConfig
.lineBuildOut
);
1850 info
->equalizer
= FST_RDB(card
, suConfig
.equalizer
);
1851 info
->loopMode
= FST_RDB(card
, suConfig
.loopMode
);
1852 info
->range
= FST_RDB(card
, suConfig
.range
);
1853 info
->txBufferMode
= FST_RDB(card
, suConfig
.txBufferMode
);
1854 info
->rxBufferMode
= FST_RDB(card
, suConfig
.rxBufferMode
);
1855 info
->startingSlot
= FST_RDB(card
, suConfig
.startingSlot
);
1856 info
->losThreshold
= FST_RDB(card
, suConfig
.losThreshold
);
1857 if (FST_RDB(card
, suConfig
.enableIdleCode
))
1858 info
->idleCode
= FST_RDB(card
, suConfig
.idleCode
);
1861 info
->receiveBufferDelay
=
1862 FST_RDL(card
, suStatus
.receiveBufferDelay
);
1863 info
->framingErrorCount
=
1864 FST_RDL(card
, suStatus
.framingErrorCount
);
1865 info
->codeViolationCount
=
1866 FST_RDL(card
, suStatus
.codeViolationCount
);
1867 info
->crcErrorCount
= FST_RDL(card
, suStatus
.crcErrorCount
);
1868 info
->lineAttenuation
= FST_RDL(card
, suStatus
.lineAttenuation
);
1869 info
->lossOfSignal
= FST_RDB(card
, suStatus
.lossOfSignal
);
1870 info
->receiveRemoteAlarm
=
1871 FST_RDB(card
, suStatus
.receiveRemoteAlarm
);
1872 info
->alarmIndicationSignal
=
1873 FST_RDB(card
, suStatus
.alarmIndicationSignal
);
1878 fst_set_iface(struct fst_card_info
*card
, struct fst_port_info
*port
,
1881 sync_serial_settings sync
;
1884 if (ifr
->ifr_settings
.size
!= sizeof (sync
)) {
1889 (&sync
, ifr
->ifr_settings
.ifs_ifsu
.sync
, sizeof (sync
))) {
1898 switch (ifr
->ifr_settings
.type
) {
1900 FST_WRW(card
, portConfig
[i
].lineInterface
, V35
);
1905 FST_WRW(card
, portConfig
[i
].lineInterface
, V24
);
1910 FST_WRW(card
, portConfig
[i
].lineInterface
, X21
);
1915 FST_WRW(card
, portConfig
[i
].lineInterface
, X21D
);
1920 FST_WRW(card
, portConfig
[i
].lineInterface
, T1
);
1925 FST_WRW(card
, portConfig
[i
].lineInterface
, E1
);
1929 case IF_IFACE_SYNC_SERIAL
:
1936 switch (sync
.clock_type
) {
1938 FST_WRB(card
, portConfig
[i
].internalClock
, EXTCLK
);
1942 FST_WRB(card
, portConfig
[i
].internalClock
, INTCLK
);
1948 FST_WRL(card
, portConfig
[i
].lineSpeed
, sync
.clock_rate
);
1953 fst_get_iface(struct fst_card_info
*card
, struct fst_port_info
*port
,
1956 sync_serial_settings sync
;
1959 /* First check what line type is set, we'll default to reporting X.21
1960 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1963 switch (port
->hwif
) {
1965 ifr
->ifr_settings
.type
= IF_IFACE_E1
;
1968 ifr
->ifr_settings
.type
= IF_IFACE_T1
;
1971 ifr
->ifr_settings
.type
= IF_IFACE_V35
;
1974 ifr
->ifr_settings
.type
= IF_IFACE_V24
;
1977 ifr
->ifr_settings
.type
= IF_IFACE_X21D
;
1981 ifr
->ifr_settings
.type
= IF_IFACE_X21
;
1984 if (ifr
->ifr_settings
.size
== 0) {
1985 return 0; /* only type requested */
1987 if (ifr
->ifr_settings
.size
< sizeof (sync
)) {
1992 sync
.clock_rate
= FST_RDL(card
, portConfig
[i
].lineSpeed
);
1993 /* Lucky card and linux use same encoding here */
1994 sync
.clock_type
= FST_RDB(card
, portConfig
[i
].internalClock
) ==
1995 INTCLK
? CLOCK_INT
: CLOCK_EXT
;
1998 if (copy_to_user(ifr
->ifr_settings
.ifs_ifsu
.sync
, &sync
, sizeof (sync
))) {
2002 ifr
->ifr_settings
.size
= sizeof (sync
);
2007 fst_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2009 struct fst_card_info
*card
;
2010 struct fst_port_info
*port
;
2011 struct fstioc_write wrthdr
;
2012 struct fstioc_info info
;
2013 unsigned long flags
;
2016 dbg(DBG_IOCTL
, "ioctl: %x, %p\n", cmd
, ifr
->ifr_data
);
2018 port
= dev_to_port(dev
);
2021 if (!capable(CAP_NET_ADMIN
))
2027 card
->state
= FST_RESET
;
2031 fst_cpurelease(card
);
2032 card
->state
= FST_STARTING
;
2035 case FSTWRITE
: /* Code write (download) */
2037 /* First copy in the header with the length and offset of data
2040 if (ifr
->ifr_data
== NULL
) {
2043 if (copy_from_user(&wrthdr
, ifr
->ifr_data
,
2044 sizeof (struct fstioc_write
))) {
2048 /* Sanity check the parameters. We don't support partial writes
2049 * when going over the top
2051 if (wrthdr
.size
> FST_MEMSIZE
|| wrthdr
.offset
> FST_MEMSIZE
2052 || wrthdr
.size
+ wrthdr
.offset
> FST_MEMSIZE
) {
2056 /* Now copy the data to the card. */
2058 buf
= kmalloc(wrthdr
.size
, GFP_KERNEL
);
2062 if (copy_from_user(buf
,
2063 ifr
->ifr_data
+ sizeof (struct fstioc_write
),
2069 memcpy_toio(card
->mem
+ wrthdr
.offset
, buf
, wrthdr
.size
);
2072 /* Writes to the memory of a card in the reset state constitute
2075 if (card
->state
== FST_RESET
) {
2076 card
->state
= FST_DOWNLOAD
;
2082 /* If card has just been started check the shared memory config
2083 * version and marker
2085 if (card
->state
== FST_STARTING
) {
2086 check_started_ok(card
);
2088 /* If everything checked out enable card interrupts */
2089 if (card
->state
== FST_RUNNING
) {
2090 spin_lock_irqsave(&card
->card_lock
, flags
);
2091 fst_enable_intr(card
);
2092 FST_WRB(card
, interruptHandshake
, 0xEE);
2093 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2097 if (ifr
->ifr_data
== NULL
) {
2101 gather_conf_info(card
, port
, &info
);
2103 if (copy_to_user(ifr
->ifr_data
, &info
, sizeof (info
))) {
2111 * Most of the settings have been moved to the generic ioctls
2112 * this just covers debug and board ident now
2115 if (card
->state
!= FST_RUNNING
) {
2117 ("Attempt to configure card %d in non-running state (%d)\n",
2118 card
->card_no
, card
->state
);
2121 if (copy_from_user(&info
, ifr
->ifr_data
, sizeof (info
))) {
2125 return set_conf_from_info(card
, port
, &info
);
2128 switch (ifr
->ifr_settings
.type
) {
2130 return fst_get_iface(card
, port
, ifr
);
2132 case IF_IFACE_SYNC_SERIAL
:
2139 return fst_set_iface(card
, port
, ifr
);
2142 port
->mode
= FST_RAW
;
2146 if (port
->mode
== FST_RAW
) {
2147 ifr
->ifr_settings
.type
= IF_PROTO_RAW
;
2150 return hdlc_ioctl(dev
, ifr
, cmd
);
2153 port
->mode
= FST_GEN_HDLC
;
2154 dbg(DBG_IOCTL
, "Passing this type to hdlc %x\n",
2155 ifr
->ifr_settings
.type
);
2156 return hdlc_ioctl(dev
, ifr
, cmd
);
2160 /* Not one of ours. Pass through to HDLC package */
2161 return hdlc_ioctl(dev
, ifr
, cmd
);
2166 fst_openport(struct fst_port_info
*port
)
2171 /* Only init things if card is actually running. This allows open to
2172 * succeed for downloads etc.
2174 if (port
->card
->state
== FST_RUNNING
) {
2176 dbg(DBG_OPEN
, "open: found port already running\n");
2178 fst_issue_cmd(port
, STOPPORT
);
2182 fst_rx_config(port
);
2183 fst_tx_config(port
);
2184 fst_op_raise(port
, OPSTS_RTS
| OPSTS_DTR
);
2186 fst_issue_cmd(port
, STARTPORT
);
2189 signals
= FST_RDL(port
->card
, v24DebouncedSts
[port
->index
]);
2190 if (signals
& (((port
->hwif
== X21
) || (port
->hwif
== X21D
))
2191 ? IPSTS_INDICATE
: IPSTS_DCD
))
2192 netif_carrier_on(port_to_dev(port
));
2194 netif_carrier_off(port_to_dev(port
));
2196 txq_length
= port
->txqe
- port
->txqs
;
2204 fst_closeport(struct fst_port_info
*port
)
2206 if (port
->card
->state
== FST_RUNNING
) {
2209 fst_op_lower(port
, OPSTS_RTS
| OPSTS_DTR
);
2211 fst_issue_cmd(port
, STOPPORT
);
2213 dbg(DBG_OPEN
, "close: port not running\n");
2219 fst_open(struct net_device
*dev
)
2222 struct fst_port_info
*port
;
2224 port
= dev_to_port(dev
);
2225 if (!try_module_get(THIS_MODULE
))
2228 if (port
->mode
!= FST_RAW
) {
2229 err
= hdlc_open(dev
);
2235 netif_wake_queue(dev
);
2240 fst_close(struct net_device
*dev
)
2242 struct fst_port_info
*port
;
2243 struct fst_card_info
*card
;
2244 unsigned char tx_dma_done
;
2245 unsigned char rx_dma_done
;
2247 port
= dev_to_port(dev
);
2250 tx_dma_done
= inb(card
->pci_conf
+ DMACSR1
);
2251 rx_dma_done
= inb(card
->pci_conf
+ DMACSR0
);
2253 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2254 card
->dmatx_in_progress
, tx_dma_done
, card
->dmarx_in_progress
,
2257 netif_stop_queue(dev
);
2258 fst_closeport(dev_to_port(dev
));
2259 if (port
->mode
!= FST_RAW
) {
2262 module_put(THIS_MODULE
);
2267 fst_attach(struct net_device
*dev
, unsigned short encoding
, unsigned short parity
)
2270 * Setting currently fixed in FarSync card so we check and forget
2272 if (encoding
!= ENCODING_NRZ
|| parity
!= PARITY_CRC16_PR1_CCITT
)
2278 fst_tx_timeout(struct net_device
*dev
)
2280 struct fst_port_info
*port
;
2281 struct fst_card_info
*card
;
2283 port
= dev_to_port(dev
);
2285 dev
->stats
.tx_errors
++;
2286 dev
->stats
.tx_aborted_errors
++;
2287 dbg(DBG_ASS
, "Tx timeout card %d port %d\n",
2288 card
->card_no
, port
->index
);
2289 fst_issue_cmd(port
, ABORTTX
);
2291 dev
->trans_start
= jiffies
;
2292 netif_wake_queue(dev
);
2297 fst_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2299 struct fst_card_info
*card
;
2300 struct fst_port_info
*port
;
2301 unsigned long flags
;
2304 port
= dev_to_port(dev
);
2306 dbg(DBG_TX
, "fst_start_xmit: length = %d\n", skb
->len
);
2308 /* Drop packet with error if we don't have carrier */
2309 if (!netif_carrier_ok(dev
)) {
2311 dev
->stats
.tx_errors
++;
2312 dev
->stats
.tx_carrier_errors
++;
2314 "Tried to transmit but no carrier on card %d port %d\n",
2315 card
->card_no
, port
->index
);
2319 /* Drop it if it's too big! MTU failure ? */
2320 if (skb
->len
> LEN_TX_BUFFER
) {
2321 dbg(DBG_ASS
, "Packet too large %d vs %d\n", skb
->len
,
2324 dev
->stats
.tx_errors
++;
2329 * We are always going to queue the packet
2330 * so that the bottom half is the only place we tx from
2331 * Check there is room in the port txq
2333 spin_lock_irqsave(&card
->card_lock
, flags
);
2334 if ((txq_length
= port
->txqe
- port
->txqs
) < 0) {
2336 * This is the case where the next free has wrapped but the
2339 txq_length
= txq_length
+ FST_TXQ_DEPTH
;
2341 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2342 if (txq_length
> fst_txq_high
) {
2344 * We have got enough buffers in the pipeline. Ask the network
2345 * layer to stop sending frames down
2347 netif_stop_queue(dev
);
2348 port
->start
= 1; /* I'm using this to signal stop sent up */
2351 if (txq_length
== FST_TXQ_DEPTH
- 1) {
2353 * This shouldn't have happened but such is life
2356 dev
->stats
.tx_errors
++;
2357 dbg(DBG_ASS
, "Tx queue overflow card %d port %d\n",
2358 card
->card_no
, port
->index
);
2365 spin_lock_irqsave(&card
->card_lock
, flags
);
2366 port
->txq
[port
->txqe
] = skb
;
2368 if (port
->txqe
== FST_TXQ_DEPTH
)
2370 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2372 /* Scehdule the bottom half which now does transmit processing */
2373 fst_q_work_item(&fst_work_txq
, card
->card_no
);
2374 tasklet_schedule(&fst_tx_task
);
2380 * Card setup having checked hardware resources.
2381 * Should be pretty bizarre if we get an error here (kernel memory
2382 * exhaustion is one possibility). If we do see a problem we report it
2383 * via a printk and leave the corresponding interface and all that follow
2386 static char *type_strings
[] __devinitdata
= {
2387 "no hardware", /* Should never be seen */
2396 static void __devinit
2397 fst_init_card(struct fst_card_info
*card
)
2402 /* We're working on a number of ports based on the card ID. If the
2403 * firmware detects something different later (should never happen)
2404 * we'll have to revise it in some way then.
2406 for (i
= 0; i
< card
->nports
; i
++) {
2407 err
= register_hdlc_device(card
->ports
[i
].dev
);
2410 printk_err ("Cannot register HDLC device for port %d"
2411 " (errno %d)\n", i
, -err
);
2412 for (j
= i
; j
< card
->nports
; j
++) {
2413 free_netdev(card
->ports
[j
].dev
);
2414 card
->ports
[j
].dev
= NULL
;
2421 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2422 port_to_dev(&card
->ports
[0])->name
,
2423 port_to_dev(&card
->ports
[card
->nports
- 1])->name
,
2424 type_strings
[card
->type
], card
->irq
, card
->nports
);
2428 * Initialise card when detected.
2429 * Returns 0 to indicate success, or errno otherwise.
2431 static int __devinit
2432 fst_add_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2434 static int firsttime_done
= 0;
2435 static int no_of_cards_added
= 0;
2436 struct fst_card_info
*card
;
2440 if (!firsttime_done
) {
2441 printk_info("FarSync WAN driver " FST_USER_VERSION
2442 " (c) 2001-2004 FarSite Communications Ltd.\n");
2444 dbg(DBG_ASS
, "The value of debug mask is %x\n", fst_debug_mask
);
2448 * We are going to be clever and allow certain cards not to be
2449 * configured. An exclude list can be provided in /etc/modules.conf
2451 if (fst_excluded_cards
!= 0) {
2453 * There are cards to exclude
2456 for (i
= 0; i
< fst_excluded_cards
; i
++) {
2457 if ((pdev
->devfn
) >> 3 == fst_excluded_list
[i
]) {
2458 printk_info("FarSync PCI device %d not assigned\n",
2459 (pdev
->devfn
) >> 3);
2465 /* Allocate driver private data */
2466 card
= kzalloc(sizeof (struct fst_card_info
), GFP_KERNEL
);
2468 printk_err("FarSync card found but insufficient memory for"
2469 " driver storage\n");
2473 /* Try to enable the device */
2474 if ((err
= pci_enable_device(pdev
)) != 0) {
2475 printk_err("Failed to enable card. Err %d\n", -err
);
2480 if ((err
= pci_request_regions(pdev
, "FarSync")) !=0) {
2481 printk_err("Failed to allocate regions. Err %d\n", -err
);
2482 pci_disable_device(pdev
);
2487 /* Get virtual addresses of memory regions */
2488 card
->pci_conf
= pci_resource_start(pdev
, 1);
2489 card
->phys_mem
= pci_resource_start(pdev
, 2);
2490 card
->phys_ctlmem
= pci_resource_start(pdev
, 3);
2491 if ((card
->mem
= ioremap(card
->phys_mem
, FST_MEMSIZE
)) == NULL
) {
2492 printk_err("Physical memory remap failed\n");
2493 pci_release_regions(pdev
);
2494 pci_disable_device(pdev
);
2498 if ((card
->ctlmem
= ioremap(card
->phys_ctlmem
, 0x10)) == NULL
) {
2499 printk_err("Control memory remap failed\n");
2500 pci_release_regions(pdev
);
2501 pci_disable_device(pdev
);
2505 dbg(DBG_PCI
, "kernel mem %p, ctlmem %p\n", card
->mem
, card
->ctlmem
);
2507 /* Register the interrupt handler */
2508 if (request_irq(pdev
->irq
, fst_intr
, IRQF_SHARED
, FST_DEV_NAME
, card
)) {
2509 printk_err("Unable to register interrupt %d\n", card
->irq
);
2510 pci_release_regions(pdev
);
2511 pci_disable_device(pdev
);
2512 iounmap(card
->ctlmem
);
2518 /* Record info we need */
2519 card
->irq
= pdev
->irq
;
2520 card
->type
= ent
->driver_data
;
2521 card
->family
= ((ent
->driver_data
== FST_TYPE_T2P
) ||
2522 (ent
->driver_data
== FST_TYPE_T4P
))
2523 ? FST_FAMILY_TXP
: FST_FAMILY_TXU
;
2524 if ((ent
->driver_data
== FST_TYPE_T1U
) ||
2525 (ent
->driver_data
== FST_TYPE_TE1
))
2528 card
->nports
= ((ent
->driver_data
== FST_TYPE_T2P
) ||
2529 (ent
->driver_data
== FST_TYPE_T2U
)) ? 2 : 4;
2531 card
->state
= FST_UNINIT
;
2532 spin_lock_init ( &card
->card_lock
);
2534 for ( i
= 0 ; i
< card
->nports
; i
++ ) {
2535 struct net_device
*dev
= alloc_hdlcdev(&card
->ports
[i
]);
2539 free_netdev(card
->ports
[i
].dev
);
2540 printk_err ("FarSync: out of memory\n");
2541 free_irq(card
->irq
, card
);
2542 pci_release_regions(pdev
);
2543 pci_disable_device(pdev
);
2544 iounmap(card
->ctlmem
);
2549 card
->ports
[i
].dev
= dev
;
2550 card
->ports
[i
].card
= card
;
2551 card
->ports
[i
].index
= i
;
2552 card
->ports
[i
].run
= 0;
2554 hdlc
= dev_to_hdlc(dev
);
2556 /* Fill in the net device info */
2557 /* Since this is a PCI setup this is purely
2558 * informational. Give them the buffer addresses
2559 * and basic card I/O.
2561 dev
->mem_start
= card
->phys_mem
2562 + BUF_OFFSET ( txBuffer
[i
][0][0]);
2563 dev
->mem_end
= card
->phys_mem
2564 + BUF_OFFSET ( txBuffer
[i
][NUM_TX_BUFFER
][0]);
2565 dev
->base_addr
= card
->pci_conf
;
2566 dev
->irq
= card
->irq
;
2568 dev
->tx_queue_len
= FST_TX_QUEUE_LEN
;
2569 dev
->open
= fst_open
;
2570 dev
->stop
= fst_close
;
2571 dev
->do_ioctl
= fst_ioctl
;
2572 dev
->watchdog_timeo
= FST_TX_TIMEOUT
;
2573 dev
->tx_timeout
= fst_tx_timeout
;
2574 hdlc
->attach
= fst_attach
;
2575 hdlc
->xmit
= fst_start_xmit
;
2578 card
->device
= pdev
;
2580 dbg(DBG_PCI
, "type %d nports %d irq %d\n", card
->type
,
2581 card
->nports
, card
->irq
);
2582 dbg(DBG_PCI
, "conf %04x mem %08x ctlmem %08x\n",
2583 card
->pci_conf
, card
->phys_mem
, card
->phys_ctlmem
);
2585 /* Reset the card's processor */
2587 card
->state
= FST_RESET
;
2589 /* Initialise DMA (if required) */
2592 /* Record driver data for later use */
2593 pci_set_drvdata(pdev
, card
);
2595 /* Remainder of card setup */
2596 fst_card_array
[no_of_cards_added
] = card
;
2597 card
->card_no
= no_of_cards_added
++; /* Record instance and bump it */
2598 fst_init_card(card
);
2599 if (card
->family
== FST_FAMILY_TXU
) {
2601 * Allocate a dma buffer for transmit and receives
2603 card
->rx_dma_handle_host
=
2604 pci_alloc_consistent(card
->device
, FST_MAX_MTU
,
2605 &card
->rx_dma_handle_card
);
2606 if (card
->rx_dma_handle_host
== NULL
) {
2607 printk_err("Could not allocate rx dma buffer\n");
2608 fst_disable_intr(card
);
2609 pci_release_regions(pdev
);
2610 pci_disable_device(pdev
);
2611 iounmap(card
->ctlmem
);
2616 card
->tx_dma_handle_host
=
2617 pci_alloc_consistent(card
->device
, FST_MAX_MTU
,
2618 &card
->tx_dma_handle_card
);
2619 if (card
->tx_dma_handle_host
== NULL
) {
2620 printk_err("Could not allocate tx dma buffer\n");
2621 fst_disable_intr(card
);
2622 pci_release_regions(pdev
);
2623 pci_disable_device(pdev
);
2624 iounmap(card
->ctlmem
);
2630 return 0; /* Success */
2634 * Cleanup and close down a card
2636 static void __devexit
2637 fst_remove_one(struct pci_dev
*pdev
)
2639 struct fst_card_info
*card
;
2642 card
= pci_get_drvdata(pdev
);
2644 for (i
= 0; i
< card
->nports
; i
++) {
2645 struct net_device
*dev
= port_to_dev(&card
->ports
[i
]);
2646 unregister_hdlc_device(dev
);
2649 fst_disable_intr(card
);
2650 free_irq(card
->irq
, card
);
2652 iounmap(card
->ctlmem
);
2654 pci_release_regions(pdev
);
2655 if (card
->family
== FST_FAMILY_TXU
) {
2659 pci_free_consistent(card
->device
, FST_MAX_MTU
,
2660 card
->rx_dma_handle_host
,
2661 card
->rx_dma_handle_card
);
2662 pci_free_consistent(card
->device
, FST_MAX_MTU
,
2663 card
->tx_dma_handle_host
,
2664 card
->tx_dma_handle_card
);
2666 fst_card_array
[card
->card_no
] = NULL
;
2669 static struct pci_driver fst_driver
= {
2671 .id_table
= fst_pci_dev_id
,
2672 .probe
= fst_add_one
,
2673 .remove
= __devexit_p(fst_remove_one
),
2683 for (i
= 0; i
< FST_MAX_CARDS
; i
++)
2684 fst_card_array
[i
] = NULL
;
2685 spin_lock_init(&fst_work_q_lock
);
2686 return pci_register_driver(&fst_driver
);
2690 fst_cleanup_module(void)
2692 printk_info("FarSync WAN driver unloading\n");
2693 pci_unregister_driver(&fst_driver
);
2696 module_init(fst_init
);
2697 module_exit(fst_cleanup_module
);