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drivers/net: Kill now superfluous ->last_rx stores.
[linux-2.6/verdex.git] / drivers / net / atlx / atl2.c
blob60c9e5375eed406dd151ac38d7254616028feb88
1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <asm/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/string.h>
44 #include <linux/tcp.h>
45 #include <linux/timer.h>
46 #include <linux/types.h>
47 #include <linux/workqueue.h>
48
49 #include "atl2.h"
50
51 #define ATL2_DRV_VERSION "2.2.3"
52
53 static char atl2_driver_name[] = "atl2";
54 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55 static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56 static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60 MODULE_LICENSE("GPL");
61 MODULE_VERSION(ATL2_DRV_VERSION);
62
63 /*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66 static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70 };
71 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73 static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75 static void atl2_check_options(struct atl2_adapter *adapter);
76
77 /*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85 static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86 {
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123 }
124
125 /*
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134 static void atl2_set_multi(struct net_device *netdev)
135 {
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct dev_mc_list *mc_ptr;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
161 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
162 atl2_hash_set(hw, hash_value);
163 }
164 }
165
166 static void init_ring_ptrs(struct atl2_adapter *adapter)
167 {
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177 }
178
179 /*
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185 static int atl2_configure(struct atl2_adapter *adapter)
186 {
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221 /*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224 */
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283 }
284
285 /*
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292 {
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
314 offset);
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336 /*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341 }
342
343 /*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348 {
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351 }
352
353 /*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358 {
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362 }
363
364 #ifdef NETIF_F_HW_VLAN_TX
365 static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367 {
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387 }
388
389 static void atl2_restore_vlan(struct atl2_adapter *adapter)
390 {
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392 }
393 #endif
394
395 static void atl2_intr_rx(struct atl2_adapter *adapter)
396 {
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
412 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
421 netdev->stats.rx_dropped++;
422 break;
423 }
424 skb_reserve(skb, NET_IP_ALIGN);
425 skb->dev = netdev;
426 memcpy(skb->data, rxd->packet, rx_size);
427 skb_put(skb, rx_size);
428 skb->protocol = eth_type_trans(skb, netdev);
429 #ifdef NETIF_F_HW_VLAN_TX
430 if (adapter->vlgrp && (rxd->status.vlan)) {
431 u16 vlan_tag = (rxd->status.vtag>>4) |
432 ((rxd->status.vtag&7) << 13) |
433 ((rxd->status.vtag&8) << 9);
434 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
435 } else
436 #endif
437 netif_rx(skb);
438 netdev->stats.rx_bytes += rx_size;
439 netdev->stats.rx_packets++;
440 } else {
441 netdev->stats.rx_errors++;
442
443 if (rxd->status.ok && rxd->status.pkt_size <= 60)
444 netdev->stats.rx_length_errors++;
445 if (rxd->status.mcast)
446 netdev->stats.multicast++;
447 if (rxd->status.crc)
448 netdev->stats.rx_crc_errors++;
449 if (rxd->status.align)
450 netdev->stats.rx_frame_errors++;
451 }
452
453 /* advance write ptr */
454 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
455 adapter->rxd_write_ptr = 0;
456 } while (1);
457
458 /* update mailbox? */
459 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
460 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
461 }
462
463 static void atl2_intr_tx(struct atl2_adapter *adapter)
464 {
465 struct net_device *netdev = adapter->netdev;
466 u32 txd_read_ptr;
467 u32 txs_write_ptr;
468 struct tx_pkt_status *txs;
469 struct tx_pkt_header *txph;
470 int free_hole = 0;
471
472 do {
473 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
474 txs = adapter->txs_ring + txs_write_ptr;
475 if (!txs->update)
476 break; /* tx stop here */
477
478 free_hole = 1;
479 txs->update = 0;
480
481 if (++txs_write_ptr == adapter->txs_ring_size)
482 txs_write_ptr = 0;
483 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
484
485 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
486 txph = (struct tx_pkt_header *)
487 (((u8 *)adapter->txd_ring) + txd_read_ptr);
488
489 if (txph->pkt_size != txs->pkt_size) {
490 struct tx_pkt_status *old_txs = txs;
491 printk(KERN_WARNING
492 "%s: txs packet size not consistent with txd"
493 " txd_:0x%08x, txs_:0x%08x!\n",
494 adapter->netdev->name,
495 *(u32 *)txph, *(u32 *)txs);
496 printk(KERN_WARNING
497 "txd read ptr: 0x%x\n",
498 txd_read_ptr);
499 txs = adapter->txs_ring + txs_write_ptr;
500 printk(KERN_WARNING
501 "txs-behind:0x%08x\n",
502 *(u32 *)txs);
503 if (txs_write_ptr < 2) {
504 txs = adapter->txs_ring +
505 (adapter->txs_ring_size +
506 txs_write_ptr - 2);
507 } else {
508 txs = adapter->txs_ring + (txs_write_ptr - 2);
509 }
510 printk(KERN_WARNING
511 "txs-before:0x%08x\n",
512 *(u32 *)txs);
513 txs = old_txs;
514 }
515
516 /* 4for TPH */
517 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
518 if (txd_read_ptr >= adapter->txd_ring_size)
519 txd_read_ptr -= adapter->txd_ring_size;
520
521 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
522
523 /* tx statistics: */
524 if (txs->ok) {
525 netdev->stats.tx_bytes += txs->pkt_size;
526 netdev->stats.tx_packets++;
527 }
528 else
529 netdev->stats.tx_errors++;
530
531 if (txs->defer)
532 netdev->stats.collisions++;
533 if (txs->abort_col)
534 netdev->stats.tx_aborted_errors++;
535 if (txs->late_col)
536 netdev->stats.tx_window_errors++;
537 if (txs->underun)
538 netdev->stats.tx_fifo_errors++;
539 } while (1);
540
541 if (free_hole) {
542 if (netif_queue_stopped(adapter->netdev) &&
543 netif_carrier_ok(adapter->netdev))
544 netif_wake_queue(adapter->netdev);
545 }
546 }
547
548 static void atl2_check_for_link(struct atl2_adapter *adapter)
549 {
550 struct net_device *netdev = adapter->netdev;
551 u16 phy_data = 0;
552
553 spin_lock(&adapter->stats_lock);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 spin_unlock(&adapter->stats_lock);
557
558 /* notify upper layer link down ASAP */
559 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
560 if (netif_carrier_ok(netdev)) { /* old link state: Up */
561 printk(KERN_INFO "%s: %s NIC Link is Down\n",
562 atl2_driver_name, netdev->name);
563 adapter->link_speed = SPEED_0;
564 netif_carrier_off(netdev);
565 netif_stop_queue(netdev);
566 }
567 }
568 schedule_work(&adapter->link_chg_task);
569 }
570
571 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
572 {
573 u16 phy_data;
574 spin_lock(&adapter->stats_lock);
575 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
576 spin_unlock(&adapter->stats_lock);
577 }
578
579 /*
580 * atl2_intr - Interrupt Handler
581 * @irq: interrupt number
582 * @data: pointer to a network interface device structure
583 * @pt_regs: CPU registers structure
584 */
585 static irqreturn_t atl2_intr(int irq, void *data)
586 {
587 struct atl2_adapter *adapter = netdev_priv(data);
588 struct atl2_hw *hw = &adapter->hw;
589 u32 status;
590
591 status = ATL2_READ_REG(hw, REG_ISR);
592 if (0 == status)
593 return IRQ_NONE;
594
595 /* link event */
596 if (status & ISR_PHY)
597 atl2_clear_phy_int(adapter);
598
599 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
600 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
601
602 /* check if PCIE PHY Link down */
603 if (status & ISR_PHY_LINKDOWN) {
604 if (netif_running(adapter->netdev)) { /* reset MAC */
605 ATL2_WRITE_REG(hw, REG_ISR, 0);
606 ATL2_WRITE_REG(hw, REG_IMR, 0);
607 ATL2_WRITE_FLUSH(hw);
608 schedule_work(&adapter->reset_task);
609 return IRQ_HANDLED;
610 }
611 }
612
613 /* check if DMA read/write error? */
614 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
615 ATL2_WRITE_REG(hw, REG_ISR, 0);
616 ATL2_WRITE_REG(hw, REG_IMR, 0);
617 ATL2_WRITE_FLUSH(hw);
618 schedule_work(&adapter->reset_task);
619 return IRQ_HANDLED;
620 }
621
622 /* link event */
623 if (status & (ISR_PHY | ISR_MANUAL)) {
624 adapter->netdev->stats.tx_carrier_errors++;
625 atl2_check_for_link(adapter);
626 }
627
628 /* transmit event */
629 if (status & ISR_TX_EVENT)
630 atl2_intr_tx(adapter);
631
632 /* rx exception */
633 if (status & ISR_RX_EVENT)
634 atl2_intr_rx(adapter);
635
636 /* re-enable Interrupt */
637 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
638 return IRQ_HANDLED;
639 }
640
641 static int atl2_request_irq(struct atl2_adapter *adapter)
642 {
643 struct net_device *netdev = adapter->netdev;
644 int flags, err = 0;
645
646 flags = IRQF_SHARED;
647 #ifdef CONFIG_PCI_MSI
648 adapter->have_msi = true;
649 err = pci_enable_msi(adapter->pdev);
650 if (err)
651 adapter->have_msi = false;
652
653 if (adapter->have_msi)
654 flags &= ~IRQF_SHARED;
655 #endif
656
657 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
658 netdev);
659 }
660
661 /*
662 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
663 * @adapter: board private structure
664 *
665 * Free all transmit software resources
666 */
667 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
668 {
669 struct pci_dev *pdev = adapter->pdev;
670 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
671 adapter->ring_dma);
672 }
673
674 /*
675 * atl2_open - Called when a network interface is made active
676 * @netdev: network interface device structure
677 *
678 * Returns 0 on success, negative value on failure
679 *
680 * The open entry point is called when a network interface is made
681 * active by the system (IFF_UP). At this point all resources needed
682 * for transmit and receive operations are allocated, the interrupt
683 * handler is registered with the OS, the watchdog timer is started,
684 * and the stack is notified that the interface is ready.
685 */
686 static int atl2_open(struct net_device *netdev)
687 {
688 struct atl2_adapter *adapter = netdev_priv(netdev);
689 int err;
690 u32 val;
691
692 /* disallow open during test */
693 if (test_bit(__ATL2_TESTING, &adapter->flags))
694 return -EBUSY;
695
696 /* allocate transmit descriptors */
697 err = atl2_setup_ring_resources(adapter);
698 if (err)
699 return err;
700
701 err = atl2_init_hw(&adapter->hw);
702 if (err) {
703 err = -EIO;
704 goto err_init_hw;
705 }
706
707 /* hardware has been reset, we need to reload some things */
708 atl2_set_multi(netdev);
709 init_ring_ptrs(adapter);
710
711 #ifdef NETIF_F_HW_VLAN_TX
712 atl2_restore_vlan(adapter);
713 #endif
714
715 if (atl2_configure(adapter)) {
716 err = -EIO;
717 goto err_config;
718 }
719
720 err = atl2_request_irq(adapter);
721 if (err)
722 goto err_req_irq;
723
724 clear_bit(__ATL2_DOWN, &adapter->flags);
725
726 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
727
728 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
729 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
730 val | MASTER_CTRL_MANUAL_INT);
731
732 atl2_irq_enable(adapter);
733
734 return 0;
735
736 err_init_hw:
737 err_req_irq:
738 err_config:
739 atl2_free_ring_resources(adapter);
740 atl2_reset_hw(&adapter->hw);
741
742 return err;
743 }
744
745 static void atl2_down(struct atl2_adapter *adapter)
746 {
747 struct net_device *netdev = adapter->netdev;
748
749 /* signal that we're down so the interrupt handler does not
750 * reschedule our watchdog timer */
751 set_bit(__ATL2_DOWN, &adapter->flags);
752
753 netif_tx_disable(netdev);
754
755 /* reset MAC to disable all RX/TX */
756 atl2_reset_hw(&adapter->hw);
757 msleep(1);
758
759 atl2_irq_disable(adapter);
760
761 del_timer_sync(&adapter->watchdog_timer);
762 del_timer_sync(&adapter->phy_config_timer);
763 clear_bit(0, &adapter->cfg_phy);
764
765 netif_carrier_off(netdev);
766 adapter->link_speed = SPEED_0;
767 adapter->link_duplex = -1;
768 }
769
770 static void atl2_free_irq(struct atl2_adapter *adapter)
771 {
772 struct net_device *netdev = adapter->netdev;
773
774 free_irq(adapter->pdev->irq, netdev);
775
776 #ifdef CONFIG_PCI_MSI
777 if (adapter->have_msi)
778 pci_disable_msi(adapter->pdev);
779 #endif
780 }
781
782 /*
783 * atl2_close - Disables a network interface
784 * @netdev: network interface device structure
785 *
786 * Returns 0, this is not allowed to fail
787 *
788 * The close entry point is called when an interface is de-activated
789 * by the OS. The hardware is still under the drivers control, but
790 * needs to be disabled. A global MAC reset is issued to stop the
791 * hardware, and all transmit and receive resources are freed.
792 */
793 static int atl2_close(struct net_device *netdev)
794 {
795 struct atl2_adapter *adapter = netdev_priv(netdev);
796
797 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
798
799 atl2_down(adapter);
800 atl2_free_irq(adapter);
801 atl2_free_ring_resources(adapter);
802
803 return 0;
804 }
805
806 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
807 {
808 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
809
810 return (adapter->txs_next_clear >= txs_write_ptr) ?
811 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
812 txs_write_ptr - 1) :
813 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
814 }
815
816 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
817 {
818 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
819
820 return (adapter->txd_write_ptr >= txd_read_ptr) ?
821 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
822 txd_read_ptr - 1) :
823 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
824 }
825
826 static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
827 {
828 struct atl2_adapter *adapter = netdev_priv(netdev);
829 struct tx_pkt_header *txph;
830 u32 offset, copy_len;
831 int txs_unused;
832 int txbuf_unused;
833
834 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
835 dev_kfree_skb_any(skb);
836 return NETDEV_TX_OK;
837 }
838
839 if (unlikely(skb->len <= 0)) {
840 dev_kfree_skb_any(skb);
841 return NETDEV_TX_OK;
842 }
843
844 txs_unused = TxsFreeUnit(adapter);
845 txbuf_unused = TxdFreeBytes(adapter);
846
847 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
848 txs_unused < 1) {
849 /* not enough resources */
850 netif_stop_queue(netdev);
851 return NETDEV_TX_BUSY;
852 }
853
854 offset = adapter->txd_write_ptr;
855
856 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
857
858 *(u32 *)txph = 0;
859 txph->pkt_size = skb->len;
860
861 offset += 4;
862 if (offset >= adapter->txd_ring_size)
863 offset -= adapter->txd_ring_size;
864 copy_len = adapter->txd_ring_size - offset;
865 if (copy_len >= skb->len) {
866 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
867 offset += ((u32)(skb->len + 3) & ~3);
868 } else {
869 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
870 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
871 skb->len-copy_len);
872 offset = ((u32)(skb->len-copy_len + 3) & ~3);
873 }
874 #ifdef NETIF_F_HW_VLAN_TX
875 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
876 u16 vlan_tag = vlan_tx_tag_get(skb);
877 vlan_tag = (vlan_tag << 4) |
878 (vlan_tag >> 13) |
879 ((vlan_tag >> 9) & 0x8);
880 txph->ins_vlan = 1;
881 txph->vlan = vlan_tag;
882 }
883 #endif
884 if (offset >= adapter->txd_ring_size)
885 offset -= adapter->txd_ring_size;
886 adapter->txd_write_ptr = offset;
887
888 /* clear txs before send */
889 adapter->txs_ring[adapter->txs_next_clear].update = 0;
890 if (++adapter->txs_next_clear == adapter->txs_ring_size)
891 adapter->txs_next_clear = 0;
892
893 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
894 (adapter->txd_write_ptr >> 2));
895
896 mmiowb();
897 netdev->trans_start = jiffies;
898 dev_kfree_skb_any(skb);
899 return NETDEV_TX_OK;
900 }
901
902 /*
903 * atl2_change_mtu - Change the Maximum Transfer Unit
904 * @netdev: network interface device structure
905 * @new_mtu: new value for maximum frame size
906 *
907 * Returns 0 on success, negative on failure
908 */
909 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
910 {
911 struct atl2_adapter *adapter = netdev_priv(netdev);
912 struct atl2_hw *hw = &adapter->hw;
913
914 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
915 return -EINVAL;
916
917 /* set MTU */
918 if (hw->max_frame_size != new_mtu) {
919 netdev->mtu = new_mtu;
920 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
921 VLAN_SIZE + ETHERNET_FCS_SIZE);
922 }
923
924 return 0;
925 }
926
927 /*
928 * atl2_set_mac - Change the Ethernet Address of the NIC
929 * @netdev: network interface device structure
930 * @p: pointer to an address structure
931 *
932 * Returns 0 on success, negative on failure
933 */
934 static int atl2_set_mac(struct net_device *netdev, void *p)
935 {
936 struct atl2_adapter *adapter = netdev_priv(netdev);
937 struct sockaddr *addr = p;
938
939 if (!is_valid_ether_addr(addr->sa_data))
940 return -EADDRNOTAVAIL;
941
942 if (netif_running(netdev))
943 return -EBUSY;
944
945 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
946 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
947
948 atl2_set_mac_addr(&adapter->hw);
949
950 return 0;
951 }
952
953 /*
954 * atl2_mii_ioctl -
955 * @netdev:
956 * @ifreq:
957 * @cmd:
958 */
959 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
960 {
961 struct atl2_adapter *adapter = netdev_priv(netdev);
962 struct mii_ioctl_data *data = if_mii(ifr);
963 unsigned long flags;
964
965 switch (cmd) {
966 case SIOCGMIIPHY:
967 data->phy_id = 0;
968 break;
969 case SIOCGMIIREG:
970 if (!capable(CAP_NET_ADMIN))
971 return -EPERM;
972 spin_lock_irqsave(&adapter->stats_lock, flags);
973 if (atl2_read_phy_reg(&adapter->hw,
974 data->reg_num & 0x1F, &data->val_out)) {
975 spin_unlock_irqrestore(&adapter->stats_lock, flags);
976 return -EIO;
977 }
978 spin_unlock_irqrestore(&adapter->stats_lock, flags);
979 break;
980 case SIOCSMIIREG:
981 if (!capable(CAP_NET_ADMIN))
982 return -EPERM;
983 if (data->reg_num & ~(0x1F))
984 return -EFAULT;
985 spin_lock_irqsave(&adapter->stats_lock, flags);
986 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
987 data->val_in)) {
988 spin_unlock_irqrestore(&adapter->stats_lock, flags);
989 return -EIO;
990 }
991 spin_unlock_irqrestore(&adapter->stats_lock, flags);
992 break;
993 default:
994 return -EOPNOTSUPP;
995 }
996 return 0;
997 }
998
999 /*
1000 * atl2_ioctl -
1001 * @netdev:
1002 * @ifreq:
1003 * @cmd:
1004 */
1005 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1006 {
1007 switch (cmd) {
1008 case SIOCGMIIPHY:
1009 case SIOCGMIIREG:
1010 case SIOCSMIIREG:
1011 return atl2_mii_ioctl(netdev, ifr, cmd);
1012 #ifdef ETHTOOL_OPS_COMPAT
1013 case SIOCETHTOOL:
1014 return ethtool_ioctl(ifr);
1015 #endif
1016 default:
1017 return -EOPNOTSUPP;
1018 }
1019 }
1020
1021 /*
1022 * atl2_tx_timeout - Respond to a Tx Hang
1023 * @netdev: network interface device structure
1024 */
1025 static void atl2_tx_timeout(struct net_device *netdev)
1026 {
1027 struct atl2_adapter *adapter = netdev_priv(netdev);
1028
1029 /* Do the reset outside of interrupt context */
1030 schedule_work(&adapter->reset_task);
1031 }
1032
1033 /*
1034 * atl2_watchdog - Timer Call-back
1035 * @data: pointer to netdev cast into an unsigned long
1036 */
1037 static void atl2_watchdog(unsigned long data)
1038 {
1039 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1040
1041 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1042 u32 drop_rxd, drop_rxs;
1043 unsigned long flags;
1044
1045 spin_lock_irqsave(&adapter->stats_lock, flags);
1046 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1047 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1048 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1049
1050 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1051
1052 /* Reset the timer */
1053 mod_timer(&adapter->watchdog_timer,
1054 round_jiffies(jiffies + 4 * HZ));
1055 }
1056 }
1057
1058 /*
1059 * atl2_phy_config - Timer Call-back
1060 * @data: pointer to netdev cast into an unsigned long
1061 */
1062 static void atl2_phy_config(unsigned long data)
1063 {
1064 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1065 struct atl2_hw *hw = &adapter->hw;
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&adapter->stats_lock, flags);
1069 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1070 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1071 MII_CR_RESTART_AUTO_NEG);
1072 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1073 clear_bit(0, &adapter->cfg_phy);
1074 }
1075
1076 static int atl2_up(struct atl2_adapter *adapter)
1077 {
1078 struct net_device *netdev = adapter->netdev;
1079 int err = 0;
1080 u32 val;
1081
1082 /* hardware has been reset, we need to reload some things */
1083
1084 err = atl2_init_hw(&adapter->hw);
1085 if (err) {
1086 err = -EIO;
1087 return err;
1088 }
1089
1090 atl2_set_multi(netdev);
1091 init_ring_ptrs(adapter);
1092
1093 #ifdef NETIF_F_HW_VLAN_TX
1094 atl2_restore_vlan(adapter);
1095 #endif
1096
1097 if (atl2_configure(adapter)) {
1098 err = -EIO;
1099 goto err_up;
1100 }
1101
1102 clear_bit(__ATL2_DOWN, &adapter->flags);
1103
1104 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1105 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1106 MASTER_CTRL_MANUAL_INT);
1107
1108 atl2_irq_enable(adapter);
1109
1110 err_up:
1111 return err;
1112 }
1113
1114 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1115 {
1116 WARN_ON(in_interrupt());
1117 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1118 msleep(1);
1119 atl2_down(adapter);
1120 atl2_up(adapter);
1121 clear_bit(__ATL2_RESETTING, &adapter->flags);
1122 }
1123
1124 static void atl2_reset_task(struct work_struct *work)
1125 {
1126 struct atl2_adapter *adapter;
1127 adapter = container_of(work, struct atl2_adapter, reset_task);
1128
1129 atl2_reinit_locked(adapter);
1130 }
1131
1132 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1133 {
1134 u32 value;
1135 struct atl2_hw *hw = &adapter->hw;
1136 struct net_device *netdev = adapter->netdev;
1137
1138 /* Config MAC CTRL Register */
1139 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1140
1141 /* duplex */
1142 if (FULL_DUPLEX == adapter->link_duplex)
1143 value |= MAC_CTRL_DUPLX;
1144
1145 /* flow control */
1146 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1147
1148 /* PAD & CRC */
1149 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1150
1151 /* preamble length */
1152 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1153 MAC_CTRL_PRMLEN_SHIFT);
1154
1155 /* vlan */
1156 if (adapter->vlgrp)
1157 value |= MAC_CTRL_RMV_VLAN;
1158
1159 /* filter mode */
1160 value |= MAC_CTRL_BC_EN;
1161 if (netdev->flags & IFF_PROMISC)
1162 value |= MAC_CTRL_PROMIS_EN;
1163 else if (netdev->flags & IFF_ALLMULTI)
1164 value |= MAC_CTRL_MC_ALL_EN;
1165
1166 /* half retry buffer */
1167 value |= (((u32)(adapter->hw.retry_buf &
1168 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1169
1170 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1171 }
1172
1173 static int atl2_check_link(struct atl2_adapter *adapter)
1174 {
1175 struct atl2_hw *hw = &adapter->hw;
1176 struct net_device *netdev = adapter->netdev;
1177 int ret_val;
1178 u16 speed, duplex, phy_data;
1179 int reconfig = 0;
1180
1181 /* MII_BMSR must read twise */
1182 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1183 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1184 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1185 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1186 u32 value;
1187 /* disable rx */
1188 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1189 value &= ~MAC_CTRL_RX_EN;
1190 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1191 adapter->link_speed = SPEED_0;
1192 netif_carrier_off(netdev);
1193 netif_stop_queue(netdev);
1194 }
1195 return 0;
1196 }
1197
1198 /* Link Up */
1199 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1200 if (ret_val)
1201 return ret_val;
1202 switch (hw->MediaType) {
1203 case MEDIA_TYPE_100M_FULL:
1204 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1205 reconfig = 1;
1206 break;
1207 case MEDIA_TYPE_100M_HALF:
1208 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1209 reconfig = 1;
1210 break;
1211 case MEDIA_TYPE_10M_FULL:
1212 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1213 reconfig = 1;
1214 break;
1215 case MEDIA_TYPE_10M_HALF:
1216 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1217 reconfig = 1;
1218 break;
1219 }
1220 /* link result is our setting */
1221 if (reconfig == 0) {
1222 if (adapter->link_speed != speed ||
1223 adapter->link_duplex != duplex) {
1224 adapter->link_speed = speed;
1225 adapter->link_duplex = duplex;
1226 atl2_setup_mac_ctrl(adapter);
1227 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1228 atl2_driver_name, netdev->name,
1229 adapter->link_speed,
1230 adapter->link_duplex == FULL_DUPLEX ?
1231 "Full Duplex" : "Half Duplex");
1232 }
1233
1234 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1235 netif_carrier_on(netdev);
1236 netif_wake_queue(netdev);
1237 }
1238 return 0;
1239 }
1240
1241 /* change original link status */
1242 if (netif_carrier_ok(netdev)) {
1243 u32 value;
1244 /* disable rx */
1245 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1246 value &= ~MAC_CTRL_RX_EN;
1247 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1248
1249 adapter->link_speed = SPEED_0;
1250 netif_carrier_off(netdev);
1251 netif_stop_queue(netdev);
1252 }
1253
1254 /* auto-neg, insert timer to re-config phy
1255 * (if interval smaller than 5 seconds, something strange) */
1256 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1257 if (!test_and_set_bit(0, &adapter->cfg_phy))
1258 mod_timer(&adapter->phy_config_timer,
1259 round_jiffies(jiffies + 5 * HZ));
1260 }
1261
1262 return 0;
1263 }
1264
1265 /*
1266 * atl2_link_chg_task - deal with link change event Out of interrupt context
1267 * @netdev: network interface device structure
1268 */
1269 static void atl2_link_chg_task(struct work_struct *work)
1270 {
1271 struct atl2_adapter *adapter;
1272 unsigned long flags;
1273
1274 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1275
1276 spin_lock_irqsave(&adapter->stats_lock, flags);
1277 atl2_check_link(adapter);
1278 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1279 }
1280
1281 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1282 {
1283 u16 cmd;
1284
1285 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1286
1287 if (cmd & PCI_COMMAND_INTX_DISABLE)
1288 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1289 if (cmd & PCI_COMMAND_IO)
1290 cmd &= ~PCI_COMMAND_IO;
1291 if (0 == (cmd & PCI_COMMAND_MEMORY))
1292 cmd |= PCI_COMMAND_MEMORY;
1293 if (0 == (cmd & PCI_COMMAND_MASTER))
1294 cmd |= PCI_COMMAND_MASTER;
1295 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1296
1297 /*
1298 * some motherboards BIOS(PXE/EFI) driver may set PME
1299 * while they transfer control to OS (Windows/Linux)
1300 * so we should clear this bit before NIC work normally
1301 */
1302 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1303 }
1304
1305 #ifdef CONFIG_NET_POLL_CONTROLLER
1306 static void atl2_poll_controller(struct net_device *netdev)
1307 {
1308 disable_irq(netdev->irq);
1309 atl2_intr(netdev->irq, netdev);
1310 enable_irq(netdev->irq);
1311 }
1312 #endif
1313
1314 /*
1315 * atl2_probe - Device Initialization Routine
1316 * @pdev: PCI device information struct
1317 * @ent: entry in atl2_pci_tbl
1318 *
1319 * Returns 0 on success, negative on failure
1320 *
1321 * atl2_probe initializes an adapter identified by a pci_dev structure.
1322 * The OS initialization, configuring of the adapter private structure,
1323 * and a hardware reset occur.
1324 */
1325 static int __devinit atl2_probe(struct pci_dev *pdev,
1326 const struct pci_device_id *ent)
1327 {
1328 struct net_device *netdev;
1329 struct atl2_adapter *adapter;
1330 static int cards_found;
1331 unsigned long mmio_start;
1332 int mmio_len;
1333 int err;
1334
1335 cards_found = 0;
1336
1337 err = pci_enable_device(pdev);
1338 if (err)
1339 return err;
1340
1341 /*
1342 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1343 * until the kernel has the proper infrastructure to support 64-bit DMA
1344 * on these devices.
1345 */
1346 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1347 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1348 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1349 goto err_dma;
1350 }
1351
1352 /* Mark all PCI regions associated with PCI device
1353 * pdev as being reserved by owner atl2_driver_name */
1354 err = pci_request_regions(pdev, atl2_driver_name);
1355 if (err)
1356 goto err_pci_reg;
1357
1358 /* Enables bus-mastering on the device and calls
1359 * pcibios_set_master to do the needed arch specific settings */
1360 pci_set_master(pdev);
1361
1362 err = -ENOMEM;
1363 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1364 if (!netdev)
1365 goto err_alloc_etherdev;
1366
1367 SET_NETDEV_DEV(netdev, &pdev->dev);
1368
1369 pci_set_drvdata(pdev, netdev);
1370 adapter = netdev_priv(netdev);
1371 adapter->netdev = netdev;
1372 adapter->pdev = pdev;
1373 adapter->hw.back = adapter;
1374
1375 mmio_start = pci_resource_start(pdev, 0x0);
1376 mmio_len = pci_resource_len(pdev, 0x0);
1377
1378 adapter->hw.mem_rang = (u32)mmio_len;
1379 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1380 if (!adapter->hw.hw_addr) {
1381 err = -EIO;
1382 goto err_ioremap;
1383 }
1384
1385 atl2_setup_pcicmd(pdev);
1386
1387 netdev->open = &atl2_open;
1388 netdev->stop = &atl2_close;
1389 netdev->hard_start_xmit = &atl2_xmit_frame;
1390 netdev->set_multicast_list = &atl2_set_multi;
1391 netdev->set_mac_address = &atl2_set_mac;
1392 netdev->change_mtu = &atl2_change_mtu;
1393 netdev->do_ioctl = &atl2_ioctl;
1394 atl2_set_ethtool_ops(netdev);
1395
1396 #ifdef CONFIG_NET_POLL_CONTROLLER
1397 netdev->poll_controller = atl2_poll_controller;
1398 #endif
1399 #ifdef HAVE_TX_TIMEOUT
1400 netdev->tx_timeout = &atl2_tx_timeout;
1401 netdev->watchdog_timeo = 5 * HZ;
1402 #endif
1403 #ifdef NETIF_F_HW_VLAN_TX
1404 netdev->vlan_rx_register = atl2_vlan_rx_register;
1405 #endif
1406 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1407
1408 netdev->mem_start = mmio_start;
1409 netdev->mem_end = mmio_start + mmio_len;
1410 adapter->bd_number = cards_found;
1411 adapter->pci_using_64 = false;
1412
1413 /* setup the private structure */
1414 err = atl2_sw_init(adapter);
1415 if (err)
1416 goto err_sw_init;
1417
1418 err = -EIO;
1419
1420 #ifdef NETIF_F_HW_VLAN_TX
1421 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1422 #endif
1423
1424 /* Init PHY as early as possible due to power saving issue */
1425 atl2_phy_init(&adapter->hw);
1426
1427 /* reset the controller to
1428 * put the device in a known good starting state */
1429
1430 if (atl2_reset_hw(&adapter->hw)) {
1431 err = -EIO;
1432 goto err_reset;
1433 }
1434
1435 /* copy the MAC address out of the EEPROM */
1436 atl2_read_mac_addr(&adapter->hw);
1437 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1438 /* FIXME: do we still need this? */
1439 #ifdef ETHTOOL_GPERMADDR
1440 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1441
1442 if (!is_valid_ether_addr(netdev->perm_addr)) {
1443 #else
1444 if (!is_valid_ether_addr(netdev->dev_addr)) {
1445 #endif
1446 err = -EIO;
1447 goto err_eeprom;
1448 }
1449
1450 atl2_check_options(adapter);
1451
1452 init_timer(&adapter->watchdog_timer);
1453 adapter->watchdog_timer.function = &atl2_watchdog;
1454 adapter->watchdog_timer.data = (unsigned long) adapter;
1455
1456 init_timer(&adapter->phy_config_timer);
1457 adapter->phy_config_timer.function = &atl2_phy_config;
1458 adapter->phy_config_timer.data = (unsigned long) adapter;
1459
1460 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1461 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1462
1463 strcpy(netdev->name, "eth%d"); /* ?? */
1464 err = register_netdev(netdev);
1465 if (err)
1466 goto err_register;
1467
1468 /* assume we have no link for now */
1469 netif_carrier_off(netdev);
1470 netif_stop_queue(netdev);
1471
1472 cards_found++;
1473
1474 return 0;
1475
1476 err_reset:
1477 err_register:
1478 err_sw_init:
1479 err_eeprom:
1480 iounmap(adapter->hw.hw_addr);
1481 err_ioremap:
1482 free_netdev(netdev);
1483 err_alloc_etherdev:
1484 pci_release_regions(pdev);
1485 err_pci_reg:
1486 err_dma:
1487 pci_disable_device(pdev);
1488 return err;
1489 }
1490
1491 /*
1492 * atl2_remove - Device Removal Routine
1493 * @pdev: PCI device information struct
1494 *
1495 * atl2_remove is called by the PCI subsystem to alert the driver
1496 * that it should release a PCI device. The could be caused by a
1497 * Hot-Plug event, or because the driver is going to be removed from
1498 * memory.
1499 */
1500 /* FIXME: write the original MAC address back in case it was changed from a
1501 * BIOS-set value, as in atl1 -- CHS */
1502 static void __devexit atl2_remove(struct pci_dev *pdev)
1503 {
1504 struct net_device *netdev = pci_get_drvdata(pdev);
1505 struct atl2_adapter *adapter = netdev_priv(netdev);
1506
1507 /* flush_scheduled work may reschedule our watchdog task, so
1508 * explicitly disable watchdog tasks from being rescheduled */
1509 set_bit(__ATL2_DOWN, &adapter->flags);
1510
1511 del_timer_sync(&adapter->watchdog_timer);
1512 del_timer_sync(&adapter->phy_config_timer);
1513
1514 flush_scheduled_work();
1515
1516 unregister_netdev(netdev);
1517
1518 atl2_force_ps(&adapter->hw);
1519
1520 iounmap(adapter->hw.hw_addr);
1521 pci_release_regions(pdev);
1522
1523 free_netdev(netdev);
1524
1525 pci_disable_device(pdev);
1526 }
1527
1528 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1529 {
1530 struct net_device *netdev = pci_get_drvdata(pdev);
1531 struct atl2_adapter *adapter = netdev_priv(netdev);
1532 struct atl2_hw *hw = &adapter->hw;
1533 u16 speed, duplex;
1534 u32 ctrl = 0;
1535 u32 wufc = adapter->wol;
1536
1537 #ifdef CONFIG_PM
1538 int retval = 0;
1539 #endif
1540
1541 netif_device_detach(netdev);
1542
1543 if (netif_running(netdev)) {
1544 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1545 atl2_down(adapter);
1546 }
1547
1548 #ifdef CONFIG_PM
1549 retval = pci_save_state(pdev);
1550 if (retval)
1551 return retval;
1552 #endif
1553
1554 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1555 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1556 if (ctrl & BMSR_LSTATUS)
1557 wufc &= ~ATLX_WUFC_LNKC;
1558
1559 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1560 u32 ret_val;
1561 /* get current link speed & duplex */
1562 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1563 if (ret_val) {
1564 printk(KERN_DEBUG
1565 "%s: get speed&duplex error while suspend\n",
1566 atl2_driver_name);
1567 goto wol_dis;
1568 }
1569
1570 ctrl = 0;
1571
1572 /* turn on magic packet wol */
1573 if (wufc & ATLX_WUFC_MAG)
1574 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1575
1576 /* ignore Link Chg event when Link is up */
1577 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1578
1579 /* Config MAC CTRL Register */
1580 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1581 if (FULL_DUPLEX == adapter->link_duplex)
1582 ctrl |= MAC_CTRL_DUPLX;
1583 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1584 ctrl |= (((u32)adapter->hw.preamble_len &
1585 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1586 ctrl |= (((u32)(adapter->hw.retry_buf &
1587 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1588 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1589 if (wufc & ATLX_WUFC_MAG) {
1590 /* magic packet maybe Broadcast&multicast&Unicast */
1591 ctrl |= MAC_CTRL_BC_EN;
1592 }
1593
1594 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1595
1596 /* pcie patch */
1597 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1598 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1599 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1600 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1601 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1602 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1603
1604 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1605 goto suspend_exit;
1606 }
1607
1608 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1609 /* link is down, so only LINK CHG WOL event enable */
1610 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1611 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1612 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1613
1614 /* pcie patch */
1615 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1616 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1617 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1618 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1619 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1620 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1621
1622 hw->phy_configured = false; /* re-init PHY when resume */
1623
1624 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1625
1626 goto suspend_exit;
1627 }
1628
1629 wol_dis:
1630 /* WOL disabled */
1631 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1632
1633 /* pcie patch */
1634 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1635 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1636 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1637 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1638 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1639 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1640
1641 atl2_force_ps(hw);
1642 hw->phy_configured = false; /* re-init PHY when resume */
1643
1644 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1645
1646 suspend_exit:
1647 if (netif_running(netdev))
1648 atl2_free_irq(adapter);
1649
1650 pci_disable_device(pdev);
1651
1652 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1653
1654 return 0;
1655 }
1656
1657 #ifdef CONFIG_PM
1658 static int atl2_resume(struct pci_dev *pdev)
1659 {
1660 struct net_device *netdev = pci_get_drvdata(pdev);
1661 struct atl2_adapter *adapter = netdev_priv(netdev);
1662 u32 err;
1663
1664 pci_set_power_state(pdev, PCI_D0);
1665 pci_restore_state(pdev);
1666
1667 err = pci_enable_device(pdev);
1668 if (err) {
1669 printk(KERN_ERR
1670 "atl2: Cannot enable PCI device from suspend\n");
1671 return err;
1672 }
1673
1674 pci_set_master(pdev);
1675
1676 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1677
1678 pci_enable_wake(pdev, PCI_D3hot, 0);
1679 pci_enable_wake(pdev, PCI_D3cold, 0);
1680
1681 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1682
1683 err = atl2_request_irq(adapter);
1684 if (netif_running(netdev) && err)
1685 return err;
1686
1687 atl2_reset_hw(&adapter->hw);
1688
1689 if (netif_running(netdev))
1690 atl2_up(adapter);
1691
1692 netif_device_attach(netdev);
1693
1694 return 0;
1695 }
1696 #endif
1697
1698 static void atl2_shutdown(struct pci_dev *pdev)
1699 {
1700 atl2_suspend(pdev, PMSG_SUSPEND);
1701 }
1702
1703 static struct pci_driver atl2_driver = {
1704 .name = atl2_driver_name,
1705 .id_table = atl2_pci_tbl,
1706 .probe = atl2_probe,
1707 .remove = __devexit_p(atl2_remove),
1708 /* Power Managment Hooks */
1709 .suspend = atl2_suspend,
1710 #ifdef CONFIG_PM
1711 .resume = atl2_resume,
1712 #endif
1713 .shutdown = atl2_shutdown,
1714 };
1715
1716 /*
1717 * atl2_init_module - Driver Registration Routine
1718 *
1719 * atl2_init_module is the first routine called when the driver is
1720 * loaded. All it does is register with the PCI subsystem.
1721 */
1722 static int __init atl2_init_module(void)
1723 {
1724 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1725 atl2_driver_version);
1726 printk(KERN_INFO "%s\n", atl2_copyright);
1727 return pci_register_driver(&atl2_driver);
1728 }
1729 module_init(atl2_init_module);
1730
1731 /*
1732 * atl2_exit_module - Driver Exit Cleanup Routine
1733 *
1734 * atl2_exit_module is called just before the driver is removed
1735 * from memory.
1736 */
1737 static void __exit atl2_exit_module(void)
1738 {
1739 pci_unregister_driver(&atl2_driver);
1740 }
1741 module_exit(atl2_exit_module);
1742
1743 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1744 {
1745 struct atl2_adapter *adapter = hw->back;
1746 pci_read_config_word(adapter->pdev, reg, value);
1747 }
1748
1749 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1750 {
1751 struct atl2_adapter *adapter = hw->back;
1752 pci_write_config_word(adapter->pdev, reg, *value);
1753 }
1754
1755 static int atl2_get_settings(struct net_device *netdev,
1756 struct ethtool_cmd *ecmd)
1757 {
1758 struct atl2_adapter *adapter = netdev_priv(netdev);
1759 struct atl2_hw *hw = &adapter->hw;
1760
1761 ecmd->supported = (SUPPORTED_10baseT_Half |
1762 SUPPORTED_10baseT_Full |
1763 SUPPORTED_100baseT_Half |
1764 SUPPORTED_100baseT_Full |
1765 SUPPORTED_Autoneg |
1766 SUPPORTED_TP);
1767 ecmd->advertising = ADVERTISED_TP;
1768
1769 ecmd->advertising |= ADVERTISED_Autoneg;
1770 ecmd->advertising |= hw->autoneg_advertised;
1771
1772 ecmd->port = PORT_TP;
1773 ecmd->phy_address = 0;
1774 ecmd->transceiver = XCVR_INTERNAL;
1775
1776 if (adapter->link_speed != SPEED_0) {
1777 ecmd->speed = adapter->link_speed;
1778 if (adapter->link_duplex == FULL_DUPLEX)
1779 ecmd->duplex = DUPLEX_FULL;
1780 else
1781 ecmd->duplex = DUPLEX_HALF;
1782 } else {
1783 ecmd->speed = -1;
1784 ecmd->duplex = -1;
1785 }
1786
1787 ecmd->autoneg = AUTONEG_ENABLE;
1788 return 0;
1789 }
1790
1791 static int atl2_set_settings(struct net_device *netdev,
1792 struct ethtool_cmd *ecmd)
1793 {
1794 struct atl2_adapter *adapter = netdev_priv(netdev);
1795 struct atl2_hw *hw = &adapter->hw;
1796
1797 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1798 msleep(1);
1799
1800 if (ecmd->autoneg == AUTONEG_ENABLE) {
1801 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1802 ADVERTISE_10_FULL | \
1803 ADVERTISE_100_HALF| \
1804 ADVERTISE_100_FULL)
1805
1806 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1807 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1808 hw->autoneg_advertised = MY_ADV_MASK;
1809 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1810 ADVERTISE_100_FULL) {
1811 hw->MediaType = MEDIA_TYPE_100M_FULL;
1812 hw->autoneg_advertised = ADVERTISE_100_FULL;
1813 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1814 ADVERTISE_100_HALF) {
1815 hw->MediaType = MEDIA_TYPE_100M_HALF;
1816 hw->autoneg_advertised = ADVERTISE_100_HALF;
1817 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1818 ADVERTISE_10_FULL) {
1819 hw->MediaType = MEDIA_TYPE_10M_FULL;
1820 hw->autoneg_advertised = ADVERTISE_10_FULL;
1821 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1822 ADVERTISE_10_HALF) {
1823 hw->MediaType = MEDIA_TYPE_10M_HALF;
1824 hw->autoneg_advertised = ADVERTISE_10_HALF;
1825 } else {
1826 clear_bit(__ATL2_RESETTING, &adapter->flags);
1827 return -EINVAL;
1828 }
1829 ecmd->advertising = hw->autoneg_advertised |
1830 ADVERTISED_TP | ADVERTISED_Autoneg;
1831 } else {
1832 clear_bit(__ATL2_RESETTING, &adapter->flags);
1833 return -EINVAL;
1834 }
1835
1836 /* reset the link */
1837 if (netif_running(adapter->netdev)) {
1838 atl2_down(adapter);
1839 atl2_up(adapter);
1840 } else
1841 atl2_reset_hw(&adapter->hw);
1842
1843 clear_bit(__ATL2_RESETTING, &adapter->flags);
1844 return 0;
1845 }
1846
1847 static u32 atl2_get_tx_csum(struct net_device *netdev)
1848 {
1849 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1850 }
1851
1852 static u32 atl2_get_msglevel(struct net_device *netdev)
1853 {
1854 return 0;
1855 }
1856
1857 /*
1858 * It's sane for this to be empty, but we might want to take advantage of this.
1859 */
1860 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1861 {
1862 }
1863
1864 static int atl2_get_regs_len(struct net_device *netdev)
1865 {
1866 #define ATL2_REGS_LEN 42
1867 return sizeof(u32) * ATL2_REGS_LEN;
1868 }
1869
1870 static void atl2_get_regs(struct net_device *netdev,
1871 struct ethtool_regs *regs, void *p)
1872 {
1873 struct atl2_adapter *adapter = netdev_priv(netdev);
1874 struct atl2_hw *hw = &adapter->hw;
1875 u32 *regs_buff = p;
1876 u16 phy_data;
1877
1878 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1879
1880 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1881
1882 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1883 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1884 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1885 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1886 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1887 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1888 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1889 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1890 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1891 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1892 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1893 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1894 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1895 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1896 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1897 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1898 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1899 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1900 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1901 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1902 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1903 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1904 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1905 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1906 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1907 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1908 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1909 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1910 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1911 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1912 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1913 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1914 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1915 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1916 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1917 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1918 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1919 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1920 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1921
1922 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1923 regs_buff[40] = (u32)phy_data;
1924 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1925 regs_buff[41] = (u32)phy_data;
1926 }
1927
1928 static int atl2_get_eeprom_len(struct net_device *netdev)
1929 {
1930 struct atl2_adapter *adapter = netdev_priv(netdev);
1931
1932 if (!atl2_check_eeprom_exist(&adapter->hw))
1933 return 512;
1934 else
1935 return 0;
1936 }
1937
1938 static int atl2_get_eeprom(struct net_device *netdev,
1939 struct ethtool_eeprom *eeprom, u8 *bytes)
1940 {
1941 struct atl2_adapter *adapter = netdev_priv(netdev);
1942 struct atl2_hw *hw = &adapter->hw;
1943 u32 *eeprom_buff;
1944 int first_dword, last_dword;
1945 int ret_val = 0;
1946 int i;
1947
1948 if (eeprom->len == 0)
1949 return -EINVAL;
1950
1951 if (atl2_check_eeprom_exist(hw))
1952 return -EINVAL;
1953
1954 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1955
1956 first_dword = eeprom->offset >> 2;
1957 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1958
1959 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1960 GFP_KERNEL);
1961 if (!eeprom_buff)
1962 return -ENOMEM;
1963
1964 for (i = first_dword; i < last_dword; i++) {
1965 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1966 return -EIO;
1967 }
1968
1969 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1970 eeprom->len);
1971 kfree(eeprom_buff);
1972
1973 return ret_val;
1974 }
1975
1976 static int atl2_set_eeprom(struct net_device *netdev,
1977 struct ethtool_eeprom *eeprom, u8 *bytes)
1978 {
1979 struct atl2_adapter *adapter = netdev_priv(netdev);
1980 struct atl2_hw *hw = &adapter->hw;
1981 u32 *eeprom_buff;
1982 u32 *ptr;
1983 int max_len, first_dword, last_dword, ret_val = 0;
1984 int i;
1985
1986 if (eeprom->len == 0)
1987 return -EOPNOTSUPP;
1988
1989 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1990 return -EFAULT;
1991
1992 max_len = 512;
1993
1994 first_dword = eeprom->offset >> 2;
1995 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1996 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1997 if (!eeprom_buff)
1998 return -ENOMEM;
1999
2000 ptr = (u32 *)eeprom_buff;
2001
2002 if (eeprom->offset & 3) {
2003 /* need read/modify/write of first changed EEPROM word */
2004 /* only the second byte of the word is being modified */
2005 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2006 return -EIO;
2007 ptr++;
2008 }
2009 if (((eeprom->offset + eeprom->len) & 3)) {
2010 /*
2011 * need read/modify/write of last changed EEPROM word
2012 * only the first byte of the word is being modified
2013 */
2014 if (!atl2_read_eeprom(hw, last_dword * 4,
2015 &(eeprom_buff[last_dword - first_dword])))
2016 return -EIO;
2017 }
2018
2019 /* Device's eeprom is always little-endian, word addressable */
2020 memcpy(ptr, bytes, eeprom->len);
2021
2022 for (i = 0; i < last_dword - first_dword + 1; i++) {
2023 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2024 return -EIO;
2025 }
2026
2027 kfree(eeprom_buff);
2028 return ret_val;
2029 }
2030
2031 static void atl2_get_drvinfo(struct net_device *netdev,
2032 struct ethtool_drvinfo *drvinfo)
2033 {
2034 struct atl2_adapter *adapter = netdev_priv(netdev);
2035
2036 strncpy(drvinfo->driver, atl2_driver_name, 32);
2037 strncpy(drvinfo->version, atl2_driver_version, 32);
2038 strncpy(drvinfo->fw_version, "L2", 32);
2039 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2040 drvinfo->n_stats = 0;
2041 drvinfo->testinfo_len = 0;
2042 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2043 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2044 }
2045
2046 static void atl2_get_wol(struct net_device *netdev,
2047 struct ethtool_wolinfo *wol)
2048 {
2049 struct atl2_adapter *adapter = netdev_priv(netdev);
2050
2051 wol->supported = WAKE_MAGIC;
2052 wol->wolopts = 0;
2053
2054 if (adapter->wol & ATLX_WUFC_EX)
2055 wol->wolopts |= WAKE_UCAST;
2056 if (adapter->wol & ATLX_WUFC_MC)
2057 wol->wolopts |= WAKE_MCAST;
2058 if (adapter->wol & ATLX_WUFC_BC)
2059 wol->wolopts |= WAKE_BCAST;
2060 if (adapter->wol & ATLX_WUFC_MAG)
2061 wol->wolopts |= WAKE_MAGIC;
2062 if (adapter->wol & ATLX_WUFC_LNKC)
2063 wol->wolopts |= WAKE_PHY;
2064 }
2065
2066 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2067 {
2068 struct atl2_adapter *adapter = netdev_priv(netdev);
2069
2070 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2071 return -EOPNOTSUPP;
2072
2073 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2074 return -EOPNOTSUPP;
2075
2076 /* these settings will always override what we currently have */
2077 adapter->wol = 0;
2078
2079 if (wol->wolopts & WAKE_MAGIC)
2080 adapter->wol |= ATLX_WUFC_MAG;
2081 if (wol->wolopts & WAKE_PHY)
2082 adapter->wol |= ATLX_WUFC_LNKC;
2083
2084 return 0;
2085 }
2086
2087 static int atl2_nway_reset(struct net_device *netdev)
2088 {
2089 struct atl2_adapter *adapter = netdev_priv(netdev);
2090 if (netif_running(netdev))
2091 atl2_reinit_locked(adapter);
2092 return 0;
2093 }
2094
2095 static struct ethtool_ops atl2_ethtool_ops = {
2096 .get_settings = atl2_get_settings,
2097 .set_settings = atl2_set_settings,
2098 .get_drvinfo = atl2_get_drvinfo,
2099 .get_regs_len = atl2_get_regs_len,
2100 .get_regs = atl2_get_regs,
2101 .get_wol = atl2_get_wol,
2102 .set_wol = atl2_set_wol,
2103 .get_msglevel = atl2_get_msglevel,
2104 .set_msglevel = atl2_set_msglevel,
2105 .nway_reset = atl2_nway_reset,
2106 .get_link = ethtool_op_get_link,
2107 .get_eeprom_len = atl2_get_eeprom_len,
2108 .get_eeprom = atl2_get_eeprom,
2109 .set_eeprom = atl2_set_eeprom,
2110 .get_tx_csum = atl2_get_tx_csum,
2111 .get_sg = ethtool_op_get_sg,
2112 .set_sg = ethtool_op_set_sg,
2113 #ifdef NETIF_F_TSO
2114 .get_tso = ethtool_op_get_tso,
2115 #endif
2116 };
2117
2118 static void atl2_set_ethtool_ops(struct net_device *netdev)
2119 {
2120 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2121 }
2122
2123 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2124 (((a) & 0xff00ff00) >> 8))
2125 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2126 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2127
2128 /*
2129 * Reset the transmit and receive units; mask and clear all interrupts.
2130 *
2131 * hw - Struct containing variables accessed by shared code
2132 * return : 0 or idle status (if error)
2133 */
2134 static s32 atl2_reset_hw(struct atl2_hw *hw)
2135 {
2136 u32 icr;
2137 u16 pci_cfg_cmd_word;
2138 int i;
2139
2140 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2141 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2142 if ((pci_cfg_cmd_word &
2143 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2144 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2145 pci_cfg_cmd_word |=
2146 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2147 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2148 }
2149
2150 /* Clear Interrupt mask to stop board from generating
2151 * interrupts & Clear any pending interrupt events
2152 */
2153 /* FIXME */
2154 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2155 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2156
2157 /* Issue Soft Reset to the MAC. This will reset the chip's
2158 * transmit, receive, DMA. It will not effect
2159 * the current PCI configuration. The global reset bit is self-
2160 * clearing, and should clear within a microsecond.
2161 */
2162 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2163 wmb();
2164 msleep(1); /* delay about 1ms */
2165
2166 /* Wait at least 10ms for All module to be Idle */
2167 for (i = 0; i < 10; i++) {
2168 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2169 if (!icr)
2170 break;
2171 msleep(1); /* delay 1 ms */
2172 cpu_relax();
2173 }
2174
2175 if (icr)
2176 return icr;
2177
2178 return 0;
2179 }
2180
2181 #define CUSTOM_SPI_CS_SETUP 2
2182 #define CUSTOM_SPI_CLK_HI 2
2183 #define CUSTOM_SPI_CLK_LO 2
2184 #define CUSTOM_SPI_CS_HOLD 2
2185 #define CUSTOM_SPI_CS_HI 3
2186
2187 static struct atl2_spi_flash_dev flash_table[] =
2188 {
2189 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2190 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2191 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2192 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2193 };
2194
2195 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2196 {
2197 int i;
2198 u32 value;
2199
2200 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2201 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2202
2203 value = SPI_FLASH_CTRL_WAIT_READY |
2204 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2205 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2206 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2207 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2208 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2209 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2210 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2211 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2212 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2213 SPI_FLASH_CTRL_CS_HI_SHIFT |
2214 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2215
2216 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2217
2218 value |= SPI_FLASH_CTRL_START;
2219
2220 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2221
2222 for (i = 0; i < 10; i++) {
2223 msleep(1);
2224 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2225 if (!(value & SPI_FLASH_CTRL_START))
2226 break;
2227 }
2228
2229 if (value & SPI_FLASH_CTRL_START)
2230 return false;
2231
2232 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2233
2234 return true;
2235 }
2236
2237 /*
2238 * get_permanent_address
2239 * return 0 if get valid mac address,
2240 */
2241 static int get_permanent_address(struct atl2_hw *hw)
2242 {
2243 u32 Addr[2];
2244 u32 i, Control;
2245 u16 Register;
2246 u8 EthAddr[NODE_ADDRESS_SIZE];
2247 bool KeyValid;
2248
2249 if (is_valid_ether_addr(hw->perm_mac_addr))
2250 return 0;
2251
2252 Addr[0] = 0;
2253 Addr[1] = 0;
2254
2255 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2256 Register = 0;
2257 KeyValid = false;
2258
2259 /* Read out all EEPROM content */
2260 i = 0;
2261 while (1) {
2262 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2263 if (KeyValid) {
2264 if (Register == REG_MAC_STA_ADDR)
2265 Addr[0] = Control;
2266 else if (Register ==
2267 (REG_MAC_STA_ADDR + 4))
2268 Addr[1] = Control;
2269 KeyValid = false;
2270 } else if ((Control & 0xff) == 0x5A) {
2271 KeyValid = true;
2272 Register = (u16) (Control >> 16);
2273 } else {
2274 /* assume data end while encount an invalid KEYWORD */
2275 break;
2276 }
2277 } else {
2278 break; /* read error */
2279 }
2280 i += 4;
2281 }
2282
2283 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2284 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2285
2286 if (is_valid_ether_addr(EthAddr)) {
2287 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2288 return 0;
2289 }
2290 return 1;
2291 }
2292
2293 /* see if SPI flash exists? */
2294 Addr[0] = 0;
2295 Addr[1] = 0;
2296 Register = 0;
2297 KeyValid = false;
2298 i = 0;
2299 while (1) {
2300 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2301 if (KeyValid) {
2302 if (Register == REG_MAC_STA_ADDR)
2303 Addr[0] = Control;
2304 else if (Register == (REG_MAC_STA_ADDR + 4))
2305 Addr[1] = Control;
2306 KeyValid = false;
2307 } else if ((Control & 0xff) == 0x5A) {
2308 KeyValid = true;
2309 Register = (u16) (Control >> 16);
2310 } else {
2311 break; /* data end */
2312 }
2313 } else {
2314 break; /* read error */
2315 }
2316 i += 4;
2317 }
2318
2319 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2320 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2321 if (is_valid_ether_addr(EthAddr)) {
2322 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2323 return 0;
2324 }
2325 /* maybe MAC-address is from BIOS */
2326 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2327 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2328 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2329 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2330
2331 if (is_valid_ether_addr(EthAddr)) {
2332 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2333 return 0;
2334 }
2335
2336 return 1;
2337 }
2338
2339 /*
2340 * Reads the adapter's MAC address from the EEPROM
2341 *
2342 * hw - Struct containing variables accessed by shared code
2343 */
2344 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2345 {
2346 u16 i;
2347
2348 if (get_permanent_address(hw)) {
2349 /* for test */
2350 /* FIXME: shouldn't we use random_ether_addr() here? */
2351 hw->perm_mac_addr[0] = 0x00;
2352 hw->perm_mac_addr[1] = 0x13;
2353 hw->perm_mac_addr[2] = 0x74;
2354 hw->perm_mac_addr[3] = 0x00;
2355 hw->perm_mac_addr[4] = 0x5c;
2356 hw->perm_mac_addr[5] = 0x38;
2357 }
2358
2359 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2360 hw->mac_addr[i] = hw->perm_mac_addr[i];
2361
2362 return 0;
2363 }
2364
2365 /*
2366 * Hashes an address to determine its location in the multicast table
2367 *
2368 * hw - Struct containing variables accessed by shared code
2369 * mc_addr - the multicast address to hash
2370 *
2371 * atl2_hash_mc_addr
2372 * purpose
2373 * set hash value for a multicast address
2374 * hash calcu processing :
2375 * 1. calcu 32bit CRC for multicast address
2376 * 2. reverse crc with MSB to LSB
2377 */
2378 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2379 {
2380 u32 crc32, value;
2381 int i;
2382
2383 value = 0;
2384 crc32 = ether_crc_le(6, mc_addr);
2385
2386 for (i = 0; i < 32; i++)
2387 value |= (((crc32 >> i) & 1) << (31 - i));
2388
2389 return value;
2390 }
2391
2392 /*
2393 * Sets the bit in the multicast table corresponding to the hash value.
2394 *
2395 * hw - Struct containing variables accessed by shared code
2396 * hash_value - Multicast address hash value
2397 */
2398 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2399 {
2400 u32 hash_bit, hash_reg;
2401 u32 mta;
2402
2403 /* The HASH Table is a register array of 2 32-bit registers.
2404 * It is treated like an array of 64 bits. We want to set
2405 * bit BitArray[hash_value]. So we figure out what register
2406 * the bit is in, read it, OR in the new bit, then write
2407 * back the new value. The register is determined by the
2408 * upper 7 bits of the hash value and the bit within that
2409 * register are determined by the lower 5 bits of the value.
2410 */
2411 hash_reg = (hash_value >> 31) & 0x1;
2412 hash_bit = (hash_value >> 26) & 0x1F;
2413
2414 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2415
2416 mta |= (1 << hash_bit);
2417
2418 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2419 }
2420
2421 /*
2422 * atl2_init_pcie - init PCIE module
2423 */
2424 static void atl2_init_pcie(struct atl2_hw *hw)
2425 {
2426 u32 value;
2427 value = LTSSM_TEST_MODE_DEF;
2428 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2429
2430 value = PCIE_DLL_TX_CTRL1_DEF;
2431 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2432 }
2433
2434 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2435 {
2436 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2437 hw->flash_vendor = 0; /* ATMEL */
2438
2439 /* Init OP table */
2440 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2441 flash_table[hw->flash_vendor].cmdPROGRAM);
2442 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2443 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2444 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2445 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2446 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2447 flash_table[hw->flash_vendor].cmdRDID);
2448 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2449 flash_table[hw->flash_vendor].cmdWREN);
2450 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2451 flash_table[hw->flash_vendor].cmdRDSR);
2452 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2453 flash_table[hw->flash_vendor].cmdWRSR);
2454 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2455 flash_table[hw->flash_vendor].cmdREAD);
2456 }
2457
2458 /********************************************************************
2459 * Performs basic configuration of the adapter.
2460 *
2461 * hw - Struct containing variables accessed by shared code
2462 * Assumes that the controller has previously been reset and is in a
2463 * post-reset uninitialized state. Initializes multicast table,
2464 * and Calls routines to setup link
2465 * Leaves the transmit and receive units disabled and uninitialized.
2466 ********************************************************************/
2467 static s32 atl2_init_hw(struct atl2_hw *hw)
2468 {
2469 u32 ret_val = 0;
2470
2471 atl2_init_pcie(hw);
2472
2473 /* Zero out the Multicast HASH table */
2474 /* clear the old settings from the multicast hash table */
2475 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2476 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2477
2478 atl2_init_flash_opcode(hw);
2479
2480 ret_val = atl2_phy_init(hw);
2481
2482 return ret_val;
2483 }
2484
2485 /*
2486 * Detects the current speed and duplex settings of the hardware.
2487 *
2488 * hw - Struct containing variables accessed by shared code
2489 * speed - Speed of the connection
2490 * duplex - Duplex setting of the connection
2491 */
2492 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2493 u16 *duplex)
2494 {
2495 s32 ret_val;
2496 u16 phy_data;
2497
2498 /* Read PHY Specific Status Register (17) */
2499 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2500 if (ret_val)
2501 return ret_val;
2502
2503 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2504 return ATLX_ERR_PHY_RES;
2505
2506 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2507 case MII_ATLX_PSSR_100MBS:
2508 *speed = SPEED_100;
2509 break;
2510 case MII_ATLX_PSSR_10MBS:
2511 *speed = SPEED_10;
2512 break;
2513 default:
2514 return ATLX_ERR_PHY_SPEED;
2515 break;
2516 }
2517
2518 if (phy_data & MII_ATLX_PSSR_DPLX)
2519 *duplex = FULL_DUPLEX;
2520 else
2521 *duplex = HALF_DUPLEX;
2522
2523 return 0;
2524 }
2525
2526 /*
2527 * Reads the value from a PHY register
2528 * hw - Struct containing variables accessed by shared code
2529 * reg_addr - address of the PHY register to read
2530 */
2531 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2532 {
2533 u32 val;
2534 int i;
2535
2536 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2537 MDIO_START |
2538 MDIO_SUP_PREAMBLE |
2539 MDIO_RW |
2540 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2541 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2542
2543 wmb();
2544
2545 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2546 udelay(2);
2547 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2548 if (!(val & (MDIO_START | MDIO_BUSY)))
2549 break;
2550 wmb();
2551 }
2552 if (!(val & (MDIO_START | MDIO_BUSY))) {
2553 *phy_data = (u16)val;
2554 return 0;
2555 }
2556
2557 return ATLX_ERR_PHY;
2558 }
2559
2560 /*
2561 * Writes a value to a PHY register
2562 * hw - Struct containing variables accessed by shared code
2563 * reg_addr - address of the PHY register to write
2564 * data - data to write to the PHY
2565 */
2566 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2567 {
2568 int i;
2569 u32 val;
2570
2571 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2572 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2573 MDIO_SUP_PREAMBLE |
2574 MDIO_START |
2575 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2576 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2577
2578 wmb();
2579
2580 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2581 udelay(2);
2582 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2583 if (!(val & (MDIO_START | MDIO_BUSY)))
2584 break;
2585
2586 wmb();
2587 }
2588
2589 if (!(val & (MDIO_START | MDIO_BUSY)))
2590 return 0;
2591
2592 return ATLX_ERR_PHY;
2593 }
2594
2595 /*
2596 * Configures PHY autoneg and flow control advertisement settings
2597 *
2598 * hw - Struct containing variables accessed by shared code
2599 */
2600 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2601 {
2602 s32 ret_val;
2603 s16 mii_autoneg_adv_reg;
2604
2605 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2606 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2607
2608 /* Need to parse autoneg_advertised and set up
2609 * the appropriate PHY registers. First we will parse for
2610 * autoneg_advertised software override. Since we can advertise
2611 * a plethora of combinations, we need to check each bit
2612 * individually.
2613 */
2614
2615 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2616 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2617 * the 1000Base-T Control Register (Address 9). */
2618 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2619
2620 /* Need to parse MediaType and setup the
2621 * appropriate PHY registers. */
2622 switch (hw->MediaType) {
2623 case MEDIA_TYPE_AUTO_SENSOR:
2624 mii_autoneg_adv_reg |=
2625 (MII_AR_10T_HD_CAPS |
2626 MII_AR_10T_FD_CAPS |
2627 MII_AR_100TX_HD_CAPS|
2628 MII_AR_100TX_FD_CAPS);
2629 hw->autoneg_advertised =
2630 ADVERTISE_10_HALF |
2631 ADVERTISE_10_FULL |
2632 ADVERTISE_100_HALF|
2633 ADVERTISE_100_FULL;
2634 break;
2635 case MEDIA_TYPE_100M_FULL:
2636 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2637 hw->autoneg_advertised = ADVERTISE_100_FULL;
2638 break;
2639 case MEDIA_TYPE_100M_HALF:
2640 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2641 hw->autoneg_advertised = ADVERTISE_100_HALF;
2642 break;
2643 case MEDIA_TYPE_10M_FULL:
2644 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2645 hw->autoneg_advertised = ADVERTISE_10_FULL;
2646 break;
2647 default:
2648 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2649 hw->autoneg_advertised = ADVERTISE_10_HALF;
2650 break;
2651 }
2652
2653 /* flow control fixed to enable all */
2654 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2655
2656 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2657
2658 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2659
2660 if (ret_val)
2661 return ret_val;
2662
2663 return 0;
2664 }
2665
2666 /*
2667 * Resets the PHY and make all config validate
2668 *
2669 * hw - Struct containing variables accessed by shared code
2670 *
2671 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2672 */
2673 static s32 atl2_phy_commit(struct atl2_hw *hw)
2674 {
2675 s32 ret_val;
2676 u16 phy_data;
2677
2678 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2679 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2680 if (ret_val) {
2681 u32 val;
2682 int i;
2683 /* pcie serdes link may be down ! */
2684 for (i = 0; i < 25; i++) {
2685 msleep(1);
2686 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2687 if (!(val & (MDIO_START | MDIO_BUSY)))
2688 break;
2689 }
2690
2691 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2692 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2693 return ret_val;
2694 }
2695 }
2696 return 0;
2697 }
2698
2699 static s32 atl2_phy_init(struct atl2_hw *hw)
2700 {
2701 s32 ret_val;
2702 u16 phy_val;
2703
2704 if (hw->phy_configured)
2705 return 0;
2706
2707 /* Enable PHY */
2708 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2709 ATL2_WRITE_FLUSH(hw);
2710 msleep(1);
2711
2712 /* check if the PHY is in powersaving mode */
2713 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2714 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2715
2716 /* 024E / 124E 0r 0274 / 1274 ? */
2717 if (phy_val & 0x1000) {
2718 phy_val &= ~0x1000;
2719 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2720 }
2721
2722 msleep(1);
2723
2724 /*Enable PHY LinkChange Interrupt */
2725 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2726 if (ret_val)
2727 return ret_val;
2728
2729 /* setup AutoNeg parameters */
2730 ret_val = atl2_phy_setup_autoneg_adv(hw);
2731 if (ret_val)
2732 return ret_val;
2733
2734 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2735 ret_val = atl2_phy_commit(hw);
2736 if (ret_val)
2737 return ret_val;
2738
2739 hw->phy_configured = true;
2740
2741 return ret_val;
2742 }
2743
2744 static void atl2_set_mac_addr(struct atl2_hw *hw)
2745 {
2746 u32 value;
2747 /* 00-0B-6A-F6-00-DC
2748 * 0: 6AF600DC 1: 000B
2749 * low dword */
2750 value = (((u32)hw->mac_addr[2]) << 24) |
2751 (((u32)hw->mac_addr[3]) << 16) |
2752 (((u32)hw->mac_addr[4]) << 8) |
2753 (((u32)hw->mac_addr[5]));
2754 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2755 /* hight dword */
2756 value = (((u32)hw->mac_addr[0]) << 8) |
2757 (((u32)hw->mac_addr[1]));
2758 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2759 }
2760
2761 /*
2762 * check_eeprom_exist
2763 * return 0 if eeprom exist
2764 */
2765 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2766 {
2767 u32 value;
2768
2769 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2770 if (value & SPI_FLASH_CTRL_EN_VPD) {
2771 value &= ~SPI_FLASH_CTRL_EN_VPD;
2772 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2773 }
2774 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2775 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2776 }
2777
2778 /* FIXME: This doesn't look right. -- CHS */
2779 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2780 {
2781 return true;
2782 }
2783
2784 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2785 {
2786 int i;
2787 u32 Control;
2788
2789 if (Offset & 0x3)
2790 return false; /* address do not align */
2791
2792 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2793 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2794 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2795
2796 for (i = 0; i < 10; i++) {
2797 msleep(2);
2798 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2799 if (Control & VPD_CAP_VPD_FLAG)
2800 break;
2801 }
2802
2803 if (Control & VPD_CAP_VPD_FLAG) {
2804 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2805 return true;
2806 }
2807 return false; /* timeout */
2808 }
2809
2810 static void atl2_force_ps(struct atl2_hw *hw)
2811 {
2812 u16 phy_val;
2813
2814 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2815 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2816 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2817
2818 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2819 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2820 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2821 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2822 }
2823
2824 /* This is the only thing that needs to be changed to adjust the
2825 * maximum number of ports that the driver can manage.
2826 */
2827 #define ATL2_MAX_NIC 4
2828
2829 #define OPTION_UNSET -1
2830 #define OPTION_DISABLED 0
2831 #define OPTION_ENABLED 1
2832
2833 /* All parameters are treated the same, as an integer array of values.
2834 * This macro just reduces the need to repeat the same declaration code
2835 * over and over (plus this helps to avoid typo bugs).
2836 */
2837 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2838 #ifndef module_param_array
2839 /* Module Parameters are always initialized to -1, so that the driver
2840 * can tell the difference between no user specified value or the
2841 * user asking for the default value.
2842 * The true default values are loaded in when atl2_check_options is called.
2843 *
2844 * This is a GCC extension to ANSI C.
2845 * See the item "Labeled Elements in Initializers" in the section
2846 * "Extensions to the C Language Family" of the GCC documentation.
2847 */
2848
2849 #define ATL2_PARAM(X, desc) \
2850 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2851 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2852 MODULE_PARM_DESC(X, desc);
2853 #else
2854 #define ATL2_PARAM(X, desc) \
2855 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2856 static int num_##X = 0; \
2857 module_param_array_named(X, X, int, &num_##X, 0); \
2858 MODULE_PARM_DESC(X, desc);
2859 #endif
2860
2861 /*
2862 * Transmit Memory Size
2863 * Valid Range: 64-2048
2864 * Default Value: 128
2865 */
2866 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2867 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2868 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2869 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2870
2871 /*
2872 * Receive Memory Block Count
2873 * Valid Range: 16-512
2874 * Default Value: 128
2875 */
2876 #define ATL2_MIN_RXD_COUNT 16
2877 #define ATL2_MAX_RXD_COUNT 512
2878 #define ATL2_DEFAULT_RXD_COUNT 64
2879 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2880
2881 /*
2882 * User Specified MediaType Override
2883 *
2884 * Valid Range: 0-5
2885 * - 0 - auto-negotiate at all supported speeds
2886 * - 1 - only link at 1000Mbps Full Duplex
2887 * - 2 - only link at 100Mbps Full Duplex
2888 * - 3 - only link at 100Mbps Half Duplex
2889 * - 4 - only link at 10Mbps Full Duplex
2890 * - 5 - only link at 10Mbps Half Duplex
2891 * Default Value: 0
2892 */
2893 ATL2_PARAM(MediaType, "MediaType Select");
2894
2895 /*
2896 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2897 * Valid Range: 10-65535
2898 * Default Value: 45000(90ms)
2899 */
2900 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2901 #define INT_MOD_MAX_CNT 65000
2902 #define INT_MOD_MIN_CNT 50
2903 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2904
2905 /*
2906 * FlashVendor
2907 * Valid Range: 0-2
2908 * 0 - Atmel
2909 * 1 - SST
2910 * 2 - ST
2911 */
2912 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2913
2914 #define AUTONEG_ADV_DEFAULT 0x2F
2915 #define AUTONEG_ADV_MASK 0x2F
2916 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2917
2918 #define FLASH_VENDOR_DEFAULT 0
2919 #define FLASH_VENDOR_MIN 0
2920 #define FLASH_VENDOR_MAX 2
2921
2922 struct atl2_option {
2923 enum { enable_option, range_option, list_option } type;
2924 char *name;
2925 char *err;
2926 int def;
2927 union {
2928 struct { /* range_option info */
2929 int min;
2930 int max;
2931 } r;
2932 struct { /* list_option info */
2933 int nr;
2934 struct atl2_opt_list { int i; char *str; } *p;
2935 } l;
2936 } arg;
2937 };
2938
2939 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2940 {
2941 int i;
2942 struct atl2_opt_list *ent;
2943
2944 if (*value == OPTION_UNSET) {
2945 *value = opt->def;
2946 return 0;
2947 }
2948
2949 switch (opt->type) {
2950 case enable_option:
2951 switch (*value) {
2952 case OPTION_ENABLED:
2953 printk(KERN_INFO "%s Enabled\n", opt->name);
2954 return 0;
2955 break;
2956 case OPTION_DISABLED:
2957 printk(KERN_INFO "%s Disabled\n", opt->name);
2958 return 0;
2959 break;
2960 }
2961 break;
2962 case range_option:
2963 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2964 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2965 return 0;
2966 }
2967 break;
2968 case list_option:
2969 for (i = 0; i < opt->arg.l.nr; i++) {
2970 ent = &opt->arg.l.p[i];
2971 if (*value == ent->i) {
2972 if (ent->str[0] != '\0')
2973 printk(KERN_INFO "%s\n", ent->str);
2974 return 0;
2975 }
2976 }
2977 break;
2978 default:
2979 BUG();
2980 }
2981
2982 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2983 opt->name, *value, opt->err);
2984 *value = opt->def;
2985 return -1;
2986 }
2987
2988 /*
2989 * atl2_check_options - Range Checking for Command Line Parameters
2990 * @adapter: board private structure
2991 *
2992 * This routine checks all command line parameters for valid user
2993 * input. If an invalid value is given, or if no user specified
2994 * value exists, a default value is used. The final value is stored
2995 * in a variable in the adapter structure.
2996 */
2997 static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2998 {
2999 int val;
3000 struct atl2_option opt;
3001 int bd = adapter->bd_number;
3002 if (bd >= ATL2_MAX_NIC) {
3003 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3004 bd);
3005 printk(KERN_NOTICE "Using defaults for all values\n");
3006 #ifndef module_param_array
3007 bd = ATL2_MAX_NIC;
3008 #endif
3009 }
3010
3011 /* Bytes of Transmit Memory */
3012 opt.type = range_option;
3013 opt.name = "Bytes of Transmit Memory";
3014 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3015 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3016 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3017 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3018 #ifdef module_param_array
3019 if (num_TxMemSize > bd) {
3020 #endif
3021 val = TxMemSize[bd];
3022 atl2_validate_option(&val, &opt);
3023 adapter->txd_ring_size = ((u32) val) * 1024;
3024 #ifdef module_param_array
3025 } else
3026 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3027 #endif
3028 /* txs ring size: */
3029 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3030 if (adapter->txs_ring_size > 160)
3031 adapter->txs_ring_size = 160;
3032
3033 /* Receive Memory Block Count */
3034 opt.type = range_option;
3035 opt.name = "Number of receive memory block";
3036 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3037 opt.def = ATL2_DEFAULT_RXD_COUNT;
3038 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3039 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3040 #ifdef module_param_array
3041 if (num_RxMemBlock > bd) {
3042 #endif
3043 val = RxMemBlock[bd];
3044 atl2_validate_option(&val, &opt);
3045 adapter->rxd_ring_size = (u32)val;
3046 /* FIXME */
3047 /* ((u16)val)&~1; */ /* even number */
3048 #ifdef module_param_array
3049 } else
3050 adapter->rxd_ring_size = (u32)opt.def;
3051 #endif
3052 /* init RXD Flow control value */
3053 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3054 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3055 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3056 (adapter->rxd_ring_size / 12);
3057
3058 /* Interrupt Moderate Timer */
3059 opt.type = range_option;
3060 opt.name = "Interrupt Moderate Timer";
3061 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3062 opt.def = INT_MOD_DEFAULT_CNT;
3063 opt.arg.r.min = INT_MOD_MIN_CNT;
3064 opt.arg.r.max = INT_MOD_MAX_CNT;
3065 #ifdef module_param_array
3066 if (num_IntModTimer > bd) {
3067 #endif
3068 val = IntModTimer[bd];
3069 atl2_validate_option(&val, &opt);
3070 adapter->imt = (u16) val;
3071 #ifdef module_param_array
3072 } else
3073 adapter->imt = (u16)(opt.def);
3074 #endif
3075 /* Flash Vendor */
3076 opt.type = range_option;
3077 opt.name = "SPI Flash Vendor";
3078 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3079 opt.def = FLASH_VENDOR_DEFAULT;
3080 opt.arg.r.min = FLASH_VENDOR_MIN;
3081 opt.arg.r.max = FLASH_VENDOR_MAX;
3082 #ifdef module_param_array
3083 if (num_FlashVendor > bd) {
3084 #endif
3085 val = FlashVendor[bd];
3086 atl2_validate_option(&val, &opt);
3087 adapter->hw.flash_vendor = (u8) val;
3088 #ifdef module_param_array
3089 } else
3090 adapter->hw.flash_vendor = (u8)(opt.def);
3091 #endif
3092 /* MediaType */
3093 opt.type = range_option;
3094 opt.name = "Speed/Duplex Selection";
3095 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3096 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3097 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3098 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3099 #ifdef module_param_array
3100 if (num_MediaType > bd) {
3101 #endif
3102 val = MediaType[bd];
3103 atl2_validate_option(&val, &opt);
3104 adapter->hw.MediaType = (u16) val;
3105 #ifdef module_param_array
3106 } else
3107 adapter->hw.MediaType = (u16)(opt.def);
3108 #endif
3109 }
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