2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
60 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
61 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
62 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
64 #ifndef PHYSICAL_PAGE_MASK
65 #define PHYSICAL_PAGE_MASK PAGE_MASK
68 /* global iommu list, set NULL for ignored DMAR units */
69 static struct intel_iommu
**g_iommus
;
71 static int rwbf_quirk
;
76 * 12-63: Context Ptr (12 - (haw-1))
83 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
84 static inline bool root_present(struct root_entry
*root
)
86 return (root
->val
& 1);
88 static inline void set_root_present(struct root_entry
*root
)
92 static inline void set_root_value(struct root_entry
*root
, unsigned long value
)
94 root
->val
|= value
& VTD_PAGE_MASK
;
97 static inline struct context_entry
*
98 get_context_addr_from_root(struct root_entry
*root
)
100 return (struct context_entry
*)
101 (root_present(root
)?phys_to_virt(
102 root
->val
& VTD_PAGE_MASK
) :
109 * 1: fault processing disable
110 * 2-3: translation type
111 * 12-63: address space root
117 struct context_entry
{
122 static inline bool context_present(struct context_entry
*context
)
124 return (context
->lo
& 1);
126 static inline void context_set_present(struct context_entry
*context
)
131 static inline void context_set_fault_enable(struct context_entry
*context
)
133 context
->lo
&= (((u64
)-1) << 2) | 1;
136 static inline void context_set_translation_type(struct context_entry
*context
,
139 context
->lo
&= (((u64
)-1) << 4) | 3;
140 context
->lo
|= (value
& 3) << 2;
143 static inline void context_set_address_root(struct context_entry
*context
,
146 context
->lo
|= value
& VTD_PAGE_MASK
;
149 static inline void context_set_address_width(struct context_entry
*context
,
152 context
->hi
|= value
& 7;
155 static inline void context_set_domain_id(struct context_entry
*context
,
158 context
->hi
|= (value
& ((1 << 16) - 1)) << 8;
161 static inline void context_clear_entry(struct context_entry
*context
)
174 * 12-63: Host physcial address
180 static inline void dma_clear_pte(struct dma_pte
*pte
)
185 static inline void dma_set_pte_readable(struct dma_pte
*pte
)
187 pte
->val
|= DMA_PTE_READ
;
190 static inline void dma_set_pte_writable(struct dma_pte
*pte
)
192 pte
->val
|= DMA_PTE_WRITE
;
195 static inline void dma_set_pte_snp(struct dma_pte
*pte
)
197 pte
->val
|= DMA_PTE_SNP
;
200 static inline void dma_set_pte_prot(struct dma_pte
*pte
, unsigned long prot
)
202 pte
->val
= (pte
->val
& ~3) | (prot
& 3);
205 static inline u64
dma_pte_addr(struct dma_pte
*pte
)
207 return (pte
->val
& VTD_PAGE_MASK
);
210 static inline void dma_set_pte_addr(struct dma_pte
*pte
, u64 addr
)
212 pte
->val
|= (addr
& VTD_PAGE_MASK
);
215 static inline bool dma_pte_present(struct dma_pte
*pte
)
217 return (pte
->val
& 3) != 0;
221 * This domain is a statically identity mapping domain.
222 * 1. This domain creats a static 1:1 mapping to all usable memory.
223 * 2. It maps to each iommu if successful.
224 * 3. Each iommu mapps to this domain if successful.
226 struct dmar_domain
*si_domain
;
228 /* devices under the same p2p bridge are owned in one domain */
229 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
231 /* domain represents a virtual machine, more than one devices
232 * across iommus may be owned in one domain, e.g. kvm guest.
234 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
236 /* si_domain contains mulitple devices */
237 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
240 int id
; /* domain id */
241 unsigned long iommu_bmp
; /* bitmap of iommus this domain uses*/
243 struct list_head devices
; /* all devices' list */
244 struct iova_domain iovad
; /* iova's that belong to this domain */
246 struct dma_pte
*pgd
; /* virtual address */
247 spinlock_t mapping_lock
; /* page table lock */
248 int gaw
; /* max guest address width */
250 /* adjusted guest address width, 0 is level 2 30-bit */
253 int flags
; /* flags to find out type of domain */
255 int iommu_coherency
;/* indicate coherency of iommu access */
256 int iommu_snooping
; /* indicate snooping control feature*/
257 int iommu_count
; /* reference count of iommu */
258 spinlock_t iommu_lock
; /* protect iommu set in domain */
259 u64 max_addr
; /* maximum mapped address */
262 /* PCI domain-device relationship */
263 struct device_domain_info
{
264 struct list_head link
; /* link to domain siblings */
265 struct list_head global
; /* link to global list */
266 int segment
; /* PCI domain */
267 u8 bus
; /* PCI bus number */
268 u8 devfn
; /* PCI devfn number */
269 struct pci_dev
*dev
; /* it's NULL for PCIE-to-PCI bridge */
270 struct intel_iommu
*iommu
; /* IOMMU used by this device */
271 struct dmar_domain
*domain
; /* pointer to domain */
274 static void flush_unmaps_timeout(unsigned long data
);
276 DEFINE_TIMER(unmap_timer
, flush_unmaps_timeout
, 0, 0);
278 #define HIGH_WATER_MARK 250
279 struct deferred_flush_tables
{
281 struct iova
*iova
[HIGH_WATER_MARK
];
282 struct dmar_domain
*domain
[HIGH_WATER_MARK
];
285 static struct deferred_flush_tables
*deferred_flush
;
287 /* bitmap for indexing intel_iommus */
288 static int g_num_of_iommus
;
290 static DEFINE_SPINLOCK(async_umap_flush_lock
);
291 static LIST_HEAD(unmaps_to_do
);
294 static long list_size
;
296 static void domain_remove_dev_info(struct dmar_domain
*domain
);
298 #ifdef CONFIG_DMAR_DEFAULT_ON
299 int dmar_disabled
= 0;
301 int dmar_disabled
= 1;
302 #endif /*CONFIG_DMAR_DEFAULT_ON*/
304 static int __initdata dmar_map_gfx
= 1;
305 static int dmar_forcedac
;
306 static int intel_iommu_strict
;
308 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
309 static DEFINE_SPINLOCK(device_domain_lock
);
310 static LIST_HEAD(device_domain_list
);
312 static struct iommu_ops intel_iommu_ops
;
314 static int __init
intel_iommu_setup(char *str
)
319 if (!strncmp(str
, "on", 2)) {
321 printk(KERN_INFO
"Intel-IOMMU: enabled\n");
322 } else if (!strncmp(str
, "off", 3)) {
324 printk(KERN_INFO
"Intel-IOMMU: disabled\n");
325 } else if (!strncmp(str
, "igfx_off", 8)) {
328 "Intel-IOMMU: disable GFX device mapping\n");
329 } else if (!strncmp(str
, "forcedac", 8)) {
331 "Intel-IOMMU: Forcing DAC for PCI devices\n");
333 } else if (!strncmp(str
, "strict", 6)) {
335 "Intel-IOMMU: disable batched IOTLB flush\n");
336 intel_iommu_strict
= 1;
339 str
+= strcspn(str
, ",");
345 __setup("intel_iommu=", intel_iommu_setup
);
347 static struct kmem_cache
*iommu_domain_cache
;
348 static struct kmem_cache
*iommu_devinfo_cache
;
349 static struct kmem_cache
*iommu_iova_cache
;
351 static inline void *iommu_kmem_cache_alloc(struct kmem_cache
*cachep
)
356 /* trying to avoid low memory issues */
357 flags
= current
->flags
& PF_MEMALLOC
;
358 current
->flags
|= PF_MEMALLOC
;
359 vaddr
= kmem_cache_alloc(cachep
, GFP_ATOMIC
);
360 current
->flags
&= (~PF_MEMALLOC
| flags
);
365 static inline void *alloc_pgtable_page(void)
370 /* trying to avoid low memory issues */
371 flags
= current
->flags
& PF_MEMALLOC
;
372 current
->flags
|= PF_MEMALLOC
;
373 vaddr
= (void *)get_zeroed_page(GFP_ATOMIC
);
374 current
->flags
&= (~PF_MEMALLOC
| flags
);
378 static inline void free_pgtable_page(void *vaddr
)
380 free_page((unsigned long)vaddr
);
383 static inline void *alloc_domain_mem(void)
385 return iommu_kmem_cache_alloc(iommu_domain_cache
);
388 static void free_domain_mem(void *vaddr
)
390 kmem_cache_free(iommu_domain_cache
, vaddr
);
393 static inline void * alloc_devinfo_mem(void)
395 return iommu_kmem_cache_alloc(iommu_devinfo_cache
);
398 static inline void free_devinfo_mem(void *vaddr
)
400 kmem_cache_free(iommu_devinfo_cache
, vaddr
);
403 struct iova
*alloc_iova_mem(void)
405 return iommu_kmem_cache_alloc(iommu_iova_cache
);
408 void free_iova_mem(struct iova
*iova
)
410 kmem_cache_free(iommu_iova_cache
, iova
);
414 static inline int width_to_agaw(int width
);
416 static int __iommu_calculate_agaw(struct intel_iommu
*iommu
, int max_gaw
)
421 sagaw
= cap_sagaw(iommu
->cap
);
422 for (agaw
= width_to_agaw(max_gaw
);
424 if (test_bit(agaw
, &sagaw
))
432 * Calculate max SAGAW for each iommu.
434 int iommu_calculate_max_sagaw(struct intel_iommu
*iommu
)
436 return __iommu_calculate_agaw(iommu
, MAX_AGAW_WIDTH
);
440 * calculate agaw for each iommu.
441 * "SAGAW" may be different across iommus, use a default agaw, and
442 * get a supported less agaw for iommus that don't support the default agaw.
444 int iommu_calculate_agaw(struct intel_iommu
*iommu
)
446 return __iommu_calculate_agaw(iommu
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
449 /* This functionin only returns single iommu in a domain */
450 static struct intel_iommu
*domain_get_iommu(struct dmar_domain
*domain
)
454 /* si_domain and vm domain should not get here. */
455 BUG_ON(domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
);
456 BUG_ON(domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
);
458 iommu_id
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
459 if (iommu_id
< 0 || iommu_id
>= g_num_of_iommus
)
462 return g_iommus
[iommu_id
];
465 static void domain_update_iommu_coherency(struct dmar_domain
*domain
)
469 domain
->iommu_coherency
= 1;
471 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
472 for (; i
< g_num_of_iommus
; ) {
473 if (!ecap_coherent(g_iommus
[i
]->ecap
)) {
474 domain
->iommu_coherency
= 0;
477 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
481 static void domain_update_iommu_snooping(struct dmar_domain
*domain
)
485 domain
->iommu_snooping
= 1;
487 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
488 for (; i
< g_num_of_iommus
; ) {
489 if (!ecap_sc_support(g_iommus
[i
]->ecap
)) {
490 domain
->iommu_snooping
= 0;
493 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
497 /* Some capabilities may be different across iommus */
498 static void domain_update_iommu_cap(struct dmar_domain
*domain
)
500 domain_update_iommu_coherency(domain
);
501 domain_update_iommu_snooping(domain
);
504 static struct intel_iommu
*device_to_iommu(int segment
, u8 bus
, u8 devfn
)
506 struct dmar_drhd_unit
*drhd
= NULL
;
509 for_each_drhd_unit(drhd
) {
512 if (segment
!= drhd
->segment
)
515 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
516 if (drhd
->devices
[i
] &&
517 drhd
->devices
[i
]->bus
->number
== bus
&&
518 drhd
->devices
[i
]->devfn
== devfn
)
520 if (drhd
->devices
[i
] &&
521 drhd
->devices
[i
]->subordinate
&&
522 drhd
->devices
[i
]->subordinate
->number
<= bus
&&
523 drhd
->devices
[i
]->subordinate
->subordinate
>= bus
)
527 if (drhd
->include_all
)
534 static void domain_flush_cache(struct dmar_domain
*domain
,
535 void *addr
, int size
)
537 if (!domain
->iommu_coherency
)
538 clflush_cache_range(addr
, size
);
541 /* Gets context entry for a given bus and devfn */
542 static struct context_entry
* device_to_context_entry(struct intel_iommu
*iommu
,
545 struct root_entry
*root
;
546 struct context_entry
*context
;
547 unsigned long phy_addr
;
550 spin_lock_irqsave(&iommu
->lock
, flags
);
551 root
= &iommu
->root_entry
[bus
];
552 context
= get_context_addr_from_root(root
);
554 context
= (struct context_entry
*)alloc_pgtable_page();
556 spin_unlock_irqrestore(&iommu
->lock
, flags
);
559 __iommu_flush_cache(iommu
, (void *)context
, CONTEXT_SIZE
);
560 phy_addr
= virt_to_phys((void *)context
);
561 set_root_value(root
, phy_addr
);
562 set_root_present(root
);
563 __iommu_flush_cache(iommu
, root
, sizeof(*root
));
565 spin_unlock_irqrestore(&iommu
->lock
, flags
);
566 return &context
[devfn
];
569 static int device_context_mapped(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
571 struct root_entry
*root
;
572 struct context_entry
*context
;
576 spin_lock_irqsave(&iommu
->lock
, flags
);
577 root
= &iommu
->root_entry
[bus
];
578 context
= get_context_addr_from_root(root
);
583 ret
= context_present(&context
[devfn
]);
585 spin_unlock_irqrestore(&iommu
->lock
, flags
);
589 static void clear_context_table(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
591 struct root_entry
*root
;
592 struct context_entry
*context
;
595 spin_lock_irqsave(&iommu
->lock
, flags
);
596 root
= &iommu
->root_entry
[bus
];
597 context
= get_context_addr_from_root(root
);
599 context_clear_entry(&context
[devfn
]);
600 __iommu_flush_cache(iommu
, &context
[devfn
], \
603 spin_unlock_irqrestore(&iommu
->lock
, flags
);
606 static void free_context_table(struct intel_iommu
*iommu
)
608 struct root_entry
*root
;
611 struct context_entry
*context
;
613 spin_lock_irqsave(&iommu
->lock
, flags
);
614 if (!iommu
->root_entry
) {
617 for (i
= 0; i
< ROOT_ENTRY_NR
; i
++) {
618 root
= &iommu
->root_entry
[i
];
619 context
= get_context_addr_from_root(root
);
621 free_pgtable_page(context
);
623 free_pgtable_page(iommu
->root_entry
);
624 iommu
->root_entry
= NULL
;
626 spin_unlock_irqrestore(&iommu
->lock
, flags
);
629 /* page table handling */
630 #define LEVEL_STRIDE (9)
631 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
633 static inline int agaw_to_level(int agaw
)
638 static inline int agaw_to_width(int agaw
)
640 return 30 + agaw
* LEVEL_STRIDE
;
644 static inline int width_to_agaw(int width
)
646 return (width
- 30) / LEVEL_STRIDE
;
649 static inline unsigned int level_to_offset_bits(int level
)
651 return (12 + (level
- 1) * LEVEL_STRIDE
);
654 static inline int address_level_offset(u64 addr
, int level
)
656 return ((addr
>> level_to_offset_bits(level
)) & LEVEL_MASK
);
659 static inline u64
level_mask(int level
)
661 return ((u64
)-1 << level_to_offset_bits(level
));
664 static inline u64
level_size(int level
)
666 return ((u64
)1 << level_to_offset_bits(level
));
669 static inline u64
align_to_level(u64 addr
, int level
)
671 return ((addr
+ level_size(level
) - 1) & level_mask(level
));
674 static struct dma_pte
* addr_to_dma_pte(struct dmar_domain
*domain
, u64 addr
)
676 int addr_width
= agaw_to_width(domain
->agaw
);
677 struct dma_pte
*parent
, *pte
= NULL
;
678 int level
= agaw_to_level(domain
->agaw
);
682 BUG_ON(!domain
->pgd
);
684 addr
&= (((u64
)1) << addr_width
) - 1;
685 parent
= domain
->pgd
;
687 spin_lock_irqsave(&domain
->mapping_lock
, flags
);
691 offset
= address_level_offset(addr
, level
);
692 pte
= &parent
[offset
];
696 if (!dma_pte_present(pte
)) {
697 tmp_page
= alloc_pgtable_page();
700 spin_unlock_irqrestore(&domain
->mapping_lock
,
704 domain_flush_cache(domain
, tmp_page
, PAGE_SIZE
);
705 dma_set_pte_addr(pte
, virt_to_phys(tmp_page
));
707 * high level table always sets r/w, last level page
708 * table control read/write
710 dma_set_pte_readable(pte
);
711 dma_set_pte_writable(pte
);
712 domain_flush_cache(domain
, pte
, sizeof(*pte
));
714 parent
= phys_to_virt(dma_pte_addr(pte
));
718 spin_unlock_irqrestore(&domain
->mapping_lock
, flags
);
722 /* return address's pte at specific level */
723 static struct dma_pte
*dma_addr_level_pte(struct dmar_domain
*domain
, u64 addr
,
726 struct dma_pte
*parent
, *pte
= NULL
;
727 int total
= agaw_to_level(domain
->agaw
);
730 parent
= domain
->pgd
;
731 while (level
<= total
) {
732 offset
= address_level_offset(addr
, total
);
733 pte
= &parent
[offset
];
737 if (!dma_pte_present(pte
))
739 parent
= phys_to_virt(dma_pte_addr(pte
));
745 /* clear one page's page table */
746 static void dma_pte_clear_one(struct dmar_domain
*domain
, u64 addr
)
748 struct dma_pte
*pte
= NULL
;
750 /* get last level pte */
751 pte
= dma_addr_level_pte(domain
, addr
, 1);
755 domain_flush_cache(domain
, pte
, sizeof(*pte
));
759 /* clear last level pte, a tlb flush should be followed */
760 static void dma_pte_clear_range(struct dmar_domain
*domain
, u64 start
, u64 end
)
762 int addr_width
= agaw_to_width(domain
->agaw
);
765 start
&= (((u64
)1) << addr_width
) - 1;
766 end
&= (((u64
)1) << addr_width
) - 1;
767 /* in case it's partial page */
769 end
= PAGE_ALIGN(end
);
770 npages
= (end
- start
) / VTD_PAGE_SIZE
;
772 /* we don't need lock here, nobody else touches the iova range */
774 dma_pte_clear_one(domain
, start
);
775 start
+= VTD_PAGE_SIZE
;
779 /* free page table pages. last level pte should already be cleared */
780 static void dma_pte_free_pagetable(struct dmar_domain
*domain
,
783 int addr_width
= agaw_to_width(domain
->agaw
);
785 int total
= agaw_to_level(domain
->agaw
);
789 start
&= (((u64
)1) << addr_width
) - 1;
790 end
&= (((u64
)1) << addr_width
) - 1;
792 /* we don't need lock here, nobody else touches the iova range */
794 while (level
<= total
) {
795 tmp
= align_to_level(start
, level
);
796 if (tmp
>= end
|| (tmp
+ level_size(level
) > end
))
800 pte
= dma_addr_level_pte(domain
, tmp
, level
);
803 phys_to_virt(dma_pte_addr(pte
)));
805 domain_flush_cache(domain
, pte
, sizeof(*pte
));
807 tmp
+= level_size(level
);
812 if (start
== 0 && end
>= ((((u64
)1) << addr_width
) - 1)) {
813 free_pgtable_page(domain
->pgd
);
819 static int iommu_alloc_root_entry(struct intel_iommu
*iommu
)
821 struct root_entry
*root
;
824 root
= (struct root_entry
*)alloc_pgtable_page();
828 __iommu_flush_cache(iommu
, root
, ROOT_SIZE
);
830 spin_lock_irqsave(&iommu
->lock
, flags
);
831 iommu
->root_entry
= root
;
832 spin_unlock_irqrestore(&iommu
->lock
, flags
);
837 static void iommu_set_root_entry(struct intel_iommu
*iommu
)
843 addr
= iommu
->root_entry
;
845 spin_lock_irqsave(&iommu
->register_lock
, flag
);
846 dmar_writeq(iommu
->reg
+ DMAR_RTADDR_REG
, virt_to_phys(addr
));
848 writel(iommu
->gcmd
| DMA_GCMD_SRTP
, iommu
->reg
+ DMAR_GCMD_REG
);
850 /* Make sure hardware complete it */
851 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
852 readl
, (sts
& DMA_GSTS_RTPS
), sts
);
854 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
857 static void iommu_flush_write_buffer(struct intel_iommu
*iommu
)
862 if (!rwbf_quirk
&& !cap_rwbf(iommu
->cap
))
865 spin_lock_irqsave(&iommu
->register_lock
, flag
);
866 writel(iommu
->gcmd
| DMA_GCMD_WBF
, iommu
->reg
+ DMAR_GCMD_REG
);
868 /* Make sure hardware complete it */
869 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
870 readl
, (!(val
& DMA_GSTS_WBFS
)), val
);
872 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
875 /* return value determine if we need a write buffer flush */
876 static void __iommu_flush_context(struct intel_iommu
*iommu
,
877 u16 did
, u16 source_id
, u8 function_mask
,
884 case DMA_CCMD_GLOBAL_INVL
:
885 val
= DMA_CCMD_GLOBAL_INVL
;
887 case DMA_CCMD_DOMAIN_INVL
:
888 val
= DMA_CCMD_DOMAIN_INVL
|DMA_CCMD_DID(did
);
890 case DMA_CCMD_DEVICE_INVL
:
891 val
= DMA_CCMD_DEVICE_INVL
|DMA_CCMD_DID(did
)
892 | DMA_CCMD_SID(source_id
) | DMA_CCMD_FM(function_mask
);
899 spin_lock_irqsave(&iommu
->register_lock
, flag
);
900 dmar_writeq(iommu
->reg
+ DMAR_CCMD_REG
, val
);
902 /* Make sure hardware complete it */
903 IOMMU_WAIT_OP(iommu
, DMAR_CCMD_REG
,
904 dmar_readq
, (!(val
& DMA_CCMD_ICC
)), val
);
906 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
909 /* return value determine if we need a write buffer flush */
910 static void __iommu_flush_iotlb(struct intel_iommu
*iommu
, u16 did
,
911 u64 addr
, unsigned int size_order
, u64 type
)
913 int tlb_offset
= ecap_iotlb_offset(iommu
->ecap
);
914 u64 val
= 0, val_iva
= 0;
918 case DMA_TLB_GLOBAL_FLUSH
:
919 /* global flush doesn't need set IVA_REG */
920 val
= DMA_TLB_GLOBAL_FLUSH
|DMA_TLB_IVT
;
922 case DMA_TLB_DSI_FLUSH
:
923 val
= DMA_TLB_DSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
925 case DMA_TLB_PSI_FLUSH
:
926 val
= DMA_TLB_PSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
927 /* Note: always flush non-leaf currently */
928 val_iva
= size_order
| addr
;
933 /* Note: set drain read/write */
936 * This is probably to be super secure.. Looks like we can
937 * ignore it without any impact.
939 if (cap_read_drain(iommu
->cap
))
940 val
|= DMA_TLB_READ_DRAIN
;
942 if (cap_write_drain(iommu
->cap
))
943 val
|= DMA_TLB_WRITE_DRAIN
;
945 spin_lock_irqsave(&iommu
->register_lock
, flag
);
946 /* Note: Only uses first TLB reg currently */
948 dmar_writeq(iommu
->reg
+ tlb_offset
, val_iva
);
949 dmar_writeq(iommu
->reg
+ tlb_offset
+ 8, val
);
951 /* Make sure hardware complete it */
952 IOMMU_WAIT_OP(iommu
, tlb_offset
+ 8,
953 dmar_readq
, (!(val
& DMA_TLB_IVT
)), val
);
955 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
957 /* check IOTLB invalidation granularity */
958 if (DMA_TLB_IAIG(val
) == 0)
959 printk(KERN_ERR
"IOMMU: flush IOTLB failed\n");
960 if (DMA_TLB_IAIG(val
) != DMA_TLB_IIRG(type
))
961 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
962 (unsigned long long)DMA_TLB_IIRG(type
),
963 (unsigned long long)DMA_TLB_IAIG(val
));
966 static struct device_domain_info
*iommu_support_dev_iotlb(
967 struct dmar_domain
*domain
, int segment
, u8 bus
, u8 devfn
)
971 struct device_domain_info
*info
;
972 struct intel_iommu
*iommu
= device_to_iommu(segment
, bus
, devfn
);
974 if (!ecap_dev_iotlb_support(iommu
->ecap
))
980 spin_lock_irqsave(&device_domain_lock
, flags
);
981 list_for_each_entry(info
, &domain
->devices
, link
)
982 if (info
->bus
== bus
&& info
->devfn
== devfn
) {
986 spin_unlock_irqrestore(&device_domain_lock
, flags
);
988 if (!found
|| !info
->dev
)
991 if (!pci_find_ext_capability(info
->dev
, PCI_EXT_CAP_ID_ATS
))
994 if (!dmar_find_matched_atsr_unit(info
->dev
))
1002 static void iommu_enable_dev_iotlb(struct device_domain_info
*info
)
1007 pci_enable_ats(info
->dev
, VTD_PAGE_SHIFT
);
1010 static void iommu_disable_dev_iotlb(struct device_domain_info
*info
)
1012 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1015 pci_disable_ats(info
->dev
);
1018 static void iommu_flush_dev_iotlb(struct dmar_domain
*domain
,
1019 u64 addr
, unsigned mask
)
1022 unsigned long flags
;
1023 struct device_domain_info
*info
;
1025 spin_lock_irqsave(&device_domain_lock
, flags
);
1026 list_for_each_entry(info
, &domain
->devices
, link
) {
1027 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1030 sid
= info
->bus
<< 8 | info
->devfn
;
1031 qdep
= pci_ats_queue_depth(info
->dev
);
1032 qi_flush_dev_iotlb(info
->iommu
, sid
, qdep
, addr
, mask
);
1034 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1037 static void iommu_flush_iotlb_psi(struct intel_iommu
*iommu
, u16 did
,
1038 u64 addr
, unsigned int pages
)
1040 unsigned int mask
= ilog2(__roundup_pow_of_two(pages
));
1042 BUG_ON(addr
& (~VTD_PAGE_MASK
));
1046 * Fallback to domain selective flush if no PSI support or the size is
1048 * PSI requires page size to be 2 ^ x, and the base address is naturally
1049 * aligned to the size
1051 if (!cap_pgsel_inv(iommu
->cap
) || mask
> cap_max_amask_val(iommu
->cap
))
1052 iommu
->flush
.flush_iotlb(iommu
, did
, 0, 0,
1055 iommu
->flush
.flush_iotlb(iommu
, did
, addr
, mask
,
1059 * In caching mode, domain ID 0 is reserved for non-present to present
1060 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1062 if (!cap_caching_mode(iommu
->cap
) || did
)
1063 iommu_flush_dev_iotlb(iommu
->domains
[did
], addr
, mask
);
1066 static void iommu_disable_protect_mem_regions(struct intel_iommu
*iommu
)
1069 unsigned long flags
;
1071 spin_lock_irqsave(&iommu
->register_lock
, flags
);
1072 pmen
= readl(iommu
->reg
+ DMAR_PMEN_REG
);
1073 pmen
&= ~DMA_PMEN_EPM
;
1074 writel(pmen
, iommu
->reg
+ DMAR_PMEN_REG
);
1076 /* wait for the protected region status bit to clear */
1077 IOMMU_WAIT_OP(iommu
, DMAR_PMEN_REG
,
1078 readl
, !(pmen
& DMA_PMEN_PRS
), pmen
);
1080 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1083 static int iommu_enable_translation(struct intel_iommu
*iommu
)
1086 unsigned long flags
;
1088 spin_lock_irqsave(&iommu
->register_lock
, flags
);
1089 iommu
->gcmd
|= DMA_GCMD_TE
;
1090 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1092 /* Make sure hardware complete it */
1093 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1094 readl
, (sts
& DMA_GSTS_TES
), sts
);
1096 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1100 static int iommu_disable_translation(struct intel_iommu
*iommu
)
1105 spin_lock_irqsave(&iommu
->register_lock
, flag
);
1106 iommu
->gcmd
&= ~DMA_GCMD_TE
;
1107 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1109 /* Make sure hardware complete it */
1110 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1111 readl
, (!(sts
& DMA_GSTS_TES
)), sts
);
1113 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
1118 static int iommu_init_domains(struct intel_iommu
*iommu
)
1120 unsigned long ndomains
;
1121 unsigned long nlongs
;
1123 ndomains
= cap_ndoms(iommu
->cap
);
1124 pr_debug("Number of Domains supportd <%ld>\n", ndomains
);
1125 nlongs
= BITS_TO_LONGS(ndomains
);
1127 /* TBD: there might be 64K domains,
1128 * consider other allocation for future chip
1130 iommu
->domain_ids
= kcalloc(nlongs
, sizeof(unsigned long), GFP_KERNEL
);
1131 if (!iommu
->domain_ids
) {
1132 printk(KERN_ERR
"Allocating domain id array failed\n");
1135 iommu
->domains
= kcalloc(ndomains
, sizeof(struct dmar_domain
*),
1137 if (!iommu
->domains
) {
1138 printk(KERN_ERR
"Allocating domain array failed\n");
1139 kfree(iommu
->domain_ids
);
1143 spin_lock_init(&iommu
->lock
);
1146 * if Caching mode is set, then invalid translations are tagged
1147 * with domainid 0. Hence we need to pre-allocate it.
1149 if (cap_caching_mode(iommu
->cap
))
1150 set_bit(0, iommu
->domain_ids
);
1155 static void domain_exit(struct dmar_domain
*domain
);
1156 static void vm_domain_exit(struct dmar_domain
*domain
);
1158 void free_dmar_iommu(struct intel_iommu
*iommu
)
1160 struct dmar_domain
*domain
;
1162 unsigned long flags
;
1164 i
= find_first_bit(iommu
->domain_ids
, cap_ndoms(iommu
->cap
));
1165 for (; i
< cap_ndoms(iommu
->cap
); ) {
1166 domain
= iommu
->domains
[i
];
1167 clear_bit(i
, iommu
->domain_ids
);
1169 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1170 if (--domain
->iommu_count
== 0) {
1171 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
)
1172 vm_domain_exit(domain
);
1174 domain_exit(domain
);
1176 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1178 i
= find_next_bit(iommu
->domain_ids
,
1179 cap_ndoms(iommu
->cap
), i
+1);
1182 if (iommu
->gcmd
& DMA_GCMD_TE
)
1183 iommu_disable_translation(iommu
);
1186 set_irq_data(iommu
->irq
, NULL
);
1187 /* This will mask the irq */
1188 free_irq(iommu
->irq
, iommu
);
1189 destroy_irq(iommu
->irq
);
1192 kfree(iommu
->domains
);
1193 kfree(iommu
->domain_ids
);
1195 g_iommus
[iommu
->seq_id
] = NULL
;
1197 /* if all iommus are freed, free g_iommus */
1198 for (i
= 0; i
< g_num_of_iommus
; i
++) {
1203 if (i
== g_num_of_iommus
)
1206 /* free context mapping */
1207 free_context_table(iommu
);
1210 static struct dmar_domain
*alloc_domain(void)
1212 struct dmar_domain
*domain
;
1214 domain
= alloc_domain_mem();
1218 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
1224 static int iommu_attach_domain(struct dmar_domain
*domain
,
1225 struct intel_iommu
*iommu
)
1228 unsigned long ndomains
;
1229 unsigned long flags
;
1231 ndomains
= cap_ndoms(iommu
->cap
);
1233 spin_lock_irqsave(&iommu
->lock
, flags
);
1235 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1236 if (num
>= ndomains
) {
1237 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1238 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1243 set_bit(num
, iommu
->domain_ids
);
1244 set_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1245 iommu
->domains
[num
] = domain
;
1246 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1251 static void iommu_detach_domain(struct dmar_domain
*domain
,
1252 struct intel_iommu
*iommu
)
1254 unsigned long flags
;
1258 spin_lock_irqsave(&iommu
->lock
, flags
);
1259 ndomains
= cap_ndoms(iommu
->cap
);
1260 num
= find_first_bit(iommu
->domain_ids
, ndomains
);
1261 for (; num
< ndomains
; ) {
1262 if (iommu
->domains
[num
] == domain
) {
1266 num
= find_next_bit(iommu
->domain_ids
,
1267 cap_ndoms(iommu
->cap
), num
+1);
1271 clear_bit(num
, iommu
->domain_ids
);
1272 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1273 iommu
->domains
[num
] = NULL
;
1275 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1278 static struct iova_domain reserved_iova_list
;
1279 static struct lock_class_key reserved_alloc_key
;
1280 static struct lock_class_key reserved_rbtree_key
;
1282 static void dmar_init_reserved_ranges(void)
1284 struct pci_dev
*pdev
= NULL
;
1289 init_iova_domain(&reserved_iova_list
, DMA_32BIT_PFN
);
1291 lockdep_set_class(&reserved_iova_list
.iova_alloc_lock
,
1292 &reserved_alloc_key
);
1293 lockdep_set_class(&reserved_iova_list
.iova_rbtree_lock
,
1294 &reserved_rbtree_key
);
1296 /* IOAPIC ranges shouldn't be accessed by DMA */
1297 iova
= reserve_iova(&reserved_iova_list
, IOVA_PFN(IOAPIC_RANGE_START
),
1298 IOVA_PFN(IOAPIC_RANGE_END
));
1300 printk(KERN_ERR
"Reserve IOAPIC range failed\n");
1302 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1303 for_each_pci_dev(pdev
) {
1306 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1307 r
= &pdev
->resource
[i
];
1308 if (!r
->flags
|| !(r
->flags
& IORESOURCE_MEM
))
1311 addr
&= PHYSICAL_PAGE_MASK
;
1312 size
= r
->end
- addr
;
1313 size
= PAGE_ALIGN(size
);
1314 iova
= reserve_iova(&reserved_iova_list
, IOVA_PFN(addr
),
1315 IOVA_PFN(size
+ addr
) - 1);
1317 printk(KERN_ERR
"Reserve iova failed\n");
1323 static void domain_reserve_special_ranges(struct dmar_domain
*domain
)
1325 copy_reserved_iova(&reserved_iova_list
, &domain
->iovad
);
1328 static inline int guestwidth_to_adjustwidth(int gaw
)
1331 int r
= (gaw
- 12) % 9;
1342 static int domain_init(struct dmar_domain
*domain
, int guest_width
)
1344 struct intel_iommu
*iommu
;
1345 int adjust_width
, agaw
;
1346 unsigned long sagaw
;
1348 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
1349 spin_lock_init(&domain
->mapping_lock
);
1350 spin_lock_init(&domain
->iommu_lock
);
1352 domain_reserve_special_ranges(domain
);
1354 /* calculate AGAW */
1355 iommu
= domain_get_iommu(domain
);
1356 if (guest_width
> cap_mgaw(iommu
->cap
))
1357 guest_width
= cap_mgaw(iommu
->cap
);
1358 domain
->gaw
= guest_width
;
1359 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
1360 agaw
= width_to_agaw(adjust_width
);
1361 sagaw
= cap_sagaw(iommu
->cap
);
1362 if (!test_bit(agaw
, &sagaw
)) {
1363 /* hardware doesn't support it, choose a bigger one */
1364 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw
);
1365 agaw
= find_next_bit(&sagaw
, 5, agaw
);
1369 domain
->agaw
= agaw
;
1370 INIT_LIST_HEAD(&domain
->devices
);
1372 if (ecap_coherent(iommu
->ecap
))
1373 domain
->iommu_coherency
= 1;
1375 domain
->iommu_coherency
= 0;
1377 if (ecap_sc_support(iommu
->ecap
))
1378 domain
->iommu_snooping
= 1;
1380 domain
->iommu_snooping
= 0;
1382 domain
->iommu_count
= 1;
1384 /* always allocate the top pgd */
1385 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page();
1388 __iommu_flush_cache(iommu
, domain
->pgd
, PAGE_SIZE
);
1392 static void domain_exit(struct dmar_domain
*domain
)
1394 struct dmar_drhd_unit
*drhd
;
1395 struct intel_iommu
*iommu
;
1398 /* Domain 0 is reserved, so dont process it */
1402 domain_remove_dev_info(domain
);
1404 put_iova_domain(&domain
->iovad
);
1405 end
= DOMAIN_MAX_ADDR(domain
->gaw
);
1406 end
= end
& (~PAGE_MASK
);
1409 dma_pte_clear_range(domain
, 0, end
);
1411 /* free page tables */
1412 dma_pte_free_pagetable(domain
, 0, end
);
1414 for_each_active_iommu(iommu
, drhd
)
1415 if (test_bit(iommu
->seq_id
, &domain
->iommu_bmp
))
1416 iommu_detach_domain(domain
, iommu
);
1418 free_domain_mem(domain
);
1421 static int domain_context_mapping_one(struct dmar_domain
*domain
, int segment
,
1422 u8 bus
, u8 devfn
, int translation
)
1424 struct context_entry
*context
;
1425 unsigned long flags
;
1426 struct intel_iommu
*iommu
;
1427 struct dma_pte
*pgd
;
1429 unsigned long ndomains
;
1432 struct device_domain_info
*info
= NULL
;
1434 pr_debug("Set context mapping for %02x:%02x.%d\n",
1435 bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
1437 BUG_ON(!domain
->pgd
);
1438 BUG_ON(translation
!= CONTEXT_TT_PASS_THROUGH
&&
1439 translation
!= CONTEXT_TT_MULTI_LEVEL
);
1441 iommu
= device_to_iommu(segment
, bus
, devfn
);
1445 context
= device_to_context_entry(iommu
, bus
, devfn
);
1448 spin_lock_irqsave(&iommu
->lock
, flags
);
1449 if (context_present(context
)) {
1450 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1457 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
1458 domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
) {
1461 /* find an available domain id for this device in iommu */
1462 ndomains
= cap_ndoms(iommu
->cap
);
1463 num
= find_first_bit(iommu
->domain_ids
, ndomains
);
1464 for (; num
< ndomains
; ) {
1465 if (iommu
->domains
[num
] == domain
) {
1470 num
= find_next_bit(iommu
->domain_ids
,
1471 cap_ndoms(iommu
->cap
), num
+1);
1475 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1476 if (num
>= ndomains
) {
1477 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1478 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1482 set_bit(num
, iommu
->domain_ids
);
1483 set_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1484 iommu
->domains
[num
] = domain
;
1488 /* Skip top levels of page tables for
1489 * iommu which has less agaw than default.
1491 for (agaw
= domain
->agaw
; agaw
!= iommu
->agaw
; agaw
--) {
1492 pgd
= phys_to_virt(dma_pte_addr(pgd
));
1493 if (!dma_pte_present(pgd
)) {
1494 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1500 context_set_domain_id(context
, id
);
1502 if (translation
!= CONTEXT_TT_PASS_THROUGH
) {
1503 info
= iommu_support_dev_iotlb(domain
, segment
, bus
, devfn
);
1504 translation
= info
? CONTEXT_TT_DEV_IOTLB
:
1505 CONTEXT_TT_MULTI_LEVEL
;
1508 * In pass through mode, AW must be programmed to indicate the largest
1509 * AGAW value supported by hardware. And ASR is ignored by hardware.
1511 if (unlikely(translation
== CONTEXT_TT_PASS_THROUGH
))
1512 context_set_address_width(context
, iommu
->msagaw
);
1514 context_set_address_root(context
, virt_to_phys(pgd
));
1515 context_set_address_width(context
, iommu
->agaw
);
1518 context_set_translation_type(context
, translation
);
1519 context_set_fault_enable(context
);
1520 context_set_present(context
);
1521 domain_flush_cache(domain
, context
, sizeof(*context
));
1524 * It's a non-present to present mapping. If hardware doesn't cache
1525 * non-present entry we only need to flush the write-buffer. If the
1526 * _does_ cache non-present entries, then it does so in the special
1527 * domain #0, which we have to flush:
1529 if (cap_caching_mode(iommu
->cap
)) {
1530 iommu
->flush
.flush_context(iommu
, 0,
1531 (((u16
)bus
) << 8) | devfn
,
1532 DMA_CCMD_MASK_NOBIT
,
1533 DMA_CCMD_DEVICE_INVL
);
1534 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_DSI_FLUSH
);
1536 iommu_flush_write_buffer(iommu
);
1538 iommu_enable_dev_iotlb(info
);
1539 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1541 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1542 if (!test_and_set_bit(iommu
->seq_id
, &domain
->iommu_bmp
)) {
1543 domain
->iommu_count
++;
1544 domain_update_iommu_cap(domain
);
1546 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1551 domain_context_mapping(struct dmar_domain
*domain
, struct pci_dev
*pdev
,
1555 struct pci_dev
*tmp
, *parent
;
1557 ret
= domain_context_mapping_one(domain
, pci_domain_nr(pdev
->bus
),
1558 pdev
->bus
->number
, pdev
->devfn
,
1563 /* dependent device mapping */
1564 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1567 /* Secondary interface's bus number and devfn 0 */
1568 parent
= pdev
->bus
->self
;
1569 while (parent
!= tmp
) {
1570 ret
= domain_context_mapping_one(domain
,
1571 pci_domain_nr(parent
->bus
),
1572 parent
->bus
->number
,
1573 parent
->devfn
, translation
);
1576 parent
= parent
->bus
->self
;
1578 if (tmp
->is_pcie
) /* this is a PCIE-to-PCI bridge */
1579 return domain_context_mapping_one(domain
,
1580 pci_domain_nr(tmp
->subordinate
),
1581 tmp
->subordinate
->number
, 0,
1583 else /* this is a legacy PCI bridge */
1584 return domain_context_mapping_one(domain
,
1585 pci_domain_nr(tmp
->bus
),
1591 static int domain_context_mapped(struct pci_dev
*pdev
)
1594 struct pci_dev
*tmp
, *parent
;
1595 struct intel_iommu
*iommu
;
1597 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
1602 ret
= device_context_mapped(iommu
, pdev
->bus
->number
, pdev
->devfn
);
1605 /* dependent device mapping */
1606 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1609 /* Secondary interface's bus number and devfn 0 */
1610 parent
= pdev
->bus
->self
;
1611 while (parent
!= tmp
) {
1612 ret
= device_context_mapped(iommu
, parent
->bus
->number
,
1616 parent
= parent
->bus
->self
;
1619 return device_context_mapped(iommu
, tmp
->subordinate
->number
,
1622 return device_context_mapped(iommu
, tmp
->bus
->number
,
1627 domain_page_mapping(struct dmar_domain
*domain
, dma_addr_t iova
,
1628 u64 hpa
, size_t size
, int prot
)
1630 u64 start_pfn
, end_pfn
;
1631 struct dma_pte
*pte
;
1633 int addr_width
= agaw_to_width(domain
->agaw
);
1635 hpa
&= (((u64
)1) << addr_width
) - 1;
1637 if ((prot
& (DMA_PTE_READ
|DMA_PTE_WRITE
)) == 0)
1640 start_pfn
= ((u64
)hpa
) >> VTD_PAGE_SHIFT
;
1641 end_pfn
= (VTD_PAGE_ALIGN(((u64
)hpa
) + size
)) >> VTD_PAGE_SHIFT
;
1643 while (start_pfn
< end_pfn
) {
1644 pte
= addr_to_dma_pte(domain
, iova
+ VTD_PAGE_SIZE
* index
);
1647 /* We don't need lock here, nobody else
1648 * touches the iova range
1650 BUG_ON(dma_pte_addr(pte
));
1651 dma_set_pte_addr(pte
, start_pfn
<< VTD_PAGE_SHIFT
);
1652 dma_set_pte_prot(pte
, prot
);
1653 if (prot
& DMA_PTE_SNP
)
1654 dma_set_pte_snp(pte
);
1655 domain_flush_cache(domain
, pte
, sizeof(*pte
));
1662 static void iommu_detach_dev(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
1667 clear_context_table(iommu
, bus
, devfn
);
1668 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
1669 DMA_CCMD_GLOBAL_INVL
);
1670 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
1673 static void domain_remove_dev_info(struct dmar_domain
*domain
)
1675 struct device_domain_info
*info
;
1676 unsigned long flags
;
1677 struct intel_iommu
*iommu
;
1679 spin_lock_irqsave(&device_domain_lock
, flags
);
1680 while (!list_empty(&domain
->devices
)) {
1681 info
= list_entry(domain
->devices
.next
,
1682 struct device_domain_info
, link
);
1683 list_del(&info
->link
);
1684 list_del(&info
->global
);
1686 info
->dev
->dev
.archdata
.iommu
= NULL
;
1687 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1689 iommu_disable_dev_iotlb(info
);
1690 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
1691 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
1692 free_devinfo_mem(info
);
1694 spin_lock_irqsave(&device_domain_lock
, flags
);
1696 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1701 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1703 static struct dmar_domain
*
1704 find_domain(struct pci_dev
*pdev
)
1706 struct device_domain_info
*info
;
1708 /* No lock here, assumes no domain exit in normal case */
1709 info
= pdev
->dev
.archdata
.iommu
;
1711 return info
->domain
;
1715 /* domain is initialized */
1716 static struct dmar_domain
*get_domain_for_dev(struct pci_dev
*pdev
, int gaw
)
1718 struct dmar_domain
*domain
, *found
= NULL
;
1719 struct intel_iommu
*iommu
;
1720 struct dmar_drhd_unit
*drhd
;
1721 struct device_domain_info
*info
, *tmp
;
1722 struct pci_dev
*dev_tmp
;
1723 unsigned long flags
;
1724 int bus
= 0, devfn
= 0;
1728 domain
= find_domain(pdev
);
1732 segment
= pci_domain_nr(pdev
->bus
);
1734 dev_tmp
= pci_find_upstream_pcie_bridge(pdev
);
1736 if (dev_tmp
->is_pcie
) {
1737 bus
= dev_tmp
->subordinate
->number
;
1740 bus
= dev_tmp
->bus
->number
;
1741 devfn
= dev_tmp
->devfn
;
1743 spin_lock_irqsave(&device_domain_lock
, flags
);
1744 list_for_each_entry(info
, &device_domain_list
, global
) {
1745 if (info
->segment
== segment
&&
1746 info
->bus
== bus
&& info
->devfn
== devfn
) {
1747 found
= info
->domain
;
1751 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1752 /* pcie-pci bridge already has a domain, uses it */
1759 domain
= alloc_domain();
1763 /* Allocate new domain for the device */
1764 drhd
= dmar_find_matched_drhd_unit(pdev
);
1766 printk(KERN_ERR
"IOMMU: can't find DMAR for device %s\n",
1770 iommu
= drhd
->iommu
;
1772 ret
= iommu_attach_domain(domain
, iommu
);
1774 domain_exit(domain
);
1778 if (domain_init(domain
, gaw
)) {
1779 domain_exit(domain
);
1783 /* register pcie-to-pci device */
1785 info
= alloc_devinfo_mem();
1787 domain_exit(domain
);
1790 info
->segment
= segment
;
1792 info
->devfn
= devfn
;
1794 info
->domain
= domain
;
1795 /* This domain is shared by devices under p2p bridge */
1796 domain
->flags
|= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES
;
1798 /* pcie-to-pci bridge already has a domain, uses it */
1800 spin_lock_irqsave(&device_domain_lock
, flags
);
1801 list_for_each_entry(tmp
, &device_domain_list
, global
) {
1802 if (tmp
->segment
== segment
&&
1803 tmp
->bus
== bus
&& tmp
->devfn
== devfn
) {
1804 found
= tmp
->domain
;
1809 free_devinfo_mem(info
);
1810 domain_exit(domain
);
1813 list_add(&info
->link
, &domain
->devices
);
1814 list_add(&info
->global
, &device_domain_list
);
1816 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1820 info
= alloc_devinfo_mem();
1823 info
->segment
= segment
;
1824 info
->bus
= pdev
->bus
->number
;
1825 info
->devfn
= pdev
->devfn
;
1827 info
->domain
= domain
;
1828 spin_lock_irqsave(&device_domain_lock
, flags
);
1829 /* somebody is fast */
1830 found
= find_domain(pdev
);
1831 if (found
!= NULL
) {
1832 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1833 if (found
!= domain
) {
1834 domain_exit(domain
);
1837 free_devinfo_mem(info
);
1840 list_add(&info
->link
, &domain
->devices
);
1841 list_add(&info
->global
, &device_domain_list
);
1842 pdev
->dev
.archdata
.iommu
= info
;
1843 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1846 /* recheck it here, maybe others set it */
1847 return find_domain(pdev
);
1850 static int iommu_identity_mapping
;
1852 static int iommu_domain_identity_map(struct dmar_domain
*domain
,
1853 unsigned long long start
,
1854 unsigned long long end
)
1857 unsigned long long base
;
1859 /* The address might not be aligned */
1860 base
= start
& PAGE_MASK
;
1862 size
= PAGE_ALIGN(size
);
1863 if (!reserve_iova(&domain
->iovad
, IOVA_PFN(base
),
1864 IOVA_PFN(base
+ size
) - 1)) {
1865 printk(KERN_ERR
"IOMMU: reserve iova failed\n");
1869 pr_debug("Mapping reserved region %lx@%llx for domain %d\n",
1870 size
, base
, domain
->id
);
1872 * RMRR range might have overlap with physical memory range,
1875 dma_pte_clear_range(domain
, base
, base
+ size
);
1877 return domain_page_mapping(domain
, base
, base
, size
,
1878 DMA_PTE_READ
|DMA_PTE_WRITE
);
1881 static int iommu_prepare_identity_map(struct pci_dev
*pdev
,
1882 unsigned long long start
,
1883 unsigned long long end
)
1885 struct dmar_domain
*domain
;
1889 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1890 pci_name(pdev
), start
, end
);
1892 if (iommu_identity_mapping
)
1895 /* page table init */
1896 domain
= get_domain_for_dev(pdev
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
1900 ret
= iommu_domain_identity_map(domain
, start
, end
);
1904 /* context entry init */
1905 ret
= domain_context_mapping(domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
1912 domain_exit(domain
);
1916 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit
*rmrr
,
1917 struct pci_dev
*pdev
)
1919 if (pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
)
1921 return iommu_prepare_identity_map(pdev
, rmrr
->base_address
,
1922 rmrr
->end_address
+ 1);
1925 struct iommu_prepare_data
{
1926 struct pci_dev
*pdev
;
1930 static int __init
iommu_prepare_work_fn(unsigned long start_pfn
,
1931 unsigned long end_pfn
, void *datax
)
1933 struct iommu_prepare_data
*data
;
1935 data
= (struct iommu_prepare_data
*)datax
;
1937 data
->ret
= iommu_prepare_identity_map(data
->pdev
,
1938 start_pfn
<<PAGE_SHIFT
, end_pfn
<<PAGE_SHIFT
);
1943 static int __init
iommu_prepare_with_active_regions(struct pci_dev
*pdev
)
1946 struct iommu_prepare_data data
;
1951 for_each_online_node(nid
) {
1952 work_with_active_regions(nid
, iommu_prepare_work_fn
, &data
);
1959 #ifdef CONFIG_DMAR_GFX_WA
1960 static void __init
iommu_prepare_gfx_mapping(void)
1962 struct pci_dev
*pdev
= NULL
;
1965 for_each_pci_dev(pdev
) {
1966 if (pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
||
1967 !IS_GFX_DEVICE(pdev
))
1969 printk(KERN_INFO
"IOMMU: gfx device %s 1-1 mapping\n",
1971 ret
= iommu_prepare_with_active_regions(pdev
);
1973 printk(KERN_ERR
"IOMMU: mapping reserved region failed\n");
1976 #else /* !CONFIG_DMAR_GFX_WA */
1977 static inline void iommu_prepare_gfx_mapping(void)
1983 #ifdef CONFIG_DMAR_FLOPPY_WA
1984 static inline void iommu_prepare_isa(void)
1986 struct pci_dev
*pdev
;
1989 pdev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
1993 printk(KERN_INFO
"IOMMU: Prepare 0-16M unity mapping for LPC\n");
1994 ret
= iommu_prepare_identity_map(pdev
, 0, 16*1024*1024);
1997 printk(KERN_ERR
"IOMMU: Failed to create 0-64M identity map, "
1998 "floppy might not work\n");
2002 static inline void iommu_prepare_isa(void)
2006 #endif /* !CONFIG_DMAR_FLPY_WA */
2008 /* Initialize each context entry as pass through.*/
2009 static int __init
init_context_pass_through(void)
2011 struct pci_dev
*pdev
= NULL
;
2012 struct dmar_domain
*domain
;
2015 for_each_pci_dev(pdev
) {
2016 domain
= get_domain_for_dev(pdev
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
2017 ret
= domain_context_mapping(domain
, pdev
,
2018 CONTEXT_TT_PASS_THROUGH
);
2025 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
);
2026 static int si_domain_init(void)
2028 struct dmar_drhd_unit
*drhd
;
2029 struct intel_iommu
*iommu
;
2032 si_domain
= alloc_domain();
2037 for_each_active_iommu(iommu
, drhd
) {
2038 ret
= iommu_attach_domain(si_domain
, iommu
);
2040 domain_exit(si_domain
);
2045 if (md_domain_init(si_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
2046 domain_exit(si_domain
);
2050 si_domain
->flags
= DOMAIN_FLAG_STATIC_IDENTITY
;
2055 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
2056 struct pci_dev
*pdev
);
2057 static int identity_mapping(struct pci_dev
*pdev
)
2059 struct device_domain_info
*info
;
2061 if (likely(!iommu_identity_mapping
))
2065 list_for_each_entry(info
, &si_domain
->devices
, link
)
2066 if (info
->dev
== pdev
)
2071 static int domain_add_dev_info(struct dmar_domain
*domain
,
2072 struct pci_dev
*pdev
)
2074 struct device_domain_info
*info
;
2075 unsigned long flags
;
2077 info
= alloc_devinfo_mem();
2081 info
->segment
= pci_domain_nr(pdev
->bus
);
2082 info
->bus
= pdev
->bus
->number
;
2083 info
->devfn
= pdev
->devfn
;
2085 info
->domain
= domain
;
2087 spin_lock_irqsave(&device_domain_lock
, flags
);
2088 list_add(&info
->link
, &domain
->devices
);
2089 list_add(&info
->global
, &device_domain_list
);
2090 pdev
->dev
.archdata
.iommu
= info
;
2091 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2096 static int iommu_prepare_static_identity_mapping(void)
2098 struct pci_dev
*pdev
= NULL
;
2101 ret
= si_domain_init();
2105 printk(KERN_INFO
"IOMMU: Setting identity map:\n");
2106 for_each_pci_dev(pdev
) {
2107 ret
= iommu_prepare_with_active_regions(pdev
);
2109 printk(KERN_INFO
"1:1 mapping to one domain failed.\n");
2112 ret
= domain_add_dev_info(si_domain
, pdev
);
2120 int __init
init_dmars(void)
2122 struct dmar_drhd_unit
*drhd
;
2123 struct dmar_rmrr_unit
*rmrr
;
2124 struct pci_dev
*pdev
;
2125 struct intel_iommu
*iommu
;
2127 int pass_through
= 1;
2130 * In case pass through can not be enabled, iommu tries to use identity
2133 if (iommu_pass_through
)
2134 iommu_identity_mapping
= 1;
2139 * initialize and program root entry to not present
2142 for_each_drhd_unit(drhd
) {
2145 * lock not needed as this is only incremented in the single
2146 * threaded kernel __init code path all other access are read
2151 g_iommus
= kcalloc(g_num_of_iommus
, sizeof(struct intel_iommu
*),
2154 printk(KERN_ERR
"Allocating global iommu array failed\n");
2159 deferred_flush
= kzalloc(g_num_of_iommus
*
2160 sizeof(struct deferred_flush_tables
), GFP_KERNEL
);
2161 if (!deferred_flush
) {
2167 for_each_drhd_unit(drhd
) {
2171 iommu
= drhd
->iommu
;
2172 g_iommus
[iommu
->seq_id
] = iommu
;
2174 ret
= iommu_init_domains(iommu
);
2180 * we could share the same root & context tables
2181 * amoung all IOMMU's. Need to Split it later.
2183 ret
= iommu_alloc_root_entry(iommu
);
2185 printk(KERN_ERR
"IOMMU: allocate root entry failed\n");
2188 if (!ecap_pass_through(iommu
->ecap
))
2191 if (iommu_pass_through
)
2192 if (!pass_through
) {
2194 "Pass Through is not supported by hardware.\n");
2195 iommu_pass_through
= 0;
2199 * Start from the sane iommu hardware state.
2201 for_each_drhd_unit(drhd
) {
2205 iommu
= drhd
->iommu
;
2208 * If the queued invalidation is already initialized by us
2209 * (for example, while enabling interrupt-remapping) then
2210 * we got the things already rolling from a sane state.
2216 * Clear any previous faults.
2218 dmar_fault(-1, iommu
);
2220 * Disable queued invalidation if supported and already enabled
2221 * before OS handover.
2223 dmar_disable_qi(iommu
);
2226 for_each_drhd_unit(drhd
) {
2230 iommu
= drhd
->iommu
;
2232 if (dmar_enable_qi(iommu
)) {
2234 * Queued Invalidate not enabled, use Register Based
2237 iommu
->flush
.flush_context
= __iommu_flush_context
;
2238 iommu
->flush
.flush_iotlb
= __iommu_flush_iotlb
;
2239 printk(KERN_INFO
"IOMMU 0x%Lx: using Register based "
2241 (unsigned long long)drhd
->reg_base_addr
);
2243 iommu
->flush
.flush_context
= qi_flush_context
;
2244 iommu
->flush
.flush_iotlb
= qi_flush_iotlb
;
2245 printk(KERN_INFO
"IOMMU 0x%Lx: using Queued "
2247 (unsigned long long)drhd
->reg_base_addr
);
2252 * If pass through is set and enabled, context entries of all pci
2253 * devices are intialized by pass through translation type.
2255 if (iommu_pass_through
) {
2256 ret
= init_context_pass_through();
2258 printk(KERN_ERR
"IOMMU: Pass through init failed.\n");
2259 iommu_pass_through
= 0;
2264 * If pass through is not set or not enabled, setup context entries for
2265 * identity mappings for rmrr, gfx, and isa and may fall back to static
2266 * identity mapping if iommu_identity_mapping is set.
2268 if (!iommu_pass_through
) {
2269 if (iommu_identity_mapping
)
2270 iommu_prepare_static_identity_mapping();
2273 * for each dev attached to rmrr
2275 * locate drhd for dev, alloc domain for dev
2276 * allocate free domain
2277 * allocate page table entries for rmrr
2278 * if context not allocated for bus
2279 * allocate and init context
2280 * set present in root table for this bus
2281 * init context with domain, translation etc
2285 printk(KERN_INFO
"IOMMU: Setting RMRR:\n");
2286 for_each_rmrr_units(rmrr
) {
2287 for (i
= 0; i
< rmrr
->devices_cnt
; i
++) {
2288 pdev
= rmrr
->devices
[i
];
2290 * some BIOS lists non-exist devices in DMAR
2295 ret
= iommu_prepare_rmrr_dev(rmrr
, pdev
);
2298 "IOMMU: mapping reserved region failed\n");
2302 iommu_prepare_gfx_mapping();
2304 iommu_prepare_isa();
2310 * global invalidate context cache
2311 * global invalidate iotlb
2312 * enable translation
2314 for_each_drhd_unit(drhd
) {
2317 iommu
= drhd
->iommu
;
2319 iommu_flush_write_buffer(iommu
);
2321 ret
= dmar_set_interrupt(iommu
);
2325 iommu_set_root_entry(iommu
);
2327 iommu
->flush
.flush_context(iommu
, 0, 0, 0, DMA_CCMD_GLOBAL_INVL
);
2328 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
2329 iommu_disable_protect_mem_regions(iommu
);
2331 ret
= iommu_enable_translation(iommu
);
2338 for_each_drhd_unit(drhd
) {
2341 iommu
= drhd
->iommu
;
2348 static inline u64
aligned_size(u64 host_addr
, size_t size
)
2351 addr
= (host_addr
& (~PAGE_MASK
)) + size
;
2352 return PAGE_ALIGN(addr
);
2356 iommu_alloc_iova(struct dmar_domain
*domain
, size_t size
, u64 end
)
2360 /* Make sure it's in range */
2361 end
= min_t(u64
, DOMAIN_MAX_ADDR(domain
->gaw
), end
);
2362 if (!size
|| (IOVA_START_ADDR
+ size
> end
))
2365 piova
= alloc_iova(&domain
->iovad
,
2366 size
>> PAGE_SHIFT
, IOVA_PFN(end
), 1);
2370 static struct iova
*
2371 __intel_alloc_iova(struct device
*dev
, struct dmar_domain
*domain
,
2372 size_t size
, u64 dma_mask
)
2374 struct pci_dev
*pdev
= to_pci_dev(dev
);
2375 struct iova
*iova
= NULL
;
2377 if (dma_mask
<= DMA_BIT_MASK(32) || dmar_forcedac
)
2378 iova
= iommu_alloc_iova(domain
, size
, dma_mask
);
2381 * First try to allocate an io virtual address in
2382 * DMA_BIT_MASK(32) and if that fails then try allocating
2385 iova
= iommu_alloc_iova(domain
, size
, DMA_BIT_MASK(32));
2387 iova
= iommu_alloc_iova(domain
, size
, dma_mask
);
2391 printk(KERN_ERR
"Allocating iova for %s failed", pci_name(pdev
));
2398 static struct dmar_domain
*
2399 get_valid_domain_for_dev(struct pci_dev
*pdev
)
2401 struct dmar_domain
*domain
;
2404 domain
= get_domain_for_dev(pdev
,
2405 DEFAULT_DOMAIN_ADDRESS_WIDTH
);
2408 "Allocating domain for %s failed", pci_name(pdev
));
2412 /* make sure context mapping is ok */
2413 if (unlikely(!domain_context_mapped(pdev
))) {
2414 ret
= domain_context_mapping(domain
, pdev
,
2415 CONTEXT_TT_MULTI_LEVEL
);
2418 "Domain context map for %s failed",
2427 static int iommu_dummy(struct pci_dev
*pdev
)
2429 return pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
;
2432 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2433 static int iommu_no_mapping(struct pci_dev
*pdev
)
2437 if (!iommu_identity_mapping
)
2438 return iommu_dummy(pdev
);
2440 found
= identity_mapping(pdev
);
2442 if (pdev
->dma_mask
> DMA_BIT_MASK(32))
2446 * 32 bit DMA is removed from si_domain and fall back
2447 * to non-identity mapping.
2449 domain_remove_one_dev_info(si_domain
, pdev
);
2450 printk(KERN_INFO
"32bit %s uses non-identity mapping\n",
2456 * In case of a detached 64 bit DMA device from vm, the device
2457 * is put into si_domain for identity mapping.
2459 if (pdev
->dma_mask
> DMA_BIT_MASK(32)) {
2461 ret
= domain_add_dev_info(si_domain
, pdev
);
2463 printk(KERN_INFO
"64bit %s uses identity mapping\n",
2470 return iommu_dummy(pdev
);
2473 static dma_addr_t
__intel_map_single(struct device
*hwdev
, phys_addr_t paddr
,
2474 size_t size
, int dir
, u64 dma_mask
)
2476 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2477 struct dmar_domain
*domain
;
2478 phys_addr_t start_paddr
;
2482 struct intel_iommu
*iommu
;
2484 BUG_ON(dir
== DMA_NONE
);
2486 if (iommu_no_mapping(pdev
))
2489 domain
= get_valid_domain_for_dev(pdev
);
2493 iommu
= domain_get_iommu(domain
);
2494 size
= aligned_size((u64
)paddr
, size
);
2496 iova
= __intel_alloc_iova(hwdev
, domain
, size
, pdev
->dma_mask
);
2500 start_paddr
= (phys_addr_t
)iova
->pfn_lo
<< PAGE_SHIFT
;
2503 * Check if DMAR supports zero-length reads on write only
2506 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
2507 !cap_zlr(iommu
->cap
))
2508 prot
|= DMA_PTE_READ
;
2509 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
2510 prot
|= DMA_PTE_WRITE
;
2512 * paddr - (paddr + size) might be partial page, we should map the whole
2513 * page. Note: if two part of one page are separately mapped, we
2514 * might have two guest_addr mapping to the same host paddr, but this
2515 * is not a big problem
2517 ret
= domain_page_mapping(domain
, start_paddr
,
2518 ((u64
)paddr
) & PHYSICAL_PAGE_MASK
,
2523 /* it's a non-present to present mapping. Only flush if caching mode */
2524 if (cap_caching_mode(iommu
->cap
))
2525 iommu_flush_iotlb_psi(iommu
, 0, start_paddr
,
2526 size
>> VTD_PAGE_SHIFT
);
2528 iommu_flush_write_buffer(iommu
);
2530 return start_paddr
+ ((u64
)paddr
& (~PAGE_MASK
));
2534 __free_iova(&domain
->iovad
, iova
);
2535 printk(KERN_ERR
"Device %s request: %zx@%llx dir %d --- failed\n",
2536 pci_name(pdev
), size
, (unsigned long long)paddr
, dir
);
2540 static dma_addr_t
intel_map_page(struct device
*dev
, struct page
*page
,
2541 unsigned long offset
, size_t size
,
2542 enum dma_data_direction dir
,
2543 struct dma_attrs
*attrs
)
2545 return __intel_map_single(dev
, page_to_phys(page
) + offset
, size
,
2546 dir
, to_pci_dev(dev
)->dma_mask
);
2549 static void flush_unmaps(void)
2555 /* just flush them all */
2556 for (i
= 0; i
< g_num_of_iommus
; i
++) {
2557 struct intel_iommu
*iommu
= g_iommus
[i
];
2561 if (!deferred_flush
[i
].next
)
2564 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
2565 DMA_TLB_GLOBAL_FLUSH
);
2566 for (j
= 0; j
< deferred_flush
[i
].next
; j
++) {
2568 struct iova
*iova
= deferred_flush
[i
].iova
[j
];
2570 mask
= (iova
->pfn_hi
- iova
->pfn_lo
+ 1) << PAGE_SHIFT
;
2571 mask
= ilog2(mask
>> VTD_PAGE_SHIFT
);
2572 iommu_flush_dev_iotlb(deferred_flush
[i
].domain
[j
],
2573 iova
->pfn_lo
<< PAGE_SHIFT
, mask
);
2574 __free_iova(&deferred_flush
[i
].domain
[j
]->iovad
, iova
);
2576 deferred_flush
[i
].next
= 0;
2582 static void flush_unmaps_timeout(unsigned long data
)
2584 unsigned long flags
;
2586 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2588 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2591 static void add_unmap(struct dmar_domain
*dom
, struct iova
*iova
)
2593 unsigned long flags
;
2595 struct intel_iommu
*iommu
;
2597 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2598 if (list_size
== HIGH_WATER_MARK
)
2601 iommu
= domain_get_iommu(dom
);
2602 iommu_id
= iommu
->seq_id
;
2604 next
= deferred_flush
[iommu_id
].next
;
2605 deferred_flush
[iommu_id
].domain
[next
] = dom
;
2606 deferred_flush
[iommu_id
].iova
[next
] = iova
;
2607 deferred_flush
[iommu_id
].next
++;
2610 mod_timer(&unmap_timer
, jiffies
+ msecs_to_jiffies(10));
2614 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2617 static void intel_unmap_page(struct device
*dev
, dma_addr_t dev_addr
,
2618 size_t size
, enum dma_data_direction dir
,
2619 struct dma_attrs
*attrs
)
2621 struct pci_dev
*pdev
= to_pci_dev(dev
);
2622 struct dmar_domain
*domain
;
2623 unsigned long start_addr
;
2625 struct intel_iommu
*iommu
;
2627 if (iommu_no_mapping(pdev
))
2630 domain
= find_domain(pdev
);
2633 iommu
= domain_get_iommu(domain
);
2635 iova
= find_iova(&domain
->iovad
, IOVA_PFN(dev_addr
));
2639 start_addr
= iova
->pfn_lo
<< PAGE_SHIFT
;
2640 size
= aligned_size((u64
)dev_addr
, size
);
2642 pr_debug("Device %s unmapping: %zx@%llx\n",
2643 pci_name(pdev
), size
, (unsigned long long)start_addr
);
2645 /* clear the whole page */
2646 dma_pte_clear_range(domain
, start_addr
, start_addr
+ size
);
2647 /* free page tables */
2648 dma_pte_free_pagetable(domain
, start_addr
, start_addr
+ size
);
2649 if (intel_iommu_strict
) {
2650 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_addr
,
2651 size
>> VTD_PAGE_SHIFT
);
2653 __free_iova(&domain
->iovad
, iova
);
2655 add_unmap(domain
, iova
);
2657 * queue up the release of the unmap to save the 1/6th of the
2658 * cpu used up by the iotlb flush operation...
2663 static void intel_unmap_single(struct device
*dev
, dma_addr_t dev_addr
, size_t size
,
2666 intel_unmap_page(dev
, dev_addr
, size
, dir
, NULL
);
2669 static void *intel_alloc_coherent(struct device
*hwdev
, size_t size
,
2670 dma_addr_t
*dma_handle
, gfp_t flags
)
2675 size
= PAGE_ALIGN(size
);
2676 order
= get_order(size
);
2677 flags
&= ~(GFP_DMA
| GFP_DMA32
);
2679 vaddr
= (void *)__get_free_pages(flags
, order
);
2682 memset(vaddr
, 0, size
);
2684 *dma_handle
= __intel_map_single(hwdev
, virt_to_bus(vaddr
), size
,
2686 hwdev
->coherent_dma_mask
);
2689 free_pages((unsigned long)vaddr
, order
);
2693 static void intel_free_coherent(struct device
*hwdev
, size_t size
, void *vaddr
,
2694 dma_addr_t dma_handle
)
2698 size
= PAGE_ALIGN(size
);
2699 order
= get_order(size
);
2701 intel_unmap_single(hwdev
, dma_handle
, size
, DMA_BIDIRECTIONAL
);
2702 free_pages((unsigned long)vaddr
, order
);
2705 static void intel_unmap_sg(struct device
*hwdev
, struct scatterlist
*sglist
,
2706 int nelems
, enum dma_data_direction dir
,
2707 struct dma_attrs
*attrs
)
2710 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2711 struct dmar_domain
*domain
;
2712 unsigned long start_addr
;
2716 struct scatterlist
*sg
;
2717 struct intel_iommu
*iommu
;
2719 if (iommu_no_mapping(pdev
))
2722 domain
= find_domain(pdev
);
2725 iommu
= domain_get_iommu(domain
);
2727 iova
= find_iova(&domain
->iovad
, IOVA_PFN(sglist
[0].dma_address
));
2730 for_each_sg(sglist
, sg
, nelems
, i
) {
2731 addr
= page_to_phys(sg_page(sg
)) + sg
->offset
;
2732 size
+= aligned_size((u64
)addr
, sg
->length
);
2735 start_addr
= iova
->pfn_lo
<< PAGE_SHIFT
;
2737 /* clear the whole page */
2738 dma_pte_clear_range(domain
, start_addr
, start_addr
+ size
);
2739 /* free page tables */
2740 dma_pte_free_pagetable(domain
, start_addr
, start_addr
+ size
);
2742 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_addr
,
2743 size
>> VTD_PAGE_SHIFT
);
2746 __free_iova(&domain
->iovad
, iova
);
2749 static int intel_nontranslate_map_sg(struct device
*hddev
,
2750 struct scatterlist
*sglist
, int nelems
, int dir
)
2753 struct scatterlist
*sg
;
2755 for_each_sg(sglist
, sg
, nelems
, i
) {
2756 BUG_ON(!sg_page(sg
));
2757 sg
->dma_address
= page_to_phys(sg_page(sg
)) + sg
->offset
;
2758 sg
->dma_length
= sg
->length
;
2763 static int intel_map_sg(struct device
*hwdev
, struct scatterlist
*sglist
, int nelems
,
2764 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2768 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2769 struct dmar_domain
*domain
;
2773 struct iova
*iova
= NULL
;
2775 struct scatterlist
*sg
;
2776 unsigned long start_addr
;
2777 struct intel_iommu
*iommu
;
2779 BUG_ON(dir
== DMA_NONE
);
2780 if (iommu_no_mapping(pdev
))
2781 return intel_nontranslate_map_sg(hwdev
, sglist
, nelems
, dir
);
2783 domain
= get_valid_domain_for_dev(pdev
);
2787 iommu
= domain_get_iommu(domain
);
2789 for_each_sg(sglist
, sg
, nelems
, i
) {
2790 addr
= page_to_phys(sg_page(sg
)) + sg
->offset
;
2791 size
+= aligned_size((u64
)addr
, sg
->length
);
2794 iova
= __intel_alloc_iova(hwdev
, domain
, size
, pdev
->dma_mask
);
2796 sglist
->dma_length
= 0;
2801 * Check if DMAR supports zero-length reads on write only
2804 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
2805 !cap_zlr(iommu
->cap
))
2806 prot
|= DMA_PTE_READ
;
2807 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
2808 prot
|= DMA_PTE_WRITE
;
2810 start_addr
= iova
->pfn_lo
<< PAGE_SHIFT
;
2812 for_each_sg(sglist
, sg
, nelems
, i
) {
2813 addr
= page_to_phys(sg_page(sg
)) + sg
->offset
;
2814 size
= aligned_size((u64
)addr
, sg
->length
);
2815 ret
= domain_page_mapping(domain
, start_addr
+ offset
,
2816 ((u64
)addr
) & PHYSICAL_PAGE_MASK
,
2819 /* clear the page */
2820 dma_pte_clear_range(domain
, start_addr
,
2821 start_addr
+ offset
);
2822 /* free page tables */
2823 dma_pte_free_pagetable(domain
, start_addr
,
2824 start_addr
+ offset
);
2826 __free_iova(&domain
->iovad
, iova
);
2829 sg
->dma_address
= start_addr
+ offset
+
2830 ((u64
)addr
& (~PAGE_MASK
));
2831 sg
->dma_length
= sg
->length
;
2835 /* it's a non-present to present mapping. Only flush if caching mode */
2836 if (cap_caching_mode(iommu
->cap
))
2837 iommu_flush_iotlb_psi(iommu
, 0, start_addr
,
2838 offset
>> VTD_PAGE_SHIFT
);
2840 iommu_flush_write_buffer(iommu
);
2845 static int intel_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
2850 struct dma_map_ops intel_dma_ops
= {
2851 .alloc_coherent
= intel_alloc_coherent
,
2852 .free_coherent
= intel_free_coherent
,
2853 .map_sg
= intel_map_sg
,
2854 .unmap_sg
= intel_unmap_sg
,
2855 .map_page
= intel_map_page
,
2856 .unmap_page
= intel_unmap_page
,
2857 .mapping_error
= intel_mapping_error
,
2860 static inline int iommu_domain_cache_init(void)
2864 iommu_domain_cache
= kmem_cache_create("iommu_domain",
2865 sizeof(struct dmar_domain
),
2870 if (!iommu_domain_cache
) {
2871 printk(KERN_ERR
"Couldn't create iommu_domain cache\n");
2878 static inline int iommu_devinfo_cache_init(void)
2882 iommu_devinfo_cache
= kmem_cache_create("iommu_devinfo",
2883 sizeof(struct device_domain_info
),
2887 if (!iommu_devinfo_cache
) {
2888 printk(KERN_ERR
"Couldn't create devinfo cache\n");
2895 static inline int iommu_iova_cache_init(void)
2899 iommu_iova_cache
= kmem_cache_create("iommu_iova",
2900 sizeof(struct iova
),
2904 if (!iommu_iova_cache
) {
2905 printk(KERN_ERR
"Couldn't create iova cache\n");
2912 static int __init
iommu_init_mempool(void)
2915 ret
= iommu_iova_cache_init();
2919 ret
= iommu_domain_cache_init();
2923 ret
= iommu_devinfo_cache_init();
2927 kmem_cache_destroy(iommu_domain_cache
);
2929 kmem_cache_destroy(iommu_iova_cache
);
2934 static void __init
iommu_exit_mempool(void)
2936 kmem_cache_destroy(iommu_devinfo_cache
);
2937 kmem_cache_destroy(iommu_domain_cache
);
2938 kmem_cache_destroy(iommu_iova_cache
);
2942 static void __init
init_no_remapping_devices(void)
2944 struct dmar_drhd_unit
*drhd
;
2946 for_each_drhd_unit(drhd
) {
2947 if (!drhd
->include_all
) {
2949 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
2950 if (drhd
->devices
[i
] != NULL
)
2952 /* ignore DMAR unit if no pci devices exist */
2953 if (i
== drhd
->devices_cnt
)
2961 for_each_drhd_unit(drhd
) {
2963 if (drhd
->ignored
|| drhd
->include_all
)
2966 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
2967 if (drhd
->devices
[i
] &&
2968 !IS_GFX_DEVICE(drhd
->devices
[i
]))
2971 if (i
< drhd
->devices_cnt
)
2974 /* bypass IOMMU if it is just for gfx devices */
2976 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
2977 if (!drhd
->devices
[i
])
2979 drhd
->devices
[i
]->dev
.archdata
.iommu
= DUMMY_DEVICE_DOMAIN_INFO
;
2984 #ifdef CONFIG_SUSPEND
2985 static int init_iommu_hw(void)
2987 struct dmar_drhd_unit
*drhd
;
2988 struct intel_iommu
*iommu
= NULL
;
2990 for_each_active_iommu(iommu
, drhd
)
2992 dmar_reenable_qi(iommu
);
2994 for_each_active_iommu(iommu
, drhd
) {
2995 iommu_flush_write_buffer(iommu
);
2997 iommu_set_root_entry(iommu
);
2999 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
3000 DMA_CCMD_GLOBAL_INVL
);
3001 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
3002 DMA_TLB_GLOBAL_FLUSH
);
3003 iommu_disable_protect_mem_regions(iommu
);
3004 iommu_enable_translation(iommu
);
3010 static void iommu_flush_all(void)
3012 struct dmar_drhd_unit
*drhd
;
3013 struct intel_iommu
*iommu
;
3015 for_each_active_iommu(iommu
, drhd
) {
3016 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
3017 DMA_CCMD_GLOBAL_INVL
);
3018 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
3019 DMA_TLB_GLOBAL_FLUSH
);
3023 static int iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
3025 struct dmar_drhd_unit
*drhd
;
3026 struct intel_iommu
*iommu
= NULL
;
3029 for_each_active_iommu(iommu
, drhd
) {
3030 iommu
->iommu_state
= kzalloc(sizeof(u32
) * MAX_SR_DMAR_REGS
,
3032 if (!iommu
->iommu_state
)
3038 for_each_active_iommu(iommu
, drhd
) {
3039 iommu_disable_translation(iommu
);
3041 spin_lock_irqsave(&iommu
->register_lock
, flag
);
3043 iommu
->iommu_state
[SR_DMAR_FECTL_REG
] =
3044 readl(iommu
->reg
+ DMAR_FECTL_REG
);
3045 iommu
->iommu_state
[SR_DMAR_FEDATA_REG
] =
3046 readl(iommu
->reg
+ DMAR_FEDATA_REG
);
3047 iommu
->iommu_state
[SR_DMAR_FEADDR_REG
] =
3048 readl(iommu
->reg
+ DMAR_FEADDR_REG
);
3049 iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
] =
3050 readl(iommu
->reg
+ DMAR_FEUADDR_REG
);
3052 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3057 for_each_active_iommu(iommu
, drhd
)
3058 kfree(iommu
->iommu_state
);
3063 static int iommu_resume(struct sys_device
*dev
)
3065 struct dmar_drhd_unit
*drhd
;
3066 struct intel_iommu
*iommu
= NULL
;
3069 if (init_iommu_hw()) {
3070 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3074 for_each_active_iommu(iommu
, drhd
) {
3076 spin_lock_irqsave(&iommu
->register_lock
, flag
);
3078 writel(iommu
->iommu_state
[SR_DMAR_FECTL_REG
],
3079 iommu
->reg
+ DMAR_FECTL_REG
);
3080 writel(iommu
->iommu_state
[SR_DMAR_FEDATA_REG
],
3081 iommu
->reg
+ DMAR_FEDATA_REG
);
3082 writel(iommu
->iommu_state
[SR_DMAR_FEADDR_REG
],
3083 iommu
->reg
+ DMAR_FEADDR_REG
);
3084 writel(iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
],
3085 iommu
->reg
+ DMAR_FEUADDR_REG
);
3087 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3090 for_each_active_iommu(iommu
, drhd
)
3091 kfree(iommu
->iommu_state
);
3096 static struct sysdev_class iommu_sysclass
= {
3098 .resume
= iommu_resume
,
3099 .suspend
= iommu_suspend
,
3102 static struct sys_device device_iommu
= {
3103 .cls
= &iommu_sysclass
,
3106 static int __init
init_iommu_sysfs(void)
3110 error
= sysdev_class_register(&iommu_sysclass
);
3114 error
= sysdev_register(&device_iommu
);
3116 sysdev_class_unregister(&iommu_sysclass
);
3122 static int __init
init_iommu_sysfs(void)
3126 #endif /* CONFIG_PM */
3128 int __init
intel_iommu_init(void)
3132 if (dmar_table_init())
3135 if (dmar_dev_scope_init())
3139 * Check the need for DMA-remapping initialization now.
3140 * Above initialization will also be used by Interrupt-remapping.
3142 if (no_iommu
|| (swiotlb
&& !iommu_pass_through
) || dmar_disabled
)
3145 iommu_init_mempool();
3146 dmar_init_reserved_ranges();
3148 init_no_remapping_devices();
3152 printk(KERN_ERR
"IOMMU: dmar init failed\n");
3153 put_iova_domain(&reserved_iova_list
);
3154 iommu_exit_mempool();
3158 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3160 init_timer(&unmap_timer
);
3163 if (!iommu_pass_through
) {
3165 "Multi-level page-table translation for DMAR.\n");
3166 dma_ops
= &intel_dma_ops
;
3169 "DMAR: Pass through translation for DMAR.\n");
3173 register_iommu(&intel_iommu_ops
);
3178 static void iommu_detach_dependent_devices(struct intel_iommu
*iommu
,
3179 struct pci_dev
*pdev
)
3181 struct pci_dev
*tmp
, *parent
;
3183 if (!iommu
|| !pdev
)
3186 /* dependent device detach */
3187 tmp
= pci_find_upstream_pcie_bridge(pdev
);
3188 /* Secondary interface's bus number and devfn 0 */
3190 parent
= pdev
->bus
->self
;
3191 while (parent
!= tmp
) {
3192 iommu_detach_dev(iommu
, parent
->bus
->number
,
3194 parent
= parent
->bus
->self
;
3196 if (tmp
->is_pcie
) /* this is a PCIE-to-PCI bridge */
3197 iommu_detach_dev(iommu
,
3198 tmp
->subordinate
->number
, 0);
3199 else /* this is a legacy PCI bridge */
3200 iommu_detach_dev(iommu
, tmp
->bus
->number
,
3205 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
3206 struct pci_dev
*pdev
)
3208 struct device_domain_info
*info
;
3209 struct intel_iommu
*iommu
;
3210 unsigned long flags
;
3212 struct list_head
*entry
, *tmp
;
3214 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3219 spin_lock_irqsave(&device_domain_lock
, flags
);
3220 list_for_each_safe(entry
, tmp
, &domain
->devices
) {
3221 info
= list_entry(entry
, struct device_domain_info
, link
);
3222 /* No need to compare PCI domain; it has to be the same */
3223 if (info
->bus
== pdev
->bus
->number
&&
3224 info
->devfn
== pdev
->devfn
) {
3225 list_del(&info
->link
);
3226 list_del(&info
->global
);
3228 info
->dev
->dev
.archdata
.iommu
= NULL
;
3229 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3231 iommu_disable_dev_iotlb(info
);
3232 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3233 iommu_detach_dependent_devices(iommu
, pdev
);
3234 free_devinfo_mem(info
);
3236 spin_lock_irqsave(&device_domain_lock
, flags
);
3244 /* if there is no other devices under the same iommu
3245 * owned by this domain, clear this iommu in iommu_bmp
3246 * update iommu count and coherency
3248 if (iommu
== device_to_iommu(info
->segment
, info
->bus
,
3254 unsigned long tmp_flags
;
3255 spin_lock_irqsave(&domain
->iommu_lock
, tmp_flags
);
3256 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
3257 domain
->iommu_count
--;
3258 domain_update_iommu_cap(domain
);
3259 spin_unlock_irqrestore(&domain
->iommu_lock
, tmp_flags
);
3262 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3265 static void vm_domain_remove_all_dev_info(struct dmar_domain
*domain
)
3267 struct device_domain_info
*info
;
3268 struct intel_iommu
*iommu
;
3269 unsigned long flags1
, flags2
;
3271 spin_lock_irqsave(&device_domain_lock
, flags1
);
3272 while (!list_empty(&domain
->devices
)) {
3273 info
= list_entry(domain
->devices
.next
,
3274 struct device_domain_info
, link
);
3275 list_del(&info
->link
);
3276 list_del(&info
->global
);
3278 info
->dev
->dev
.archdata
.iommu
= NULL
;
3280 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3282 iommu_disable_dev_iotlb(info
);
3283 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
3284 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3285 iommu_detach_dependent_devices(iommu
, info
->dev
);
3287 /* clear this iommu in iommu_bmp, update iommu count
3290 spin_lock_irqsave(&domain
->iommu_lock
, flags2
);
3291 if (test_and_clear_bit(iommu
->seq_id
,
3292 &domain
->iommu_bmp
)) {
3293 domain
->iommu_count
--;
3294 domain_update_iommu_cap(domain
);
3296 spin_unlock_irqrestore(&domain
->iommu_lock
, flags2
);
3298 free_devinfo_mem(info
);
3299 spin_lock_irqsave(&device_domain_lock
, flags1
);
3301 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3304 /* domain id for virtual machine, it won't be set in context */
3305 static unsigned long vm_domid
;
3307 static int vm_domain_min_agaw(struct dmar_domain
*domain
)
3310 int min_agaw
= domain
->agaw
;
3312 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
3313 for (; i
< g_num_of_iommus
; ) {
3314 if (min_agaw
> g_iommus
[i
]->agaw
)
3315 min_agaw
= g_iommus
[i
]->agaw
;
3317 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
3323 static struct dmar_domain
*iommu_alloc_vm_domain(void)
3325 struct dmar_domain
*domain
;
3327 domain
= alloc_domain_mem();
3331 domain
->id
= vm_domid
++;
3332 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
3333 domain
->flags
= DOMAIN_FLAG_VIRTUAL_MACHINE
;
3338 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
)
3342 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
3343 spin_lock_init(&domain
->mapping_lock
);
3344 spin_lock_init(&domain
->iommu_lock
);
3346 domain_reserve_special_ranges(domain
);
3348 /* calculate AGAW */
3349 domain
->gaw
= guest_width
;
3350 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
3351 domain
->agaw
= width_to_agaw(adjust_width
);
3353 INIT_LIST_HEAD(&domain
->devices
);
3355 domain
->iommu_count
= 0;
3356 domain
->iommu_coherency
= 0;
3357 domain
->max_addr
= 0;
3359 /* always allocate the top pgd */
3360 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page();
3363 domain_flush_cache(domain
, domain
->pgd
, PAGE_SIZE
);
3367 static void iommu_free_vm_domain(struct dmar_domain
*domain
)
3369 unsigned long flags
;
3370 struct dmar_drhd_unit
*drhd
;
3371 struct intel_iommu
*iommu
;
3373 unsigned long ndomains
;
3375 for_each_drhd_unit(drhd
) {
3378 iommu
= drhd
->iommu
;
3380 ndomains
= cap_ndoms(iommu
->cap
);
3381 i
= find_first_bit(iommu
->domain_ids
, ndomains
);
3382 for (; i
< ndomains
; ) {
3383 if (iommu
->domains
[i
] == domain
) {
3384 spin_lock_irqsave(&iommu
->lock
, flags
);
3385 clear_bit(i
, iommu
->domain_ids
);
3386 iommu
->domains
[i
] = NULL
;
3387 spin_unlock_irqrestore(&iommu
->lock
, flags
);
3390 i
= find_next_bit(iommu
->domain_ids
, ndomains
, i
+1);
3395 static void vm_domain_exit(struct dmar_domain
*domain
)
3399 /* Domain 0 is reserved, so dont process it */
3403 vm_domain_remove_all_dev_info(domain
);
3405 put_iova_domain(&domain
->iovad
);
3406 end
= DOMAIN_MAX_ADDR(domain
->gaw
);
3407 end
= end
& (~VTD_PAGE_MASK
);
3410 dma_pte_clear_range(domain
, 0, end
);
3412 /* free page tables */
3413 dma_pte_free_pagetable(domain
, 0, end
);
3415 iommu_free_vm_domain(domain
);
3416 free_domain_mem(domain
);
3419 static int intel_iommu_domain_init(struct iommu_domain
*domain
)
3421 struct dmar_domain
*dmar_domain
;
3423 dmar_domain
= iommu_alloc_vm_domain();
3426 "intel_iommu_domain_init: dmar_domain == NULL\n");
3429 if (md_domain_init(dmar_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
3431 "intel_iommu_domain_init() failed\n");
3432 vm_domain_exit(dmar_domain
);
3435 domain
->priv
= dmar_domain
;
3440 static void intel_iommu_domain_destroy(struct iommu_domain
*domain
)
3442 struct dmar_domain
*dmar_domain
= domain
->priv
;
3444 domain
->priv
= NULL
;
3445 vm_domain_exit(dmar_domain
);
3448 static int intel_iommu_attach_device(struct iommu_domain
*domain
,
3451 struct dmar_domain
*dmar_domain
= domain
->priv
;
3452 struct pci_dev
*pdev
= to_pci_dev(dev
);
3453 struct intel_iommu
*iommu
;
3458 /* normally pdev is not mapped */
3459 if (unlikely(domain_context_mapped(pdev
))) {
3460 struct dmar_domain
*old_domain
;
3462 old_domain
= find_domain(pdev
);
3464 if (dmar_domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
3465 dmar_domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
)
3466 domain_remove_one_dev_info(old_domain
, pdev
);
3468 domain_remove_dev_info(old_domain
);
3472 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3477 /* check if this iommu agaw is sufficient for max mapped address */
3478 addr_width
= agaw_to_width(iommu
->agaw
);
3479 end
= DOMAIN_MAX_ADDR(addr_width
);
3480 end
= end
& VTD_PAGE_MASK
;
3481 if (end
< dmar_domain
->max_addr
) {
3482 printk(KERN_ERR
"%s: iommu agaw (%d) is not "
3483 "sufficient for the mapped address (%llx)\n",
3484 __func__
, iommu
->agaw
, dmar_domain
->max_addr
);
3488 ret
= domain_add_dev_info(dmar_domain
, pdev
);
3492 ret
= domain_context_mapping(dmar_domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
3496 static void intel_iommu_detach_device(struct iommu_domain
*domain
,
3499 struct dmar_domain
*dmar_domain
= domain
->priv
;
3500 struct pci_dev
*pdev
= to_pci_dev(dev
);
3502 domain_remove_one_dev_info(dmar_domain
, pdev
);
3505 static int intel_iommu_map_range(struct iommu_domain
*domain
,
3506 unsigned long iova
, phys_addr_t hpa
,
3507 size_t size
, int iommu_prot
)
3509 struct dmar_domain
*dmar_domain
= domain
->priv
;
3515 if (iommu_prot
& IOMMU_READ
)
3516 prot
|= DMA_PTE_READ
;
3517 if (iommu_prot
& IOMMU_WRITE
)
3518 prot
|= DMA_PTE_WRITE
;
3519 if ((iommu_prot
& IOMMU_CACHE
) && dmar_domain
->iommu_snooping
)
3520 prot
|= DMA_PTE_SNP
;
3522 max_addr
= (iova
& VTD_PAGE_MASK
) + VTD_PAGE_ALIGN(size
);
3523 if (dmar_domain
->max_addr
< max_addr
) {
3527 /* check if minimum agaw is sufficient for mapped address */
3528 min_agaw
= vm_domain_min_agaw(dmar_domain
);
3529 addr_width
= agaw_to_width(min_agaw
);
3530 end
= DOMAIN_MAX_ADDR(addr_width
);
3531 end
= end
& VTD_PAGE_MASK
;
3532 if (end
< max_addr
) {
3533 printk(KERN_ERR
"%s: iommu agaw (%d) is not "
3534 "sufficient for the mapped address (%llx)\n",
3535 __func__
, min_agaw
, max_addr
);
3538 dmar_domain
->max_addr
= max_addr
;
3541 ret
= domain_page_mapping(dmar_domain
, iova
, hpa
, size
, prot
);
3545 static void intel_iommu_unmap_range(struct iommu_domain
*domain
,
3546 unsigned long iova
, size_t size
)
3548 struct dmar_domain
*dmar_domain
= domain
->priv
;
3551 /* The address might not be aligned */
3552 base
= iova
& VTD_PAGE_MASK
;
3553 size
= VTD_PAGE_ALIGN(size
);
3554 dma_pte_clear_range(dmar_domain
, base
, base
+ size
);
3556 if (dmar_domain
->max_addr
== base
+ size
)
3557 dmar_domain
->max_addr
= base
;
3560 static phys_addr_t
intel_iommu_iova_to_phys(struct iommu_domain
*domain
,
3563 struct dmar_domain
*dmar_domain
= domain
->priv
;
3564 struct dma_pte
*pte
;
3567 pte
= addr_to_dma_pte(dmar_domain
, iova
);
3569 phys
= dma_pte_addr(pte
);
3574 static int intel_iommu_domain_has_cap(struct iommu_domain
*domain
,
3577 struct dmar_domain
*dmar_domain
= domain
->priv
;
3579 if (cap
== IOMMU_CAP_CACHE_COHERENCY
)
3580 return dmar_domain
->iommu_snooping
;
3585 static struct iommu_ops intel_iommu_ops
= {
3586 .domain_init
= intel_iommu_domain_init
,
3587 .domain_destroy
= intel_iommu_domain_destroy
,
3588 .attach_dev
= intel_iommu_attach_device
,
3589 .detach_dev
= intel_iommu_detach_device
,
3590 .map
= intel_iommu_map_range
,
3591 .unmap
= intel_iommu_unmap_range
,
3592 .iova_to_phys
= intel_iommu_iova_to_phys
,
3593 .domain_has_cap
= intel_iommu_domain_has_cap
,
3596 static void __devinit
quirk_iommu_rwbf(struct pci_dev
*dev
)
3599 * Mobile 4 Series Chipset neglects to set RWBF capability,
3602 printk(KERN_INFO
"DMAR: Forcing write-buffer flush capability\n");
3606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2a40, quirk_iommu_rwbf
);