arch/arm/mach-omap2/sram34xx.S

   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
   7  * Copyright (C) 2008 Nokia Corporation
   8  *
   9  * Rajendra Nayak <rnayak@ti.com>
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Paul Walmsley
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 #include <linux/linkage.h>
  29 #include <asm/assembler.h>
  30 #include <mach/hardware.h>
  31
  32 #include <mach/io.h>
  33
  34 #include "sdrc.h"
  35 #include "cm.h"
  36
  37         .text
  38
  39 /* r1 parameters */
  40 #define SDRC_NO_UNLOCK_DLL              0x0
  41 #define SDRC_UNLOCK_DLL                 0x1
  42
  43 /* SDRC_DLLA_CTRL bit settings */
  44 #define FIXEDDELAY_SHIFT                24
  45 #define FIXEDDELAY_MASK                 (0xff << FIXEDDELAY_SHIFT)
  46 #define DLLIDLE_MASK                    0x4
  47
  48 /*
  49  * SDRC_DLLA_CTRL default values: TI hardware team indicates that
  50  * FIXEDDELAY should be initialized to 0xf.  This apparently was
  51  * empirically determined during process testing, so no derivation
  52  * was provided.
  53  */
  54 #define FIXEDDELAY_DEFAULT              (0x0f << FIXEDDELAY_SHIFT)
  55
  56 /* SDRC_DLLA_STATUS bit settings */
  57 #define LOCKSTATUS_MASK                 0x4
  58
  59 /* SDRC_POWER bit settings */
  60 #define SRFRONIDLEREQ_MASK              0x40
  61
  62 /* CM_IDLEST1_CORE bit settings */
  63 #define ST_SDRC_MASK                    0x2
  64
  65 /* CM_ICLKEN1_CORE bit settings */
  66 #define EN_SDRC_MASK                    0x2
  67
  68 /* CM_CLKSEL1_PLL bit settings */
  69 #define CORE_DPLL_CLKOUT_DIV_SHIFT      0x1b
  70
  71 /*
  72  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
  73  *
  74  * Params passed in registers:
  75  *  r0 = new M2 divider setting (only 1 and 2 supported right now)
  76  *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  77  *      SDRC rates < 83MHz
  78  *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  79  *      reprogramming the SDRC when switching to a slower MPU speed
  80  *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
  81  *
  82  * Params passed via the stack. The needed params will be copied in SRAM
  83  *  before use by the code in SRAM (SDRAM is not accessible during SDRC
  84  *  reconfiguration):
  85  *  new SDRC_RFR_CTRL_0 register contents
  86  *  new SDRC_ACTIM_CTRL_A_0 register contents
  87  *  new SDRC_ACTIM_CTRL_B_0 register contents
  88  *  new SDRC_MR_0 register value
  89  *  new SDRC_RFR_CTRL_1 register contents
  90  *  new SDRC_ACTIM_CTRL_A_1 register contents
  91  *  new SDRC_ACTIM_CTRL_B_1 register contents
  92  *  new SDRC_MR_1 register value
  93  *
  94  * If the param SDRC_RFR_CTRL_1 is 0, the parameters
  95  *  are not programmed into the SDRC CS1 registers
  96  */
  97 ENTRY(omap3_sram_configure_core_dpll)
  98         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
  99
 100                                         @ pull the extra args off the stack
 101                                         @  and store them in SRAM
 102         ldr     r4, [sp, #52]
 103         str     r4, omap_sdrc_rfr_ctrl_0_val
 104         ldr     r4, [sp, #56]
 105         str     r4, omap_sdrc_actim_ctrl_a_0_val
 106         ldr     r4, [sp, #60]
 107         str     r4, omap_sdrc_actim_ctrl_b_0_val
 108         ldr     r4, [sp, #64]
 109         str     r4, omap_sdrc_mr_0_val
 110         ldr     r4, [sp, #68]
 111         str     r4, omap_sdrc_rfr_ctrl_1_val
 112         cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
 113         beq     skip_cs1_params         @  do not use cs1 params
 114         ldr     r4, [sp, #72]
 115         str     r4, omap_sdrc_actim_ctrl_a_1_val
 116         ldr     r4, [sp, #76]
 117         str     r4, omap_sdrc_actim_ctrl_b_1_val
 118         ldr     r4, [sp, #80]
 119         str     r4, omap_sdrc_mr_1_val
 120 skip_cs1_params:
 121         dsb                             @ flush buffered writes to interconnect
 122
 123         cmp     r3, #1                  @ if increasing SDRC clk rate,
 124         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
 125         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
 126         bleq    unlock_dll
 127         blne    lock_dll
 128         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
 129         bl      configure_core_dpll     @ change the DPLL3 M2 divider
 130         mov     r12, r2
 131         bl      wait_clk_stable         @ wait for SDRC to stabilize
 132         bl      enable_sdrc             @ take SDRC out of idle
 133         cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
 134         bleq    wait_dll_unlock
 135         blne    wait_dll_lock
 136         cmp     r3, #1                  @ if increasing SDRC clk rate,
 137         beq     return_to_sdram         @ return to SDRAM code, otherwise,
 138         bl      configure_sdrc          @ reprogram SDRC regs now
 139 return_to_sdram:
 140         isb                             @ prevent speculative exec past here
 141         mov     r0, #0                  @ return value
 142         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 143 unlock_dll:
 144         ldr     r11, omap3_sdrc_dlla_ctrl
 145         ldr     r12, [r11]
 146         bic     r12, r12, #FIXEDDELAY_MASK
 147         orr     r12, r12, #FIXEDDELAY_DEFAULT
 148         orr     r12, r12, #DLLIDLE_MASK
 149         str     r12, [r11]              @ (no OCP barrier needed)
 150         bx      lr
 151 lock_dll:
 152         ldr     r11, omap3_sdrc_dlla_ctrl
 153         ldr     r12, [r11]
 154         bic     r12, r12, #DLLIDLE_MASK
 155         str     r12, [r11]              @ (no OCP barrier needed)
 156         bx      lr
 157 sdram_in_selfrefresh:
 158         ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
 159         ldr     r12, [r11]              @ read the contents of SDRC_POWER
 160         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
 161         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
 162         str     r12, [r11]              @ write back to SDRC_POWER register
 163         ldr     r12, [r11]              @ posted-write barrier for SDRC
 164 idle_sdrc:
 165         ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
 166         ldr     r12, [r11]
 167         bic     r12, r12, #EN_SDRC_MASK         @ disable iclk bit for SDRC
 168         str     r12, [r11]
 169 wait_sdrc_idle:
 170         ldr     r11, omap3_cm_idlest1_core
 171         ldr     r12, [r11]
 172         and     r12, r12, #ST_SDRC_MASK         @ check for SDRC idle
 173         cmp     r12, #ST_SDRC_MASK
 174         bne     wait_sdrc_idle
 175         bx      lr
 176 configure_core_dpll:
 177         ldr     r11, omap3_cm_clksel1_pll
 178         ldr     r12, [r11]
 179         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
 180         and     r12, r12, r10
 181         orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 182         str     r12, [r11]
 183         ldr     r12, [r11]              @ posted-write barrier for CM
 184         bx      lr
 185 wait_clk_stable:
 186         subs    r12, r12, #1
 187         bne     wait_clk_stable
 188         bx      lr
 189 enable_sdrc:
 190         ldr     r11, omap3_cm_iclken1_core
 191         ldr     r12, [r11]
 192         orr     r12, r12, #EN_SDRC_MASK         @ enable iclk bit for SDRC
 193         str     r12, [r11]
 194 wait_sdrc_idle1:
 195         ldr     r11, omap3_cm_idlest1_core
 196         ldr     r12, [r11]
 197         and     r12, r12, #ST_SDRC_MASK
 198         cmp     r12, #0
 199         bne     wait_sdrc_idle1
 200 restore_sdrc_power_val:
 201         ldr     r11, omap3_sdrc_power
 202         str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
 203         bx      lr
 204 wait_dll_lock:
 205         ldr     r11, omap3_sdrc_dlla_status
 206         ldr     r12, [r11]
 207         and     r12, r12, #LOCKSTATUS_MASK
 208         cmp     r12, #LOCKSTATUS_MASK
 209         bne     wait_dll_lock
 210         bx      lr
 211 wait_dll_unlock:
 212         ldr     r11, omap3_sdrc_dlla_status
 213         ldr     r12, [r11]
 214         and     r12, r12, #LOCKSTATUS_MASK
 215         cmp     r12, #0x0
 216         bne     wait_dll_unlock
 217         bx      lr
 218 configure_sdrc:
 219         ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
 220         ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
 221         str     r12, [r11]                      @ store
 222         ldr     r12, omap_sdrc_actim_ctrl_a_0_val
 223         ldr     r11, omap3_sdrc_actim_ctrl_a_0
 224         str     r12, [r11]
 225         ldr     r12, omap_sdrc_actim_ctrl_b_0_val
 226         ldr     r11, omap3_sdrc_actim_ctrl_b_0
 227         str     r12, [r11]
 228         ldr     r12, omap_sdrc_mr_0_val
 229         ldr     r11, omap3_sdrc_mr_0
 230         str     r12, [r11]
 231         ldr     r12, omap_sdrc_rfr_ctrl_1_val
 232         cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
 233         beq     skip_cs1_prog           @  do not program cs1 params
 234         ldr     r11, omap3_sdrc_rfr_ctrl_1
 235         str     r12, [r11]
 236         ldr     r12, omap_sdrc_actim_ctrl_a_1_val
 237         ldr     r11, omap3_sdrc_actim_ctrl_a_1
 238         str     r12, [r11]
 239         ldr     r12, omap_sdrc_actim_ctrl_b_1_val
 240         ldr     r11, omap3_sdrc_actim_ctrl_b_1
 241         str     r12, [r11]
 242         ldr     r12, omap_sdrc_mr_1_val
 243         ldr     r11, omap3_sdrc_mr_1
 244         str     r12, [r11]
 245 skip_cs1_prog:
 246         ldr     r12, [r11]              @ posted-write barrier for SDRC
 247         bx      lr
 248
 249 omap3_sdrc_power:
 250         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 251 omap3_cm_clksel1_pll:
 252         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 253 omap3_cm_idlest1_core:
 254         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 255 omap3_cm_iclken1_core:
 256         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 257
 258 omap3_sdrc_rfr_ctrl_0:
 259         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 260 omap3_sdrc_rfr_ctrl_1:
 261         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
 262 omap3_sdrc_actim_ctrl_a_0:
 263         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 264 omap3_sdrc_actim_ctrl_a_1:
 265         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
 266 omap3_sdrc_actim_ctrl_b_0:
 267         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 268 omap3_sdrc_actim_ctrl_b_1:
 269         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 270 omap3_sdrc_mr_0:
 271         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
 272 omap3_sdrc_mr_1:
 273         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
 274 omap_sdrc_rfr_ctrl_0_val:
 275         .word 0xDEADBEEF
 276 omap_sdrc_rfr_ctrl_1_val:
 277         .word 0xDEADBEEF
 278 omap_sdrc_actim_ctrl_a_0_val:
 279         .word 0xDEADBEEF
 280 omap_sdrc_actim_ctrl_a_1_val:
 281         .word 0xDEADBEEF
 282 omap_sdrc_actim_ctrl_b_0_val:
 283         .word 0xDEADBEEF
 284 omap_sdrc_actim_ctrl_b_1_val:
 285         .word 0xDEADBEEF
 286 omap_sdrc_mr_0_val:
 287         .word 0xDEADBEEF
 288 omap_sdrc_mr_1_val:
 289         .word 0xDEADBEEF
 290
 291 omap3_sdrc_dlla_status:
 292         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 293 omap3_sdrc_dlla_ctrl:
 294         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 295 core_m2_mask_val:
 296         .word 0x07FFFFFF
 297
 298 ENTRY(omap3_sram_configure_core_dpll_sz)
 299         .word   . - omap3_sram_configure_core_dpll
 300