arch/arm/mach-omap2/cm.h

   1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
   2 #define __ARCH_ASM_MACH_OMAP2_CM_H
   3
   4 /*
   5  * OMAP2/3 Clock Management (CM) register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prcm-common.h"
  18
  19 #define OMAP2420_CM_REGADDR(module, reg)                                \
  20                         IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
  21 #define OMAP2430_CM_REGADDR(module, reg)                                \
  22                         IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
  23 #define OMAP34XX_CM_REGADDR(module, reg)                                \
  24                         IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  25
  26 /*
  27  * Architecture-specific global CM registers
  28  * Use cm_{read,write}_reg() with these registers.
  29  * These registers appear once per CM module.
  30  */
  31
  32 #define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
  33 #define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
  34 #define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
  35
  36 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
  37 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  38
  39 /*
  40  * Module specific CM registers from CM_BASE + domain offset
  41  * Use cm_{read,write}_mod_reg() with these registers.
  42  * These register offsets generally appear in more than one PRCM submodule.
  43  */
  44
  45 /* Common between 24xx and 34xx */
  46
  47 #define CM_FCLKEN                                       0x0000
  48 #define CM_FCLKEN1                                      CM_FCLKEN
  49 #define CM_CLKEN                                        CM_FCLKEN
  50 #define CM_ICLKEN                                       0x0010
  51 #define CM_ICLKEN1                                      CM_ICLKEN
  52 #define CM_ICLKEN2                                      0x0014
  53 #define CM_ICLKEN3                                      0x0018
  54 #define CM_IDLEST                                       0x0020
  55 #define CM_IDLEST1                                      CM_IDLEST
  56 #define CM_IDLEST2                                      0x0024
  57 #define CM_AUTOIDLE                                     0x0030
  58 #define CM_AUTOIDLE1                                    CM_AUTOIDLE
  59 #define CM_AUTOIDLE2                                    0x0034
  60 #define CM_AUTOIDLE3                                    0x0038
  61 #define CM_CLKSEL                                       0x0040
  62 #define CM_CLKSEL1                                      CM_CLKSEL
  63 #define CM_CLKSEL2                                      0x0044
  64 #define CM_CLKSTCTRL                                    0x0048
  65
  66
  67 /* Architecture-specific registers */
  68
  69 #define OMAP24XX_CM_FCLKEN2                             0x0004
  70 #define OMAP24XX_CM_ICLKEN4                             0x001c
  71 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
  72
  73 #define OMAP2430_CM_IDLEST3                             0x0028
  74
  75 #define OMAP3430_CM_CLKEN_PLL                           0x0004
  76 #define OMAP3430ES2_CM_CLKEN2                           0x0004
  77 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
  78 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
  79 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
  80 #define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
  81 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
  82 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
  83 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
  84 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
  85 #define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
  86 #define OMAP3430_CM_CLKSTST                             0x004c
  87 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
  88 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
  89 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
  90 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
  91
  92
  93 /* Clock management domain register get/set */
  94
  95 #ifndef __ASSEMBLER__
  96
  97 extern u32 cm_read_mod_reg(s16 module, u16 idx);
  98 extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
  99 extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 100
 101 static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 102 {
 103         return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 104 }
 105
 106 static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 107 {
 108         return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 109 }
 110
 111 #endif
 112
 113 /* CM register bits shared between 24XX and 3430 */
 114
 115 /* CM_CLKSEL_GFX */
 116 #define OMAP_CLKSEL_GFX_SHIFT                           0
 117 #define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
 118
 119 /* CM_ICLKEN_GFX */
 120 #define OMAP_EN_GFX_SHIFT                               0
 121 #define OMAP_EN_GFX                                     (1 << 0)
 122
 123 /* CM_IDLEST_GFX */
 124 #define OMAP_ST_GFX                                     (1 << 0)
 125
 126
 127 #endif