arch/arm/mach-mx2/devices.c

   1 /*
   2  * Author: MontaVista Software, Inc.
   3  *       <source@mvista.com>
   4  *
   5  * Based on the OMAP devices.c
   6  *
   7  * 2005 (c) MontaVista Software, Inc. This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  *
  12  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27  * MA 02110-1301, USA.
  28  */
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/gpio.h>
  34
  35 #include <mach/irqs.h>
  36 #include <mach/hardware.h>
  37 #include <mach/common.h>
  38 #include <mach/mmc.h>
  39
  40 #include "devices.h"
  41
  42 /*
  43  * Resource definition for the MXC IrDA
  44  */
  45 static struct resource mxc_irda_resources[] = {
  46         [0] = {
  47                 .start   = UART3_BASE_ADDR,
  48                 .end     = UART3_BASE_ADDR + SZ_4K - 1,
  49                 .flags   = IORESOURCE_MEM,
  50         },
  51         [1] = {
  52                 .start   = MXC_INT_UART3,
  53                 .end     = MXC_INT_UART3,
  54                 .flags   = IORESOURCE_IRQ,
  55         },
  56 };
  57
  58 /* Platform Data for MXC IrDA */
  59 struct platform_device mxc_irda_device = {
  60         .name = "mxc_irda",
  61         .id = 0,
  62         .num_resources = ARRAY_SIZE(mxc_irda_resources),
  63         .resource = mxc_irda_resources,
  64 };
  65
  66 /*
  67  * General Purpose Timer
  68  * - i.MX1: 2 timer (slighly different register handling)
  69  * - i.MX21: 3 timer
  70  * - i.MX27: 6 timer
  71  */
  72
  73 /* We use gpt0 as system timer, so do not add a device for this one */
  74
  75 static struct resource timer1_resources[] = {
  76         [0] = {
  77                 .start  = GPT2_BASE_ADDR,
  78                 .end    = GPT2_BASE_ADDR + 0x17,
  79                 .flags  = IORESOURCE_MEM
  80         },
  81         [1] = {
  82                 .start   = MXC_INT_GPT2,
  83                 .end     = MXC_INT_GPT2,
  84                 .flags   = IORESOURCE_IRQ,
  85         }
  86 };
  87
  88 struct platform_device mxc_gpt1 = {
  89         .name = "imx_gpt",
  90         .id = 1,
  91         .num_resources = ARRAY_SIZE(timer1_resources),
  92         .resource = timer1_resources
  93 };
  94
  95 static struct resource timer2_resources[] = {
  96         [0] = {
  97                 .start  = GPT3_BASE_ADDR,
  98                 .end    = GPT3_BASE_ADDR + 0x17,
  99                 .flags  = IORESOURCE_MEM
 100         },
 101         [1] = {
 102                 .start   = MXC_INT_GPT3,
 103                 .end     = MXC_INT_GPT3,
 104                 .flags   = IORESOURCE_IRQ,
 105         }
 106 };
 107
 108 struct platform_device mxc_gpt2 = {
 109         .name = "imx_gpt",
 110         .id = 2,
 111         .num_resources = ARRAY_SIZE(timer2_resources),
 112         .resource = timer2_resources
 113 };
 114
 115 #ifdef CONFIG_MACH_MX27
 116 static struct resource timer3_resources[] = {
 117         [0] = {
 118                 .start  = GPT4_BASE_ADDR,
 119                 .end    = GPT4_BASE_ADDR + 0x17,
 120                 .flags  = IORESOURCE_MEM
 121         },
 122         [1] = {
 123                 .start   = MXC_INT_GPT4,
 124                 .end     = MXC_INT_GPT4,
 125                 .flags   = IORESOURCE_IRQ,
 126         }
 127 };
 128
 129 struct platform_device mxc_gpt3 = {
 130         .name = "imx_gpt",
 131         .id = 3,
 132         .num_resources = ARRAY_SIZE(timer3_resources),
 133         .resource = timer3_resources
 134 };
 135
 136 static struct resource timer4_resources[] = {
 137         [0] = {
 138                 .start  = GPT5_BASE_ADDR,
 139                 .end    = GPT5_BASE_ADDR + 0x17,
 140                 .flags  = IORESOURCE_MEM
 141         },
 142         [1] = {
 143                 .start   = MXC_INT_GPT5,
 144                 .end     = MXC_INT_GPT5,
 145                 .flags   = IORESOURCE_IRQ,
 146         }
 147 };
 148
 149 struct platform_device mxc_gpt4 = {
 150         .name = "imx_gpt",
 151         .id = 4,
 152         .num_resources = ARRAY_SIZE(timer4_resources),
 153         .resource = timer4_resources
 154 };
 155
 156 static struct resource timer5_resources[] = {
 157         [0] = {
 158                 .start  = GPT6_BASE_ADDR,
 159                 .end    = GPT6_BASE_ADDR + 0x17,
 160                 .flags  = IORESOURCE_MEM
 161         },
 162         [1] = {
 163                 .start   = MXC_INT_GPT6,
 164                 .end     = MXC_INT_GPT6,
 165                 .flags   = IORESOURCE_IRQ,
 166         }
 167 };
 168
 169 struct platform_device mxc_gpt5 = {
 170         .name = "imx_gpt",
 171         .id = 5,
 172         .num_resources = ARRAY_SIZE(timer5_resources),
 173         .resource = timer5_resources
 174 };
 175 #endif
 176
 177 /*
 178  * Watchdog:
 179  * - i.MX1
 180  * - i.MX21
 181  * - i.MX27
 182  */
 183 static struct resource mxc_wdt_resources[] = {
 184         {
 185                 .start  = WDOG_BASE_ADDR,
 186                 .end    = WDOG_BASE_ADDR + 0x30,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189 };
 190
 191 struct platform_device mxc_wdt = {
 192         .name = "mxc_wdt",
 193         .id = 0,
 194         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
 195         .resource = mxc_wdt_resources,
 196 };
 197
 198 static struct resource mxc_w1_master_resources[] = {
 199         {
 200                 .start = OWIRE_BASE_ADDR,
 201                 .end   = OWIRE_BASE_ADDR + SZ_4K - 1,
 202                 .flags = IORESOURCE_MEM,
 203         },
 204 };
 205
 206 struct platform_device mxc_w1_master_device = {
 207         .name = "mxc_w1",
 208         .id = 0,
 209         .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
 210         .resource = mxc_w1_master_resources,
 211 };
 212
 213 static struct resource mxc_nand_resources[] = {
 214         {
 215                 .start  = NFC_BASE_ADDR,
 216                 .end    = NFC_BASE_ADDR + 0xfff,
 217                 .flags  = IORESOURCE_MEM
 218         }, {
 219                 .start  = MXC_INT_NANDFC,
 220                 .end    = MXC_INT_NANDFC,
 221                 .flags  = IORESOURCE_IRQ
 222         },
 223 };
 224
 225 struct platform_device mxc_nand_device = {
 226         .name = "mxc_nand",
 227         .id = 0,
 228         .num_resources = ARRAY_SIZE(mxc_nand_resources),
 229         .resource = mxc_nand_resources,
 230 };
 231
 232 /*
 233  * lcdc:
 234  * - i.MX1: the basic controller
 235  * - i.MX21: to be checked
 236  * - i.MX27: like i.MX1, with slightly variations
 237  */
 238 static struct resource mxc_fb[] = {
 239         {
 240                 .start = LCDC_BASE_ADDR,
 241                 .end   = LCDC_BASE_ADDR + 0xFFF,
 242                 .flags = IORESOURCE_MEM,
 243         },
 244         {
 245                 .start = MXC_INT_LCDC,
 246                 .end   = MXC_INT_LCDC,
 247                 .flags = IORESOURCE_IRQ,
 248         }
 249 };
 250
 251 /* mxc lcd driver */
 252 struct platform_device mxc_fb_device = {
 253         .name = "imx-fb",
 254         .id = 0,
 255         .num_resources = ARRAY_SIZE(mxc_fb),
 256         .resource = mxc_fb,
 257         .dev = {
 258                 .coherent_dma_mask = 0xFFFFFFFF,
 259         },
 260 };
 261
 262 #ifdef CONFIG_MACH_MX27
 263 static struct resource mxc_fec_resources[] = {
 264         {
 265                 .start  = FEC_BASE_ADDR,
 266                 .end    = FEC_BASE_ADDR + 0xfff,
 267                 .flags  = IORESOURCE_MEM
 268         }, {
 269                 .start  = MXC_INT_FEC,
 270                 .end    = MXC_INT_FEC,
 271                 .flags  = IORESOURCE_IRQ
 272         },
 273 };
 274
 275 struct platform_device mxc_fec_device = {
 276         .name = "fec",
 277         .id = 0,
 278         .num_resources = ARRAY_SIZE(mxc_fec_resources),
 279         .resource = mxc_fec_resources,
 280 };
 281 #endif
 282
 283 static struct resource mxc_i2c_1_resources[] = {
 284         [0] = {
 285                 .start  = I2C_BASE_ADDR,
 286                 .end    = I2C_BASE_ADDR + 0x0fff,
 287                 .flags  = IORESOURCE_MEM
 288         },
 289         [1] = {
 290                 .start  = MXC_INT_I2C,
 291                 .end    = MXC_INT_I2C,
 292                 .flags  = IORESOURCE_IRQ
 293         }
 294 };
 295
 296 struct platform_device mxc_i2c_device0 = {
 297         .name = "imx-i2c",
 298         .id = 0,
 299         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
 300         .resource = mxc_i2c_1_resources
 301 };
 302
 303 #ifdef CONFIG_MACH_MX27
 304 static struct resource mxc_i2c_2_resources[] = {
 305         [0] = {
 306                 .start  = I2C2_BASE_ADDR,
 307                 .end    = I2C2_BASE_ADDR + 0x0fff,
 308                 .flags  = IORESOURCE_MEM
 309         },
 310         [1] = {
 311                 .start  = MXC_INT_I2C2,
 312                 .end    = MXC_INT_I2C2,
 313                 .flags  = IORESOURCE_IRQ
 314         }
 315 };
 316
 317 struct platform_device mxc_i2c_device1 = {
 318         .name = "imx-i2c",
 319         .id = 1,
 320         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
 321         .resource = mxc_i2c_2_resources
 322 };
 323 #endif
 324
 325 static struct resource mxc_pwm_resources[] = {
 326         [0] = {
 327                 .start  = PWM_BASE_ADDR,
 328                 .end    = PWM_BASE_ADDR + 0x0fff,
 329                 .flags  = IORESOURCE_MEM
 330         },
 331         [1] = {
 332                 .start   = MXC_INT_PWM,
 333                 .end     = MXC_INT_PWM,
 334                 .flags   = IORESOURCE_IRQ,
 335         }
 336 };
 337
 338 struct platform_device mxc_pwm_device = {
 339         .name = "mxc_pwm",
 340         .id = 0,
 341         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
 342         .resource = mxc_pwm_resources
 343 };
 344
 345 /*
 346  * Resource definition for the MXC SDHC
 347  */
 348 static struct resource mxc_sdhc1_resources[] = {
 349         [0] = {
 350                         .start = SDHC1_BASE_ADDR,
 351                         .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
 352                         .flags = IORESOURCE_MEM,
 353                         },
 354         [1] = {
 355                         .start = MXC_INT_SDHC1,
 356                         .end   = MXC_INT_SDHC1,
 357                         .flags = IORESOURCE_IRQ,
 358                         },
 359         [2] = {
 360                         .start  = DMA_REQ_SDHC1,
 361                         .end    = DMA_REQ_SDHC1,
 362                         .flags  = IORESOURCE_DMA
 363                 },
 364 };
 365
 366 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
 367
 368 struct platform_device mxc_sdhc_device0 = {
 369        .name           = "mxc-mmc",
 370        .id             = 0,
 371        .dev            = {
 372                .dma_mask = &mxc_sdhc1_dmamask,
 373                .coherent_dma_mask = 0xffffffff,
 374        },
 375        .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
 376        .resource       = mxc_sdhc1_resources,
 377 };
 378
 379 static struct resource mxc_sdhc2_resources[] = {
 380         [0] = {
 381                         .start = SDHC2_BASE_ADDR,
 382                         .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
 383                         .flags = IORESOURCE_MEM,
 384                         },
 385         [1] = {
 386                         .start = MXC_INT_SDHC2,
 387                         .end   = MXC_INT_SDHC2,
 388                         .flags = IORESOURCE_IRQ,
 389                         },
 390         [2] = {
 391                         .start  = DMA_REQ_SDHC2,
 392                         .end    = DMA_REQ_SDHC2,
 393                         .flags  = IORESOURCE_DMA
 394                 },
 395 };
 396
 397 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
 398
 399 struct platform_device mxc_sdhc_device1 = {
 400        .name           = "mxc-mmc",
 401        .id             = 1,
 402        .dev            = {
 403                .dma_mask = &mxc_sdhc2_dmamask,
 404                .coherent_dma_mask = 0xffffffff,
 405        },
 406        .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
 407        .resource       = mxc_sdhc2_resources,
 408 };
 409
 410 /* GPIO port description */
 411 static struct mxc_gpio_port imx_gpio_ports[] = {
 412         [0] = {
 413                 .chip.label = "gpio-0",
 414                 .irq = MXC_INT_GPIO,
 415                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
 416                 .virtual_irq_start = MXC_GPIO_IRQ_START,
 417         },
 418         [1] = {
 419                 .chip.label = "gpio-1",
 420                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
 421                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
 422         },
 423         [2] = {
 424                 .chip.label = "gpio-2",
 425                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
 426                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
 427         },
 428         [3] = {
 429                 .chip.label = "gpio-3",
 430                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
 431                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
 432         },
 433         [4] = {
 434                 .chip.label = "gpio-4",
 435                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
 436                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
 437         },
 438         [5] = {
 439                 .chip.label = "gpio-5",
 440                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
 441                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
 442         }
 443 };
 444
 445 int __init mxc_register_gpios(void)
 446 {
 447         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 448 }