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sparc64: Set IRQF_DISABLED on LDC channel IRQs.
[linux-2.6/verdex.git] / arch / arm / mach-integrator / integrator_cp.c
blob4ac04055c2eadaefbffc0bdfa28372ab8d718ec9
1 /*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19 #include <linux/amba/bus.h>
20 #include <linux/amba/kmi.h>
21 #include <linux/amba/clcd.h>
22 #include <linux/io.h>
23
24 #include <asm/clkdev.h>
25 #include <mach/clkdev.h>
26 #include <mach/hardware.h>
27 #include <asm/irq.h>
28 #include <asm/setup.h>
29 #include <asm/mach-types.h>
30 #include <asm/hardware/icst525.h>
31
32 #include <mach/cm.h>
33 #include <mach/lm.h>
34
35 #include <asm/mach/arch.h>
36 #include <asm/mach/flash.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/mmc.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/time.h>
41
42 #include "common.h"
43
44 #define INTCP_PA_MMC_BASE 0x1c000000
45 #define INTCP_PA_AACI_BASE 0x1d000000
46
47 #define INTCP_PA_FLASH_BASE 0x24000000
48 #define INTCP_FLASH_SIZE SZ_32M
49
50 #define INTCP_PA_CLCD_BASE 0xc0000000
51
52 #define INTCP_VA_CIC_BASE 0xf1000040
53 #define INTCP_VA_PIC_BASE 0xf1400000
54 #define INTCP_VA_SIC_BASE 0xfca00000
55
56 #define INTCP_PA_ETH_BASE 0xc8000000
57 #define INTCP_ETH_SIZE 0x10
58
59 #define INTCP_VA_CTRL_BASE 0xfcb00000
60 #define INTCP_FLASHPROG 0x04
61 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
62 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
63
64 /*
65 * Logical Physical
66 * f1000000 10000000 Core module registers
67 * f1100000 11000000 System controller registers
68 * f1200000 12000000 EBI registers
69 * f1300000 13000000 Counter/Timer
70 * f1400000 14000000 Interrupt controller
71 * f1600000 16000000 UART 0
72 * f1700000 17000000 UART 1
73 * f1a00000 1a000000 Debug LEDs
74 * f1b00000 1b000000 GPIO
75 */
76
77 static struct map_desc intcp_io_desc[] __initdata = {
78 {
79 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
80 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
81 .length = SZ_4K,
82 .type = MT_DEVICE
83 }, {
84 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
85 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE
88 }, {
89 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
90 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
91 .length = SZ_4K,
92 .type = MT_DEVICE
93 }, {
94 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = 0xfca00000,
125 .pfn = __phys_to_pfn(0xca000000),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
129 .virtual = 0xfcb00000,
130 .pfn = __phys_to_pfn(0xcb000000),
131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }
134 };
135
136 static void __init intcp_map_io(void)
137 {
138 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
139 }
140
141 #define cic_writel __raw_writel
142 #define cic_readl __raw_readl
143 #define pic_writel __raw_writel
144 #define pic_readl __raw_readl
145 #define sic_writel __raw_writel
146 #define sic_readl __raw_readl
147
148 static void cic_mask_irq(unsigned int irq)
149 {
150 irq -= IRQ_CIC_START;
151 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
152 }
153
154 static void cic_unmask_irq(unsigned int irq)
155 {
156 irq -= IRQ_CIC_START;
157 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
158 }
159
160 static struct irq_chip cic_chip = {
161 .name = "CIC",
162 .ack = cic_mask_irq,
163 .mask = cic_mask_irq,
164 .unmask = cic_unmask_irq,
165 };
166
167 static void pic_mask_irq(unsigned int irq)
168 {
169 irq -= IRQ_PIC_START;
170 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
171 }
172
173 static void pic_unmask_irq(unsigned int irq)
174 {
175 irq -= IRQ_PIC_START;
176 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
177 }
178
179 static struct irq_chip pic_chip = {
180 .name = "PIC",
181 .ack = pic_mask_irq,
182 .mask = pic_mask_irq,
183 .unmask = pic_unmask_irq,
184 };
185
186 static void sic_mask_irq(unsigned int irq)
187 {
188 irq -= IRQ_SIC_START;
189 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
190 }
191
192 static void sic_unmask_irq(unsigned int irq)
193 {
194 irq -= IRQ_SIC_START;
195 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
196 }
197
198 static struct irq_chip sic_chip = {
199 .name = "SIC",
200 .ack = sic_mask_irq,
201 .mask = sic_mask_irq,
202 .unmask = sic_unmask_irq,
203 };
204
205 static void
206 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
207 {
208 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
209
210 if (status == 0) {
211 do_bad_IRQ(irq, desc);
212 return;
213 }
214
215 do {
216 irq = ffs(status) - 1;
217 status &= ~(1 << irq);
218
219 irq += IRQ_SIC_START;
220
221 generic_handle_irq(irq);
222 } while (status);
223 }
224
225 static void __init intcp_init_irq(void)
226 {
227 unsigned int i;
228
229 /*
230 * Disable all interrupt sources
231 */
232 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
233 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
234
235 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
236 if (i == 11)
237 i = 22;
238 if (i == 29)
239 break;
240 set_irq_chip(i, &pic_chip);
241 set_irq_handler(i, handle_level_irq);
242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243 }
244
245 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
246 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
247
248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
249 set_irq_chip(i, &cic_chip);
250 set_irq_handler(i, handle_level_irq);
251 set_irq_flags(i, IRQF_VALID);
252 }
253
254 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
255 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
256
257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
258 set_irq_chip(i, &sic_chip);
259 set_irq_handler(i, handle_level_irq);
260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
261 }
262
263 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
264 }
265
266 /*
267 * Clock handling
268 */
269 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
270 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
271
272 static const struct icst525_params cp_auxvco_params = {
273 .ref = 24000,
274 .vco_max = 320000,
275 .vd_min = 8,
276 .vd_max = 263,
277 .rd_min = 3,
278 .rd_max = 65,
279 };
280
281 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
282 {
283 u32 val;
284
285 val = readl(CM_AUXOSC) & ~0x7ffff;
286 val |= vco.v | (vco.r << 9) | (vco.s << 16);
287
288 writel(0xa05f, CM_LOCK);
289 writel(val, CM_AUXOSC);
290 writel(0, CM_LOCK);
291 }
292
293 static struct clk cp_auxclk = {
294 .params = &cp_auxvco_params,
295 .setvco = cp_auxvco_set,
296 };
297
298 static struct clk_lookup cp_lookups[] = {
299 { /* CLCD */
300 .dev_id = "mb:c0",
301 .clk = &cp_auxclk,
302 },
303 };
304
305 /*
306 * Flash handling.
307 */
308 static int intcp_flash_init(void)
309 {
310 u32 val;
311
312 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
313 val |= CINTEGRATOR_FLASHPROG_FLWREN;
314 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
315
316 return 0;
317 }
318
319 static void intcp_flash_exit(void)
320 {
321 u32 val;
322
323 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
324 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
325 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
326 }
327
328 static void intcp_flash_set_vpp(int on)
329 {
330 u32 val;
331
332 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
333 if (on)
334 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
335 else
336 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
337 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
338 }
339
340 static struct flash_platform_data intcp_flash_data = {
341 .map_name = "cfi_probe",
342 .width = 4,
343 .init = intcp_flash_init,
344 .exit = intcp_flash_exit,
345 .set_vpp = intcp_flash_set_vpp,
346 };
347
348 static struct resource intcp_flash_resource = {
349 .start = INTCP_PA_FLASH_BASE,
350 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
351 .flags = IORESOURCE_MEM,
352 };
353
354 static struct platform_device intcp_flash_device = {
355 .name = "armflash",
356 .id = 0,
357 .dev = {
358 .platform_data = &intcp_flash_data,
359 },
360 .num_resources = 1,
361 .resource = &intcp_flash_resource,
362 };
363
364 static struct resource smc91x_resources[] = {
365 [0] = {
366 .start = INTCP_PA_ETH_BASE,
367 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = IRQ_CP_ETHINT,
372 .end = IRQ_CP_ETHINT,
373 .flags = IORESOURCE_IRQ,
374 },
375 };
376
377 static struct platform_device smc91x_device = {
378 .name = "smc91x",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(smc91x_resources),
381 .resource = smc91x_resources,
382 };
383
384 static struct platform_device *intcp_devs[] __initdata = {
385 &intcp_flash_device,
386 &smc91x_device,
387 };
388
389 /*
390 * It seems that the card insertion interrupt remains active after
391 * we've acknowledged it. We therefore ignore the interrupt, and
392 * rely on reading it from the SIC. This also means that we must
393 * clear the latched interrupt.
394 */
395 static unsigned int mmc_status(struct device *dev)
396 {
397 unsigned int status = readl(0xfca00004);
398 writel(8, 0xfcb00008);
399
400 return status & 8;
401 }
402
403 static struct mmc_platform_data mmc_data = {
404 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
405 .status = mmc_status,
406 };
407
408 static struct amba_device mmc_device = {
409 .dev = {
410 .init_name = "mb:1c",
411 .platform_data = &mmc_data,
412 },
413 .res = {
414 .start = INTCP_PA_MMC_BASE,
415 .end = INTCP_PA_MMC_BASE + SZ_4K - 1,
416 .flags = IORESOURCE_MEM,
417 },
418 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
419 .periphid = 0,
420 };
421
422 static struct amba_device aaci_device = {
423 .dev = {
424 .init_name = "mb:1d",
425 },
426 .res = {
427 .start = INTCP_PA_AACI_BASE,
428 .end = INTCP_PA_AACI_BASE + SZ_4K - 1,
429 .flags = IORESOURCE_MEM,
430 },
431 .irq = { IRQ_CP_AACIINT, NO_IRQ },
432 .periphid = 0,
433 };
434
435
436 /*
437 * CLCD support
438 */
439 static struct clcd_panel vga = {
440 .mode = {
441 .name = "VGA",
442 .refresh = 60,
443 .xres = 640,
444 .yres = 480,
445 .pixclock = 39721,
446 .left_margin = 40,
447 .right_margin = 24,
448 .upper_margin = 32,
449 .lower_margin = 11,
450 .hsync_len = 96,
451 .vsync_len = 2,
452 .sync = 0,
453 .vmode = FB_VMODE_NONINTERLACED,
454 },
455 .width = -1,
456 .height = -1,
457 .tim2 = TIM2_BCD | TIM2_IPC,
458 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
459 .bpp = 16,
460 .grayscale = 0,
461 };
462
463 /*
464 * Ensure VGA is selected.
465 */
466 static void cp_clcd_enable(struct clcd_fb *fb)
467 {
468 u32 val;
469
470 if (fb->fb.var.bits_per_pixel <= 8)
471 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
472 else if (fb->fb.var.bits_per_pixel <= 16)
473 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
474 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
475 | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
476 else
477 val = 0; /* no idea for this, don't trust the docs */
478
479 cm_control(CM_CTRL_LCDMUXSEL_MASK|
480 CM_CTRL_LCDEN0|
481 CM_CTRL_LCDEN1|
482 CM_CTRL_STATIC1|
483 CM_CTRL_STATIC2|
484 CM_CTRL_STATIC|
485 CM_CTRL_n24BITEN, val);
486 }
487
488 static unsigned long framesize = SZ_1M;
489
490 static int cp_clcd_setup(struct clcd_fb *fb)
491 {
492 dma_addr_t dma;
493
494 fb->panel = &vga;
495
496 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
497 &dma, GFP_KERNEL);
498 if (!fb->fb.screen_base) {
499 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
500 return -ENOMEM;
501 }
502
503 fb->fb.fix.smem_start = dma;
504 fb->fb.fix.smem_len = framesize;
505
506 return 0;
507 }
508
509 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
510 {
511 return dma_mmap_writecombine(&fb->dev->dev, vma,
512 fb->fb.screen_base,
513 fb->fb.fix.smem_start,
514 fb->fb.fix.smem_len);
515 }
516
517 static void cp_clcd_remove(struct clcd_fb *fb)
518 {
519 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
520 fb->fb.screen_base, fb->fb.fix.smem_start);
521 }
522
523 static struct clcd_board clcd_data = {
524 .name = "Integrator/CP",
525 .check = clcdfb_check,
526 .decode = clcdfb_decode,
527 .enable = cp_clcd_enable,
528 .setup = cp_clcd_setup,
529 .mmap = cp_clcd_mmap,
530 .remove = cp_clcd_remove,
531 };
532
533 static struct amba_device clcd_device = {
534 .dev = {
535 .init_name = "mb:c0",
536 .coherent_dma_mask = ~0,
537 .platform_data = &clcd_data,
538 },
539 .res = {
540 .start = INTCP_PA_CLCD_BASE,
541 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
542 .flags = IORESOURCE_MEM,
543 },
544 .dma_mask = ~0,
545 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
546 .periphid = 0,
547 };
548
549 static struct amba_device *amba_devs[] __initdata = {
550 &mmc_device,
551 &aaci_device,
552 &clcd_device,
553 };
554
555 static void __init intcp_init(void)
556 {
557 int i;
558
559 for (i = 0; i < ARRAY_SIZE(cp_lookups); i++)
560 clkdev_add(&cp_lookups[i]);
561
562 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
563
564 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
565 struct amba_device *d = amba_devs[i];
566 amba_device_register(d, &iomem_resource);
567 }
568 }
569
570 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
571
572 static void __init intcp_timer_init(void)
573 {
574 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
575 }
576
577 static struct sys_timer cp_timer = {
578 .init = intcp_timer_init,
579 .offset = integrator_gettimeoffset,
580 };
581
582 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
583 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
584 .phys_io = 0x16000000,
585 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
586 .boot_params = 0x00000100,
587 .map_io = intcp_map_io,
588 .init_irq = intcp_init_irq,
589 .timer = &cp_timer,
590 .init_machine = intcp_init,
591 MACHINE_END
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