arch/arm/plat-mxc/gpio.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/irq.h>
  25 #include <linux/gpio.h>
  26 #include <mach/hardware.h>
  27 #include <asm-generic/bug.h>
  28
  29 static struct mxc_gpio_port *mxc_gpio_ports;
  30 static int gpio_table_size;
  31
  32 /* Note: This driver assumes 32 GPIOs are handled in one register */
  33
  34 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
  35 {
  36         __raw_writel(1 << index, port->base + GPIO_ISR);
  37 }
  38
  39 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
  40                                 int enable)
  41 {
  42         u32 l;
  43
  44         l = __raw_readl(port->base + GPIO_IMR);
  45         l = (l & (~(1 << index))) | (!!enable << index);
  46         __raw_writel(l, port->base + GPIO_IMR);
  47 }
  48
  49 static void gpio_ack_irq(u32 irq)
  50 {
  51         u32 gpio = irq_to_gpio(irq);
  52         _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
  53 }
  54
  55 static void gpio_mask_irq(u32 irq)
  56 {
  57         u32 gpio = irq_to_gpio(irq);
  58         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
  59 }
  60
  61 static void gpio_unmask_irq(u32 irq)
  62 {
  63         u32 gpio = irq_to_gpio(irq);
  64         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
  65 }
  66
  67 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
  68
  69 static int gpio_set_irq_type(u32 irq, u32 type)
  70 {
  71         u32 gpio = irq_to_gpio(irq);
  72         struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
  73         u32 bit, val;
  74         int edge;
  75         void __iomem *reg = port->base;
  76
  77         port->both_edges &= ~(1 << (gpio & 31));
  78         switch (type) {
  79         case IRQ_TYPE_EDGE_RISING:
  80                 edge = GPIO_INT_RISE_EDGE;
  81                 break;
  82         case IRQ_TYPE_EDGE_FALLING:
  83                 edge = GPIO_INT_FALL_EDGE;
  84                 break;
  85         case IRQ_TYPE_EDGE_BOTH:
  86                 val = mxc_gpio_get(&port->chip, gpio & 31);
  87                 if (val) {
  88                         edge = GPIO_INT_LOW_LEV;
  89                         pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
  90                 } else {
  91                         edge = GPIO_INT_HIGH_LEV;
  92                         pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
  93                 }
  94                 port->both_edges |= 1 << (gpio & 31);
  95                 break;
  96         case IRQ_TYPE_LEVEL_LOW:
  97                 edge = GPIO_INT_LOW_LEV;
  98                 break;
  99         case IRQ_TYPE_LEVEL_HIGH:
 100                 edge = GPIO_INT_HIGH_LEV;
 101                 break;
 102         default:
 103                 return -EINVAL;
 104         }
 105
 106         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 107         bit = gpio & 0xf;
 108         val = __raw_readl(reg) & ~(0x3 << (bit << 1));
 109         __raw_writel(val | (edge << (bit << 1)), reg);
 110         _clear_gpio_irqstatus(port, gpio & 0x1f);
 111
 112         return 0;
 113 }
 114
 115 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 116 {
 117         void __iomem *reg = port->base;
 118         u32 bit, val;
 119         int edge;
 120
 121         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 122         bit = gpio & 0xf;
 123         val = __raw_readl(reg);
 124         edge = (val >> (bit << 1)) & 3;
 125         val &= ~(0x3 << (bit << 1));
 126         switch (edge) {
 127         case GPIO_INT_HIGH_LEV:
 128                 edge = GPIO_INT_LOW_LEV;
 129                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 130                 break;
 131         case GPIO_INT_LOW_LEV:
 132                 edge = GPIO_INT_HIGH_LEV;
 133                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 134                 break;
 135         default:
 136                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 137                        gpio, edge);
 138                 return;
 139         }
 140         __raw_writel(val | (edge << (bit << 1)), reg);
 141 }
 142
 143 /* handle n interrupts in one status register */
 144 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 145 {
 146         u32 gpio_irq_no;
 147
 148         gpio_irq_no = port->virtual_irq_start;
 149         for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
 150                 u32 gpio = irq_to_gpio(gpio_irq_no);
 151
 152                 if ((irq_stat & 1) == 0)
 153                         continue;
 154
 155                 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
 156
 157                 if (port->both_edges & (1 << (gpio & 31)))
 158                         mxc_flip_edge(port, gpio);
 159
 160                 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
 161                                 &irq_desc[gpio_irq_no]);
 162         }
 163 }
 164
 165 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 166 /* MX1 and MX3 has one interrupt *per* gpio port */
 167 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 168 {
 169         u32 irq_stat;
 170         struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
 171
 172         irq_stat = __raw_readl(port->base + GPIO_ISR) &
 173                         __raw_readl(port->base + GPIO_IMR);
 174
 175         mxc_gpio_irq_handler(port, irq_stat);
 176 }
 177 #endif
 178
 179 #ifdef CONFIG_ARCH_MX2
 180 /* MX2 has one interrupt *for all* gpio ports */
 181 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 182 {
 183         int i;
 184         u32 irq_msk, irq_stat;
 185         struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
 186
 187         /* walk through all interrupt status registers */
 188         for (i = 0; i < gpio_table_size; i++) {
 189                 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
 190                 if (!irq_msk)
 191                         continue;
 192
 193                 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
 194                 if (irq_stat)
 195                         mxc_gpio_irq_handler(&port[i], irq_stat);
 196         }
 197 }
 198 #endif
 199
 200 static struct irq_chip gpio_irq_chip = {
 201         .ack = gpio_ack_irq,
 202         .mask = gpio_mask_irq,
 203         .unmask = gpio_unmask_irq,
 204         .set_type = gpio_set_irq_type,
 205 };
 206
 207 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 208                                 int dir)
 209 {
 210         struct mxc_gpio_port *port =
 211                 container_of(chip, struct mxc_gpio_port, chip);
 212         u32 l;
 213
 214         l = __raw_readl(port->base + GPIO_GDIR);
 215         if (dir)
 216                 l |= 1 << offset;
 217         else
 218                 l &= ~(1 << offset);
 219         __raw_writel(l, port->base + GPIO_GDIR);
 220 }
 221
 222 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 223 {
 224         struct mxc_gpio_port *port =
 225                 container_of(chip, struct mxc_gpio_port, chip);
 226         void __iomem *reg = port->base + GPIO_DR;
 227         u32 l;
 228
 229         l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
 230         __raw_writel(l, reg);
 231 }
 232
 233 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
 234 {
 235         struct mxc_gpio_port *port =
 236                 container_of(chip, struct mxc_gpio_port, chip);
 237
 238         return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
 239 }
 240
 241 static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 242 {
 243         _set_gpio_direction(chip, offset, 0);
 244         return 0;
 245 }
 246
 247 static int mxc_gpio_direction_output(struct gpio_chip *chip,
 248                                      unsigned offset, int value)
 249 {
 250         mxc_gpio_set(chip, offset, value);
 251         _set_gpio_direction(chip, offset, 1);
 252         return 0;
 253 }
 254
 255 int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 256 {
 257         int i, j;
 258
 259         /* save for local usage */
 260         mxc_gpio_ports = port;
 261         gpio_table_size = cnt;
 262
 263         printk(KERN_INFO "MXC GPIO hardware\n");
 264
 265         for (i = 0; i < cnt; i++) {
 266                 /* disable the interrupt and clear the status */
 267                 __raw_writel(0, port[i].base + GPIO_IMR);
 268                 __raw_writel(~0, port[i].base + GPIO_ISR);
 269                 for (j = port[i].virtual_irq_start;
 270                         j < port[i].virtual_irq_start + 32; j++) {
 271                         set_irq_chip(j, &gpio_irq_chip);
 272                         set_irq_handler(j, handle_edge_irq);
 273                         set_irq_flags(j, IRQF_VALID);
 274                 }
 275
 276                 /* register gpio chip */
 277                 port[i].chip.direction_input = mxc_gpio_direction_input;
 278                 port[i].chip.direction_output = mxc_gpio_direction_output;
 279                 port[i].chip.get = mxc_gpio_get;
 280                 port[i].chip.set = mxc_gpio_set;
 281                 port[i].chip.base = i * 32;
 282                 port[i].chip.ngpio = 32;
 283
 284                 /* its a serious configuration bug when it fails */
 285                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 286
 287 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 288                 /* setup one handler for each entry */
 289                 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
 290                 set_irq_data(port[i].irq, &port[i]);
 291 #endif
 292         }
 293
 294 #ifdef CONFIG_ARCH_MX2
 295         /* setup one handler for all GPIO interrupts */
 296         set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
 297         set_irq_data(port[0].irq, port);
 298 #endif
 299         return 0;
 300 }