2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 static int __init
parse_noapic(char *str
)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic
);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list
{
121 struct irq_pin_list
*next
;
124 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
126 struct irq_pin_list
*pin
;
129 node
= cpu_to_node(cpu
);
131 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
132 printk(KERN_DEBUG
" alloc irq_2_pin on cpu %d node %d\n", cpu
, node
);
138 struct irq_pin_list
*irq_2_pin
;
139 cpumask_var_t domain
;
140 cpumask_var_t old_domain
;
141 unsigned move_cleanup_count
;
143 u8 move_in_progress
: 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending
: 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx
[] = {
153 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
155 [0] = { .vector
= IRQ0_VECTOR
, },
156 [1] = { .vector
= IRQ1_VECTOR
, },
157 [2] = { .vector
= IRQ2_VECTOR
, },
158 [3] = { .vector
= IRQ3_VECTOR
, },
159 [4] = { .vector
= IRQ4_VECTOR
, },
160 [5] = { .vector
= IRQ5_VECTOR
, },
161 [6] = { .vector
= IRQ6_VECTOR
, },
162 [7] = { .vector
= IRQ7_VECTOR
, },
163 [8] = { .vector
= IRQ8_VECTOR
, },
164 [9] = { .vector
= IRQ9_VECTOR
, },
165 [10] = { .vector
= IRQ10_VECTOR
, },
166 [11] = { .vector
= IRQ11_VECTOR
, },
167 [12] = { .vector
= IRQ12_VECTOR
, },
168 [13] = { .vector
= IRQ13_VECTOR
, },
169 [14] = { .vector
= IRQ14_VECTOR
, },
170 [15] = { .vector
= IRQ15_VECTOR
, },
173 void __init
arch_early_irq_init(void)
176 struct irq_desc
*desc
;
181 count
= ARRAY_SIZE(irq_cfgx
);
183 for (i
= 0; i
< count
; i
++) {
184 desc
= irq_to_desc(i
);
185 desc
->chip_data
= &cfg
[i
];
186 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
187 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
188 if (i
< NR_IRQS_LEGACY
)
189 cpumask_setall(cfg
[i
].domain
);
193 #ifdef CONFIG_SPARSE_IRQ
194 static struct irq_cfg
*irq_cfg(unsigned int irq
)
196 struct irq_cfg
*cfg
= NULL
;
197 struct irq_desc
*desc
;
199 desc
= irq_to_desc(irq
);
201 cfg
= desc
->chip_data
;
206 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
211 node
= cpu_to_node(cpu
);
213 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
215 /* FIXME: needs alloc_cpumask_var_node() */
216 if (!alloc_cpumask_var(&cfg
->domain
, GFP_ATOMIC
)) {
219 } else if (!alloc_cpumask_var(&cfg
->old_domain
, GFP_ATOMIC
)) {
220 free_cpumask_var(cfg
->domain
);
224 cpumask_clear(cfg
->domain
);
225 cpumask_clear(cfg
->old_domain
);
228 printk(KERN_DEBUG
" alloc irq_cfg on cpu %d node %d\n", cpu
, node
);
233 void arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
237 cfg
= desc
->chip_data
;
239 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
240 if (!desc
->chip_data
) {
241 printk(KERN_ERR
"can not alloc irq_cfg\n");
247 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
250 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
252 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
254 cfg
->irq_2_pin
= NULL
;
255 old_entry
= old_cfg
->irq_2_pin
;
259 entry
= get_one_free_irq_2_pin(cpu
);
263 entry
->apic
= old_entry
->apic
;
264 entry
->pin
= old_entry
->pin
;
267 old_entry
= old_entry
->next
;
269 entry
= get_one_free_irq_2_pin(cpu
);
277 /* still use the old one */
280 entry
->apic
= old_entry
->apic
;
281 entry
->pin
= old_entry
->pin
;
284 old_entry
= old_entry
->next
;
288 cfg
->irq_2_pin
= head
;
291 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
293 struct irq_pin_list
*entry
, *next
;
295 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
298 entry
= old_cfg
->irq_2_pin
;
305 old_cfg
->irq_2_pin
= NULL
;
308 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
309 struct irq_desc
*desc
, int cpu
)
312 struct irq_cfg
*old_cfg
;
314 cfg
= get_one_free_irq_cfg(cpu
);
319 desc
->chip_data
= cfg
;
321 old_cfg
= old_desc
->chip_data
;
323 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
325 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
328 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
333 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
335 struct irq_cfg
*old_cfg
, *cfg
;
337 old_cfg
= old_desc
->chip_data
;
338 cfg
= desc
->chip_data
;
344 free_irq_2_pin(old_cfg
, cfg
);
345 free_irq_cfg(old_cfg
);
346 old_desc
->chip_data
= NULL
;
351 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
353 struct irq_cfg
*cfg
= desc
->chip_data
;
355 if (!cfg
->move_in_progress
) {
356 /* it means that domain is not changed */
357 if (!cpumask_intersects(&desc
->affinity
, mask
))
358 cfg
->move_desc_pending
= 1;
364 static struct irq_cfg
*irq_cfg(unsigned int irq
)
366 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
371 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
373 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
380 unsigned int unused
[3];
384 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
386 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
387 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
390 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
392 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
393 writel(reg
, &io_apic
->index
);
394 return readl(&io_apic
->data
);
397 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
399 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
400 writel(reg
, &io_apic
->index
);
401 writel(value
, &io_apic
->data
);
405 * Re-write a value: to be used for read-modify-write
406 * cycles where the read already set up the index register.
408 * Older SiS APIC requires we rewrite the index register
410 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
412 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
415 writel(reg
, &io_apic
->index
);
416 writel(value
, &io_apic
->data
);
419 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
421 struct irq_pin_list
*entry
;
424 spin_lock_irqsave(&ioapic_lock
, flags
);
425 entry
= cfg
->irq_2_pin
;
433 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
434 /* Is the remote IRR bit set? */
435 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
436 spin_unlock_irqrestore(&ioapic_lock
, flags
);
443 spin_unlock_irqrestore(&ioapic_lock
, flags
);
449 struct { u32 w1
, w2
; };
450 struct IO_APIC_route_entry entry
;
453 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
455 union entry_union eu
;
457 spin_lock_irqsave(&ioapic_lock
, flags
);
458 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
459 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
460 spin_unlock_irqrestore(&ioapic_lock
, flags
);
465 * When we write a new IO APIC routing entry, we need to write the high
466 * word first! If the mask bit in the low word is clear, we will enable
467 * the interrupt, and we need to make sure the entry is fully populated
468 * before that happens.
471 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
473 union entry_union eu
;
475 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
476 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
479 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
482 spin_lock_irqsave(&ioapic_lock
, flags
);
483 __ioapic_write_entry(apic
, pin
, e
);
484 spin_unlock_irqrestore(&ioapic_lock
, flags
);
488 * When we mask an IO APIC routing entry, we need to write the low
489 * word first, in order to set the mask bit before we change the
492 static void ioapic_mask_entry(int apic
, int pin
)
495 union entry_union eu
= { .entry
.mask
= 1 };
497 spin_lock_irqsave(&ioapic_lock
, flags
);
498 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
499 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
500 spin_unlock_irqrestore(&ioapic_lock
, flags
);
504 static void send_cleanup_vector(struct irq_cfg
*cfg
)
506 cpumask_var_t cleanup_mask
;
508 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
510 cfg
->move_cleanup_count
= 0;
511 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
512 cfg
->move_cleanup_count
++;
513 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
514 send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
516 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
517 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
518 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
519 free_cpumask_var(cleanup_mask
);
521 cfg
->move_in_progress
= 0;
524 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
527 struct irq_pin_list
*entry
;
528 u8 vector
= cfg
->vector
;
530 entry
= cfg
->irq_2_pin
;
539 #ifdef CONFIG_INTR_REMAP
541 * With interrupt-remapping, destination information comes
542 * from interrupt-remapping table entry.
544 if (!irq_remapped(irq
))
545 io_apic_write(apic
, 0x11 + pin
*2, dest
);
547 io_apic_write(apic
, 0x11 + pin
*2, dest
);
549 reg
= io_apic_read(apic
, 0x10 + pin
*2);
550 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
552 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
560 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
563 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
564 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
567 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
572 if (!cpumask_intersects(mask
, cpu_online_mask
))
576 cfg
= desc
->chip_data
;
577 if (assign_irq_vector(irq
, cfg
, mask
))
580 cpumask_and(&desc
->affinity
, cfg
->domain
, mask
);
581 set_extra_move_desc(desc
, mask
);
582 return cpu_mask_to_apicid_and(&desc
->affinity
, cpu_online_mask
);
586 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
594 cfg
= desc
->chip_data
;
596 spin_lock_irqsave(&ioapic_lock
, flags
);
597 dest
= set_desc_affinity(desc
, mask
);
598 if (dest
!= BAD_APICID
) {
599 /* Only the high 8 bits are valid. */
600 dest
= SET_APIC_LOGICAL_ID(dest
);
601 __target_IO_APIC_irq(irq
, dest
, cfg
);
603 spin_unlock_irqrestore(&ioapic_lock
, flags
);
607 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
609 struct irq_desc
*desc
;
611 desc
= irq_to_desc(irq
);
613 set_ioapic_affinity_irq_desc(desc
, mask
);
615 #endif /* CONFIG_SMP */
618 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
619 * shared ISA-space IRQs, so we have to support them. We are super
620 * fast in the common case, and fast for shared ISA-space IRQs.
622 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
624 struct irq_pin_list
*entry
;
626 entry
= cfg
->irq_2_pin
;
628 entry
= get_one_free_irq_2_pin(cpu
);
630 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
634 cfg
->irq_2_pin
= entry
;
640 while (entry
->next
) {
641 /* not again, please */
642 if (entry
->apic
== apic
&& entry
->pin
== pin
)
648 entry
->next
= get_one_free_irq_2_pin(cpu
);
655 * Reroute an IRQ to a different pin.
657 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
658 int oldapic
, int oldpin
,
659 int newapic
, int newpin
)
661 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
665 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
666 entry
->apic
= newapic
;
669 /* every one is different, right? */
675 /* why? call replace before add? */
677 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
680 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
681 int mask_and
, int mask_or
,
682 void (*final
)(struct irq_pin_list
*entry
))
685 struct irq_pin_list
*entry
;
687 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
690 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
693 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
699 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
701 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
705 void io_apic_sync(struct irq_pin_list
*entry
)
708 * Synchronize the IO-APIC and the CPU by doing
709 * a dummy read from the IO-APIC
711 struct io_apic __iomem
*io_apic
;
712 io_apic
= io_apic_base(entry
->apic
);
713 readl(&io_apic
->data
);
716 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
718 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
720 #else /* CONFIG_X86_32 */
721 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
723 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
726 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
728 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
729 IO_APIC_REDIR_MASKED
, NULL
);
732 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
734 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
735 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
737 #endif /* CONFIG_X86_32 */
739 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
741 struct irq_cfg
*cfg
= desc
->chip_data
;
746 spin_lock_irqsave(&ioapic_lock
, flags
);
747 __mask_IO_APIC_irq(cfg
);
748 spin_unlock_irqrestore(&ioapic_lock
, flags
);
751 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
753 struct irq_cfg
*cfg
= desc
->chip_data
;
756 spin_lock_irqsave(&ioapic_lock
, flags
);
757 __unmask_IO_APIC_irq(cfg
);
758 spin_unlock_irqrestore(&ioapic_lock
, flags
);
761 static void mask_IO_APIC_irq(unsigned int irq
)
763 struct irq_desc
*desc
= irq_to_desc(irq
);
765 mask_IO_APIC_irq_desc(desc
);
767 static void unmask_IO_APIC_irq(unsigned int irq
)
769 struct irq_desc
*desc
= irq_to_desc(irq
);
771 unmask_IO_APIC_irq_desc(desc
);
774 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
776 struct IO_APIC_route_entry entry
;
778 /* Check delivery_mode to be sure we're not clearing an SMI pin */
779 entry
= ioapic_read_entry(apic
, pin
);
780 if (entry
.delivery_mode
== dest_SMI
)
783 * Disable it in the IO-APIC irq-routing table:
785 ioapic_mask_entry(apic
, pin
);
788 static void clear_IO_APIC (void)
792 for (apic
= 0; apic
< nr_ioapics
; apic
++)
793 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
794 clear_IO_APIC_pin(apic
, pin
);
797 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
798 void send_IPI_self(int vector
)
805 apic_wait_icr_idle();
806 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
808 * Send the IPI. The write to APIC_ICR fires this off.
810 apic_write(APIC_ICR
, cfg
);
812 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
816 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
817 * specific CPU-side IRQs.
821 static int pirq_entries
[MAX_PIRQS
];
822 static int pirqs_enabled
;
824 static int __init
ioapic_pirq_setup(char *str
)
827 int ints
[MAX_PIRQS
+1];
829 get_options(str
, ARRAY_SIZE(ints
), ints
);
831 for (i
= 0; i
< MAX_PIRQS
; i
++)
832 pirq_entries
[i
] = -1;
835 apic_printk(APIC_VERBOSE
, KERN_INFO
836 "PIRQ redirection, working around broken MP-BIOS.\n");
838 if (ints
[0] < MAX_PIRQS
)
841 for (i
= 0; i
< max
; i
++) {
842 apic_printk(APIC_VERBOSE
, KERN_DEBUG
843 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
845 * PIRQs are mapped upside down, usually.
847 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
852 __setup("pirq=", ioapic_pirq_setup
);
853 #endif /* CONFIG_X86_32 */
855 #ifdef CONFIG_INTR_REMAP
856 /* I/O APIC RTE contents at the OS boot up */
857 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
860 * Saves and masks all the unmasked IO-APIC RTE's
862 int save_mask_IO_APIC_setup(void)
864 union IO_APIC_reg_01 reg_01
;
869 * The number of IO-APIC IRQ registers (== #pins):
871 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
872 spin_lock_irqsave(&ioapic_lock
, flags
);
873 reg_01
.raw
= io_apic_read(apic
, 1);
874 spin_unlock_irqrestore(&ioapic_lock
, flags
);
875 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
878 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
879 early_ioapic_entries
[apic
] =
880 kzalloc(sizeof(struct IO_APIC_route_entry
) *
881 nr_ioapic_registers
[apic
], GFP_KERNEL
);
882 if (!early_ioapic_entries
[apic
])
886 for (apic
= 0; apic
< nr_ioapics
; apic
++)
887 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
888 struct IO_APIC_route_entry entry
;
890 entry
= early_ioapic_entries
[apic
][pin
] =
891 ioapic_read_entry(apic
, pin
);
894 ioapic_write_entry(apic
, pin
, entry
);
902 kfree(early_ioapic_entries
[apic
--]);
903 memset(early_ioapic_entries
, 0,
904 ARRAY_SIZE(early_ioapic_entries
));
909 void restore_IO_APIC_setup(void)
913 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
914 if (!early_ioapic_entries
[apic
])
916 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
917 ioapic_write_entry(apic
, pin
,
918 early_ioapic_entries
[apic
][pin
]);
919 kfree(early_ioapic_entries
[apic
]);
920 early_ioapic_entries
[apic
] = NULL
;
924 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
927 * for now plain restore of previous settings.
928 * TBD: In the case of OS enabling interrupt-remapping,
929 * IO-APIC RTE's need to be setup to point to interrupt-remapping
930 * table entries. for now, do a plain restore, and wait for
931 * the setup_IO_APIC_irqs() to do proper initialization.
933 restore_IO_APIC_setup();
938 * Find the IRQ entry number of a certain pin.
940 static int find_irq_entry(int apic
, int pin
, int type
)
944 for (i
= 0; i
< mp_irq_entries
; i
++)
945 if (mp_irqs
[i
].mp_irqtype
== type
&&
946 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
947 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
948 mp_irqs
[i
].mp_dstirq
== pin
)
955 * Find the pin to which IRQ[irq] (ISA) is connected
957 static int __init
find_isa_irq_pin(int irq
, int type
)
961 for (i
= 0; i
< mp_irq_entries
; i
++) {
962 int lbus
= mp_irqs
[i
].mp_srcbus
;
964 if (test_bit(lbus
, mp_bus_not_pci
) &&
965 (mp_irqs
[i
].mp_irqtype
== type
) &&
966 (mp_irqs
[i
].mp_srcbusirq
== irq
))
968 return mp_irqs
[i
].mp_dstirq
;
973 static int __init
find_isa_irq_apic(int irq
, int type
)
977 for (i
= 0; i
< mp_irq_entries
; i
++) {
978 int lbus
= mp_irqs
[i
].mp_srcbus
;
980 if (test_bit(lbus
, mp_bus_not_pci
) &&
981 (mp_irqs
[i
].mp_irqtype
== type
) &&
982 (mp_irqs
[i
].mp_srcbusirq
== irq
))
985 if (i
< mp_irq_entries
) {
987 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
988 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
997 * Find a specific PCI IRQ entry.
998 * Not an __init, possibly needed by modules
1000 static int pin_2_irq(int idx
, int apic
, int pin
);
1002 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1004 int apic
, i
, best_guess
= -1;
1006 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1008 if (test_bit(bus
, mp_bus_not_pci
)) {
1009 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1012 for (i
= 0; i
< mp_irq_entries
; i
++) {
1013 int lbus
= mp_irqs
[i
].mp_srcbus
;
1015 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1016 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
1017 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
1020 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1021 !mp_irqs
[i
].mp_irqtype
&&
1023 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
1024 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
1026 if (!(apic
|| IO_APIC_IRQ(irq
)))
1029 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
1032 * Use the first all-but-pin matching entry as a
1033 * best-guess fuzzy result for broken mptables.
1042 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1044 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1046 * EISA Edge/Level control register, ELCR
1048 static int EISA_ELCR(unsigned int irq
)
1050 if (irq
< NR_IRQS_LEGACY
) {
1051 unsigned int port
= 0x4d0 + (irq
>> 3);
1052 return (inb(port
) >> (irq
& 7)) & 1;
1054 apic_printk(APIC_VERBOSE
, KERN_INFO
1055 "Broken MPtable reports ISA irq %d\n", irq
);
1061 /* ISA interrupts are always polarity zero edge triggered,
1062 * when listed as conforming in the MP table. */
1064 #define default_ISA_trigger(idx) (0)
1065 #define default_ISA_polarity(idx) (0)
1067 /* EISA interrupts are always polarity zero and can be edge or level
1068 * trigger depending on the ELCR value. If an interrupt is listed as
1069 * EISA conforming in the MP table, that means its trigger type must
1070 * be read in from the ELCR */
1072 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1073 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1075 /* PCI interrupts are always polarity one level triggered,
1076 * when listed as conforming in the MP table. */
1078 #define default_PCI_trigger(idx) (1)
1079 #define default_PCI_polarity(idx) (1)
1081 /* MCA interrupts are always polarity zero level triggered,
1082 * when listed as conforming in the MP table. */
1084 #define default_MCA_trigger(idx) (1)
1085 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1087 static int MPBIOS_polarity(int idx
)
1089 int bus
= mp_irqs
[idx
].mp_srcbus
;
1093 * Determine IRQ line polarity (high active or low active):
1095 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1097 case 0: /* conforms, ie. bus-type dependent polarity */
1098 if (test_bit(bus
, mp_bus_not_pci
))
1099 polarity
= default_ISA_polarity(idx
);
1101 polarity
= default_PCI_polarity(idx
);
1103 case 1: /* high active */
1108 case 2: /* reserved */
1110 printk(KERN_WARNING
"broken BIOS!!\n");
1114 case 3: /* low active */
1119 default: /* invalid */
1121 printk(KERN_WARNING
"broken BIOS!!\n");
1129 static int MPBIOS_trigger(int idx
)
1131 int bus
= mp_irqs
[idx
].mp_srcbus
;
1135 * Determine IRQ trigger mode (edge or level sensitive):
1137 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1139 case 0: /* conforms, ie. bus-type dependent */
1140 if (test_bit(bus
, mp_bus_not_pci
))
1141 trigger
= default_ISA_trigger(idx
);
1143 trigger
= default_PCI_trigger(idx
);
1144 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1145 switch (mp_bus_id_to_type
[bus
]) {
1146 case MP_BUS_ISA
: /* ISA pin */
1148 /* set before the switch */
1151 case MP_BUS_EISA
: /* EISA pin */
1153 trigger
= default_EISA_trigger(idx
);
1156 case MP_BUS_PCI
: /* PCI pin */
1158 /* set before the switch */
1161 case MP_BUS_MCA
: /* MCA pin */
1163 trigger
= default_MCA_trigger(idx
);
1168 printk(KERN_WARNING
"broken BIOS!!\n");
1180 case 2: /* reserved */
1182 printk(KERN_WARNING
"broken BIOS!!\n");
1191 default: /* invalid */
1193 printk(KERN_WARNING
"broken BIOS!!\n");
1201 static inline int irq_polarity(int idx
)
1203 return MPBIOS_polarity(idx
);
1206 static inline int irq_trigger(int idx
)
1208 return MPBIOS_trigger(idx
);
1211 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1212 static int pin_2_irq(int idx
, int apic
, int pin
)
1215 int bus
= mp_irqs
[idx
].mp_srcbus
;
1218 * Debugging check, we are in big trouble if this message pops up!
1220 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1221 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1223 if (test_bit(bus
, mp_bus_not_pci
)) {
1224 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1227 * PCI IRQs are mapped in order
1231 irq
+= nr_ioapic_registers
[i
++];
1234 * For MPS mode, so far only needed by ES7000 platform
1236 if (ioapic_renumber_irq
)
1237 irq
= ioapic_renumber_irq(apic
, irq
);
1240 #ifdef CONFIG_X86_32
1242 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1244 if ((pin
>= 16) && (pin
<= 23)) {
1245 if (pirq_entries
[pin
-16] != -1) {
1246 if (!pirq_entries
[pin
-16]) {
1247 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1248 "disabling PIRQ%d\n", pin
-16);
1250 irq
= pirq_entries
[pin
-16];
1251 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1252 "using PIRQ%d -> IRQ %d\n",
1262 void lock_vector_lock(void)
1264 /* Used to the online set of cpus does not change
1265 * during assign_irq_vector.
1267 spin_lock(&vector_lock
);
1270 void unlock_vector_lock(void)
1272 spin_unlock(&vector_lock
);
1276 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1279 * NOTE! The local APIC isn't very good at handling
1280 * multiple interrupts at the same interrupt level.
1281 * As the interrupt level is determined by taking the
1282 * vector number and shifting that right by 4, we
1283 * want to spread these out a bit so that they don't
1284 * all fall in the same interrupt level.
1286 * Also, we've got to be careful not to trash gate
1287 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1289 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1290 unsigned int old_vector
;
1292 cpumask_var_t tmp_mask
;
1294 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1297 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1300 old_vector
= cfg
->vector
;
1302 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1303 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1304 if (!cpumask_empty(tmp_mask
)) {
1305 free_cpumask_var(tmp_mask
);
1310 /* Only try and allocate irqs on cpus that are present */
1312 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1316 vector_allocation_domain(cpu
, tmp_mask
);
1318 vector
= current_vector
;
1319 offset
= current_offset
;
1322 if (vector
>= first_system_vector
) {
1323 /* If out of vectors on large boxen, must share them. */
1324 offset
= (offset
+ 1) % 8;
1325 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1327 if (unlikely(current_vector
== vector
))
1329 #ifdef CONFIG_X86_64
1330 if (vector
== IA32_SYSCALL_VECTOR
)
1333 if (vector
== SYSCALL_VECTOR
)
1336 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1337 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1340 current_vector
= vector
;
1341 current_offset
= offset
;
1343 cfg
->move_in_progress
= 1;
1344 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1346 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1347 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1348 cfg
->vector
= vector
;
1349 cpumask_copy(cfg
->domain
, tmp_mask
);
1353 free_cpumask_var(tmp_mask
);
1358 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1361 unsigned long flags
;
1363 spin_lock_irqsave(&vector_lock
, flags
);
1364 err
= __assign_irq_vector(irq
, cfg
, mask
);
1365 spin_unlock_irqrestore(&vector_lock
, flags
);
1369 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1373 BUG_ON(!cfg
->vector
);
1375 vector
= cfg
->vector
;
1376 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1377 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1380 cpumask_clear(cfg
->domain
);
1382 if (likely(!cfg
->move_in_progress
))
1384 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1385 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1387 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1389 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1393 cfg
->move_in_progress
= 0;
1396 void __setup_vector_irq(int cpu
)
1398 /* Initialize vector_irq on a new cpu */
1399 /* This function must be called with vector_lock held */
1401 struct irq_cfg
*cfg
;
1402 struct irq_desc
*desc
;
1404 /* Mark the inuse vectors */
1405 for_each_irq_desc(irq
, desc
) {
1408 cfg
= desc
->chip_data
;
1409 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1411 vector
= cfg
->vector
;
1412 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1414 /* Mark the free vectors */
1415 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1416 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1421 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1422 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1426 static struct irq_chip ioapic_chip
;
1427 #ifdef CONFIG_INTR_REMAP
1428 static struct irq_chip ir_ioapic_chip
;
1431 #define IOAPIC_AUTO -1
1432 #define IOAPIC_EDGE 0
1433 #define IOAPIC_LEVEL 1
1435 #ifdef CONFIG_X86_32
1436 static inline int IO_APIC_irq_trigger(int irq
)
1440 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1441 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1442 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1443 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1444 return irq_trigger(idx
);
1448 * nonexistent IRQs are edge default
1453 static inline int IO_APIC_irq_trigger(int irq
)
1459 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1462 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1463 trigger
== IOAPIC_LEVEL
)
1464 desc
->status
|= IRQ_LEVEL
;
1466 desc
->status
&= ~IRQ_LEVEL
;
1468 #ifdef CONFIG_INTR_REMAP
1469 if (irq_remapped(irq
)) {
1470 desc
->status
|= IRQ_MOVE_PCNTXT
;
1472 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1476 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1477 handle_edge_irq
, "edge");
1481 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1482 trigger
== IOAPIC_LEVEL
)
1483 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1487 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1488 handle_edge_irq
, "edge");
1491 static int setup_ioapic_entry(int apic
, int irq
,
1492 struct IO_APIC_route_entry
*entry
,
1493 unsigned int destination
, int trigger
,
1494 int polarity
, int vector
)
1497 * add it to the IO-APIC irq-routing table:
1499 memset(entry
,0,sizeof(*entry
));
1501 #ifdef CONFIG_INTR_REMAP
1502 if (intr_remapping_enabled
) {
1503 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1505 struct IR_IO_APIC_route_entry
*ir_entry
=
1506 (struct IR_IO_APIC_route_entry
*) entry
;
1510 panic("No mapping iommu for ioapic %d\n", apic
);
1512 index
= alloc_irte(iommu
, irq
, 1);
1514 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1516 memset(&irte
, 0, sizeof(irte
));
1519 irte
.dst_mode
= INT_DEST_MODE
;
1520 irte
.trigger_mode
= trigger
;
1521 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1522 irte
.vector
= vector
;
1523 irte
.dest_id
= IRTE_DEST(destination
);
1525 modify_irte(irq
, &irte
);
1527 ir_entry
->index2
= (index
>> 15) & 0x1;
1529 ir_entry
->format
= 1;
1530 ir_entry
->index
= (index
& 0x7fff);
1534 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1535 entry
->dest_mode
= INT_DEST_MODE
;
1536 entry
->dest
= destination
;
1539 entry
->mask
= 0; /* enable IRQ */
1540 entry
->trigger
= trigger
;
1541 entry
->polarity
= polarity
;
1542 entry
->vector
= vector
;
1544 /* Mask level triggered irqs.
1545 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1552 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1553 int trigger
, int polarity
)
1555 struct irq_cfg
*cfg
;
1556 struct IO_APIC_route_entry entry
;
1559 if (!IO_APIC_IRQ(irq
))
1562 cfg
= desc
->chip_data
;
1564 if (assign_irq_vector(irq
, cfg
, TARGET_CPUS
))
1567 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
1569 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1570 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1571 "IRQ %d Mode:%i Active:%i)\n",
1572 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1573 irq
, trigger
, polarity
);
1576 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1577 dest
, trigger
, polarity
, cfg
->vector
)) {
1578 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1579 mp_ioapics
[apic
].mp_apicid
, pin
);
1580 __clear_irq_vector(irq
, cfg
);
1584 ioapic_register_intr(irq
, desc
, trigger
);
1585 if (irq
< NR_IRQS_LEGACY
)
1586 disable_8259A_irq(irq
);
1588 ioapic_write_entry(apic
, pin
, entry
);
1591 static void __init
setup_IO_APIC_irqs(void)
1593 int apic
, pin
, idx
, irq
;
1595 struct irq_desc
*desc
;
1596 struct irq_cfg
*cfg
;
1597 int cpu
= boot_cpu_id
;
1599 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1601 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1602 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1604 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1608 apic_printk(APIC_VERBOSE
,
1609 KERN_DEBUG
" %d-%d",
1610 mp_ioapics
[apic
].mp_apicid
,
1613 apic_printk(APIC_VERBOSE
, " %d-%d",
1614 mp_ioapics
[apic
].mp_apicid
,
1619 apic_printk(APIC_VERBOSE
,
1620 " (apicid-pin) not connected\n");
1624 irq
= pin_2_irq(idx
, apic
, pin
);
1625 #ifdef CONFIG_X86_32
1626 if (multi_timer_check(apic
, irq
))
1629 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1631 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1634 cfg
= desc
->chip_data
;
1635 add_pin_to_irq_cpu(cfg
, cpu
, apic
, pin
);
1637 setup_IO_APIC_irq(apic
, pin
, irq
, desc
,
1638 irq_trigger(idx
), irq_polarity(idx
));
1643 apic_printk(APIC_VERBOSE
,
1644 " (apicid-pin) not connected\n");
1648 * Set up the timer pin, possibly with the 8259A-master behind.
1650 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1653 struct IO_APIC_route_entry entry
;
1655 #ifdef CONFIG_INTR_REMAP
1656 if (intr_remapping_enabled
)
1660 memset(&entry
, 0, sizeof(entry
));
1663 * We use logical delivery to get the timer IRQ
1666 entry
.dest_mode
= INT_DEST_MODE
;
1667 entry
.mask
= 1; /* mask IRQ now */
1668 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1669 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1672 entry
.vector
= vector
;
1675 * The timer IRQ doesn't have to know that behind the
1676 * scene we may have a 8259A-master in AEOI mode ...
1678 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1681 * Add it to the IO-APIC irq-routing table:
1683 ioapic_write_entry(apic
, pin
, entry
);
1687 __apicdebuginit(void) print_IO_APIC(void)
1690 union IO_APIC_reg_00 reg_00
;
1691 union IO_APIC_reg_01 reg_01
;
1692 union IO_APIC_reg_02 reg_02
;
1693 union IO_APIC_reg_03 reg_03
;
1694 unsigned long flags
;
1695 struct irq_cfg
*cfg
;
1696 struct irq_desc
*desc
;
1699 if (apic_verbosity
== APIC_QUIET
)
1702 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1703 for (i
= 0; i
< nr_ioapics
; i
++)
1704 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1705 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1708 * We are a bit conservative about what we expect. We have to
1709 * know about every hardware change ASAP.
1711 printk(KERN_INFO
"testing the IO APIC.......................\n");
1713 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1715 spin_lock_irqsave(&ioapic_lock
, flags
);
1716 reg_00
.raw
= io_apic_read(apic
, 0);
1717 reg_01
.raw
= io_apic_read(apic
, 1);
1718 if (reg_01
.bits
.version
>= 0x10)
1719 reg_02
.raw
= io_apic_read(apic
, 2);
1720 if (reg_01
.bits
.version
>= 0x20)
1721 reg_03
.raw
= io_apic_read(apic
, 3);
1722 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1725 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1726 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1727 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1728 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1729 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1731 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1732 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1734 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1735 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1738 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1739 * but the value of reg_02 is read as the previous read register
1740 * value, so ignore it if reg_02 == reg_01.
1742 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1743 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1744 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1748 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1749 * or reg_03, but the value of reg_0[23] is read as the previous read
1750 * register value, so ignore it if reg_03 == reg_0[12].
1752 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1753 reg_03
.raw
!= reg_01
.raw
) {
1754 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1755 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1758 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1760 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1761 " Stat Dmod Deli Vect: \n");
1763 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1764 struct IO_APIC_route_entry entry
;
1766 entry
= ioapic_read_entry(apic
, i
);
1768 printk(KERN_DEBUG
" %02x %03X ",
1773 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1778 entry
.delivery_status
,
1780 entry
.delivery_mode
,
1785 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1786 for_each_irq_desc(irq
, desc
) {
1787 struct irq_pin_list
*entry
;
1791 cfg
= desc
->chip_data
;
1792 entry
= cfg
->irq_2_pin
;
1795 printk(KERN_DEBUG
"IRQ%d ", irq
);
1797 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1800 entry
= entry
->next
;
1805 printk(KERN_INFO
".................................... done.\n");
1810 __apicdebuginit(void) print_APIC_bitfield(int base
)
1815 if (apic_verbosity
== APIC_QUIET
)
1818 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1819 for (i
= 0; i
< 8; i
++) {
1820 v
= apic_read(base
+ i
*0x10);
1821 for (j
= 0; j
< 32; j
++) {
1831 __apicdebuginit(void) print_local_APIC(void *dummy
)
1833 unsigned int v
, ver
, maxlvt
;
1836 if (apic_verbosity
== APIC_QUIET
)
1839 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1840 smp_processor_id(), hard_smp_processor_id());
1841 v
= apic_read(APIC_ID
);
1842 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1843 v
= apic_read(APIC_LVR
);
1844 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1845 ver
= GET_APIC_VERSION(v
);
1846 maxlvt
= lapic_get_maxlvt();
1848 v
= apic_read(APIC_TASKPRI
);
1849 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1851 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1852 if (!APIC_XAPIC(ver
)) {
1853 v
= apic_read(APIC_ARBPRI
);
1854 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1855 v
& APIC_ARBPRI_MASK
);
1857 v
= apic_read(APIC_PROCPRI
);
1858 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1862 * Remote read supported only in the 82489DX and local APIC for
1863 * Pentium processors.
1865 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1866 v
= apic_read(APIC_RRR
);
1867 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1870 v
= apic_read(APIC_LDR
);
1871 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1872 if (!x2apic_enabled()) {
1873 v
= apic_read(APIC_DFR
);
1874 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1876 v
= apic_read(APIC_SPIV
);
1877 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1879 printk(KERN_DEBUG
"... APIC ISR field:\n");
1880 print_APIC_bitfield(APIC_ISR
);
1881 printk(KERN_DEBUG
"... APIC TMR field:\n");
1882 print_APIC_bitfield(APIC_TMR
);
1883 printk(KERN_DEBUG
"... APIC IRR field:\n");
1884 print_APIC_bitfield(APIC_IRR
);
1886 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1887 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1888 apic_write(APIC_ESR
, 0);
1890 v
= apic_read(APIC_ESR
);
1891 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1894 icr
= apic_icr_read();
1895 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1896 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1898 v
= apic_read(APIC_LVTT
);
1899 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1901 if (maxlvt
> 3) { /* PC is LVT#4. */
1902 v
= apic_read(APIC_LVTPC
);
1903 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1905 v
= apic_read(APIC_LVT0
);
1906 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1907 v
= apic_read(APIC_LVT1
);
1908 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1910 if (maxlvt
> 2) { /* ERR is LVT#3. */
1911 v
= apic_read(APIC_LVTERR
);
1912 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1915 v
= apic_read(APIC_TMICT
);
1916 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1917 v
= apic_read(APIC_TMCCT
);
1918 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1919 v
= apic_read(APIC_TDCR
);
1920 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1924 __apicdebuginit(void) print_all_local_APICs(void)
1929 for_each_online_cpu(cpu
)
1930 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1934 __apicdebuginit(void) print_PIC(void)
1937 unsigned long flags
;
1939 if (apic_verbosity
== APIC_QUIET
)
1942 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1944 spin_lock_irqsave(&i8259A_lock
, flags
);
1946 v
= inb(0xa1) << 8 | inb(0x21);
1947 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1949 v
= inb(0xa0) << 8 | inb(0x20);
1950 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1954 v
= inb(0xa0) << 8 | inb(0x20);
1958 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1960 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1962 v
= inb(0x4d1) << 8 | inb(0x4d0);
1963 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1966 __apicdebuginit(int) print_all_ICs(void)
1969 print_all_local_APICs();
1975 fs_initcall(print_all_ICs
);
1978 /* Where if anywhere is the i8259 connect in external int mode */
1979 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1981 void __init
enable_IO_APIC(void)
1983 union IO_APIC_reg_01 reg_01
;
1984 int i8259_apic
, i8259_pin
;
1986 unsigned long flags
;
1988 #ifdef CONFIG_X86_32
1991 for (i
= 0; i
< MAX_PIRQS
; i
++)
1992 pirq_entries
[i
] = -1;
1996 * The number of IO-APIC IRQ registers (== #pins):
1998 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1999 spin_lock_irqsave(&ioapic_lock
, flags
);
2000 reg_01
.raw
= io_apic_read(apic
, 1);
2001 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2002 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2004 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2006 /* See if any of the pins is in ExtINT mode */
2007 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2008 struct IO_APIC_route_entry entry
;
2009 entry
= ioapic_read_entry(apic
, pin
);
2011 /* If the interrupt line is enabled and in ExtInt mode
2012 * I have found the pin where the i8259 is connected.
2014 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2015 ioapic_i8259
.apic
= apic
;
2016 ioapic_i8259
.pin
= pin
;
2022 /* Look to see what if the MP table has reported the ExtINT */
2023 /* If we could not find the appropriate pin by looking at the ioapic
2024 * the i8259 probably is not connected the ioapic but give the
2025 * mptable a chance anyway.
2027 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2028 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2029 /* Trust the MP table if nothing is setup in the hardware */
2030 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2031 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2032 ioapic_i8259
.pin
= i8259_pin
;
2033 ioapic_i8259
.apic
= i8259_apic
;
2035 /* Complain if the MP table and the hardware disagree */
2036 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2037 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2039 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2043 * Do not trust the IO-APIC being empty at bootup
2049 * Not an __init, needed by the reboot code
2051 void disable_IO_APIC(void)
2054 * Clear the IO-APIC before rebooting:
2059 * If the i8259 is routed through an IOAPIC
2060 * Put that IOAPIC in virtual wire mode
2061 * so legacy interrupts can be delivered.
2063 if (ioapic_i8259
.pin
!= -1) {
2064 struct IO_APIC_route_entry entry
;
2066 memset(&entry
, 0, sizeof(entry
));
2067 entry
.mask
= 0; /* Enabled */
2068 entry
.trigger
= 0; /* Edge */
2070 entry
.polarity
= 0; /* High */
2071 entry
.delivery_status
= 0;
2072 entry
.dest_mode
= 0; /* Physical */
2073 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2075 entry
.dest
= read_apic_id();
2078 * Add it to the IO-APIC irq-routing table:
2080 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2083 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2086 #ifdef CONFIG_X86_32
2088 * function to set the IO-APIC physical IDs based on the
2089 * values stored in the MPC table.
2091 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2094 static void __init
setup_ioapic_ids_from_mpc(void)
2096 union IO_APIC_reg_00 reg_00
;
2097 physid_mask_t phys_id_present_map
;
2100 unsigned char old_id
;
2101 unsigned long flags
;
2103 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2107 * Don't check I/O APIC IDs for xAPIC systems. They have
2108 * no meaning without the serial APIC bus.
2110 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2111 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2114 * This is broken; anything with a real cpu count has to
2115 * circumvent this idiocy regardless.
2117 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2120 * Set the IOAPIC ID to the value stored in the MPC table.
2122 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2124 /* Read the register 0 value */
2125 spin_lock_irqsave(&ioapic_lock
, flags
);
2126 reg_00
.raw
= io_apic_read(apic
, 0);
2127 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2129 old_id
= mp_ioapics
[apic
].mp_apicid
;
2131 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2132 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2133 apic
, mp_ioapics
[apic
].mp_apicid
);
2134 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2136 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2140 * Sanity check, is the ID really free? Every APIC in a
2141 * system must have a unique ID or we get lots of nice
2142 * 'stuck on smp_invalidate_needed IPI wait' messages.
2144 if (check_apicid_used(phys_id_present_map
,
2145 mp_ioapics
[apic
].mp_apicid
)) {
2146 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2147 apic
, mp_ioapics
[apic
].mp_apicid
);
2148 for (i
= 0; i
< get_physical_broadcast(); i
++)
2149 if (!physid_isset(i
, phys_id_present_map
))
2151 if (i
>= get_physical_broadcast())
2152 panic("Max APIC ID exceeded!\n");
2153 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2155 physid_set(i
, phys_id_present_map
);
2156 mp_ioapics
[apic
].mp_apicid
= i
;
2159 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2160 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2161 "phys_id_present_map\n",
2162 mp_ioapics
[apic
].mp_apicid
);
2163 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2168 * We need to adjust the IRQ routing table
2169 * if the ID changed.
2171 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2172 for (i
= 0; i
< mp_irq_entries
; i
++)
2173 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2174 mp_irqs
[i
].mp_dstapic
2175 = mp_ioapics
[apic
].mp_apicid
;
2178 * Read the right value from the MPC table and
2179 * write it into the ID register.
2181 apic_printk(APIC_VERBOSE
, KERN_INFO
2182 "...changing IO-APIC physical APIC ID to %d ...",
2183 mp_ioapics
[apic
].mp_apicid
);
2185 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2186 spin_lock_irqsave(&ioapic_lock
, flags
);
2187 io_apic_write(apic
, 0, reg_00
.raw
);
2188 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2193 spin_lock_irqsave(&ioapic_lock
, flags
);
2194 reg_00
.raw
= io_apic_read(apic
, 0);
2195 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2196 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2197 printk("could not set ID!\n");
2199 apic_printk(APIC_VERBOSE
, " ok.\n");
2204 int no_timer_check __initdata
;
2206 static int __init
notimercheck(char *s
)
2211 __setup("no_timer_check", notimercheck
);
2214 * There is a nasty bug in some older SMP boards, their mptable lies
2215 * about the timer IRQ. We do the following to work around the situation:
2217 * - timer IRQ defaults to IO-APIC IRQ
2218 * - if this function detects that timer IRQs are defunct, then we fall
2219 * back to ISA timer IRQs
2221 static int __init
timer_irq_works(void)
2223 unsigned long t1
= jiffies
;
2224 unsigned long flags
;
2229 local_save_flags(flags
);
2231 /* Let ten ticks pass... */
2232 mdelay((10 * 1000) / HZ
);
2233 local_irq_restore(flags
);
2236 * Expect a few ticks at least, to be sure some possible
2237 * glue logic does not lock up after one or two first
2238 * ticks in a non-ExtINT mode. Also the local APIC
2239 * might have cached one ExtINT interrupt. Finally, at
2240 * least one tick may be lost due to delays.
2244 if (time_after(jiffies
, t1
+ 4))
2250 * In the SMP+IOAPIC case it might happen that there are an unspecified
2251 * number of pending IRQ events unhandled. These cases are very rare,
2252 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2253 * better to do it this way as thus we do not have to be aware of
2254 * 'pending' interrupts in the IRQ path, except at this point.
2257 * Edge triggered needs to resend any interrupt
2258 * that was delayed but this is now handled in the device
2263 * Starting up a edge-triggered IO-APIC interrupt is
2264 * nasty - we need to make sure that we get the edge.
2265 * If it is already asserted for some reason, we need
2266 * return 1 to indicate that is was pending.
2268 * This is not complete - we should be able to fake
2269 * an edge even if it isn't on the 8259A...
2272 static unsigned int startup_ioapic_irq(unsigned int irq
)
2274 int was_pending
= 0;
2275 unsigned long flags
;
2276 struct irq_cfg
*cfg
;
2278 spin_lock_irqsave(&ioapic_lock
, flags
);
2279 if (irq
< NR_IRQS_LEGACY
) {
2280 disable_8259A_irq(irq
);
2281 if (i8259A_irq_pending(irq
))
2285 __unmask_IO_APIC_irq(cfg
);
2286 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2291 #ifdef CONFIG_X86_64
2292 static int ioapic_retrigger_irq(unsigned int irq
)
2295 struct irq_cfg
*cfg
= irq_cfg(irq
);
2296 unsigned long flags
;
2298 spin_lock_irqsave(&vector_lock
, flags
);
2299 send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2300 spin_unlock_irqrestore(&vector_lock
, flags
);
2305 static int ioapic_retrigger_irq(unsigned int irq
)
2307 send_IPI_self(irq_cfg(irq
)->vector
);
2314 * Level and edge triggered IO-APIC interrupts need different handling,
2315 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2316 * handled with the level-triggered descriptor, but that one has slightly
2317 * more overhead. Level-triggered interrupts cannot be handled with the
2318 * edge-triggered handler, without risking IRQ storms and other ugly
2324 #ifdef CONFIG_INTR_REMAP
2325 static void ir_irq_migration(struct work_struct
*work
);
2327 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2330 * Migrate the IO-APIC irq in the presence of intr-remapping.
2332 * For edge triggered, irq migration is a simple atomic update(of vector
2333 * and cpu destination) of IRTE and flush the hardware cache.
2335 * For level triggered, we need to modify the io-apic RTE aswell with the update
2336 * vector information, along with modifying IRTE with vector and destination.
2337 * So irq migration for level triggered is little bit more complex compared to
2338 * edge triggered migration. But the good news is, we use the same algorithm
2339 * for level triggered migration as we have today, only difference being,
2340 * we now initiate the irq migration from process context instead of the
2341 * interrupt context.
2343 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2344 * suppression) to the IO-APIC, level triggered irq migration will also be
2345 * as simple as edge triggered migration and we can do the irq migration
2346 * with a simple atomic update to IO-APIC RTE.
2349 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2351 struct irq_cfg
*cfg
;
2353 int modify_ioapic_rte
;
2355 unsigned long flags
;
2358 if (!cpumask_intersects(mask
, cpu_online_mask
))
2362 if (get_irte(irq
, &irte
))
2365 cfg
= desc
->chip_data
;
2366 if (assign_irq_vector(irq
, cfg
, mask
))
2369 set_extra_move_desc(desc
, mask
);
2371 dest
= cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2373 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2374 if (modify_ioapic_rte
) {
2375 spin_lock_irqsave(&ioapic_lock
, flags
);
2376 __target_IO_APIC_irq(irq
, dest
, cfg
);
2377 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2380 irte
.vector
= cfg
->vector
;
2381 irte
.dest_id
= IRTE_DEST(dest
);
2384 * Modified the IRTE and flushes the Interrupt entry cache.
2386 modify_irte(irq
, &irte
);
2388 if (cfg
->move_in_progress
)
2389 send_cleanup_vector(cfg
);
2391 cpumask_copy(&desc
->affinity
, mask
);
2394 static int migrate_irq_remapped_level_desc(struct irq_desc
*desc
)
2397 struct irq_cfg
*cfg
= desc
->chip_data
;
2399 mask_IO_APIC_irq_desc(desc
);
2401 if (io_apic_level_ack_pending(cfg
)) {
2403 * Interrupt in progress. Migrating irq now will change the
2404 * vector information in the IO-APIC RTE and that will confuse
2405 * the EOI broadcast performed by cpu.
2406 * So, delay the irq migration to the next instance.
2408 schedule_delayed_work(&ir_migration_work
, 1);
2412 /* everthing is clear. we have right of way */
2413 migrate_ioapic_irq_desc(desc
, &desc
->pending_mask
);
2416 desc
->status
&= ~IRQ_MOVE_PENDING
;
2417 cpumask_clear(&desc
->pending_mask
);
2420 unmask_IO_APIC_irq_desc(desc
);
2425 static void ir_irq_migration(struct work_struct
*work
)
2428 struct irq_desc
*desc
;
2430 for_each_irq_desc(irq
, desc
) {
2434 if (desc
->status
& IRQ_MOVE_PENDING
) {
2435 unsigned long flags
;
2437 spin_lock_irqsave(&desc
->lock
, flags
);
2438 if (!desc
->chip
->set_affinity
||
2439 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2440 desc
->status
&= ~IRQ_MOVE_PENDING
;
2441 spin_unlock_irqrestore(&desc
->lock
, flags
);
2445 desc
->chip
->set_affinity(irq
, &desc
->pending_mask
);
2446 spin_unlock_irqrestore(&desc
->lock
, flags
);
2452 * Migrates the IRQ destination in the process context.
2454 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2455 const struct cpumask
*mask
)
2457 if (desc
->status
& IRQ_LEVEL
) {
2458 desc
->status
|= IRQ_MOVE_PENDING
;
2459 cpumask_copy(&desc
->pending_mask
, mask
);
2460 migrate_irq_remapped_level_desc(desc
);
2464 migrate_ioapic_irq_desc(desc
, mask
);
2466 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2467 const struct cpumask
*mask
)
2469 struct irq_desc
*desc
= irq_to_desc(irq
);
2471 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2475 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2477 unsigned vector
, me
;
2479 #ifdef CONFIG_X86_64
2484 me
= smp_processor_id();
2485 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2487 struct irq_desc
*desc
;
2488 struct irq_cfg
*cfg
;
2489 irq
= __get_cpu_var(vector_irq
)[vector
];
2494 desc
= irq_to_desc(irq
);
2499 spin_lock(&desc
->lock
);
2500 if (!cfg
->move_cleanup_count
)
2503 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2506 __get_cpu_var(vector_irq
)[vector
] = -1;
2507 cfg
->move_cleanup_count
--;
2509 spin_unlock(&desc
->lock
);
2515 static void irq_complete_move(struct irq_desc
**descp
)
2517 struct irq_desc
*desc
= *descp
;
2518 struct irq_cfg
*cfg
= desc
->chip_data
;
2519 unsigned vector
, me
;
2521 if (likely(!cfg
->move_in_progress
)) {
2522 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2523 if (likely(!cfg
->move_desc_pending
))
2526 /* domain is not change, but affinity is changed */
2527 me
= smp_processor_id();
2528 if (cpu_isset(me
, desc
->affinity
)) {
2529 *descp
= desc
= move_irq_desc(desc
, me
);
2530 /* get the new one */
2531 cfg
= desc
->chip_data
;
2532 cfg
->move_desc_pending
= 0;
2538 vector
= ~get_irq_regs()->orig_ax
;
2539 me
= smp_processor_id();
2540 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2541 *descp
= desc
= move_irq_desc(desc
, me
);
2542 /* get the new one */
2543 cfg
= desc
->chip_data
;
2546 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2547 send_cleanup_vector(cfg
);
2550 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2553 #ifdef CONFIG_INTR_REMAP
2554 static void ack_x2apic_level(unsigned int irq
)
2559 static void ack_x2apic_edge(unsigned int irq
)
2566 static void ack_apic_edge(unsigned int irq
)
2568 struct irq_desc
*desc
= irq_to_desc(irq
);
2570 irq_complete_move(&desc
);
2571 move_native_irq(irq
);
2575 atomic_t irq_mis_count
;
2577 static void ack_apic_level(unsigned int irq
)
2579 struct irq_desc
*desc
= irq_to_desc(irq
);
2581 #ifdef CONFIG_X86_32
2585 struct irq_cfg
*cfg
;
2586 int do_unmask_irq
= 0;
2588 irq_complete_move(&desc
);
2589 #ifdef CONFIG_GENERIC_PENDING_IRQ
2590 /* If we are moving the irq we need to mask it */
2591 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2593 mask_IO_APIC_irq_desc(desc
);
2597 #ifdef CONFIG_X86_32
2599 * It appears there is an erratum which affects at least version 0x11
2600 * of I/O APIC (that's the 82093AA and cores integrated into various
2601 * chipsets). Under certain conditions a level-triggered interrupt is
2602 * erroneously delivered as edge-triggered one but the respective IRR
2603 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2604 * message but it will never arrive and further interrupts are blocked
2605 * from the source. The exact reason is so far unknown, but the
2606 * phenomenon was observed when two consecutive interrupt requests
2607 * from a given source get delivered to the same CPU and the source is
2608 * temporarily disabled in between.
2610 * A workaround is to simulate an EOI message manually. We achieve it
2611 * by setting the trigger mode to edge and then to level when the edge
2612 * trigger mode gets detected in the TMR of a local APIC for a
2613 * level-triggered interrupt. We mask the source for the time of the
2614 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2615 * The idea is from Manfred Spraul. --macro
2617 cfg
= desc
->chip_data
;
2620 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2624 * We must acknowledge the irq before we move it or the acknowledge will
2625 * not propagate properly.
2629 /* Now we can move and renable the irq */
2630 if (unlikely(do_unmask_irq
)) {
2631 /* Only migrate the irq if the ack has been received.
2633 * On rare occasions the broadcast level triggered ack gets
2634 * delayed going to ioapics, and if we reprogram the
2635 * vector while Remote IRR is still set the irq will never
2638 * To prevent this scenario we read the Remote IRR bit
2639 * of the ioapic. This has two effects.
2640 * - On any sane system the read of the ioapic will
2641 * flush writes (and acks) going to the ioapic from
2643 * - We get to see if the ACK has actually been delivered.
2645 * Based on failed experiments of reprogramming the
2646 * ioapic entry from outside of irq context starting
2647 * with masking the ioapic entry and then polling until
2648 * Remote IRR was clear before reprogramming the
2649 * ioapic I don't trust the Remote IRR bit to be
2650 * completey accurate.
2652 * However there appears to be no other way to plug
2653 * this race, so if the Remote IRR bit is not
2654 * accurate and is causing problems then it is a hardware bug
2655 * and you can go talk to the chipset vendor about it.
2657 cfg
= desc
->chip_data
;
2658 if (!io_apic_level_ack_pending(cfg
))
2659 move_masked_irq(irq
);
2660 unmask_IO_APIC_irq_desc(desc
);
2663 #ifdef CONFIG_X86_32
2664 if (!(v
& (1 << (i
& 0x1f)))) {
2665 atomic_inc(&irq_mis_count
);
2666 spin_lock(&ioapic_lock
);
2667 __mask_and_edge_IO_APIC_irq(cfg
);
2668 __unmask_and_level_IO_APIC_irq(cfg
);
2669 spin_unlock(&ioapic_lock
);
2674 static struct irq_chip ioapic_chip __read_mostly
= {
2676 .startup
= startup_ioapic_irq
,
2677 .mask
= mask_IO_APIC_irq
,
2678 .unmask
= unmask_IO_APIC_irq
,
2679 .ack
= ack_apic_edge
,
2680 .eoi
= ack_apic_level
,
2682 .set_affinity
= set_ioapic_affinity_irq
,
2684 .retrigger
= ioapic_retrigger_irq
,
2687 #ifdef CONFIG_INTR_REMAP
2688 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2689 .name
= "IR-IO-APIC",
2690 .startup
= startup_ioapic_irq
,
2691 .mask
= mask_IO_APIC_irq
,
2692 .unmask
= unmask_IO_APIC_irq
,
2693 .ack
= ack_x2apic_edge
,
2694 .eoi
= ack_x2apic_level
,
2696 .set_affinity
= set_ir_ioapic_affinity_irq
,
2698 .retrigger
= ioapic_retrigger_irq
,
2702 static inline void init_IO_APIC_traps(void)
2705 struct irq_desc
*desc
;
2706 struct irq_cfg
*cfg
;
2709 * NOTE! The local APIC isn't very good at handling
2710 * multiple interrupts at the same interrupt level.
2711 * As the interrupt level is determined by taking the
2712 * vector number and shifting that right by 4, we
2713 * want to spread these out a bit so that they don't
2714 * all fall in the same interrupt level.
2716 * Also, we've got to be careful not to trash gate
2717 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2719 for_each_irq_desc(irq
, desc
) {
2723 cfg
= desc
->chip_data
;
2724 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2726 * Hmm.. We don't have an entry for this,
2727 * so default to an old-fashioned 8259
2728 * interrupt if we can..
2730 if (irq
< NR_IRQS_LEGACY
)
2731 make_8259A_irq(irq
);
2733 /* Strange. Oh, well.. */
2734 desc
->chip
= &no_irq_chip
;
2740 * The local APIC irq-chip implementation:
2743 static void mask_lapic_irq(unsigned int irq
)
2747 v
= apic_read(APIC_LVT0
);
2748 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2751 static void unmask_lapic_irq(unsigned int irq
)
2755 v
= apic_read(APIC_LVT0
);
2756 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2759 static void ack_lapic_irq(unsigned int irq
)
2764 static struct irq_chip lapic_chip __read_mostly
= {
2765 .name
= "local-APIC",
2766 .mask
= mask_lapic_irq
,
2767 .unmask
= unmask_lapic_irq
,
2768 .ack
= ack_lapic_irq
,
2771 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2773 desc
->status
&= ~IRQ_LEVEL
;
2774 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2778 static void __init
setup_nmi(void)
2781 * Dirty trick to enable the NMI watchdog ...
2782 * We put the 8259A master into AEOI mode and
2783 * unmask on all local APICs LVT0 as NMI.
2785 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2786 * is from Maciej W. Rozycki - so we do not have to EOI from
2787 * the NMI handler or the timer interrupt.
2789 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2791 enable_NMI_through_LVT0();
2793 apic_printk(APIC_VERBOSE
, " done.\n");
2797 * This looks a bit hackish but it's about the only one way of sending
2798 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2799 * not support the ExtINT mode, unfortunately. We need to send these
2800 * cycles as some i82489DX-based boards have glue logic that keeps the
2801 * 8259A interrupt line asserted until INTA. --macro
2803 static inline void __init
unlock_ExtINT_logic(void)
2806 struct IO_APIC_route_entry entry0
, entry1
;
2807 unsigned char save_control
, save_freq_select
;
2809 pin
= find_isa_irq_pin(8, mp_INT
);
2814 apic
= find_isa_irq_apic(8, mp_INT
);
2820 entry0
= ioapic_read_entry(apic
, pin
);
2821 clear_IO_APIC_pin(apic
, pin
);
2823 memset(&entry1
, 0, sizeof(entry1
));
2825 entry1
.dest_mode
= 0; /* physical delivery */
2826 entry1
.mask
= 0; /* unmask IRQ now */
2827 entry1
.dest
= hard_smp_processor_id();
2828 entry1
.delivery_mode
= dest_ExtINT
;
2829 entry1
.polarity
= entry0
.polarity
;
2833 ioapic_write_entry(apic
, pin
, entry1
);
2835 save_control
= CMOS_READ(RTC_CONTROL
);
2836 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2837 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2839 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2844 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2848 CMOS_WRITE(save_control
, RTC_CONTROL
);
2849 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2850 clear_IO_APIC_pin(apic
, pin
);
2852 ioapic_write_entry(apic
, pin
, entry0
);
2855 static int disable_timer_pin_1 __initdata
;
2856 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2857 static int __init
disable_timer_pin_setup(char *arg
)
2859 disable_timer_pin_1
= 1;
2862 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2864 int timer_through_8259 __initdata
;
2867 * This code may look a bit paranoid, but it's supposed to cooperate with
2868 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2869 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2870 * fanatically on his truly buggy board.
2872 * FIXME: really need to revamp this for all platforms.
2874 static inline void __init
check_timer(void)
2876 struct irq_desc
*desc
= irq_to_desc(0);
2877 struct irq_cfg
*cfg
= desc
->chip_data
;
2878 int cpu
= boot_cpu_id
;
2879 int apic1
, pin1
, apic2
, pin2
;
2880 unsigned long flags
;
2884 local_irq_save(flags
);
2886 ver
= apic_read(APIC_LVR
);
2887 ver
= GET_APIC_VERSION(ver
);
2890 * get/set the timer IRQ vector:
2892 disable_8259A_irq(0);
2893 assign_irq_vector(0, cfg
, TARGET_CPUS
);
2896 * As IRQ0 is to be enabled in the 8259A, the virtual
2897 * wire has to be disabled in the local APIC. Also
2898 * timer interrupts need to be acknowledged manually in
2899 * the 8259A for the i82489DX when using the NMI
2900 * watchdog as that APIC treats NMIs as level-triggered.
2901 * The AEOI mode will finish them in the 8259A
2904 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2906 #ifdef CONFIG_X86_32
2907 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2910 pin1
= find_isa_irq_pin(0, mp_INT
);
2911 apic1
= find_isa_irq_apic(0, mp_INT
);
2912 pin2
= ioapic_i8259
.pin
;
2913 apic2
= ioapic_i8259
.apic
;
2915 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2916 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2917 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2920 * Some BIOS writers are clueless and report the ExtINTA
2921 * I/O APIC input from the cascaded 8259A as the timer
2922 * interrupt input. So just in case, if only one pin
2923 * was found above, try it both directly and through the
2927 #ifdef CONFIG_INTR_REMAP
2928 if (intr_remapping_enabled
)
2929 panic("BIOS bug: timer not connected to IO-APIC");
2934 } else if (pin2
== -1) {
2941 * Ok, does IRQ0 through the IOAPIC work?
2944 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2945 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2947 unmask_IO_APIC_irq_desc(desc
);
2948 if (timer_irq_works()) {
2949 if (nmi_watchdog
== NMI_IO_APIC
) {
2951 enable_8259A_irq(0);
2953 if (disable_timer_pin_1
> 0)
2954 clear_IO_APIC_pin(0, pin1
);
2957 #ifdef CONFIG_INTR_REMAP
2958 if (intr_remapping_enabled
)
2959 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2961 clear_IO_APIC_pin(apic1
, pin1
);
2963 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2964 "8254 timer not connected to IO-APIC\n");
2966 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2967 "(IRQ0) through the 8259A ...\n");
2968 apic_printk(APIC_QUIET
, KERN_INFO
2969 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2971 * legacy devices should be connected to IO APIC #0
2973 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2974 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2975 unmask_IO_APIC_irq_desc(desc
);
2976 enable_8259A_irq(0);
2977 if (timer_irq_works()) {
2978 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2979 timer_through_8259
= 1;
2980 if (nmi_watchdog
== NMI_IO_APIC
) {
2981 disable_8259A_irq(0);
2983 enable_8259A_irq(0);
2988 * Cleanup, just in case ...
2990 disable_8259A_irq(0);
2991 clear_IO_APIC_pin(apic2
, pin2
);
2992 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2995 if (nmi_watchdog
== NMI_IO_APIC
) {
2996 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2997 "through the IO-APIC - disabling NMI Watchdog!\n");
2998 nmi_watchdog
= NMI_NONE
;
3000 #ifdef CONFIG_X86_32
3004 apic_printk(APIC_QUIET
, KERN_INFO
3005 "...trying to set up timer as Virtual Wire IRQ...\n");
3007 lapic_register_intr(0, desc
);
3008 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3009 enable_8259A_irq(0);
3011 if (timer_irq_works()) {
3012 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3015 disable_8259A_irq(0);
3016 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3017 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3019 apic_printk(APIC_QUIET
, KERN_INFO
3020 "...trying to set up timer as ExtINT IRQ...\n");
3024 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3026 unlock_ExtINT_logic();
3028 if (timer_irq_works()) {
3029 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3032 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3033 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3034 "report. Then try booting with the 'noapic' option.\n");
3036 local_irq_restore(flags
);
3040 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3041 * to devices. However there may be an I/O APIC pin available for
3042 * this interrupt regardless. The pin may be left unconnected, but
3043 * typically it will be reused as an ExtINT cascade interrupt for
3044 * the master 8259A. In the MPS case such a pin will normally be
3045 * reported as an ExtINT interrupt in the MP table. With ACPI
3046 * there is no provision for ExtINT interrupts, and in the absence
3047 * of an override it would be treated as an ordinary ISA I/O APIC
3048 * interrupt, that is edge-triggered and unmasked by default. We
3049 * used to do this, but it caused problems on some systems because
3050 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3051 * the same ExtINT cascade interrupt to drive the local APIC of the
3052 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3053 * the I/O APIC in all cases now. No actual device should request
3054 * it anyway. --macro
3056 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3058 void __init
setup_IO_APIC(void)
3061 #ifdef CONFIG_X86_32
3065 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3069 io_apic_irqs
= ~PIC_IRQS
;
3071 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3073 * Set up IO-APIC IRQ routing.
3075 #ifdef CONFIG_X86_32
3077 setup_ioapic_ids_from_mpc();
3080 setup_IO_APIC_irqs();
3081 init_IO_APIC_traps();
3086 * Called after all the initialization is done. If we didnt find any
3087 * APIC bugs then we can allow the modify fast path
3090 static int __init
io_apic_bug_finalize(void)
3092 if (sis_apic_bug
== -1)
3097 late_initcall(io_apic_bug_finalize
);
3099 struct sysfs_ioapic_data
{
3100 struct sys_device dev
;
3101 struct IO_APIC_route_entry entry
[0];
3103 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3105 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3107 struct IO_APIC_route_entry
*entry
;
3108 struct sysfs_ioapic_data
*data
;
3111 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3112 entry
= data
->entry
;
3113 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3114 *entry
= ioapic_read_entry(dev
->id
, i
);
3119 static int ioapic_resume(struct sys_device
*dev
)
3121 struct IO_APIC_route_entry
*entry
;
3122 struct sysfs_ioapic_data
*data
;
3123 unsigned long flags
;
3124 union IO_APIC_reg_00 reg_00
;
3127 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3128 entry
= data
->entry
;
3130 spin_lock_irqsave(&ioapic_lock
, flags
);
3131 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3132 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3133 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3134 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3136 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3137 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3138 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3143 static struct sysdev_class ioapic_sysdev_class
= {
3145 .suspend
= ioapic_suspend
,
3146 .resume
= ioapic_resume
,
3149 static int __init
ioapic_init_sysfs(void)
3151 struct sys_device
* dev
;
3154 error
= sysdev_class_register(&ioapic_sysdev_class
);
3158 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3159 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3160 * sizeof(struct IO_APIC_route_entry
);
3161 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3162 if (!mp_ioapic_data
[i
]) {
3163 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3166 dev
= &mp_ioapic_data
[i
]->dev
;
3168 dev
->cls
= &ioapic_sysdev_class
;
3169 error
= sysdev_register(dev
);
3171 kfree(mp_ioapic_data
[i
]);
3172 mp_ioapic_data
[i
] = NULL
;
3173 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3181 device_initcall(ioapic_init_sysfs
);
3184 * Dynamic irq allocate and deallocation
3186 unsigned int create_irq_nr(unsigned int irq_want
)
3188 /* Allocate an unused irq */
3191 unsigned long flags
;
3192 struct irq_cfg
*cfg_new
= NULL
;
3193 int cpu
= boot_cpu_id
;
3194 struct irq_desc
*desc_new
= NULL
;
3197 spin_lock_irqsave(&vector_lock
, flags
);
3198 for (new = irq_want
; new < NR_IRQS
; new++) {
3199 if (platform_legacy_irq(new))
3202 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3204 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3207 cfg_new
= desc_new
->chip_data
;
3209 if (cfg_new
->vector
!= 0)
3211 if (__assign_irq_vector(new, cfg_new
, TARGET_CPUS
) == 0)
3215 spin_unlock_irqrestore(&vector_lock
, flags
);
3218 dynamic_irq_init(irq
);
3219 /* restore it, in case dynamic_irq_init clear it */
3221 desc_new
->chip_data
= cfg_new
;
3226 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3227 int create_irq(void)
3229 unsigned int irq_want
;
3232 irq_want
= nr_irqs_gsi
;
3233 irq
= create_irq_nr(irq_want
);
3241 void destroy_irq(unsigned int irq
)
3243 unsigned long flags
;
3244 struct irq_cfg
*cfg
;
3245 struct irq_desc
*desc
;
3247 /* store it, in case dynamic_irq_cleanup clear it */
3248 desc
= irq_to_desc(irq
);
3249 cfg
= desc
->chip_data
;
3250 dynamic_irq_cleanup(irq
);
3251 /* connect back irq_cfg */
3253 desc
->chip_data
= cfg
;
3255 #ifdef CONFIG_INTR_REMAP
3258 spin_lock_irqsave(&vector_lock
, flags
);
3259 __clear_irq_vector(irq
, cfg
);
3260 spin_unlock_irqrestore(&vector_lock
, flags
);
3264 * MSI message composition
3266 #ifdef CONFIG_PCI_MSI
3267 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3269 struct irq_cfg
*cfg
;
3274 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3278 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3280 #ifdef CONFIG_INTR_REMAP
3281 if (irq_remapped(irq
)) {
3286 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3287 BUG_ON(ir_index
== -1);
3289 memset (&irte
, 0, sizeof(irte
));
3292 irte
.dst_mode
= INT_DEST_MODE
;
3293 irte
.trigger_mode
= 0; /* edge */
3294 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3295 irte
.vector
= cfg
->vector
;
3296 irte
.dest_id
= IRTE_DEST(dest
);
3298 modify_irte(irq
, &irte
);
3300 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3301 msg
->data
= sub_handle
;
3302 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3304 MSI_ADDR_IR_INDEX1(ir_index
) |
3305 MSI_ADDR_IR_INDEX2(ir_index
);
3309 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3312 ((INT_DEST_MODE
== 0) ?
3313 MSI_ADDR_DEST_MODE_PHYSICAL
:
3314 MSI_ADDR_DEST_MODE_LOGICAL
) |
3315 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3316 MSI_ADDR_REDIRECTION_CPU
:
3317 MSI_ADDR_REDIRECTION_LOWPRI
) |
3318 MSI_ADDR_DEST_ID(dest
);
3321 MSI_DATA_TRIGGER_EDGE
|
3322 MSI_DATA_LEVEL_ASSERT
|
3323 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3324 MSI_DATA_DELIVERY_FIXED
:
3325 MSI_DATA_DELIVERY_LOWPRI
) |
3326 MSI_DATA_VECTOR(cfg
->vector
);
3332 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3334 struct irq_desc
*desc
= irq_to_desc(irq
);
3335 struct irq_cfg
*cfg
;
3339 dest
= set_desc_affinity(desc
, mask
);
3340 if (dest
== BAD_APICID
)
3343 cfg
= desc
->chip_data
;
3345 read_msi_msg_desc(desc
, &msg
);
3347 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3348 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3349 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3350 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3352 write_msi_msg_desc(desc
, &msg
);
3354 #ifdef CONFIG_INTR_REMAP
3356 * Migrate the MSI irq to another cpumask. This migration is
3357 * done in the process context using interrupt-remapping hardware.
3360 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3362 struct irq_desc
*desc
= irq_to_desc(irq
);
3363 struct irq_cfg
*cfg
= desc
->chip_data
;
3367 if (get_irte(irq
, &irte
))
3370 dest
= set_desc_affinity(desc
, mask
);
3371 if (dest
== BAD_APICID
)
3374 irte
.vector
= cfg
->vector
;
3375 irte
.dest_id
= IRTE_DEST(dest
);
3378 * atomically update the IRTE with the new destination and vector.
3380 modify_irte(irq
, &irte
);
3383 * After this point, all the interrupts will start arriving
3384 * at the new destination. So, time to cleanup the previous
3385 * vector allocation.
3387 if (cfg
->move_in_progress
)
3388 send_cleanup_vector(cfg
);
3392 #endif /* CONFIG_SMP */
3395 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3396 * which implement the MSI or MSI-X Capability Structure.
3398 static struct irq_chip msi_chip
= {
3400 .unmask
= unmask_msi_irq
,
3401 .mask
= mask_msi_irq
,
3402 .ack
= ack_apic_edge
,
3404 .set_affinity
= set_msi_irq_affinity
,
3406 .retrigger
= ioapic_retrigger_irq
,
3409 #ifdef CONFIG_INTR_REMAP
3410 static struct irq_chip msi_ir_chip
= {
3411 .name
= "IR-PCI-MSI",
3412 .unmask
= unmask_msi_irq
,
3413 .mask
= mask_msi_irq
,
3414 .ack
= ack_x2apic_edge
,
3416 .set_affinity
= ir_set_msi_irq_affinity
,
3418 .retrigger
= ioapic_retrigger_irq
,
3422 * Map the PCI dev to the corresponding remapping hardware unit
3423 * and allocate 'nvec' consecutive interrupt-remapping table entries
3426 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3428 struct intel_iommu
*iommu
;
3431 iommu
= map_dev_to_ir(dev
);
3434 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3438 index
= alloc_irte(iommu
, irq
, nvec
);
3441 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3449 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3454 ret
= msi_compose_msg(dev
, irq
, &msg
);
3458 set_irq_msi(irq
, msidesc
);
3459 write_msi_msg(irq
, &msg
);
3461 #ifdef CONFIG_INTR_REMAP
3462 if (irq_remapped(irq
)) {
3463 struct irq_desc
*desc
= irq_to_desc(irq
);
3465 * irq migration in process context
3467 desc
->status
|= IRQ_MOVE_PCNTXT
;
3468 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3471 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3473 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3478 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
)
3482 unsigned int irq_want
;
3484 irq_want
= nr_irqs_gsi
;
3485 irq
= create_irq_nr(irq_want
);
3489 #ifdef CONFIG_INTR_REMAP
3490 if (!intr_remapping_enabled
)
3493 ret
= msi_alloc_irte(dev
, irq
, 1);
3498 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3505 #ifdef CONFIG_INTR_REMAP
3512 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3515 int ret
, sub_handle
;
3516 struct msi_desc
*msidesc
;
3517 unsigned int irq_want
;
3519 #ifdef CONFIG_INTR_REMAP
3520 struct intel_iommu
*iommu
= 0;
3524 irq_want
= nr_irqs_gsi
;
3526 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3527 irq
= create_irq_nr(irq_want
);
3531 #ifdef CONFIG_INTR_REMAP
3532 if (!intr_remapping_enabled
)
3537 * allocate the consecutive block of IRTE's
3540 index
= msi_alloc_irte(dev
, irq
, nvec
);
3546 iommu
= map_dev_to_ir(dev
);
3552 * setup the mapping between the irq and the IRTE
3553 * base index, the sub_handle pointing to the
3554 * appropriate interrupt remap table entry.
3556 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3560 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3572 void arch_teardown_msi_irq(unsigned int irq
)
3579 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3581 struct irq_desc
*desc
= irq_to_desc(irq
);
3582 struct irq_cfg
*cfg
;
3586 dest
= set_desc_affinity(desc
, mask
);
3587 if (dest
== BAD_APICID
)
3590 cfg
= desc
->chip_data
;
3592 dmar_msi_read(irq
, &msg
);
3594 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3595 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3596 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3597 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3599 dmar_msi_write(irq
, &msg
);
3602 #endif /* CONFIG_SMP */
3604 struct irq_chip dmar_msi_type
= {
3606 .unmask
= dmar_msi_unmask
,
3607 .mask
= dmar_msi_mask
,
3608 .ack
= ack_apic_edge
,
3610 .set_affinity
= dmar_msi_set_affinity
,
3612 .retrigger
= ioapic_retrigger_irq
,
3615 int arch_setup_dmar_msi(unsigned int irq
)
3620 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3623 dmar_msi_write(irq
, &msg
);
3624 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3630 #ifdef CONFIG_HPET_TIMER
3633 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3635 struct irq_desc
*desc
= irq_to_desc(irq
);
3636 struct irq_cfg
*cfg
;
3640 dest
= set_desc_affinity(desc
, mask
);
3641 if (dest
== BAD_APICID
)
3644 cfg
= desc
->chip_data
;
3646 hpet_msi_read(irq
, &msg
);
3648 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3649 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3650 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3651 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3653 hpet_msi_write(irq
, &msg
);
3656 #endif /* CONFIG_SMP */
3658 struct irq_chip hpet_msi_type
= {
3660 .unmask
= hpet_msi_unmask
,
3661 .mask
= hpet_msi_mask
,
3662 .ack
= ack_apic_edge
,
3664 .set_affinity
= hpet_msi_set_affinity
,
3666 .retrigger
= ioapic_retrigger_irq
,
3669 int arch_setup_hpet_msi(unsigned int irq
)
3674 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3678 hpet_msi_write(irq
, &msg
);
3679 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3686 #endif /* CONFIG_PCI_MSI */
3688 * Hypertransport interrupt support
3690 #ifdef CONFIG_HT_IRQ
3694 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3696 struct ht_irq_msg msg
;
3697 fetch_ht_irq_msg(irq
, &msg
);
3699 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3700 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3702 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3703 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3705 write_ht_irq_msg(irq
, &msg
);
3708 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3710 struct irq_desc
*desc
= irq_to_desc(irq
);
3711 struct irq_cfg
*cfg
;
3714 dest
= set_desc_affinity(desc
, mask
);
3715 if (dest
== BAD_APICID
)
3718 cfg
= desc
->chip_data
;
3720 target_ht_irq(irq
, dest
, cfg
->vector
);
3725 static struct irq_chip ht_irq_chip
= {
3727 .mask
= mask_ht_irq
,
3728 .unmask
= unmask_ht_irq
,
3729 .ack
= ack_apic_edge
,
3731 .set_affinity
= set_ht_irq_affinity
,
3733 .retrigger
= ioapic_retrigger_irq
,
3736 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3738 struct irq_cfg
*cfg
;
3742 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3744 struct ht_irq_msg msg
;
3747 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3749 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3753 HT_IRQ_LOW_DEST_ID(dest
) |
3754 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3755 ((INT_DEST_MODE
== 0) ?
3756 HT_IRQ_LOW_DM_PHYSICAL
:
3757 HT_IRQ_LOW_DM_LOGICAL
) |
3758 HT_IRQ_LOW_RQEOI_EDGE
|
3759 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3760 HT_IRQ_LOW_MT_FIXED
:
3761 HT_IRQ_LOW_MT_ARBITRATED
) |
3762 HT_IRQ_LOW_IRQ_MASKED
;
3764 write_ht_irq_msg(irq
, &msg
);
3766 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3767 handle_edge_irq
, "edge");
3769 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3773 #endif /* CONFIG_HT_IRQ */
3775 #ifdef CONFIG_X86_64
3777 * Re-target the irq to the specified CPU and enable the specified MMR located
3778 * on the specified blade to allow the sending of MSIs to the specified CPU.
3780 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3781 unsigned long mmr_offset
)
3783 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3784 struct irq_cfg
*cfg
;
3786 unsigned long mmr_value
;
3787 struct uv_IO_APIC_route_entry
*entry
;
3788 unsigned long flags
;
3793 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3797 spin_lock_irqsave(&vector_lock
, flags
);
3798 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3800 spin_unlock_irqrestore(&vector_lock
, flags
);
3803 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3804 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3806 entry
->vector
= cfg
->vector
;
3807 entry
->delivery_mode
= INT_DELIVERY_MODE
;
3808 entry
->dest_mode
= INT_DEST_MODE
;
3809 entry
->polarity
= 0;
3812 entry
->dest
= cpu_mask_to_apicid(eligible_cpu
);
3814 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3815 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3821 * Disable the specified MMR located on the specified blade so that MSIs are
3822 * longer allowed to be sent.
3824 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3826 unsigned long mmr_value
;
3827 struct uv_IO_APIC_route_entry
*entry
;
3831 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3832 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3836 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3837 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3839 #endif /* CONFIG_X86_64 */
3841 int __init
io_apic_get_redir_entries (int ioapic
)
3843 union IO_APIC_reg_01 reg_01
;
3844 unsigned long flags
;
3846 spin_lock_irqsave(&ioapic_lock
, flags
);
3847 reg_01
.raw
= io_apic_read(ioapic
, 1);
3848 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3850 return reg_01
.bits
.entries
;
3853 void __init
probe_nr_irqs_gsi(void)
3858 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3859 nr
+= io_apic_get_redir_entries(idx
) + 1;
3861 if (nr
> nr_irqs_gsi
)
3865 /* --------------------------------------------------------------------------
3866 ACPI-based IOAPIC Configuration
3867 -------------------------------------------------------------------------- */
3871 #ifdef CONFIG_X86_32
3872 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3874 union IO_APIC_reg_00 reg_00
;
3875 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3877 unsigned long flags
;
3881 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3882 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3883 * supports up to 16 on one shared APIC bus.
3885 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3886 * advantage of new APIC bus architecture.
3889 if (physids_empty(apic_id_map
))
3890 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3892 spin_lock_irqsave(&ioapic_lock
, flags
);
3893 reg_00
.raw
= io_apic_read(ioapic
, 0);
3894 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3896 if (apic_id
>= get_physical_broadcast()) {
3897 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3898 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3899 apic_id
= reg_00
.bits
.ID
;
3903 * Every APIC in a system must have a unique ID or we get lots of nice
3904 * 'stuck on smp_invalidate_needed IPI wait' messages.
3906 if (check_apicid_used(apic_id_map
, apic_id
)) {
3908 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3909 if (!check_apicid_used(apic_id_map
, i
))
3913 if (i
== get_physical_broadcast())
3914 panic("Max apic_id exceeded!\n");
3916 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3917 "trying %d\n", ioapic
, apic_id
, i
);
3922 tmp
= apicid_to_cpu_present(apic_id
);
3923 physids_or(apic_id_map
, apic_id_map
, tmp
);
3925 if (reg_00
.bits
.ID
!= apic_id
) {
3926 reg_00
.bits
.ID
= apic_id
;
3928 spin_lock_irqsave(&ioapic_lock
, flags
);
3929 io_apic_write(ioapic
, 0, reg_00
.raw
);
3930 reg_00
.raw
= io_apic_read(ioapic
, 0);
3931 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3934 if (reg_00
.bits
.ID
!= apic_id
) {
3935 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3940 apic_printk(APIC_VERBOSE
, KERN_INFO
3941 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3946 int __init
io_apic_get_version(int ioapic
)
3948 union IO_APIC_reg_01 reg_01
;
3949 unsigned long flags
;
3951 spin_lock_irqsave(&ioapic_lock
, flags
);
3952 reg_01
.raw
= io_apic_read(ioapic
, 1);
3953 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3955 return reg_01
.bits
.version
;
3959 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3961 struct irq_desc
*desc
;
3962 struct irq_cfg
*cfg
;
3963 int cpu
= boot_cpu_id
;
3965 if (!IO_APIC_IRQ(irq
)) {
3966 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3971 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3973 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3978 * IRQs < 16 are already in the irq_2_pin[] map
3980 if (irq
>= NR_IRQS_LEGACY
) {
3981 cfg
= desc
->chip_data
;
3982 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3985 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3991 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3995 if (skip_ioapic_setup
)
3998 for (i
= 0; i
< mp_irq_entries
; i
++)
3999 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
4000 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
4002 if (i
>= mp_irq_entries
)
4005 *trigger
= irq_trigger(i
);
4006 *polarity
= irq_polarity(i
);
4010 #endif /* CONFIG_ACPI */
4013 * This function currently is only a helper for the i386 smp boot process where
4014 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4015 * so mask in all cases should simply be TARGET_CPUS
4018 void __init
setup_ioapic_dest(void)
4020 int pin
, ioapic
, irq
, irq_entry
;
4021 struct irq_desc
*desc
;
4022 struct irq_cfg
*cfg
;
4023 const struct cpumask
*mask
;
4025 if (skip_ioapic_setup
== 1)
4028 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4029 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4030 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4031 if (irq_entry
== -1)
4033 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4035 /* setup_IO_APIC_irqs could fail to get vector for some device
4036 * when you have too many devices, because at that time only boot
4039 desc
= irq_to_desc(irq
);
4040 cfg
= desc
->chip_data
;
4042 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4043 irq_trigger(irq_entry
),
4044 irq_polarity(irq_entry
));
4050 * Honour affinities which have been set in early boot
4053 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4054 mask
= &desc
->affinity
;
4058 #ifdef CONFIG_INTR_REMAP
4059 if (intr_remapping_enabled
)
4060 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4063 set_ioapic_affinity_irq_desc(desc
, mask
);
4070 #define IOAPIC_RESOURCE_NAME_SIZE 11
4072 static struct resource
*ioapic_resources
;
4074 static struct resource
* __init
ioapic_setup_resources(void)
4077 struct resource
*res
;
4081 if (nr_ioapics
<= 0)
4084 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4087 mem
= alloc_bootmem(n
);
4091 mem
+= sizeof(struct resource
) * nr_ioapics
;
4093 for (i
= 0; i
< nr_ioapics
; i
++) {
4095 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4096 sprintf(mem
, "IOAPIC %u", i
);
4097 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4101 ioapic_resources
= res
;
4106 void __init
ioapic_init_mappings(void)
4108 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4109 struct resource
*ioapic_res
;
4112 ioapic_res
= ioapic_setup_resources();
4113 for (i
= 0; i
< nr_ioapics
; i
++) {
4114 if (smp_found_config
) {
4115 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
4116 #ifdef CONFIG_X86_32
4119 "WARNING: bogus zero IO-APIC "
4120 "address found in MPTABLE, "
4121 "disabling IO/APIC support!\n");
4122 smp_found_config
= 0;
4123 skip_ioapic_setup
= 1;
4124 goto fake_ioapic_page
;
4128 #ifdef CONFIG_X86_32
4131 ioapic_phys
= (unsigned long)
4132 alloc_bootmem_pages(PAGE_SIZE
);
4133 ioapic_phys
= __pa(ioapic_phys
);
4135 set_fixmap_nocache(idx
, ioapic_phys
);
4136 apic_printk(APIC_VERBOSE
,
4137 "mapped IOAPIC to %08lx (%08lx)\n",
4138 __fix_to_virt(idx
), ioapic_phys
);
4141 if (ioapic_res
!= NULL
) {
4142 ioapic_res
->start
= ioapic_phys
;
4143 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4149 static int __init
ioapic_insert_resources(void)
4152 struct resource
*r
= ioapic_resources
;
4156 "IO APIC resources could be not be allocated.\n");
4160 for (i
= 0; i
< nr_ioapics
; i
++) {
4161 insert_resource(&iomem_resource
, r
);
4168 /* Insert the IO APIC resources after PCI initialization has occured to handle
4169 * IO APICS that are mapped in on a BAR in PCI space. */
4170 late_initcall(ioapic_insert_resources
);