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drm: GEM mmap support
[linux-2.6/verdex.git] / drivers / usb / host / isp1760-hcd.c
blob8017f1cf78e244b0f37c4a32d2833de3d2d2a586
1 /*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 */
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/list.h>
16 #include <linux/usb.h>
17 #include <linux/debugfs.h>
18 #include <linux/uaccess.h>
19 #include <linux/io.h>
20 #include <asm/unaligned.h>
21
22 #include "../core/hcd.h"
23 #include "isp1760-hcd.h"
24
25 static struct kmem_cache *qtd_cachep;
26 static struct kmem_cache *qh_cachep;
27
28 struct isp1760_hcd {
29 u32 hcs_params;
30 spinlock_t lock;
31 struct inter_packet_info atl_ints[32];
32 struct inter_packet_info int_ints[32];
33 struct memory_chunk memory_pool[BLOCKS];
34
35 /* periodic schedule support */
36 #define DEFAULT_I_TDPS 1024
37 unsigned periodic_size;
38 unsigned i_thresh;
39 unsigned long reset_done;
40 unsigned long next_statechange;
41 unsigned int devflags;
42 };
43
44 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
45 {
46 return (struct isp1760_hcd *) (hcd->hcd_priv);
47 }
48 static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
49 {
50 return container_of((void *) priv, struct usb_hcd, hcd_priv);
51 }
52
53 /* Section 2.2 Host Controller Capability Registers */
54 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
55 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
56 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
57 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
58 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
59 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
60 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
61
62 /* Section 2.3 Host Controller Operational Registers */
63 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
64 #define CMD_RESET (1<<1) /* reset HC not bus */
65 #define CMD_RUN (1<<0) /* start/stop HC */
66 #define STS_PCD (1<<2) /* port change detect */
67 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
68
69 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
70 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
71 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
72 #define PORT_RESET (1<<8) /* reset port */
73 #define PORT_SUSPEND (1<<7) /* suspend port */
74 #define PORT_RESUME (1<<6) /* resume it */
75 #define PORT_PE (1<<2) /* port enable */
76 #define PORT_CSC (1<<1) /* connect status change */
77 #define PORT_CONNECT (1<<0) /* device connected */
78 #define PORT_RWC_BITS (PORT_CSC)
79
80 struct isp1760_qtd {
81 struct isp1760_qtd *hw_next;
82 u8 packet_type;
83 u8 toggle;
84
85 void *data_buffer;
86 /* the rest is HCD-private */
87 struct list_head qtd_list;
88 struct urb *urb;
89 size_t length;
90
91 /* isp special*/
92 u32 status;
93 #define URB_COMPLETE_NOTIFY (1 << 0)
94 #define URB_ENQUEUED (1 << 1)
95 #define URB_TYPE_ATL (1 << 2)
96 #define URB_TYPE_INT (1 << 3)
97 };
98
99 struct isp1760_qh {
100 /* first part defined by EHCI spec */
101 struct list_head qtd_list;
102 struct isp1760_hcd *priv;
103
104 /* periodic schedule info */
105 unsigned short period; /* polling interval */
106 struct usb_device *dev;
107
108 u32 toggle;
109 u32 ping;
110 };
111
112 #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED)
113
114 static unsigned int isp1760_readl(__u32 __iomem *regs)
115 {
116 return readl(regs);
117 }
118
119 static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
120 {
121 writel(val, regs);
122 }
123
124 /*
125 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
126 * doesn't quite work because some people have to enforce 32-bit access
127 */
128 static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
129 __u32 __iomem *dst, u32 len)
130 {
131 u32 val;
132 u8 *buff8;
133
134 if (!src) {
135 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
136 return;
137 }
138
139 while (len >= 4) {
140 *src = __raw_readl(dst);
141 len -= 4;
142 src++;
143 dst++;
144 }
145
146 if (!len)
147 return;
148
149 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
150 * allocated.
151 */
152 val = isp1760_readl(dst);
153
154 buff8 = (u8 *)src;
155 while (len) {
156
157 *buff8 = val;
158 val >>= 8;
159 len--;
160 buff8++;
161 }
162 }
163
164 static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
165 __u32 __iomem *dst, u32 len)
166 {
167 while (len >= 4) {
168 __raw_writel(*src, dst);
169 len -= 4;
170 src++;
171 dst++;
172 }
173
174 if (!len)
175 return;
176 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
177 * extra bytes should not be read by the HW
178 */
179
180 __raw_writel(*src, dst);
181 }
182
183 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
184 static void init_memory(struct isp1760_hcd *priv)
185 {
186 int i;
187 u32 payload;
188
189 payload = 0x1000;
190 for (i = 0; i < BLOCK_1_NUM; i++) {
191 priv->memory_pool[i].start = payload;
192 priv->memory_pool[i].size = BLOCK_1_SIZE;
193 priv->memory_pool[i].free = 1;
194 payload += priv->memory_pool[i].size;
195 }
196
197
198 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
199 priv->memory_pool[i].start = payload;
200 priv->memory_pool[i].size = BLOCK_2_SIZE;
201 priv->memory_pool[i].free = 1;
202 payload += priv->memory_pool[i].size;
203 }
204
205
206 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
207 priv->memory_pool[i].start = payload;
208 priv->memory_pool[i].size = BLOCK_3_SIZE;
209 priv->memory_pool[i].free = 1;
210 payload += priv->memory_pool[i].size;
211 }
212
213 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
214 }
215
216 static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
217 {
218 int i;
219
220 if (!size)
221 return ISP1760_NULL_POINTER;
222
223 for (i = 0; i < BLOCKS; i++) {
224 if (priv->memory_pool[i].size >= size &&
225 priv->memory_pool[i].free) {
226
227 priv->memory_pool[i].free = 0;
228 return priv->memory_pool[i].start;
229 }
230 }
231
232 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
233 size);
234 printk(KERN_ERR "Current memory map:\n");
235 for (i = 0; i < BLOCKS; i++) {
236 printk(KERN_ERR "Pool %2d size %4d status: %d\n",
237 i, priv->memory_pool[i].size,
238 priv->memory_pool[i].free);
239 }
240 /* XXX maybe -ENOMEM could be possible */
241 BUG();
242 return 0;
243 }
244
245 static void free_mem(struct isp1760_hcd *priv, u32 mem)
246 {
247 int i;
248
249 if (mem == ISP1760_NULL_POINTER)
250 return;
251
252 for (i = 0; i < BLOCKS; i++) {
253 if (priv->memory_pool[i].start == mem) {
254
255 BUG_ON(priv->memory_pool[i].free);
256
257 priv->memory_pool[i].free = 1;
258 return ;
259 }
260 }
261
262 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
263 mem);
264 BUG();
265 }
266
267 static void isp1760_init_regs(struct usb_hcd *hcd)
268 {
269 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
270 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
271 HC_ATL_PTD_SKIPMAP_REG);
272 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
273 HC_INT_PTD_SKIPMAP_REG);
274 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
275 HC_ISO_PTD_SKIPMAP_REG);
276
277 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
278 HC_ATL_PTD_DONEMAP_REG);
279 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
280 HC_INT_PTD_DONEMAP_REG);
281 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
282 HC_ISO_PTD_DONEMAP_REG);
283 }
284
285 static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
286 u32 mask, u32 done, int usec)
287 {
288 u32 result;
289
290 do {
291 result = isp1760_readl(ptr);
292 if (result == ~0)
293 return -ENODEV;
294 result &= mask;
295 if (result == done)
296 return 0;
297 udelay(1);
298 usec--;
299 } while (usec > 0);
300 return -ETIMEDOUT;
301 }
302
303 /* reset a non-running (STS_HALT == 1) controller */
304 static int ehci_reset(struct isp1760_hcd *priv)
305 {
306 int retval;
307 struct usb_hcd *hcd = priv_to_hcd(priv);
308 u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
309
310 command |= CMD_RESET;
311 isp1760_writel(command, hcd->regs + HC_USBCMD);
312 hcd->state = HC_STATE_HALT;
313 priv->next_statechange = jiffies;
314 retval = handshake(priv, hcd->regs + HC_USBCMD,
315 CMD_RESET, 0, 250 * 1000);
316 return retval;
317 }
318
319 static void qh_destroy(struct isp1760_qh *qh)
320 {
321 BUG_ON(!list_empty(&qh->qtd_list));
322 kmem_cache_free(qh_cachep, qh);
323 }
324
325 static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
326 gfp_t flags)
327 {
328 struct isp1760_qh *qh;
329
330 qh = kmem_cache_zalloc(qh_cachep, flags);
331 if (!qh)
332 return qh;
333
334 INIT_LIST_HEAD(&qh->qtd_list);
335 qh->priv = priv;
336 return qh;
337 }
338
339 /* magic numbers that can affect system performance */
340 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
341 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
342 #define EHCI_TUNE_RL_TT 0
343 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
344 #define EHCI_TUNE_MULT_TT 1
345 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
346
347 /* one-time init, only for memory state */
348 static int priv_init(struct usb_hcd *hcd)
349 {
350 struct isp1760_hcd *priv = hcd_to_priv(hcd);
351 u32 hcc_params;
352
353 spin_lock_init(&priv->lock);
354
355 /*
356 * hw default: 1K periodic list heads, one per frame.
357 * periodic_size can shrink by USBCMD update if hcc_params allows.
358 */
359 priv->periodic_size = DEFAULT_I_TDPS;
360
361 /* controllers may cache some of the periodic schedule ... */
362 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
363 /* full frame cache */
364 if (HCC_ISOC_CACHE(hcc_params))
365 priv->i_thresh = 8;
366 else /* N microframes cached */
367 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
368
369 return 0;
370 }
371
372 static int isp1760_hc_setup(struct usb_hcd *hcd)
373 {
374 struct isp1760_hcd *priv = hcd_to_priv(hcd);
375 int result;
376 u32 scratch, hwmode;
377
378 /* Setup HW Mode Control: This assumes a level active-low interrupt */
379 hwmode = HW_DATA_BUS_32BIT;
380
381 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
382 hwmode &= ~HW_DATA_BUS_32BIT;
383 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
384 hwmode |= HW_ANA_DIGI_OC;
385 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
386 hwmode |= HW_DACK_POL_HIGH;
387 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
388 hwmode |= HW_DREQ_POL_HIGH;
389
390 /*
391 * We have to set this first in case we're in 16-bit mode.
392 * Write it twice to ensure correct upper bits if switching
393 * to 16-bit mode.
394 */
395 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
396 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
397
398 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
399 /* Change bus pattern */
400 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
401 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
402 if (scratch != 0xdeadbabe) {
403 printk(KERN_ERR "ISP1760: Scratch test failed.\n");
404 return -ENODEV;
405 }
406
407 /* pre reset */
408 isp1760_init_regs(hcd);
409
410 /* reset */
411 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
412 mdelay(100);
413
414 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
415 mdelay(100);
416
417 result = ehci_reset(priv);
418 if (result)
419 return result;
420
421 /* Step 11 passed */
422
423 isp1760_info(priv, "bus width: %d, oc: %s\n",
424 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
425 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
426 "analog" : "digital");
427
428 /* ATL reset */
429 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
430 mdelay(10);
431 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
432
433 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
434 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
435
436 /*
437 * PORT 1 Control register of the ISP1760 is the OTG control
438 * register on ISP1761.
439 */
440 if (!(priv->devflags & ISP1760_FLAG_ISP1761) &&
441 !(priv->devflags & ISP1760_FLAG_PORT1_DIS)) {
442 isp1760_writel(PORT1_POWER | PORT1_INIT2,
443 hcd->regs + HC_PORT1_CTRL);
444 mdelay(10);
445 }
446
447 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
448
449 return priv_init(hcd);
450 }
451
452 static void isp1760_init_maps(struct usb_hcd *hcd)
453 {
454 /*set last maps, for iso its only 1, else 32 tds bitmap*/
455 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
456 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
457 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
458 }
459
460 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
461 {
462 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
463 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
464 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
465 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
466 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
467 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
468 /* step 23 passed */
469 }
470
471 static int isp1760_run(struct usb_hcd *hcd)
472 {
473 struct isp1760_hcd *priv = hcd_to_priv(hcd);
474 int retval;
475 u32 temp;
476 u32 command;
477 u32 chipid;
478
479 hcd->uses_new_polling = 1;
480 hcd->poll_rh = 0;
481
482 hcd->state = HC_STATE_RUNNING;
483 isp1760_enable_interrupts(hcd);
484 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
485 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
486
487 command = isp1760_readl(hcd->regs + HC_USBCMD);
488 command &= ~(CMD_LRESET|CMD_RESET);
489 command |= CMD_RUN;
490 isp1760_writel(command, hcd->regs + HC_USBCMD);
491
492 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
493 250 * 1000);
494 if (retval)
495 return retval;
496
497 /*
498 * XXX
499 * Spec says to write FLAG_CF as last config action, priv code grabs
500 * the semaphore while doing so.
501 */
502 down_write(&ehci_cf_port_reset_rwsem);
503 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
504
505 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
506 250 * 1000);
507 up_write(&ehci_cf_port_reset_rwsem);
508 if (retval)
509 return retval;
510
511 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
512 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
513 chipid >> 16);
514
515 /* PTD Register Init Part 2, Step 28 */
516 /* enable INTs */
517 isp1760_init_maps(hcd);
518
519 /* GRR this is run-once init(), being done every time the HC starts.
520 * So long as they're part of class devices, we can't do it init()
521 * since the class device isn't created that early.
522 */
523 return 0;
524 }
525
526 static u32 base_to_chip(u32 base)
527 {
528 return ((base - 0x400) >> 3);
529 }
530
531 static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
532 struct isp1760_qtd *qtd, struct urb *urb,
533 u32 payload, struct ptd *ptd)
534 {
535 u32 dw0;
536 u32 dw1;
537 u32 dw2;
538 u32 dw3;
539 u32 maxpacket;
540 u32 multi;
541 u32 pid_code;
542 u32 rl = RL_COUNTER;
543 u32 nak = NAK_COUNTER;
544
545 /* according to 3.6.2, max packet len can not be > 0x400 */
546 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
547 multi = 1 + ((maxpacket >> 11) & 0x3);
548 maxpacket &= 0x7ff;
549
550 /* DW0 */
551 dw0 = PTD_VALID;
552 dw0 |= PTD_LENGTH(qtd->length);
553 dw0 |= PTD_MAXPACKET(maxpacket);
554 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
555 dw1 = usb_pipeendpoint(urb->pipe) >> 1;
556
557 /* DW1 */
558 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
559
560 pid_code = qtd->packet_type;
561 dw1 |= PTD_PID_TOKEN(pid_code);
562
563 if (usb_pipebulk(urb->pipe))
564 dw1 |= PTD_TRANS_BULK;
565 else if (usb_pipeint(urb->pipe))
566 dw1 |= PTD_TRANS_INT;
567
568 if (urb->dev->speed != USB_SPEED_HIGH) {
569 /* split transaction */
570
571 dw1 |= PTD_TRANS_SPLIT;
572 if (urb->dev->speed == USB_SPEED_LOW)
573 dw1 |= PTD_SE_USB_LOSPEED;
574
575 dw1 |= PTD_PORT_NUM(urb->dev->ttport);
576 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
577
578 /* SE bit for Split INT transfers */
579 if (usb_pipeint(urb->pipe) &&
580 (urb->dev->speed == USB_SPEED_LOW))
581 dw1 |= 2 << 16;
582
583 dw3 = 0;
584 rl = 0;
585 nak = 0;
586 } else {
587 dw0 |= PTD_MULTI(multi);
588 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
589 dw3 = qh->ping;
590 else
591 dw3 = 0;
592 }
593 /* DW2 */
594 dw2 = 0;
595 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
596 dw2 |= PTD_RL_CNT(rl);
597 dw3 |= PTD_NAC_CNT(nak);
598
599 /* DW3 */
600 if (usb_pipecontrol(urb->pipe))
601 dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
602 else
603 dw3 |= qh->toggle;
604
605
606 dw3 |= PTD_ACTIVE;
607 /* Cerr */
608 dw3 |= PTD_CERR(ERR_COUNTER);
609
610 memset(ptd, 0, sizeof(*ptd));
611
612 ptd->dw0 = cpu_to_le32(dw0);
613 ptd->dw1 = cpu_to_le32(dw1);
614 ptd->dw2 = cpu_to_le32(dw2);
615 ptd->dw3 = cpu_to_le32(dw3);
616 }
617
618 static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
619 struct isp1760_qtd *qtd, struct urb *urb,
620 u32 payload, struct ptd *ptd)
621 {
622 u32 maxpacket;
623 u32 multi;
624 u32 numberofusofs;
625 u32 i;
626 u32 usofmask, usof;
627 u32 period;
628
629 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
630 multi = 1 + ((maxpacket >> 11) & 0x3);
631 maxpacket &= 0x7ff;
632 /* length of the data per uframe */
633 maxpacket = multi * maxpacket;
634
635 numberofusofs = urb->transfer_buffer_length / maxpacket;
636 if (urb->transfer_buffer_length % maxpacket)
637 numberofusofs += 1;
638
639 usofmask = 1;
640 usof = 0;
641 for (i = 0; i < numberofusofs; i++) {
642 usof |= usofmask;
643 usofmask <<= 1;
644 }
645
646 if (urb->dev->speed != USB_SPEED_HIGH) {
647 /* split */
648 ptd->dw5 = __constant_cpu_to_le32(0x1c);
649
650 if (qh->period >= 32)
651 period = qh->period / 2;
652 else
653 period = qh->period;
654
655 } else {
656
657 if (qh->period >= 8)
658 period = qh->period/8;
659 else
660 period = qh->period;
661
662 if (period >= 32)
663 period = 16;
664
665 if (qh->period >= 8) {
666 /* millisecond period */
667 period = (period << 3);
668 } else {
669 /* usof based tranmsfers */
670 /* minimum 4 usofs */
671 usof = 0x11;
672 }
673 }
674
675 ptd->dw2 |= cpu_to_le32(period);
676 ptd->dw4 = cpu_to_le32(usof);
677 }
678
679 static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
680 struct isp1760_qtd *qtd, struct urb *urb,
681 u32 payload, struct ptd *ptd)
682 {
683 transform_into_atl(priv, qh, qtd, urb, payload, ptd);
684 transform_add_int(priv, qh, qtd, urb, payload, ptd);
685 }
686
687 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
688 u32 token)
689 {
690 int count;
691
692 qtd->data_buffer = databuffer;
693 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
694 qtd->toggle = GET_DATA_TOGGLE(token);
695
696 if (len > HC_ATL_PL_SIZE)
697 count = HC_ATL_PL_SIZE;
698 else
699 count = len;
700
701 qtd->length = count;
702 return count;
703 }
704
705 static int check_error(struct ptd *ptd)
706 {
707 int error = 0;
708 u32 dw3;
709
710 dw3 = le32_to_cpu(ptd->dw3);
711 if (dw3 & DW3_HALT_BIT)
712 error = -EPIPE;
713
714 if (dw3 & DW3_ERROR_BIT) {
715 printk(KERN_ERR "error bit is set in DW3\n");
716 error = -EPIPE;
717 }
718
719 if (dw3 & DW3_QTD_ACTIVE) {
720 printk(KERN_ERR "transfer active bit is set DW3\n");
721 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
722 (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
723 }
724
725 return error;
726 }
727
728 static void check_int_err_status(u32 dw4)
729 {
730 u32 i;
731
732 dw4 >>= 8;
733
734 for (i = 0; i < 8; i++) {
735 switch (dw4 & 0x7) {
736 case INT_UNDERRUN:
737 printk(KERN_ERR "ERROR: under run , %d\n", i);
738 break;
739
740 case INT_EXACT:
741 printk(KERN_ERR "ERROR: transaction error, %d\n", i);
742 break;
743
744 case INT_BABBLE:
745 printk(KERN_ERR "ERROR: babble error, %d\n", i);
746 break;
747 }
748 dw4 >>= 3;
749 }
750 }
751
752 static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
753 u32 payload)
754 {
755 u32 token;
756 struct usb_hcd *hcd = priv_to_hcd(priv);
757
758 token = qtd->packet_type;
759
760 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
761 switch (token) {
762 case IN_PID:
763 break;
764 case OUT_PID:
765 case SETUP_PID:
766 priv_write_copy(priv, qtd->data_buffer,
767 hcd->regs + payload,
768 qtd->length);
769 }
770 }
771 }
772
773 static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
774 struct isp1760_hcd *priv, struct isp1760_qh *qh,
775 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
776 {
777 struct ptd ptd;
778 struct usb_hcd *hcd = priv_to_hcd(priv);
779
780 transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
781 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
782 enqueue_one_qtd(qtd, priv, payload);
783
784 priv->atl_ints[slot].urb = urb;
785 priv->atl_ints[slot].qh = qh;
786 priv->atl_ints[slot].qtd = qtd;
787 priv->atl_ints[slot].data_buffer = qtd->data_buffer;
788 priv->atl_ints[slot].payload = payload;
789 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
790 qtd->status |= slot << 16;
791 }
792
793 static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
794 struct isp1760_hcd *priv, struct isp1760_qh *qh,
795 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
796 {
797 struct ptd ptd;
798 struct usb_hcd *hcd = priv_to_hcd(priv);
799
800 transform_into_int(priv, qh, qtd, urb, payload, &ptd);
801 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
802 enqueue_one_qtd(qtd, priv, payload);
803
804 priv->int_ints[slot].urb = urb;
805 priv->int_ints[slot].qh = qh;
806 priv->int_ints[slot].qtd = qtd;
807 priv->int_ints[slot].data_buffer = qtd->data_buffer;
808 priv->int_ints[slot].payload = payload;
809 qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
810 qtd->status |= slot << 16;
811 }
812
813 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
814 struct isp1760_qtd *qtd)
815 {
816 struct isp1760_hcd *priv = hcd_to_priv(hcd);
817 u32 skip_map, or_map;
818 u32 queue_entry;
819 u32 slot;
820 u32 atl_regs, payload;
821 u32 buffstatus;
822
823 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
824
825 BUG_ON(!skip_map);
826 slot = __ffs(skip_map);
827 queue_entry = 1 << slot;
828
829 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
830
831 payload = alloc_mem(priv, qtd->length);
832
833 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
834
835 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
836 or_map |= queue_entry;
837 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
838
839 skip_map &= ~queue_entry;
840 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
841
842 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
843 buffstatus |= ATL_BUFFER;
844 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
845 }
846
847 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
848 struct isp1760_qtd *qtd)
849 {
850 struct isp1760_hcd *priv = hcd_to_priv(hcd);
851 u32 skip_map, or_map;
852 u32 queue_entry;
853 u32 slot;
854 u32 int_regs, payload;
855 u32 buffstatus;
856
857 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
858
859 BUG_ON(!skip_map);
860 slot = __ffs(skip_map);
861 queue_entry = 1 << slot;
862
863 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
864
865 payload = alloc_mem(priv, qtd->length);
866
867 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
868
869 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
870 or_map |= queue_entry;
871 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
872
873 skip_map &= ~queue_entry;
874 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
875
876 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
877 buffstatus |= INT_BUFFER;
878 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
879 }
880
881 static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
882 __releases(priv->lock)
883 __acquires(priv->lock)
884 {
885 if (!urb->unlinked) {
886 if (status == -EINPROGRESS)
887 status = 0;
888 }
889
890 /* complete() can reenter this HCD */
891 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
892 spin_unlock(&priv->lock);
893 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
894 spin_lock(&priv->lock);
895 }
896
897 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
898 {
899 kmem_cache_free(qtd_cachep, qtd);
900 }
901
902 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
903 {
904 struct isp1760_qtd *tmp_qtd;
905
906 tmp_qtd = qtd->hw_next;
907 list_del(&qtd->qtd_list);
908 isp1760_qtd_free(qtd);
909 return tmp_qtd;
910 }
911
912 /*
913 * Remove this QTD from the QH list and free its memory. If this QTD
914 * isn't the last one than remove also his successor(s).
915 * Returns the QTD which is part of an new URB and should be enqueued.
916 */
917 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
918 {
919 struct isp1760_qtd *tmp_qtd;
920 int last_one;
921
922 do {
923 tmp_qtd = qtd->hw_next;
924 last_one = qtd->status & URB_COMPLETE_NOTIFY;
925 list_del(&qtd->qtd_list);
926 isp1760_qtd_free(qtd);
927 qtd = tmp_qtd;
928 } while (!last_one && qtd);
929
930 return qtd;
931 }
932
933 static void do_atl_int(struct usb_hcd *usb_hcd)
934 {
935 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
936 u32 done_map, skip_map;
937 struct ptd ptd;
938 struct urb *urb = NULL;
939 u32 atl_regs_base;
940 u32 atl_regs;
941 u32 queue_entry;
942 u32 payload;
943 u32 length;
944 u32 or_map;
945 u32 status = -EINVAL;
946 int error;
947 struct isp1760_qtd *qtd;
948 struct isp1760_qh *qh;
949 u32 rl;
950 u32 nakcount;
951
952 done_map = isp1760_readl(usb_hcd->regs +
953 HC_ATL_PTD_DONEMAP_REG);
954 skip_map = isp1760_readl(usb_hcd->regs +
955 HC_ATL_PTD_SKIPMAP_REG);
956
957 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
958 or_map &= ~done_map;
959 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
960
961 atl_regs_base = ATL_REGS_OFFSET;
962 while (done_map) {
963 u32 dw1;
964 u32 dw2;
965 u32 dw3;
966
967 status = 0;
968
969 queue_entry = __ffs(done_map);
970 done_map &= ~(1 << queue_entry);
971 skip_map |= 1 << queue_entry;
972
973 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
974
975 urb = priv->atl_ints[queue_entry].urb;
976 qtd = priv->atl_ints[queue_entry].qtd;
977 qh = priv->atl_ints[queue_entry].qh;
978 payload = priv->atl_ints[queue_entry].payload;
979
980 if (!qh) {
981 printk(KERN_ERR "qh is 0\n");
982 continue;
983 }
984 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
985 HC_MEMORY_REG);
986 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
987 HC_MEMORY_REG);
988 /*
989 * write bank1 address twice to ensure the 90ns delay (time
990 * between BANK0 write and the priv_read_copy() call is at
991 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
992 */
993 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
994 HC_MEMORY_REG);
995
996 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
997 ISP_BANK(0), sizeof(ptd));
998
999 dw1 = le32_to_cpu(ptd.dw1);
1000 dw2 = le32_to_cpu(ptd.dw2);
1001 dw3 = le32_to_cpu(ptd.dw3);
1002 rl = (dw2 >> 25) & 0x0f;
1003 nakcount = (dw3 >> 19) & 0xf;
1004
1005 /* Transfer Error, *but* active and no HALT -> reload */
1006 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
1007 !(dw3 & DW3_HALT_BIT)) {
1008
1009 /* according to ppriv code, we have to
1010 * reload this one if trasfered bytes != requested bytes
1011 * else act like everything went smooth..
1012 * XXX This just doesn't feel right and hasn't
1013 * triggered so far.
1014 */
1015
1016 length = PTD_XFERRED_LENGTH(dw3);
1017 printk(KERN_ERR "Should reload now.... transfered %d "
1018 "of %zu\n", length, qtd->length);
1019 BUG();
1020 }
1021
1022 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
1023 u32 buffstatus;
1024
1025 /* XXX
1026 * NAKs are handled in HW by the chip. Usually if the
1027 * device is not able to send data fast enough.
1028 * This did not trigger for a long time now.
1029 */
1030 printk(KERN_ERR "Reloading ptd %p/%p... qh %p readed: "
1031 "%d of %zu done: %08x cur: %08x\n", qtd,
1032 urb, qh, PTD_XFERRED_LENGTH(dw3),
1033 qtd->length, done_map,
1034 (1 << queue_entry));
1035
1036 /* RL counter = ERR counter */
1037 dw3 &= ~(0xf << 19);
1038 dw3 |= rl << 19;
1039 dw3 &= ~(3 << (55 - 32));
1040 dw3 |= ERR_COUNTER << (55 - 32);
1041
1042 /*
1043 * It is not needed to write skip map back because it
1044 * is unchanged. Just make sure that this entry is
1045 * unskipped once it gets written to the HW.
1046 */
1047 skip_map &= ~(1 << queue_entry);
1048 or_map = isp1760_readl(usb_hcd->regs +
1049 HC_ATL_IRQ_MASK_OR_REG);
1050 or_map |= 1 << queue_entry;
1051 isp1760_writel(or_map, usb_hcd->regs +
1052 HC_ATL_IRQ_MASK_OR_REG);
1053
1054 ptd.dw3 = cpu_to_le32(dw3);
1055 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1056 atl_regs, sizeof(ptd));
1057
1058 ptd.dw0 |= __constant_cpu_to_le32(PTD_VALID);
1059 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1060 atl_regs, sizeof(ptd));
1061
1062 buffstatus = isp1760_readl(usb_hcd->regs +
1063 HC_BUFFER_STATUS_REG);
1064 buffstatus |= ATL_BUFFER;
1065 isp1760_writel(buffstatus, usb_hcd->regs +
1066 HC_BUFFER_STATUS_REG);
1067 continue;
1068 }
1069
1070 error = check_error(&ptd);
1071 if (error) {
1072 status = error;
1073 priv->atl_ints[queue_entry].qh->toggle = 0;
1074 priv->atl_ints[queue_entry].qh->ping = 0;
1075 urb->status = -EPIPE;
1076
1077 #if 0
1078 printk(KERN_ERR "Error in %s().\n", __func__);
1079 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1080 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1081 "%08x dw7: %08x\n",
1082 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1083 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1084 #endif
1085 } else {
1086 if (usb_pipetype(urb->pipe) == PIPE_BULK) {
1087 priv->atl_ints[queue_entry].qh->toggle = dw3 &
1088 (1 << 25);
1089 priv->atl_ints[queue_entry].qh->ping = dw3 &
1090 (1 << 26);
1091 }
1092 }
1093
1094 length = PTD_XFERRED_LENGTH(dw3);
1095 if (length) {
1096 switch (DW1_GET_PID(dw1)) {
1097 case IN_PID:
1098 priv_read_copy(priv,
1099 priv->atl_ints[queue_entry].data_buffer,
1100 usb_hcd->regs + payload + ISP_BANK(1),
1101 length);
1102
1103 case OUT_PID:
1104
1105 urb->actual_length += length;
1106
1107 case SETUP_PID:
1108 break;
1109 }
1110 }
1111
1112 priv->atl_ints[queue_entry].data_buffer = NULL;
1113 priv->atl_ints[queue_entry].urb = NULL;
1114 priv->atl_ints[queue_entry].qtd = NULL;
1115 priv->atl_ints[queue_entry].qh = NULL;
1116
1117 free_mem(priv, payload);
1118
1119 isp1760_writel(skip_map, usb_hcd->regs +
1120 HC_ATL_PTD_SKIPMAP_REG);
1121
1122 if (urb->status == -EPIPE) {
1123 /* HALT was received */
1124
1125 qtd = clean_up_qtdlist(qtd);
1126 isp1760_urb_done(priv, urb, urb->status);
1127
1128 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
1129 /* short BULK received */
1130
1131 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1132 urb->status = -EREMOTEIO;
1133 isp1760_dbg(priv, "short bulk, %d instead %zu "
1134 "with URB_SHORT_NOT_OK flag.\n",
1135 length, qtd->length);
1136 }
1137
1138 if (urb->status == -EINPROGRESS)
1139 urb->status = 0;
1140
1141 qtd = clean_up_qtdlist(qtd);
1142
1143 isp1760_urb_done(priv, urb, urb->status);
1144
1145 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1146 /* that was the last qtd of that URB */
1147
1148 if (urb->status == -EINPROGRESS)
1149 urb->status = 0;
1150
1151 qtd = clean_this_qtd(qtd);
1152 isp1760_urb_done(priv, urb, urb->status);
1153
1154 } else {
1155 /* next QTD of this URB */
1156
1157 qtd = clean_this_qtd(qtd);
1158 BUG_ON(!qtd);
1159 }
1160
1161 if (qtd)
1162 enqueue_an_ATL_packet(usb_hcd, qh, qtd);
1163
1164 skip_map = isp1760_readl(usb_hcd->regs +
1165 HC_ATL_PTD_SKIPMAP_REG);
1166 }
1167 }
1168
1169 static void do_intl_int(struct usb_hcd *usb_hcd)
1170 {
1171 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1172 u32 done_map, skip_map;
1173 struct ptd ptd;
1174 struct urb *urb = NULL;
1175 u32 int_regs;
1176 u32 int_regs_base;
1177 u32 payload;
1178 u32 length;
1179 u32 or_map;
1180 int error;
1181 u32 queue_entry;
1182 struct isp1760_qtd *qtd;
1183 struct isp1760_qh *qh;
1184
1185 done_map = isp1760_readl(usb_hcd->regs +
1186 HC_INT_PTD_DONEMAP_REG);
1187 skip_map = isp1760_readl(usb_hcd->regs +
1188 HC_INT_PTD_SKIPMAP_REG);
1189
1190 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1191 or_map &= ~done_map;
1192 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1193
1194 int_regs_base = INT_REGS_OFFSET;
1195
1196 while (done_map) {
1197 u32 dw1;
1198 u32 dw3;
1199
1200 queue_entry = __ffs(done_map);
1201 done_map &= ~(1 << queue_entry);
1202 skip_map |= 1 << queue_entry;
1203
1204 int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
1205 urb = priv->int_ints[queue_entry].urb;
1206 qtd = priv->int_ints[queue_entry].qtd;
1207 qh = priv->int_ints[queue_entry].qh;
1208 payload = priv->int_ints[queue_entry].payload;
1209
1210 if (!qh) {
1211 printk(KERN_ERR "(INT) qh is 0\n");
1212 continue;
1213 }
1214
1215 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
1216 HC_MEMORY_REG);
1217 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1218 HC_MEMORY_REG);
1219 /*
1220 * write bank1 address twice to ensure the 90ns delay (time
1221 * between BANK0 write and the priv_read_copy() call is at
1222 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
1223 */
1224 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1225 HC_MEMORY_REG);
1226
1227 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
1228 ISP_BANK(0), sizeof(ptd));
1229 dw1 = le32_to_cpu(ptd.dw1);
1230 dw3 = le32_to_cpu(ptd.dw3);
1231 check_int_err_status(le32_to_cpu(ptd.dw4));
1232
1233 error = check_error(&ptd);
1234 if (error) {
1235 #if 0
1236 printk(KERN_ERR "Error in %s().\n", __func__);
1237 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1238 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1239 "%08x dw7: %08x\n",
1240 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1241 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1242 #endif
1243 urb->status = -EPIPE;
1244 priv->int_ints[queue_entry].qh->toggle = 0;
1245 priv->int_ints[queue_entry].qh->ping = 0;
1246
1247 } else {
1248 priv->int_ints[queue_entry].qh->toggle =
1249 dw3 & (1 << 25);
1250 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
1251 }
1252
1253 if (urb->dev->speed != USB_SPEED_HIGH)
1254 length = PTD_XFERRED_LENGTH_LO(dw3);
1255 else
1256 length = PTD_XFERRED_LENGTH(dw3);
1257
1258 if (length) {
1259 switch (DW1_GET_PID(dw1)) {
1260 case IN_PID:
1261 priv_read_copy(priv,
1262 priv->int_ints[queue_entry].data_buffer,
1263 usb_hcd->regs + payload + ISP_BANK(1),
1264 length);
1265 case OUT_PID:
1266
1267 urb->actual_length += length;
1268
1269 case SETUP_PID:
1270 break;
1271 }
1272 }
1273
1274 priv->int_ints[queue_entry].data_buffer = NULL;
1275 priv->int_ints[queue_entry].urb = NULL;
1276 priv->int_ints[queue_entry].qtd = NULL;
1277 priv->int_ints[queue_entry].qh = NULL;
1278
1279 isp1760_writel(skip_map, usb_hcd->regs +
1280 HC_INT_PTD_SKIPMAP_REG);
1281 free_mem(priv, payload);
1282
1283 if (urb->status == -EPIPE) {
1284 /* HALT received */
1285
1286 qtd = clean_up_qtdlist(qtd);
1287 isp1760_urb_done(priv, urb, urb->status);
1288
1289 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1290
1291 if (urb->status == -EINPROGRESS)
1292 urb->status = 0;
1293
1294 qtd = clean_this_qtd(qtd);
1295 isp1760_urb_done(priv, urb, urb->status);
1296
1297 } else {
1298 /* next QTD of this URB */
1299
1300 qtd = clean_this_qtd(qtd);
1301 BUG_ON(!qtd);
1302 }
1303
1304 if (qtd)
1305 enqueue_an_INT_packet(usb_hcd, qh, qtd);
1306
1307 skip_map = isp1760_readl(usb_hcd->regs +
1308 HC_INT_PTD_SKIPMAP_REG);
1309 }
1310 }
1311
1312 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1313 static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1314 gfp_t flags)
1315 {
1316 struct isp1760_qh *qh;
1317 int is_input, type;
1318
1319 qh = isp1760_qh_alloc(priv, flags);
1320 if (!qh)
1321 return qh;
1322
1323 /*
1324 * init endpoint/device data for this QH
1325 */
1326 is_input = usb_pipein(urb->pipe);
1327 type = usb_pipetype(urb->pipe);
1328
1329 if (type == PIPE_INTERRUPT) {
1330
1331 if (urb->dev->speed == USB_SPEED_HIGH) {
1332
1333 qh->period = urb->interval >> 3;
1334 if (qh->period == 0 && urb->interval != 1) {
1335 /* NOTE interval 2 or 4 uframes could work.
1336 * But interval 1 scheduling is simpler, and
1337 * includes high bandwidth.
1338 */
1339 printk(KERN_ERR "intr period %d uframes, NYET!",
1340 urb->interval);
1341 qh_destroy(qh);
1342 return NULL;
1343 }
1344 } else {
1345 qh->period = urb->interval;
1346 }
1347 }
1348
1349 /* support for tt scheduling, and access to toggles */
1350 qh->dev = urb->dev;
1351
1352 if (!usb_pipecontrol(urb->pipe))
1353 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1354 1);
1355 return qh;
1356 }
1357
1358 /*
1359 * For control/bulk/interrupt, return QH with these TDs appended.
1360 * Allocates and initializes the QH if necessary.
1361 * Returns null if it can't allocate a QH it needs to.
1362 * If the QH has TDs (urbs) already, that's great.
1363 */
1364 static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
1365 struct urb *urb, struct list_head *qtd_list, int epnum,
1366 void **ptr)
1367 {
1368 struct isp1760_qh *qh;
1369 struct isp1760_qtd *qtd;
1370 struct isp1760_qtd *prev_qtd;
1371
1372 qh = (struct isp1760_qh *)*ptr;
1373 if (!qh) {
1374 /* can't sleep here, we have priv->lock... */
1375 qh = qh_make(priv, urb, GFP_ATOMIC);
1376 if (!qh)
1377 return qh;
1378 *ptr = qh;
1379 }
1380
1381 qtd = list_entry(qtd_list->next, struct isp1760_qtd,
1382 qtd_list);
1383 if (!list_empty(&qh->qtd_list))
1384 prev_qtd = list_entry(qh->qtd_list.prev,
1385 struct isp1760_qtd, qtd_list);
1386 else
1387 prev_qtd = NULL;
1388
1389 list_splice(qtd_list, qh->qtd_list.prev);
1390 if (prev_qtd) {
1391 BUG_ON(prev_qtd->hw_next);
1392 prev_qtd->hw_next = qtd;
1393 }
1394
1395 urb->hcpriv = qh;
1396 return qh;
1397 }
1398
1399 static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
1400 struct list_head *qtd_list)
1401 {
1402 struct list_head *entry, *temp;
1403
1404 list_for_each_safe(entry, temp, qtd_list) {
1405 struct isp1760_qtd *qtd;
1406
1407 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1408 list_del(&qtd->qtd_list);
1409 isp1760_qtd_free(qtd);
1410 }
1411 }
1412
1413 static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1414 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1415 {
1416 struct isp1760_qtd *qtd;
1417 int epnum;
1418 unsigned long flags;
1419 struct isp1760_qh *qh = NULL;
1420 int rc;
1421 int qh_busy;
1422
1423 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1424 epnum = urb->ep->desc.bEndpointAddress;
1425
1426 spin_lock_irqsave(&priv->lock, flags);
1427 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
1428 rc = -ESHUTDOWN;
1429 goto done;
1430 }
1431 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
1432 if (rc)
1433 goto done;
1434
1435 qh = urb->ep->hcpriv;
1436 if (qh)
1437 qh_busy = !list_empty(&qh->qtd_list);
1438 else
1439 qh_busy = 0;
1440
1441 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
1442 if (!qh) {
1443 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
1444 rc = -ENOMEM;
1445 goto done;
1446 }
1447
1448 if (!qh_busy)
1449 p(priv_to_hcd(priv), qh, qtd);
1450
1451 done:
1452 spin_unlock_irqrestore(&priv->lock, flags);
1453 if (!qh)
1454 qtd_list_free(priv, urb, qtd_list);
1455 return rc;
1456 }
1457
1458 static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
1459 gfp_t flags)
1460 {
1461 struct isp1760_qtd *qtd;
1462
1463 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1464 if (qtd)
1465 INIT_LIST_HEAD(&qtd->qtd_list);
1466
1467 return qtd;
1468 }
1469
1470 /*
1471 * create a list of filled qtds for this URB; won't link into qh.
1472 */
1473 static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1474 struct urb *urb, struct list_head *head, gfp_t flags)
1475 {
1476 struct isp1760_qtd *qtd, *qtd_prev;
1477 void *buf;
1478 int len, maxpacket;
1479 int is_input;
1480 u32 token;
1481
1482 /*
1483 * URBs map to sequences of QTDs: one logical transaction
1484 */
1485 qtd = isp1760_qtd_alloc(priv, flags);
1486 if (!qtd)
1487 return NULL;
1488
1489 list_add_tail(&qtd->qtd_list, head);
1490 qtd->urb = urb;
1491 urb->status = -EINPROGRESS;
1492
1493 token = 0;
1494 /* for split transactions, SplitXState initialized to zero */
1495
1496 len = urb->transfer_buffer_length;
1497 is_input = usb_pipein(urb->pipe);
1498 if (usb_pipecontrol(urb->pipe)) {
1499 /* SETUP pid */
1500 qtd_fill(qtd, urb->setup_packet,
1501 sizeof(struct usb_ctrlrequest),
1502 token | SETUP_PID);
1503
1504 /* ... and always at least one more pid */
1505 token ^= DATA_TOGGLE;
1506 qtd_prev = qtd;
1507 qtd = isp1760_qtd_alloc(priv, flags);
1508 if (!qtd)
1509 goto cleanup;
1510 qtd->urb = urb;
1511 qtd_prev->hw_next = qtd;
1512 list_add_tail(&qtd->qtd_list, head);
1513
1514 /* for zero length DATA stages, STATUS is always IN */
1515 if (len == 0)
1516 token |= IN_PID;
1517 }
1518
1519 /*
1520 * data transfer stage: buffer setup
1521 */
1522 buf = urb->transfer_buffer;
1523
1524 if (is_input)
1525 token |= IN_PID;
1526 else
1527 token |= OUT_PID;
1528
1529 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1530
1531 /*
1532 * buffer gets wrapped in one or more qtds;
1533 * last one may be "short" (including zero len)
1534 * and may serve as a control status ack
1535 */
1536 for (;;) {
1537 int this_qtd_len;
1538
1539 if (!buf && len) {
1540 /* XXX This looks like usb storage / SCSI bug */
1541 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
1542 (long unsigned)urb->transfer_dma, len);
1543 WARN_ON(1);
1544 }
1545
1546 this_qtd_len = qtd_fill(qtd, buf, len, token);
1547 len -= this_qtd_len;
1548 buf += this_qtd_len;
1549
1550 /* qh makes control packets use qtd toggle; maybe switch it */
1551 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1552 token ^= DATA_TOGGLE;
1553
1554 if (len <= 0)
1555 break;
1556
1557 qtd_prev = qtd;
1558 qtd = isp1760_qtd_alloc(priv, flags);
1559 if (!qtd)
1560 goto cleanup;
1561 qtd->urb = urb;
1562 qtd_prev->hw_next = qtd;
1563 list_add_tail(&qtd->qtd_list, head);
1564 }
1565
1566 /*
1567 * control requests may need a terminating data "status" ack;
1568 * bulk ones may need a terminating short packet (zero length).
1569 */
1570 if (urb->transfer_buffer_length != 0) {
1571 int one_more = 0;
1572
1573 if (usb_pipecontrol(urb->pipe)) {
1574 one_more = 1;
1575 /* "in" <--> "out" */
1576 token ^= IN_PID;
1577 /* force DATA1 */
1578 token |= DATA_TOGGLE;
1579 } else if (usb_pipebulk(urb->pipe)
1580 && (urb->transfer_flags & URB_ZERO_PACKET)
1581 && !(urb->transfer_buffer_length % maxpacket)) {
1582 one_more = 1;
1583 }
1584 if (one_more) {
1585 qtd_prev = qtd;
1586 qtd = isp1760_qtd_alloc(priv, flags);
1587 if (!qtd)
1588 goto cleanup;
1589 qtd->urb = urb;
1590 qtd_prev->hw_next = qtd;
1591 list_add_tail(&qtd->qtd_list, head);
1592
1593 /* never any data in such packets */
1594 qtd_fill(qtd, NULL, 0, token);
1595 }
1596 }
1597
1598 qtd->status = URB_COMPLETE_NOTIFY;
1599 return head;
1600
1601 cleanup:
1602 qtd_list_free(priv, urb, head);
1603 return NULL;
1604 }
1605
1606 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1607 gfp_t mem_flags)
1608 {
1609 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1610 struct list_head qtd_list;
1611 packet_enqueue *pe;
1612
1613 INIT_LIST_HEAD(&qtd_list);
1614
1615 switch (usb_pipetype(urb->pipe)) {
1616 case PIPE_CONTROL:
1617 case PIPE_BULK:
1618
1619 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1620 return -ENOMEM;
1621 pe = enqueue_an_ATL_packet;
1622 break;
1623
1624 case PIPE_INTERRUPT:
1625 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1626 return -ENOMEM;
1627 pe = enqueue_an_INT_packet;
1628 break;
1629
1630 case PIPE_ISOCHRONOUS:
1631 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
1632 default:
1633 return -EPIPE;
1634 }
1635
1636 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
1637 }
1638
1639 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1640 int status)
1641 {
1642 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1643 struct inter_packet_info *ints;
1644 u32 i;
1645 u32 reg_base, or_reg, skip_reg;
1646 unsigned long flags;
1647 struct ptd ptd;
1648
1649 switch (usb_pipetype(urb->pipe)) {
1650 case PIPE_ISOCHRONOUS:
1651 return -EPIPE;
1652 break;
1653
1654 case PIPE_INTERRUPT:
1655 ints = priv->int_ints;
1656 reg_base = INT_REGS_OFFSET;
1657 or_reg = HC_INT_IRQ_MASK_OR_REG;
1658 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1659 break;
1660
1661 default:
1662 ints = priv->atl_ints;
1663 reg_base = ATL_REGS_OFFSET;
1664 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1665 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1666 break;
1667 }
1668
1669 memset(&ptd, 0, sizeof(ptd));
1670 spin_lock_irqsave(&priv->lock, flags);
1671
1672 for (i = 0; i < 32; i++) {
1673 if (ints->urb == urb) {
1674 u32 skip_map;
1675 u32 or_map;
1676 struct isp1760_qtd *qtd;
1677
1678 skip_map = isp1760_readl(hcd->regs + skip_reg);
1679 skip_map |= 1 << i;
1680 isp1760_writel(skip_map, hcd->regs + skip_reg);
1681
1682 or_map = isp1760_readl(hcd->regs + or_reg);
1683 or_map &= ~(1 << i);
1684 isp1760_writel(or_map, hcd->regs + or_reg);
1685
1686 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
1687 + i * sizeof(ptd), sizeof(ptd));
1688 qtd = ints->qtd;
1689
1690 clean_up_qtdlist(qtd);
1691
1692 free_mem(priv, ints->payload);
1693
1694 ints->urb = NULL;
1695 ints->qh = NULL;
1696 ints->qtd = NULL;
1697 ints->data_buffer = NULL;
1698 ints->payload = 0;
1699
1700 isp1760_urb_done(priv, urb, status);
1701 break;
1702 }
1703 ints++;
1704 }
1705
1706 spin_unlock_irqrestore(&priv->lock, flags);
1707 return 0;
1708 }
1709
1710 static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
1711 {
1712 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1713 u32 imask;
1714 irqreturn_t irqret = IRQ_NONE;
1715
1716 spin_lock(&priv->lock);
1717
1718 if (!(usb_hcd->state & HC_STATE_RUNNING))
1719 goto leave;
1720
1721 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
1722 if (unlikely(!imask))
1723 goto leave;
1724
1725 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
1726 if (imask & HC_ATL_INT)
1727 do_atl_int(usb_hcd);
1728
1729 if (imask & HC_INTL_INT)
1730 do_intl_int(usb_hcd);
1731
1732 irqret = IRQ_HANDLED;
1733 leave:
1734 spin_unlock(&priv->lock);
1735 return irqret;
1736 }
1737
1738 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1739 {
1740 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1741 u32 temp, status = 0;
1742 u32 mask;
1743 int retval = 1;
1744 unsigned long flags;
1745
1746 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1747 if (!HC_IS_RUNNING(hcd->state))
1748 return 0;
1749
1750 /* init status to no-changes */
1751 buf[0] = 0;
1752 mask = PORT_CSC;
1753
1754 spin_lock_irqsave(&priv->lock, flags);
1755 temp = isp1760_readl(hcd->regs + HC_PORTSC1);
1756
1757 if (temp & PORT_OWNER) {
1758 if (temp & PORT_CSC) {
1759 temp &= ~PORT_CSC;
1760 isp1760_writel(temp, hcd->regs + HC_PORTSC1);
1761 goto done;
1762 }
1763 }
1764
1765 /*
1766 * Return status information even for ports with OWNER set.
1767 * Otherwise khubd wouldn't see the disconnect event when a
1768 * high-speed device is switched over to the companion
1769 * controller by the user.
1770 */
1771
1772 if ((temp & mask) != 0
1773 || ((temp & PORT_RESUME) != 0
1774 && time_after_eq(jiffies,
1775 priv->reset_done))) {
1776 buf [0] |= 1 << (0 + 1);
1777 status = STS_PCD;
1778 }
1779 /* FIXME autosuspend idle root hubs */
1780 done:
1781 spin_unlock_irqrestore(&priv->lock, flags);
1782 return status ? retval : 0;
1783 }
1784
1785 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1786 struct usb_hub_descriptor *desc)
1787 {
1788 int ports = HCS_N_PORTS(priv->hcs_params);
1789 u16 temp;
1790
1791 desc->bDescriptorType = 0x29;
1792 /* priv 1.0, 2.3.9 says 20ms max */
1793 desc->bPwrOn2PwrGood = 10;
1794 desc->bHubContrCurrent = 0;
1795
1796 desc->bNbrPorts = ports;
1797 temp = 1 + (ports / 8);
1798 desc->bDescLength = 7 + 2 * temp;
1799
1800 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1801 memset(&desc->bitmap[0], 0, temp);
1802 memset(&desc->bitmap[temp], 0xff, temp);
1803
1804 /* per-port overcurrent reporting */
1805 temp = 0x0008;
1806 if (HCS_PPC(priv->hcs_params))
1807 /* per-port power control */
1808 temp |= 0x0001;
1809 else
1810 /* no power switching */
1811 temp |= 0x0002;
1812 desc->wHubCharacteristics = cpu_to_le16(temp);
1813 }
1814
1815 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1816
1817 static int check_reset_complete(struct isp1760_hcd *priv, int index,
1818 u32 __iomem *status_reg, int port_status)
1819 {
1820 if (!(port_status & PORT_CONNECT))
1821 return port_status;
1822
1823 /* if reset finished and it's still not enabled -- handoff */
1824 if (!(port_status & PORT_PE)) {
1825
1826 printk(KERN_ERR "port %d full speed --> companion\n",
1827 index + 1);
1828
1829 port_status |= PORT_OWNER;
1830 port_status &= ~PORT_RWC_BITS;
1831 isp1760_writel(port_status, status_reg);
1832
1833 } else
1834 printk(KERN_ERR "port %d high speed\n", index + 1);
1835
1836 return port_status;
1837 }
1838
1839 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1840 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1841 {
1842 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1843 int ports = HCS_N_PORTS(priv->hcs_params);
1844 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
1845 u32 temp, status;
1846 unsigned long flags;
1847 int retval = 0;
1848 unsigned selector;
1849
1850 /*
1851 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1852 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1853 * (track current state ourselves) ... blink for diagnostics,
1854 * power, "this is the one", etc. EHCI spec supports this.
1855 */
1856
1857 spin_lock_irqsave(&priv->lock, flags);
1858 switch (typeReq) {
1859 case ClearHubFeature:
1860 switch (wValue) {
1861 case C_HUB_LOCAL_POWER:
1862 case C_HUB_OVER_CURRENT:
1863 /* no hub-wide feature/status flags */
1864 break;
1865 default:
1866 goto error;
1867 }
1868 break;
1869 case ClearPortFeature:
1870 if (!wIndex || wIndex > ports)
1871 goto error;
1872 wIndex--;
1873 temp = isp1760_readl(status_reg);
1874
1875 /*
1876 * Even if OWNER is set, so the port is owned by the
1877 * companion controller, khubd needs to be able to clear
1878 * the port-change status bits (especially
1879 * USB_PORT_FEAT_C_CONNECTION).
1880 */
1881
1882 switch (wValue) {
1883 case USB_PORT_FEAT_ENABLE:
1884 isp1760_writel(temp & ~PORT_PE, status_reg);
1885 break;
1886 case USB_PORT_FEAT_C_ENABLE:
1887 /* XXX error? */
1888 break;
1889 case USB_PORT_FEAT_SUSPEND:
1890 if (temp & PORT_RESET)
1891 goto error;
1892
1893 if (temp & PORT_SUSPEND) {
1894 if ((temp & PORT_PE) == 0)
1895 goto error;
1896 /* resume signaling for 20 msec */
1897 temp &= ~(PORT_RWC_BITS);
1898 isp1760_writel(temp | PORT_RESUME,
1899 status_reg);
1900 priv->reset_done = jiffies +
1901 msecs_to_jiffies(20);
1902 }
1903 break;
1904 case USB_PORT_FEAT_C_SUSPEND:
1905 /* we auto-clear this feature */
1906 break;
1907 case USB_PORT_FEAT_POWER:
1908 if (HCS_PPC(priv->hcs_params))
1909 isp1760_writel(temp & ~PORT_POWER, status_reg);
1910 break;
1911 case USB_PORT_FEAT_C_CONNECTION:
1912 isp1760_writel(temp | PORT_CSC,
1913 status_reg);
1914 break;
1915 case USB_PORT_FEAT_C_OVER_CURRENT:
1916 /* XXX error ?*/
1917 break;
1918 case USB_PORT_FEAT_C_RESET:
1919 /* GetPortStatus clears reset */
1920 break;
1921 default:
1922 goto error;
1923 }
1924 isp1760_readl(hcd->regs + HC_USBCMD);
1925 break;
1926 case GetHubDescriptor:
1927 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1928 buf);
1929 break;
1930 case GetHubStatus:
1931 /* no hub-wide feature/status flags */
1932 memset(buf, 0, 4);
1933 break;
1934 case GetPortStatus:
1935 if (!wIndex || wIndex > ports)
1936 goto error;
1937 wIndex--;
1938 status = 0;
1939 temp = isp1760_readl(status_reg);
1940
1941 /* wPortChange bits */
1942 if (temp & PORT_CSC)
1943 status |= 1 << USB_PORT_FEAT_C_CONNECTION;
1944
1945
1946 /* whoever resumes must GetPortStatus to complete it!! */
1947 if (temp & PORT_RESUME) {
1948 printk(KERN_ERR "Port resume should be skipped.\n");
1949
1950 /* Remote Wakeup received? */
1951 if (!priv->reset_done) {
1952 /* resume signaling for 20 msec */
1953 priv->reset_done = jiffies
1954 + msecs_to_jiffies(20);
1955 /* check the port again */
1956 mod_timer(&priv_to_hcd(priv)->rh_timer,
1957 priv->reset_done);
1958 }
1959
1960 /* resume completed? */
1961 else if (time_after_eq(jiffies,
1962 priv->reset_done)) {
1963 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
1964 priv->reset_done = 0;
1965
1966 /* stop resume signaling */
1967 temp = isp1760_readl(status_reg);
1968 isp1760_writel(
1969 temp & ~(PORT_RWC_BITS | PORT_RESUME),
1970 status_reg);
1971 retval = handshake(priv, status_reg,
1972 PORT_RESUME, 0, 2000 /* 2msec */);
1973 if (retval != 0) {
1974 isp1760_err(priv,
1975 "port %d resume error %d\n",
1976 wIndex + 1, retval);
1977 goto error;
1978 }
1979 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1980 }
1981 }
1982
1983 /* whoever resets must GetPortStatus to complete it!! */
1984 if ((temp & PORT_RESET)
1985 && time_after_eq(jiffies,
1986 priv->reset_done)) {
1987 status |= 1 << USB_PORT_FEAT_C_RESET;
1988 priv->reset_done = 0;
1989
1990 /* force reset to complete */
1991 isp1760_writel(temp & ~PORT_RESET,
1992 status_reg);
1993 /* REVISIT: some hardware needs 550+ usec to clear
1994 * this bit; seems too long to spin routinely...
1995 */
1996 retval = handshake(priv, status_reg,
1997 PORT_RESET, 0, 750);
1998 if (retval != 0) {
1999 isp1760_err(priv, "port %d reset error %d\n",
2000 wIndex + 1, retval);
2001 goto error;
2002 }
2003
2004 /* see what we found out */
2005 temp = check_reset_complete(priv, wIndex, status_reg,
2006 isp1760_readl(status_reg));
2007 }
2008 /*
2009 * Even if OWNER is set, there's no harm letting khubd
2010 * see the wPortStatus values (they should all be 0 except
2011 * for PORT_POWER anyway).
2012 */
2013
2014 if (temp & PORT_OWNER)
2015 printk(KERN_ERR "Warning: PORT_OWNER is set\n");
2016
2017 if (temp & PORT_CONNECT) {
2018 status |= 1 << USB_PORT_FEAT_CONNECTION;
2019 /* status may be from integrated TT */
2020 status |= ehci_port_speed(priv, temp);
2021 }
2022 if (temp & PORT_PE)
2023 status |= 1 << USB_PORT_FEAT_ENABLE;
2024 if (temp & (PORT_SUSPEND|PORT_RESUME))
2025 status |= 1 << USB_PORT_FEAT_SUSPEND;
2026 if (temp & PORT_RESET)
2027 status |= 1 << USB_PORT_FEAT_RESET;
2028 if (temp & PORT_POWER)
2029 status |= 1 << USB_PORT_FEAT_POWER;
2030
2031 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2032 break;
2033 case SetHubFeature:
2034 switch (wValue) {
2035 case C_HUB_LOCAL_POWER:
2036 case C_HUB_OVER_CURRENT:
2037 /* no hub-wide feature/status flags */
2038 break;
2039 default:
2040 goto error;
2041 }
2042 break;
2043 case SetPortFeature:
2044 selector = wIndex >> 8;
2045 wIndex &= 0xff;
2046 if (!wIndex || wIndex > ports)
2047 goto error;
2048 wIndex--;
2049 temp = isp1760_readl(status_reg);
2050 if (temp & PORT_OWNER)
2051 break;
2052
2053 /* temp &= ~PORT_RWC_BITS; */
2054 switch (wValue) {
2055 case USB_PORT_FEAT_ENABLE:
2056 isp1760_writel(temp | PORT_PE, status_reg);
2057 break;
2058
2059 case USB_PORT_FEAT_SUSPEND:
2060 if ((temp & PORT_PE) == 0
2061 || (temp & PORT_RESET) != 0)
2062 goto error;
2063
2064 isp1760_writel(temp | PORT_SUSPEND, status_reg);
2065 break;
2066 case USB_PORT_FEAT_POWER:
2067 if (HCS_PPC(priv->hcs_params))
2068 isp1760_writel(temp | PORT_POWER,
2069 status_reg);
2070 break;
2071 case USB_PORT_FEAT_RESET:
2072 if (temp & PORT_RESUME)
2073 goto error;
2074 /* line status bits may report this as low speed,
2075 * which can be fine if this root hub has a
2076 * transaction translator built in.
2077 */
2078 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2079 && PORT_USB11(temp)) {
2080 temp |= PORT_OWNER;
2081 } else {
2082 temp |= PORT_RESET;
2083 temp &= ~PORT_PE;
2084
2085 /*
2086 * caller must wait, then call GetPortStatus
2087 * usb 2.0 spec says 50 ms resets on root
2088 */
2089 priv->reset_done = jiffies +
2090 msecs_to_jiffies(50);
2091 }
2092 isp1760_writel(temp, status_reg);
2093 break;
2094 default:
2095 goto error;
2096 }
2097 isp1760_readl(hcd->regs + HC_USBCMD);
2098 break;
2099
2100 default:
2101 error:
2102 /* "stall" on error */
2103 retval = -EPIPE;
2104 }
2105 spin_unlock_irqrestore(&priv->lock, flags);
2106 return retval;
2107 }
2108
2109 static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
2110 struct usb_host_endpoint *ep)
2111 {
2112 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
2113 struct isp1760_qh *qh;
2114 struct isp1760_qtd *qtd;
2115 unsigned long flags;
2116
2117 spin_lock_irqsave(&priv->lock, flags);
2118 qh = ep->hcpriv;
2119 if (!qh)
2120 goto out;
2121
2122 ep->hcpriv = NULL;
2123 do {
2124 /* more than entry might get removed */
2125 if (list_empty(&qh->qtd_list))
2126 break;
2127
2128 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2129 qtd_list);
2130
2131 if (qtd->status & URB_ENQUEUED) {
2132
2133 spin_unlock_irqrestore(&priv->lock, flags);
2134 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
2135 spin_lock_irqsave(&priv->lock, flags);
2136 } else {
2137 struct urb *urb;
2138
2139 urb = qtd->urb;
2140 clean_up_qtdlist(qtd);
2141 isp1760_urb_done(priv, urb, -ECONNRESET);
2142 }
2143 } while (1);
2144
2145 qh_destroy(qh);
2146 /* remove requests and leak them.
2147 * ATL are pretty fast done, INT could take a while...
2148 * The latter shoule be removed
2149 */
2150 out:
2151 spin_unlock_irqrestore(&priv->lock, flags);
2152 }
2153
2154 static int isp1760_get_frame(struct usb_hcd *hcd)
2155 {
2156 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2157 u32 fr;
2158
2159 fr = isp1760_readl(hcd->regs + HC_FRINDEX);
2160 return (fr >> 3) % priv->periodic_size;
2161 }
2162
2163 static void isp1760_stop(struct usb_hcd *hcd)
2164 {
2165 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2166 u32 temp;
2167
2168 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2169 NULL, 0);
2170 mdelay(20);
2171
2172 spin_lock_irq(&priv->lock);
2173 ehci_reset(priv);
2174 /* Disable IRQ */
2175 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2176 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
2177 spin_unlock_irq(&priv->lock);
2178
2179 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
2180 }
2181
2182 static void isp1760_shutdown(struct usb_hcd *hcd)
2183 {
2184 u32 command, temp;
2185
2186 isp1760_stop(hcd);
2187 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2188 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
2189
2190 command = isp1760_readl(hcd->regs + HC_USBCMD);
2191 command &= ~CMD_RUN;
2192 isp1760_writel(command, hcd->regs + HC_USBCMD);
2193 }
2194
2195 static const struct hc_driver isp1760_hc_driver = {
2196 .description = "isp1760-hcd",
2197 .product_desc = "NXP ISP1760 USB Host Controller",
2198 .hcd_priv_size = sizeof(struct isp1760_hcd),
2199 .irq = isp1760_irq,
2200 .flags = HCD_MEMORY | HCD_USB2,
2201 .reset = isp1760_hc_setup,
2202 .start = isp1760_run,
2203 .stop = isp1760_stop,
2204 .shutdown = isp1760_shutdown,
2205 .urb_enqueue = isp1760_urb_enqueue,
2206 .urb_dequeue = isp1760_urb_dequeue,
2207 .endpoint_disable = isp1760_endpoint_disable,
2208 .get_frame_number = isp1760_get_frame,
2209 .hub_status_data = isp1760_hub_status_data,
2210 .hub_control = isp1760_hub_control,
2211 };
2212
2213 int __init init_kmem_once(void)
2214 {
2215 qtd_cachep = kmem_cache_create("isp1760_qtd",
2216 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2217 SLAB_MEM_SPREAD, NULL);
2218
2219 if (!qtd_cachep)
2220 return -ENOMEM;
2221
2222 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2223 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2224
2225 if (!qh_cachep) {
2226 kmem_cache_destroy(qtd_cachep);
2227 return -ENOMEM;
2228 }
2229
2230 return 0;
2231 }
2232
2233 void deinit_kmem_cache(void)
2234 {
2235 kmem_cache_destroy(qtd_cachep);
2236 kmem_cache_destroy(qh_cachep);
2237 }
2238
2239 struct usb_hcd *isp1760_register(u64 res_start, u64 res_len, int irq,
2240 u64 irqflags, struct device *dev, const char *busname,
2241 unsigned int devflags)
2242 {
2243 struct usb_hcd *hcd;
2244 struct isp1760_hcd *priv;
2245 int ret;
2246
2247 if (usb_disabled())
2248 return ERR_PTR(-ENODEV);
2249
2250 /* prevent usb-core allocating DMA pages */
2251 dev->dma_mask = NULL;
2252
2253 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2254 if (!hcd)
2255 return ERR_PTR(-ENOMEM);
2256
2257 priv = hcd_to_priv(hcd);
2258 priv->devflags = devflags;
2259 init_memory(priv);
2260 hcd->regs = ioremap(res_start, res_len);
2261 if (!hcd->regs) {
2262 ret = -EIO;
2263 goto err_put;
2264 }
2265
2266 hcd->irq = irq;
2267 hcd->rsrc_start = res_start;
2268 hcd->rsrc_len = res_len;
2269
2270 ret = usb_add_hcd(hcd, irq, irqflags);
2271 if (ret)
2272 goto err_unmap;
2273
2274 return hcd;
2275
2276 err_unmap:
2277 iounmap(hcd->regs);
2278
2279 err_put:
2280 usb_put_hcd(hcd);
2281
2282 return ERR_PTR(ret);
2283 }
2284
2285 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2286 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2287 MODULE_LICENSE("GPL v2");
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