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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / ixgbe / ixgbe_ethtool.c
blobfa314cb005a4dcf15ce8884c0da5e9987f1e2604
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 struct ixgbe_stats {
44 char stat_string[ETH_GSTRING_LEN];
45 int sizeof_stat;
46 int stat_offset;
47 };
48
49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
50 offsetof(struct ixgbe_adapter, m)
51 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
52 {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
53 {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
54 {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
55 {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
56 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
57 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
58 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
59 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
60 {"lsc_int", IXGBE_STAT(lsc_int)},
61 {"tx_busy", IXGBE_STAT(tx_busy)},
62 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
63 {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
64 {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
65 {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
66 {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
67 {"multicast", IXGBE_STAT(net_stats.multicast)},
68 {"broadcast", IXGBE_STAT(stats.bprc)},
69 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
70 {"collisions", IXGBE_STAT(net_stats.collisions)},
71 {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
72 {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
73 {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
74 {"hw_rsc_count", IXGBE_STAT(rsc_count)},
75 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
76 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
77 {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
78 {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
79 {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
80 {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
81 {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
82 {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
83 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
84 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
85 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
86 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
87 {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
88 {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
89 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
90 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
91 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
92 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
93 {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
94 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
95 {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
96 {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
97 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
98 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
99 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
100 #ifdef IXGBE_FCOE
101 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
102 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
103 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
104 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
105 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
106 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
107 #endif /* IXGBE_FCOE */
108 };
109
110 #define IXGBE_QUEUE_STATS_LEN \
111 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
112 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
113 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
114 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
115 #define IXGBE_PB_STATS_LEN ( \
116 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
117 IXGBE_FLAG_DCB_ENABLED) ? \
118 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
119 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
120 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
121 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
122 / sizeof(u64) : 0)
123 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
124 IXGBE_PB_STATS_LEN + \
125 IXGBE_QUEUE_STATS_LEN)
126
127 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
128 "Register test (offline)", "Eeprom test (offline)",
129 "Interrupt test (offline)", "Loopback test (offline)",
130 "Link test (on/offline)"
131 };
132 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
133
134 static int ixgbe_get_settings(struct net_device *netdev,
135 struct ethtool_cmd *ecmd)
136 {
137 struct ixgbe_adapter *adapter = netdev_priv(netdev);
138 struct ixgbe_hw *hw = &adapter->hw;
139 u32 link_speed = 0;
140 bool link_up;
141
142 ecmd->supported = SUPPORTED_10000baseT_Full;
143 ecmd->autoneg = AUTONEG_ENABLE;
144 ecmd->transceiver = XCVR_EXTERNAL;
145 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
146 (hw->phy.multispeed_fiber)) {
147 ecmd->supported |= (SUPPORTED_1000baseT_Full |
148 SUPPORTED_Autoneg);
149
150 ecmd->advertising = ADVERTISED_Autoneg;
151 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
152 ecmd->advertising |= ADVERTISED_10000baseT_Full;
153 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
154 ecmd->advertising |= ADVERTISED_1000baseT_Full;
155 /*
156 * It's possible that phy.autoneg_advertised may not be
157 * set yet. If so display what the default would be -
158 * both 1G and 10G supported.
159 */
160 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
161 ADVERTISED_10000baseT_Full)))
162 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
163 ADVERTISED_1000baseT_Full);
164
165 if (hw->phy.media_type == ixgbe_media_type_copper) {
166 ecmd->supported |= SUPPORTED_TP;
167 ecmd->advertising |= ADVERTISED_TP;
168 ecmd->port = PORT_TP;
169 } else {
170 ecmd->supported |= SUPPORTED_FIBRE;
171 ecmd->advertising |= ADVERTISED_FIBRE;
172 ecmd->port = PORT_FIBRE;
173 }
174 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
175 /* Set as FIBRE until SERDES defined in kernel */
176 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
177 ecmd->supported = (SUPPORTED_1000baseT_Full |
178 SUPPORTED_FIBRE);
179 ecmd->advertising = (ADVERTISED_1000baseT_Full |
180 ADVERTISED_FIBRE);
181 ecmd->port = PORT_FIBRE;
182 ecmd->autoneg = AUTONEG_DISABLE;
183 } else {
184 ecmd->supported |= (SUPPORTED_1000baseT_Full |
185 SUPPORTED_FIBRE);
186 ecmd->advertising = (ADVERTISED_10000baseT_Full |
187 ADVERTISED_1000baseT_Full |
188 ADVERTISED_FIBRE);
189 ecmd->port = PORT_FIBRE;
190 }
191 } else {
192 ecmd->supported |= SUPPORTED_FIBRE;
193 ecmd->advertising = (ADVERTISED_10000baseT_Full |
194 ADVERTISED_FIBRE);
195 ecmd->port = PORT_FIBRE;
196 ecmd->autoneg = AUTONEG_DISABLE;
197 }
198
199 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
200 if (link_up) {
201 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
202 SPEED_10000 : SPEED_1000;
203 ecmd->duplex = DUPLEX_FULL;
204 } else {
205 ecmd->speed = -1;
206 ecmd->duplex = -1;
207 }
208
209 return 0;
210 }
211
212 static int ixgbe_set_settings(struct net_device *netdev,
213 struct ethtool_cmd *ecmd)
214 {
215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
216 struct ixgbe_hw *hw = &adapter->hw;
217 u32 advertised, old;
218 s32 err = 0;
219
220 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
221 (hw->phy.multispeed_fiber)) {
222 /* 10000/copper and 1000/copper must autoneg
223 * this function does not support any duplex forcing, but can
224 * limit the advertising of the adapter to only 10000 or 1000 */
225 if (ecmd->autoneg == AUTONEG_DISABLE)
226 return -EINVAL;
227
228 old = hw->phy.autoneg_advertised;
229 advertised = 0;
230 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
231 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
232
233 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
234 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
235
236 if (old == advertised)
237 return err;
238 /* this sets the link speed and restarts auto-neg */
239 hw->mac.autotry_restart = true;
240 err = hw->mac.ops.setup_link(hw, advertised, true, true);
241 if (err) {
242 DPRINTK(PROBE, INFO,
243 "setup link failed with code %d\n", err);
244 hw->mac.ops.setup_link(hw, old, true, true);
245 }
246 } else {
247 /* in this case we currently only support 10Gb/FULL */
248 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
249 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
250 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
251 return -EINVAL;
252 }
253
254 return err;
255 }
256
257 static void ixgbe_get_pauseparam(struct net_device *netdev,
258 struct ethtool_pauseparam *pause)
259 {
260 struct ixgbe_adapter *adapter = netdev_priv(netdev);
261 struct ixgbe_hw *hw = &adapter->hw;
262
263 /*
264 * Flow Control Autoneg isn't on if
265 * - we didn't ask for it OR
266 * - it failed, we know this by tx & rx being off
267 */
268 if (hw->fc.disable_fc_autoneg ||
269 (hw->fc.current_mode == ixgbe_fc_none))
270 pause->autoneg = 0;
271 else
272 pause->autoneg = 1;
273
274 #ifdef CONFIG_DCB
275 if (hw->fc.current_mode == ixgbe_fc_pfc) {
276 pause->rx_pause = 0;
277 pause->tx_pause = 0;
278 }
279
280 #endif
281 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
282 pause->rx_pause = 1;
283 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
284 pause->tx_pause = 1;
285 } else if (hw->fc.current_mode == ixgbe_fc_full) {
286 pause->rx_pause = 1;
287 pause->tx_pause = 1;
288 }
289 }
290
291 static int ixgbe_set_pauseparam(struct net_device *netdev,
292 struct ethtool_pauseparam *pause)
293 {
294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
295 struct ixgbe_hw *hw = &adapter->hw;
296 struct ixgbe_fc_info fc;
297
298 #ifdef CONFIG_DCB
299 if (adapter->dcb_cfg.pfc_mode_enable ||
300 ((hw->mac.type == ixgbe_mac_82598EB) &&
301 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
302 return -EINVAL;
303
304 #endif
305
306 fc = hw->fc;
307
308 if (pause->autoneg != AUTONEG_ENABLE)
309 fc.disable_fc_autoneg = true;
310 else
311 fc.disable_fc_autoneg = false;
312
313 if (pause->rx_pause && pause->tx_pause)
314 fc.requested_mode = ixgbe_fc_full;
315 else if (pause->rx_pause && !pause->tx_pause)
316 fc.requested_mode = ixgbe_fc_rx_pause;
317 else if (!pause->rx_pause && pause->tx_pause)
318 fc.requested_mode = ixgbe_fc_tx_pause;
319 else if (!pause->rx_pause && !pause->tx_pause)
320 fc.requested_mode = ixgbe_fc_none;
321 else
322 return -EINVAL;
323
324 #ifdef CONFIG_DCB
325 adapter->last_lfc_mode = fc.requested_mode;
326 #endif
327
328 /* if the thing changed then we'll update and use new autoneg */
329 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
330 hw->fc = fc;
331 if (netif_running(netdev))
332 ixgbe_reinit_locked(adapter);
333 else
334 ixgbe_reset(adapter);
335 }
336
337 return 0;
338 }
339
340 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
341 {
342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
343 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
344 }
345
346 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
347 {
348 struct ixgbe_adapter *adapter = netdev_priv(netdev);
349 if (data)
350 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
351 else
352 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
353
354 if (netif_running(netdev))
355 ixgbe_reinit_locked(adapter);
356 else
357 ixgbe_reset(adapter);
358
359 return 0;
360 }
361
362 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
363 {
364 return (netdev->features & NETIF_F_IP_CSUM) != 0;
365 }
366
367 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
368 {
369 struct ixgbe_adapter *adapter = netdev_priv(netdev);
370
371 if (data) {
372 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
373 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
374 netdev->features |= NETIF_F_SCTP_CSUM;
375 } else {
376 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
377 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
378 netdev->features &= ~NETIF_F_SCTP_CSUM;
379 }
380
381 return 0;
382 }
383
384 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
385 {
386 if (data) {
387 netdev->features |= NETIF_F_TSO;
388 netdev->features |= NETIF_F_TSO6;
389 } else {
390 netif_tx_stop_all_queues(netdev);
391 netdev->features &= ~NETIF_F_TSO;
392 netdev->features &= ~NETIF_F_TSO6;
393 netif_tx_start_all_queues(netdev);
394 }
395 return 0;
396 }
397
398 static u32 ixgbe_get_msglevel(struct net_device *netdev)
399 {
400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
401 return adapter->msg_enable;
402 }
403
404 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
405 {
406 struct ixgbe_adapter *adapter = netdev_priv(netdev);
407 adapter->msg_enable = data;
408 }
409
410 static int ixgbe_get_regs_len(struct net_device *netdev)
411 {
412 #define IXGBE_REGS_LEN 1128
413 return IXGBE_REGS_LEN * sizeof(u32);
414 }
415
416 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
417
418 static void ixgbe_get_regs(struct net_device *netdev,
419 struct ethtool_regs *regs, void *p)
420 {
421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
422 struct ixgbe_hw *hw = &adapter->hw;
423 u32 *regs_buff = p;
424 u8 i;
425
426 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
427
428 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
429
430 /* General Registers */
431 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
432 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
433 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
434 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
435 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
436 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
437 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
438 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
439
440 /* NVM Register */
441 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
442 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
443 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
444 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
445 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
446 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
447 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
448 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
449 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
450 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
451
452 /* Interrupt */
453 /* don't read EICR because it can clear interrupt causes, instead
454 * read EICS which is a shadow but doesn't clear EICR */
455 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
456 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
457 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
458 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
459 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
460 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
461 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
462 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
463 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
464 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
465 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
466 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
467
468 /* Flow Control */
469 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
470 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
471 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
472 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
473 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
474 for (i = 0; i < 8; i++)
475 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
476 for (i = 0; i < 8; i++)
477 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
478 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
479 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
480
481 /* Receive DMA */
482 for (i = 0; i < 64; i++)
483 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 for (i = 0; i < 64; i++)
485 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
486 for (i = 0; i < 64; i++)
487 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
488 for (i = 0; i < 64; i++)
489 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
490 for (i = 0; i < 64; i++)
491 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
492 for (i = 0; i < 64; i++)
493 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
494 for (i = 0; i < 16; i++)
495 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
496 for (i = 0; i < 16; i++)
497 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
498 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
499 for (i = 0; i < 8; i++)
500 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
501 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
502 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
503
504 /* Receive */
505 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
506 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
507 for (i = 0; i < 16; i++)
508 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
509 for (i = 0; i < 16; i++)
510 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
511 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
512 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
513 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
514 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
515 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
516 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
517 for (i = 0; i < 8; i++)
518 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
519 for (i = 0; i < 8; i++)
520 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
521 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
522
523 /* Transmit */
524 for (i = 0; i < 32; i++)
525 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
526 for (i = 0; i < 32; i++)
527 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
528 for (i = 0; i < 32; i++)
529 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
530 for (i = 0; i < 32; i++)
531 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
532 for (i = 0; i < 32; i++)
533 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
534 for (i = 0; i < 32; i++)
535 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
536 for (i = 0; i < 32; i++)
537 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
538 for (i = 0; i < 32; i++)
539 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
540 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
541 for (i = 0; i < 16; i++)
542 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
543 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
544 for (i = 0; i < 8; i++)
545 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
546 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
547
548 /* Wake Up */
549 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
550 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
551 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
552 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
553 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
554 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
555 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
556 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
557 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
558
559 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
560 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
561 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
562 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
563 for (i = 0; i < 8; i++)
564 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
565 for (i = 0; i < 8; i++)
566 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
567 for (i = 0; i < 8; i++)
568 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
569 for (i = 0; i < 8; i++)
570 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
571 for (i = 0; i < 8; i++)
572 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
573 for (i = 0; i < 8; i++)
574 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
575
576 /* Statistics */
577 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
578 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
579 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
580 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
581 for (i = 0; i < 8; i++)
582 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
583 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
584 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
585 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
586 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
587 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
588 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
589 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
590 for (i = 0; i < 8; i++)
591 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
592 for (i = 0; i < 8; i++)
593 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
594 for (i = 0; i < 8; i++)
595 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
596 for (i = 0; i < 8; i++)
597 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
598 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
599 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
600 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
601 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
602 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
603 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
604 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
605 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
606 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
607 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
608 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
609 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
610 for (i = 0; i < 8; i++)
611 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
612 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
613 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
614 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
615 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
616 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
617 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
618 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
619 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
620 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
621 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
622 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
623 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
624 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
625 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
626 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
627 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
628 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
629 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
630 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
631 for (i = 0; i < 16; i++)
632 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
633 for (i = 0; i < 16; i++)
634 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
635 for (i = 0; i < 16; i++)
636 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
637 for (i = 0; i < 16; i++)
638 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
639
640 /* MAC */
641 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
642 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
643 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
644 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
645 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
646 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
647 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
648 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
649 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
650 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
651 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
652 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
653 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
654 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
655 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
656 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
657 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
658 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
659 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
660 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
661 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
662 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
663 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
664 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
665 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
666 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
667 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
668 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
669 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
670 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
671 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
672 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
673 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
674
675 /* Diagnostic */
676 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
677 for (i = 0; i < 8; i++)
678 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
679 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
680 for (i = 0; i < 4; i++)
681 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
682 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
683 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
684 for (i = 0; i < 8; i++)
685 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
686 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
687 for (i = 0; i < 4; i++)
688 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
689 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
690 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
691 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
692 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
693 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
694 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
695 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
696 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
697 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
698 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
699 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
700 for (i = 0; i < 8; i++)
701 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
702 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
703 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
704 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
705 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
706 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
707 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
708 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
709 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
710 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
711 }
712
713 static int ixgbe_get_eeprom_len(struct net_device *netdev)
714 {
715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
716 return adapter->hw.eeprom.word_size * 2;
717 }
718
719 static int ixgbe_get_eeprom(struct net_device *netdev,
720 struct ethtool_eeprom *eeprom, u8 *bytes)
721 {
722 struct ixgbe_adapter *adapter = netdev_priv(netdev);
723 struct ixgbe_hw *hw = &adapter->hw;
724 u16 *eeprom_buff;
725 int first_word, last_word, eeprom_len;
726 int ret_val = 0;
727 u16 i;
728
729 if (eeprom->len == 0)
730 return -EINVAL;
731
732 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
733
734 first_word = eeprom->offset >> 1;
735 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
736 eeprom_len = last_word - first_word + 1;
737
738 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
739 if (!eeprom_buff)
740 return -ENOMEM;
741
742 for (i = 0; i < eeprom_len; i++) {
743 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
744 &eeprom_buff[i])))
745 break;
746 }
747
748 /* Device's eeprom is always little-endian, word addressable */
749 for (i = 0; i < eeprom_len; i++)
750 le16_to_cpus(&eeprom_buff[i]);
751
752 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
753 kfree(eeprom_buff);
754
755 return ret_val;
756 }
757
758 static void ixgbe_get_drvinfo(struct net_device *netdev,
759 struct ethtool_drvinfo *drvinfo)
760 {
761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
762 char firmware_version[32];
763
764 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
765 strncpy(drvinfo->version, ixgbe_driver_version, 32);
766
767 sprintf(firmware_version, "%d.%d-%d",
768 (adapter->eeprom_version & 0xF000) >> 12,
769 (adapter->eeprom_version & 0x0FF0) >> 4,
770 adapter->eeprom_version & 0x000F);
771
772 strncpy(drvinfo->fw_version, firmware_version, 32);
773 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
774 drvinfo->n_stats = IXGBE_STATS_LEN;
775 drvinfo->testinfo_len = IXGBE_TEST_LEN;
776 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
777 }
778
779 static void ixgbe_get_ringparam(struct net_device *netdev,
780 struct ethtool_ringparam *ring)
781 {
782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
783 struct ixgbe_ring *tx_ring = adapter->tx_ring;
784 struct ixgbe_ring *rx_ring = adapter->rx_ring;
785
786 ring->rx_max_pending = IXGBE_MAX_RXD;
787 ring->tx_max_pending = IXGBE_MAX_TXD;
788 ring->rx_mini_max_pending = 0;
789 ring->rx_jumbo_max_pending = 0;
790 ring->rx_pending = rx_ring->count;
791 ring->tx_pending = tx_ring->count;
792 ring->rx_mini_pending = 0;
793 ring->rx_jumbo_pending = 0;
794 }
795
796 static int ixgbe_set_ringparam(struct net_device *netdev,
797 struct ethtool_ringparam *ring)
798 {
799 struct ixgbe_adapter *adapter = netdev_priv(netdev);
800 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
801 int i, err;
802 u32 new_rx_count, new_tx_count;
803 bool need_update = false;
804
805 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
806 return -EINVAL;
807
808 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
809 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
810 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
811
812 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
813 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
814 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
815
816 if ((new_tx_count == adapter->tx_ring->count) &&
817 (new_rx_count == adapter->rx_ring->count)) {
818 /* nothing to do */
819 return 0;
820 }
821
822 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
823 msleep(1);
824
825 temp_tx_ring = kcalloc(adapter->num_tx_queues,
826 sizeof(struct ixgbe_ring), GFP_KERNEL);
827 if (!temp_tx_ring) {
828 err = -ENOMEM;
829 goto err_setup;
830 }
831
832 if (new_tx_count != adapter->tx_ring_count) {
833 memcpy(temp_tx_ring, adapter->tx_ring,
834 adapter->num_tx_queues * sizeof(struct ixgbe_ring));
835 for (i = 0; i < adapter->num_tx_queues; i++) {
836 temp_tx_ring[i].count = new_tx_count;
837 err = ixgbe_setup_tx_resources(adapter,
838 &temp_tx_ring[i]);
839 if (err) {
840 while (i) {
841 i--;
842 ixgbe_free_tx_resources(adapter,
843 &temp_tx_ring[i]);
844 }
845 goto err_setup;
846 }
847 }
848 need_update = true;
849 }
850
851 temp_rx_ring = kcalloc(adapter->num_rx_queues,
852 sizeof(struct ixgbe_ring), GFP_KERNEL);
853 if ((!temp_rx_ring) && (need_update)) {
854 for (i = 0; i < adapter->num_tx_queues; i++)
855 ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
856 kfree(temp_tx_ring);
857 err = -ENOMEM;
858 goto err_setup;
859 }
860
861 if (new_rx_count != adapter->rx_ring_count) {
862 memcpy(temp_rx_ring, adapter->rx_ring,
863 adapter->num_rx_queues * sizeof(struct ixgbe_ring));
864 for (i = 0; i < adapter->num_rx_queues; i++) {
865 temp_rx_ring[i].count = new_rx_count;
866 err = ixgbe_setup_rx_resources(adapter,
867 &temp_rx_ring[i]);
868 if (err) {
869 while (i) {
870 i--;
871 ixgbe_free_rx_resources(adapter,
872 &temp_rx_ring[i]);
873 }
874 goto err_setup;
875 }
876 }
877 need_update = true;
878 }
879
880 /* if rings need to be updated, here's the place to do it in one shot */
881 if (need_update) {
882 if (netif_running(netdev))
883 ixgbe_down(adapter);
884
885 /* tx */
886 if (new_tx_count != adapter->tx_ring_count) {
887 kfree(adapter->tx_ring);
888 adapter->tx_ring = temp_tx_ring;
889 temp_tx_ring = NULL;
890 adapter->tx_ring_count = new_tx_count;
891 }
892
893 /* rx */
894 if (new_rx_count != adapter->rx_ring_count) {
895 kfree(adapter->rx_ring);
896 adapter->rx_ring = temp_rx_ring;
897 temp_rx_ring = NULL;
898 adapter->rx_ring_count = new_rx_count;
899 }
900 }
901
902 /* success! */
903 err = 0;
904 if (netif_running(netdev))
905 ixgbe_up(adapter);
906
907 err_setup:
908 clear_bit(__IXGBE_RESETTING, &adapter->state);
909 return err;
910 }
911
912 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
913 {
914 switch (sset) {
915 case ETH_SS_TEST:
916 return IXGBE_TEST_LEN;
917 case ETH_SS_STATS:
918 return IXGBE_STATS_LEN;
919 default:
920 return -EOPNOTSUPP;
921 }
922 }
923
924 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
925 struct ethtool_stats *stats, u64 *data)
926 {
927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
928 u64 *queue_stat;
929 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
930 int j, k;
931 int i;
932
933 ixgbe_update_stats(adapter);
934 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
935 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
936 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
937 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
938 }
939 for (j = 0; j < adapter->num_tx_queues; j++) {
940 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
941 for (k = 0; k < stat_count; k++)
942 data[i + k] = queue_stat[k];
943 i += k;
944 }
945 for (j = 0; j < adapter->num_rx_queues; j++) {
946 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
947 for (k = 0; k < stat_count; k++)
948 data[i + k] = queue_stat[k];
949 i += k;
950 }
951 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
952 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
953 data[i++] = adapter->stats.pxontxc[j];
954 data[i++] = adapter->stats.pxofftxc[j];
955 }
956 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
957 data[i++] = adapter->stats.pxonrxc[j];
958 data[i++] = adapter->stats.pxoffrxc[j];
959 }
960 }
961 }
962
963 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
964 u8 *data)
965 {
966 struct ixgbe_adapter *adapter = netdev_priv(netdev);
967 char *p = (char *)data;
968 int i;
969
970 switch (stringset) {
971 case ETH_SS_TEST:
972 memcpy(data, *ixgbe_gstrings_test,
973 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
974 break;
975 case ETH_SS_STATS:
976 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
977 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
978 ETH_GSTRING_LEN);
979 p += ETH_GSTRING_LEN;
980 }
981 for (i = 0; i < adapter->num_tx_queues; i++) {
982 sprintf(p, "tx_queue_%u_packets", i);
983 p += ETH_GSTRING_LEN;
984 sprintf(p, "tx_queue_%u_bytes", i);
985 p += ETH_GSTRING_LEN;
986 }
987 for (i = 0; i < adapter->num_rx_queues; i++) {
988 sprintf(p, "rx_queue_%u_packets", i);
989 p += ETH_GSTRING_LEN;
990 sprintf(p, "rx_queue_%u_bytes", i);
991 p += ETH_GSTRING_LEN;
992 }
993 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
994 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
995 sprintf(p, "tx_pb_%u_pxon", i);
996 p += ETH_GSTRING_LEN;
997 sprintf(p, "tx_pb_%u_pxoff", i);
998 p += ETH_GSTRING_LEN;
999 }
1000 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1001 sprintf(p, "rx_pb_%u_pxon", i);
1002 p += ETH_GSTRING_LEN;
1003 sprintf(p, "rx_pb_%u_pxoff", i);
1004 p += ETH_GSTRING_LEN;
1005 }
1006 }
1007 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1008 break;
1009 }
1010 }
1011
1012 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1013 {
1014 struct ixgbe_hw *hw = &adapter->hw;
1015 bool link_up;
1016 u32 link_speed = 0;
1017 *data = 0;
1018
1019 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1020 if (link_up)
1021 return *data;
1022 else
1023 *data = 1;
1024 return *data;
1025 }
1026
1027 /* ethtool register test data */
1028 struct ixgbe_reg_test {
1029 u16 reg;
1030 u8 array_len;
1031 u8 test_type;
1032 u32 mask;
1033 u32 write;
1034 };
1035
1036 /* In the hardware, registers are laid out either singly, in arrays
1037 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1038 * most tests take place on arrays or single registers (handled
1039 * as a single-element array) and special-case the tables.
1040 * Table tests are always pattern tests.
1041 *
1042 * We also make provision for some required setup steps by specifying
1043 * registers to be written without any read-back testing.
1044 */
1045
1046 #define PATTERN_TEST 1
1047 #define SET_READ_TEST 2
1048 #define WRITE_NO_TEST 3
1049 #define TABLE32_TEST 4
1050 #define TABLE64_TEST_LO 5
1051 #define TABLE64_TEST_HI 6
1052
1053 /* default 82599 register test */
1054 static struct ixgbe_reg_test reg_test_82599[] = {
1055 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1056 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1057 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1058 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1059 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1060 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1061 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1062 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1063 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1064 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1065 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1066 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1067 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1068 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1069 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1070 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1071 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1072 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1073 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1074 { 0, 0, 0, 0 }
1075 };
1076
1077 /* default 82598 register test */
1078 static struct ixgbe_reg_test reg_test_82598[] = {
1079 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1080 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1081 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1083 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1084 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1085 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1086 /* Enable all four RX queues before testing. */
1087 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1088 /* RDH is read-only for 82598, only test RDT. */
1089 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1090 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1091 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1092 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1093 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1094 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1095 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1096 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1097 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1098 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1099 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1100 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1101 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1102 { 0, 0, 0, 0 }
1103 };
1104
1105 #define REG_PATTERN_TEST(R, M, W) \
1106 { \
1107 u32 pat, val, before; \
1108 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1109 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1110 before = readl(adapter->hw.hw_addr + R); \
1111 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1112 val = readl(adapter->hw.hw_addr + R); \
1113 if (val != (_test[pat] & W & M)) { \
1114 DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1115 "0x%08X expected 0x%08X\n", \
1116 R, val, (_test[pat] & W & M)); \
1117 *data = R; \
1118 writel(before, adapter->hw.hw_addr + R); \
1119 return 1; \
1120 } \
1121 writel(before, adapter->hw.hw_addr + R); \
1122 } \
1123 }
1124
1125 #define REG_SET_AND_CHECK(R, M, W) \
1126 { \
1127 u32 val, before; \
1128 before = readl(adapter->hw.hw_addr + R); \
1129 writel((W & M), (adapter->hw.hw_addr + R)); \
1130 val = readl(adapter->hw.hw_addr + R); \
1131 if ((W & M) != (val & M)) { \
1132 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1133 "expected 0x%08X\n", R, (val & M), (W & M)); \
1134 *data = R; \
1135 writel(before, (adapter->hw.hw_addr + R)); \
1136 return 1; \
1137 } \
1138 writel(before, (adapter->hw.hw_addr + R)); \
1139 }
1140
1141 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1142 {
1143 struct ixgbe_reg_test *test;
1144 u32 value, before, after;
1145 u32 i, toggle;
1146
1147 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1148 toggle = 0x7FFFF30F;
1149 test = reg_test_82599;
1150 } else {
1151 toggle = 0x7FFFF3FF;
1152 test = reg_test_82598;
1153 }
1154
1155 /*
1156 * Because the status register is such a special case,
1157 * we handle it separately from the rest of the register
1158 * tests. Some bits are read-only, some toggle, and some
1159 * are writeable on newer MACs.
1160 */
1161 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1162 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1163 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1164 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1165 if (value != after) {
1166 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1167 "0x%08X expected: 0x%08X\n", after, value);
1168 *data = 1;
1169 return 1;
1170 }
1171 /* restore previous status */
1172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1173
1174 /*
1175 * Perform the remainder of the register test, looping through
1176 * the test table until we either fail or reach the null entry.
1177 */
1178 while (test->reg) {
1179 for (i = 0; i < test->array_len; i++) {
1180 switch (test->test_type) {
1181 case PATTERN_TEST:
1182 REG_PATTERN_TEST(test->reg + (i * 0x40),
1183 test->mask,
1184 test->write);
1185 break;
1186 case SET_READ_TEST:
1187 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1188 test->mask,
1189 test->write);
1190 break;
1191 case WRITE_NO_TEST:
1192 writel(test->write,
1193 (adapter->hw.hw_addr + test->reg)
1194 + (i * 0x40));
1195 break;
1196 case TABLE32_TEST:
1197 REG_PATTERN_TEST(test->reg + (i * 4),
1198 test->mask,
1199 test->write);
1200 break;
1201 case TABLE64_TEST_LO:
1202 REG_PATTERN_TEST(test->reg + (i * 8),
1203 test->mask,
1204 test->write);
1205 break;
1206 case TABLE64_TEST_HI:
1207 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1208 test->mask,
1209 test->write);
1210 break;
1211 }
1212 }
1213 test++;
1214 }
1215
1216 *data = 0;
1217 return 0;
1218 }
1219
1220 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1221 {
1222 struct ixgbe_hw *hw = &adapter->hw;
1223 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1224 *data = 1;
1225 else
1226 *data = 0;
1227 return *data;
1228 }
1229
1230 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1231 {
1232 struct net_device *netdev = (struct net_device *) data;
1233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1234
1235 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1236
1237 return IRQ_HANDLED;
1238 }
1239
1240 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1241 {
1242 struct net_device *netdev = adapter->netdev;
1243 u32 mask, i = 0, shared_int = true;
1244 u32 irq = adapter->pdev->irq;
1245
1246 *data = 0;
1247
1248 /* Hook up test interrupt handler just for this test */
1249 if (adapter->msix_entries) {
1250 /* NOTE: we don't test MSI-X interrupts here, yet */
1251 return 0;
1252 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1253 shared_int = false;
1254 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1255 netdev)) {
1256 *data = 1;
1257 return -1;
1258 }
1259 } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1260 netdev->name, netdev)) {
1261 shared_int = false;
1262 } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1263 netdev->name, netdev)) {
1264 *data = 1;
1265 return -1;
1266 }
1267 DPRINTK(HW, INFO, "testing %s interrupt\n",
1268 (shared_int ? "shared" : "unshared"));
1269
1270 /* Disable all the interrupts */
1271 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1272 msleep(10);
1273
1274 /* Test each interrupt */
1275 for (; i < 10; i++) {
1276 /* Interrupt to test */
1277 mask = 1 << i;
1278
1279 if (!shared_int) {
1280 /*
1281 * Disable the interrupts to be reported in
1282 * the cause register and then force the same
1283 * interrupt and see if one gets posted. If
1284 * an interrupt was posted to the bus, the
1285 * test failed.
1286 */
1287 adapter->test_icr = 0;
1288 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1289 ~mask & 0x00007FFF);
1290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1291 ~mask & 0x00007FFF);
1292 msleep(10);
1293
1294 if (adapter->test_icr & mask) {
1295 *data = 3;
1296 break;
1297 }
1298 }
1299
1300 /*
1301 * Enable the interrupt to be reported in the cause
1302 * register and then force the same interrupt and see
1303 * if one gets posted. If an interrupt was not posted
1304 * to the bus, the test failed.
1305 */
1306 adapter->test_icr = 0;
1307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1308 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1309 msleep(10);
1310
1311 if (!(adapter->test_icr &mask)) {
1312 *data = 4;
1313 break;
1314 }
1315
1316 if (!shared_int) {
1317 /*
1318 * Disable the other interrupts to be reported in
1319 * the cause register and then force the other
1320 * interrupts and see if any get posted. If
1321 * an interrupt was posted to the bus, the
1322 * test failed.
1323 */
1324 adapter->test_icr = 0;
1325 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1326 ~mask & 0x00007FFF);
1327 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1328 ~mask & 0x00007FFF);
1329 msleep(10);
1330
1331 if (adapter->test_icr) {
1332 *data = 5;
1333 break;
1334 }
1335 }
1336 }
1337
1338 /* Disable all the interrupts */
1339 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1340 msleep(10);
1341
1342 /* Unhook test interrupt handler */
1343 free_irq(irq, netdev);
1344
1345 return *data;
1346 }
1347
1348 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1349 {
1350 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1351 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1352 struct ixgbe_hw *hw = &adapter->hw;
1353 struct pci_dev *pdev = adapter->pdev;
1354 u32 reg_ctl;
1355 int i;
1356
1357 /* shut down the DMA engines now so they can be reinitialized later */
1358
1359 /* first Rx */
1360 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1361 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1362 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1363 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1364 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1365 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1366
1367 /* now Tx */
1368 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1369 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1370 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1371 if (hw->mac.type == ixgbe_mac_82599EB) {
1372 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1373 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1375 }
1376
1377 ixgbe_reset(adapter);
1378
1379 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1380 for (i = 0; i < tx_ring->count; i++) {
1381 struct ixgbe_tx_buffer *buf =
1382 &(tx_ring->tx_buffer_info[i]);
1383 if (buf->dma)
1384 pci_unmap_single(pdev, buf->dma, buf->length,
1385 PCI_DMA_TODEVICE);
1386 if (buf->skb)
1387 dev_kfree_skb(buf->skb);
1388 }
1389 }
1390
1391 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1392 for (i = 0; i < rx_ring->count; i++) {
1393 struct ixgbe_rx_buffer *buf =
1394 &(rx_ring->rx_buffer_info[i]);
1395 if (buf->dma)
1396 pci_unmap_single(pdev, buf->dma,
1397 IXGBE_RXBUFFER_2048,
1398 PCI_DMA_FROMDEVICE);
1399 if (buf->skb)
1400 dev_kfree_skb(buf->skb);
1401 }
1402 }
1403
1404 if (tx_ring->desc) {
1405 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1406 tx_ring->dma);
1407 tx_ring->desc = NULL;
1408 }
1409 if (rx_ring->desc) {
1410 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1411 rx_ring->dma);
1412 rx_ring->desc = NULL;
1413 }
1414
1415 kfree(tx_ring->tx_buffer_info);
1416 tx_ring->tx_buffer_info = NULL;
1417 kfree(rx_ring->rx_buffer_info);
1418 rx_ring->rx_buffer_info = NULL;
1419
1420 return;
1421 }
1422
1423 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1424 {
1425 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1426 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1427 struct pci_dev *pdev = adapter->pdev;
1428 u32 rctl, reg_data;
1429 int i, ret_val;
1430
1431 /* Setup Tx descriptor ring and Tx buffers */
1432
1433 if (!tx_ring->count)
1434 tx_ring->count = IXGBE_DEFAULT_TXD;
1435
1436 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1437 sizeof(struct ixgbe_tx_buffer),
1438 GFP_KERNEL);
1439 if (!(tx_ring->tx_buffer_info)) {
1440 ret_val = 1;
1441 goto err_nomem;
1442 }
1443
1444 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1445 tx_ring->size = ALIGN(tx_ring->size, 4096);
1446 if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1447 &tx_ring->dma))) {
1448 ret_val = 2;
1449 goto err_nomem;
1450 }
1451 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1452
1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1454 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1456 ((u64) tx_ring->dma >> 32));
1457 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1458 tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1459 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1461
1462 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1463 reg_data |= IXGBE_HLREG0_TXPADEN;
1464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1465
1466 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1467 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1468 reg_data |= IXGBE_DMATXCTL_TE;
1469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1470 }
1471 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1472 reg_data |= IXGBE_TXDCTL_ENABLE;
1473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1474
1475 for (i = 0; i < tx_ring->count; i++) {
1476 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1477 struct sk_buff *skb;
1478 unsigned int size = 1024;
1479
1480 skb = alloc_skb(size, GFP_KERNEL);
1481 if (!skb) {
1482 ret_val = 3;
1483 goto err_nomem;
1484 }
1485 skb_put(skb, size);
1486 tx_ring->tx_buffer_info[i].skb = skb;
1487 tx_ring->tx_buffer_info[i].length = skb->len;
1488 tx_ring->tx_buffer_info[i].dma =
1489 pci_map_single(pdev, skb->data, skb->len,
1490 PCI_DMA_TODEVICE);
1491 desc->read.buffer_addr =
1492 cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1493 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1494 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1495 IXGBE_TXD_CMD_IFCS |
1496 IXGBE_TXD_CMD_RS);
1497 desc->read.olinfo_status = 0;
1498 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1499 desc->read.olinfo_status |=
1500 (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1501
1502 }
1503
1504 /* Setup Rx Descriptor ring and Rx buffers */
1505
1506 if (!rx_ring->count)
1507 rx_ring->count = IXGBE_DEFAULT_RXD;
1508
1509 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1510 sizeof(struct ixgbe_rx_buffer),
1511 GFP_KERNEL);
1512 if (!(rx_ring->rx_buffer_info)) {
1513 ret_val = 4;
1514 goto err_nomem;
1515 }
1516
1517 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1518 rx_ring->size = ALIGN(rx_ring->size, 4096);
1519 if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1520 &rx_ring->dma))) {
1521 ret_val = 5;
1522 goto err_nomem;
1523 }
1524 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1525
1526 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1527 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1528 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1529 ((u64)rx_ring->dma & 0xFFFFFFFF));
1530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1531 ((u64) rx_ring->dma >> 32));
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1535
1536 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1537 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1539
1540 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1541 reg_data &= ~IXGBE_HLREG0_LPBK;
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1543
1544 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1545 #define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1546 Threshold Size mask */
1547 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1549
1550 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1551 #define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1552 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1553 reg_data |= adapter->hw.mac.mc_filter_type;
1554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1555
1556 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1557 reg_data |= IXGBE_RXDCTL_ENABLE;
1558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1559 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1560 int j = adapter->rx_ring[0].reg_idx;
1561 u32 k;
1562 for (k = 0; k < 10; k++) {
1563 if (IXGBE_READ_REG(&adapter->hw,
1564 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1565 break;
1566 else
1567 msleep(1);
1568 }
1569 }
1570
1571 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1573
1574 for (i = 0; i < rx_ring->count; i++) {
1575 union ixgbe_adv_rx_desc *rx_desc =
1576 IXGBE_RX_DESC_ADV(*rx_ring, i);
1577 struct sk_buff *skb;
1578
1579 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1580 if (!skb) {
1581 ret_val = 6;
1582 goto err_nomem;
1583 }
1584 skb_reserve(skb, NET_IP_ALIGN);
1585 rx_ring->rx_buffer_info[i].skb = skb;
1586 rx_ring->rx_buffer_info[i].dma =
1587 pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1588 PCI_DMA_FROMDEVICE);
1589 rx_desc->read.pkt_addr =
1590 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1591 memset(skb->data, 0x00, skb->len);
1592 }
1593
1594 return 0;
1595
1596 err_nomem:
1597 ixgbe_free_desc_rings(adapter);
1598 return ret_val;
1599 }
1600
1601 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1602 {
1603 struct ixgbe_hw *hw = &adapter->hw;
1604 u32 reg_data;
1605
1606 /* right now we only support MAC loopback in the driver */
1607
1608 /* Setup MAC loopback */
1609 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1610 reg_data |= IXGBE_HLREG0_LPBK;
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1612
1613 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1614 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1615 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1617
1618 /* Disable Atlas Tx lanes; re-enabled in reset path */
1619 if (hw->mac.type == ixgbe_mac_82598EB) {
1620 u8 atlas;
1621
1622 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1623 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1624 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1625
1626 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1627 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1628 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1629
1630 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1631 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1632 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1633
1634 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1635 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1636 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1637 }
1638
1639 return 0;
1640 }
1641
1642 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1643 {
1644 u32 reg_data;
1645
1646 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1647 reg_data &= ~IXGBE_HLREG0_LPBK;
1648 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1649 }
1650
1651 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1652 unsigned int frame_size)
1653 {
1654 memset(skb->data, 0xFF, frame_size);
1655 frame_size &= ~1;
1656 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1657 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1658 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1659 }
1660
1661 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1662 unsigned int frame_size)
1663 {
1664 frame_size &= ~1;
1665 if (*(skb->data + 3) == 0xFF) {
1666 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1667 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1668 return 0;
1669 }
1670 }
1671 return 13;
1672 }
1673
1674 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1675 {
1676 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1677 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1678 struct pci_dev *pdev = adapter->pdev;
1679 int i, j, k, l, lc, good_cnt, ret_val = 0;
1680 unsigned long time;
1681
1682 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1683
1684 /*
1685 * Calculate the loop count based on the largest descriptor ring
1686 * The idea is to wrap the largest ring a number of times using 64
1687 * send/receive pairs during each loop
1688 */
1689
1690 if (rx_ring->count <= tx_ring->count)
1691 lc = ((tx_ring->count / 64) * 2) + 1;
1692 else
1693 lc = ((rx_ring->count / 64) * 2) + 1;
1694
1695 k = l = 0;
1696 for (j = 0; j <= lc; j++) {
1697 for (i = 0; i < 64; i++) {
1698 ixgbe_create_lbtest_frame(
1699 tx_ring->tx_buffer_info[k].skb,
1700 1024);
1701 pci_dma_sync_single_for_device(pdev,
1702 tx_ring->tx_buffer_info[k].dma,
1703 tx_ring->tx_buffer_info[k].length,
1704 PCI_DMA_TODEVICE);
1705 if (unlikely(++k == tx_ring->count))
1706 k = 0;
1707 }
1708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1709 msleep(200);
1710 /* set the start time for the receive */
1711 time = jiffies;
1712 good_cnt = 0;
1713 do {
1714 /* receive the sent packets */
1715 pci_dma_sync_single_for_cpu(pdev,
1716 rx_ring->rx_buffer_info[l].dma,
1717 IXGBE_RXBUFFER_2048,
1718 PCI_DMA_FROMDEVICE);
1719 ret_val = ixgbe_check_lbtest_frame(
1720 rx_ring->rx_buffer_info[l].skb, 1024);
1721 if (!ret_val)
1722 good_cnt++;
1723 if (++l == rx_ring->count)
1724 l = 0;
1725 /*
1726 * time + 20 msecs (200 msecs on 2.4) is more than
1727 * enough time to complete the receives, if it's
1728 * exceeded, break and error off
1729 */
1730 } while (good_cnt < 64 && jiffies < (time + 20));
1731 if (good_cnt != 64) {
1732 /* ret_val is the same as mis-compare */
1733 ret_val = 13;
1734 break;
1735 }
1736 if (jiffies >= (time + 20)) {
1737 /* Error code for time out error */
1738 ret_val = 14;
1739 break;
1740 }
1741 }
1742
1743 return ret_val;
1744 }
1745
1746 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1747 {
1748 *data = ixgbe_setup_desc_rings(adapter);
1749 if (*data)
1750 goto out;
1751 *data = ixgbe_setup_loopback_test(adapter);
1752 if (*data)
1753 goto err_loopback;
1754 *data = ixgbe_run_loopback_test(adapter);
1755 ixgbe_loopback_cleanup(adapter);
1756
1757 err_loopback:
1758 ixgbe_free_desc_rings(adapter);
1759 out:
1760 return *data;
1761 }
1762
1763 static void ixgbe_diag_test(struct net_device *netdev,
1764 struct ethtool_test *eth_test, u64 *data)
1765 {
1766 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1767 bool if_running = netif_running(netdev);
1768
1769 set_bit(__IXGBE_TESTING, &adapter->state);
1770 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1771 /* Offline tests */
1772
1773 DPRINTK(HW, INFO, "offline testing starting\n");
1774
1775 /* Link test performed before hardware reset so autoneg doesn't
1776 * interfere with test result */
1777 if (ixgbe_link_test(adapter, &data[4]))
1778 eth_test->flags |= ETH_TEST_FL_FAILED;
1779
1780 if (if_running)
1781 /* indicate we're in test mode */
1782 dev_close(netdev);
1783 else
1784 ixgbe_reset(adapter);
1785
1786 DPRINTK(HW, INFO, "register testing starting\n");
1787 if (ixgbe_reg_test(adapter, &data[0]))
1788 eth_test->flags |= ETH_TEST_FL_FAILED;
1789
1790 ixgbe_reset(adapter);
1791 DPRINTK(HW, INFO, "eeprom testing starting\n");
1792 if (ixgbe_eeprom_test(adapter, &data[1]))
1793 eth_test->flags |= ETH_TEST_FL_FAILED;
1794
1795 ixgbe_reset(adapter);
1796 DPRINTK(HW, INFO, "interrupt testing starting\n");
1797 if (ixgbe_intr_test(adapter, &data[2]))
1798 eth_test->flags |= ETH_TEST_FL_FAILED;
1799
1800 ixgbe_reset(adapter);
1801 DPRINTK(HW, INFO, "loopback testing starting\n");
1802 if (ixgbe_loopback_test(adapter, &data[3]))
1803 eth_test->flags |= ETH_TEST_FL_FAILED;
1804
1805 ixgbe_reset(adapter);
1806
1807 clear_bit(__IXGBE_TESTING, &adapter->state);
1808 if (if_running)
1809 dev_open(netdev);
1810 } else {
1811 DPRINTK(HW, INFO, "online testing starting\n");
1812 /* Online tests */
1813 if (ixgbe_link_test(adapter, &data[4]))
1814 eth_test->flags |= ETH_TEST_FL_FAILED;
1815
1816 /* Online tests aren't run; pass by default */
1817 data[0] = 0;
1818 data[1] = 0;
1819 data[2] = 0;
1820 data[3] = 0;
1821
1822 clear_bit(__IXGBE_TESTING, &adapter->state);
1823 }
1824 msleep_interruptible(4 * 1000);
1825 }
1826
1827 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1828 struct ethtool_wolinfo *wol)
1829 {
1830 struct ixgbe_hw *hw = &adapter->hw;
1831 int retval = 1;
1832
1833 switch(hw->device_id) {
1834 case IXGBE_DEV_ID_82599_KX4:
1835 retval = 0;
1836 break;
1837 default:
1838 wol->supported = 0;
1839 }
1840
1841 return retval;
1842 }
1843
1844 static void ixgbe_get_wol(struct net_device *netdev,
1845 struct ethtool_wolinfo *wol)
1846 {
1847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1848
1849 wol->supported = WAKE_UCAST | WAKE_MCAST |
1850 WAKE_BCAST | WAKE_MAGIC;
1851 wol->wolopts = 0;
1852
1853 if (ixgbe_wol_exclusion(adapter, wol) ||
1854 !device_can_wakeup(&adapter->pdev->dev))
1855 return;
1856
1857 if (adapter->wol & IXGBE_WUFC_EX)
1858 wol->wolopts |= WAKE_UCAST;
1859 if (adapter->wol & IXGBE_WUFC_MC)
1860 wol->wolopts |= WAKE_MCAST;
1861 if (adapter->wol & IXGBE_WUFC_BC)
1862 wol->wolopts |= WAKE_BCAST;
1863 if (adapter->wol & IXGBE_WUFC_MAG)
1864 wol->wolopts |= WAKE_MAGIC;
1865
1866 return;
1867 }
1868
1869 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1870 {
1871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1872
1873 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1874 return -EOPNOTSUPP;
1875
1876 if (ixgbe_wol_exclusion(adapter, wol))
1877 return wol->wolopts ? -EOPNOTSUPP : 0;
1878
1879 adapter->wol = 0;
1880
1881 if (wol->wolopts & WAKE_UCAST)
1882 adapter->wol |= IXGBE_WUFC_EX;
1883 if (wol->wolopts & WAKE_MCAST)
1884 adapter->wol |= IXGBE_WUFC_MC;
1885 if (wol->wolopts & WAKE_BCAST)
1886 adapter->wol |= IXGBE_WUFC_BC;
1887 if (wol->wolopts & WAKE_MAGIC)
1888 adapter->wol |= IXGBE_WUFC_MAG;
1889
1890 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1891
1892 return 0;
1893 }
1894
1895 static int ixgbe_nway_reset(struct net_device *netdev)
1896 {
1897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1898
1899 if (netif_running(netdev))
1900 ixgbe_reinit_locked(adapter);
1901
1902 return 0;
1903 }
1904
1905 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1906 {
1907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1908 struct ixgbe_hw *hw = &adapter->hw;
1909 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1910 u32 i;
1911
1912 if (!data || data > 300)
1913 data = 300;
1914
1915 for (i = 0; i < (data * 1000); i += 400) {
1916 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1917 msleep_interruptible(200);
1918 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1919 msleep_interruptible(200);
1920 }
1921
1922 /* Restore LED settings */
1923 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1924
1925 return 0;
1926 }
1927
1928 static int ixgbe_get_coalesce(struct net_device *netdev,
1929 struct ethtool_coalesce *ec)
1930 {
1931 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1932
1933 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1934
1935 /* only valid if in constant ITR mode */
1936 switch (adapter->rx_itr_setting) {
1937 case 0:
1938 /* throttling disabled */
1939 ec->rx_coalesce_usecs = 0;
1940 break;
1941 case 1:
1942 /* dynamic ITR mode */
1943 ec->rx_coalesce_usecs = 1;
1944 break;
1945 default:
1946 /* fixed interrupt rate mode */
1947 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
1948 break;
1949 }
1950
1951 /* only valid if in constant ITR mode */
1952 switch (adapter->tx_itr_setting) {
1953 case 0:
1954 /* throttling disabled */
1955 ec->tx_coalesce_usecs = 0;
1956 break;
1957 case 1:
1958 /* dynamic ITR mode */
1959 ec->tx_coalesce_usecs = 1;
1960 break;
1961 default:
1962 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1963 break;
1964 }
1965
1966 return 0;
1967 }
1968
1969 static int ixgbe_set_coalesce(struct net_device *netdev,
1970 struct ethtool_coalesce *ec)
1971 {
1972 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1973 struct ixgbe_q_vector *q_vector;
1974 int i;
1975
1976 /*
1977 * don't accept tx specific changes if we've got mixed RxTx vectors
1978 * test and jump out here if needed before changing the rx numbers
1979 */
1980 if ((1000000/ec->tx_coalesce_usecs) != adapter->tx_eitr_param &&
1981 adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1982 return -EINVAL;
1983
1984 if (ec->tx_max_coalesced_frames_irq)
1985 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1986
1987 if (ec->rx_coalesce_usecs > 1) {
1988 /* check the limits */
1989 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1990 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1991 return -EINVAL;
1992
1993 /* store the value in ints/second */
1994 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
1995
1996 /* static value of interrupt rate */
1997 adapter->rx_itr_setting = adapter->rx_eitr_param;
1998 /* clear the lower bit as its used for dynamic state */
1999 adapter->rx_itr_setting &= ~1;
2000 } else if (ec->rx_coalesce_usecs == 1) {
2001 /* 1 means dynamic mode */
2002 adapter->rx_eitr_param = 20000;
2003 adapter->rx_itr_setting = 1;
2004 } else {
2005 /*
2006 * any other value means disable eitr, which is best
2007 * served by setting the interrupt rate very high
2008 */
2009 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2010 adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2011 else
2012 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2013 adapter->rx_itr_setting = 0;
2014 }
2015
2016 if (ec->tx_coalesce_usecs > 1) {
2017 /* check the limits */
2018 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2019 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2020 return -EINVAL;
2021
2022 /* store the value in ints/second */
2023 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2024
2025 /* static value of interrupt rate */
2026 adapter->tx_itr_setting = adapter->tx_eitr_param;
2027
2028 /* clear the lower bit as its used for dynamic state */
2029 adapter->tx_itr_setting &= ~1;
2030 } else if (ec->tx_coalesce_usecs == 1) {
2031 /* 1 means dynamic mode */
2032 adapter->tx_eitr_param = 10000;
2033 adapter->tx_itr_setting = 1;
2034 } else {
2035 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2036 adapter->tx_itr_setting = 0;
2037 }
2038
2039 /* MSI/MSIx Interrupt Mode */
2040 if (adapter->flags &
2041 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2042 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2043 for (i = 0; i < num_vectors; i++) {
2044 q_vector = adapter->q_vector[i];
2045 if (q_vector->txr_count && !q_vector->rxr_count)
2046 /* tx only */
2047 q_vector->eitr = adapter->tx_eitr_param;
2048 else
2049 /* rx only or mixed */
2050 q_vector->eitr = adapter->rx_eitr_param;
2051 ixgbe_write_eitr(q_vector);
2052 }
2053 /* Legacy Interrupt Mode */
2054 } else {
2055 q_vector = adapter->q_vector[0];
2056 q_vector->eitr = adapter->rx_eitr_param;
2057 ixgbe_write_eitr(q_vector);
2058 }
2059
2060 return 0;
2061 }
2062
2063 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2064 {
2065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2066
2067 ethtool_op_set_flags(netdev, data);
2068
2069 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2070 return 0;
2071
2072 /* if state changes we need to update adapter->flags and reset */
2073 if ((!!(data & ETH_FLAG_LRO)) !=
2074 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2075 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2076 if (netif_running(netdev))
2077 ixgbe_reinit_locked(adapter);
2078 else
2079 ixgbe_reset(adapter);
2080 }
2081 return 0;
2082
2083 }
2084
2085 static const struct ethtool_ops ixgbe_ethtool_ops = {
2086 .get_settings = ixgbe_get_settings,
2087 .set_settings = ixgbe_set_settings,
2088 .get_drvinfo = ixgbe_get_drvinfo,
2089 .get_regs_len = ixgbe_get_regs_len,
2090 .get_regs = ixgbe_get_regs,
2091 .get_wol = ixgbe_get_wol,
2092 .set_wol = ixgbe_set_wol,
2093 .nway_reset = ixgbe_nway_reset,
2094 .get_link = ethtool_op_get_link,
2095 .get_eeprom_len = ixgbe_get_eeprom_len,
2096 .get_eeprom = ixgbe_get_eeprom,
2097 .get_ringparam = ixgbe_get_ringparam,
2098 .set_ringparam = ixgbe_set_ringparam,
2099 .get_pauseparam = ixgbe_get_pauseparam,
2100 .set_pauseparam = ixgbe_set_pauseparam,
2101 .get_rx_csum = ixgbe_get_rx_csum,
2102 .set_rx_csum = ixgbe_set_rx_csum,
2103 .get_tx_csum = ixgbe_get_tx_csum,
2104 .set_tx_csum = ixgbe_set_tx_csum,
2105 .get_sg = ethtool_op_get_sg,
2106 .set_sg = ethtool_op_set_sg,
2107 .get_msglevel = ixgbe_get_msglevel,
2108 .set_msglevel = ixgbe_set_msglevel,
2109 .get_tso = ethtool_op_get_tso,
2110 .set_tso = ixgbe_set_tso,
2111 .self_test = ixgbe_diag_test,
2112 .get_strings = ixgbe_get_strings,
2113 .phys_id = ixgbe_phys_id,
2114 .get_sset_count = ixgbe_get_sset_count,
2115 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2116 .get_coalesce = ixgbe_get_coalesce,
2117 .set_coalesce = ixgbe_set_coalesce,
2118 .get_flags = ethtool_op_get_flags,
2119 .set_flags = ixgbe_set_flags,
2120 };
2121
2122 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2123 {
2124 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2125 }
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