[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / au1000_eth.c
blob04f63c77071dfc17c7e75a335c92768e1c85d236
1 /*
3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
18 * ########################################################################
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
33 * ########################################################################
37 #include <linux/dma-mapping.h>
38 #include <linux/module.h>
39 #include <linux/kernel.h>
40 #include <linux/string.h>
41 #include <linux/timer.h>
42 #include <linux/errno.h>
43 #include <linux/in.h>
44 #include <linux/ioport.h>
45 #include <linux/bitops.h>
46 #include <linux/slab.h>
47 #include <linux/interrupt.h>
48 #include <linux/init.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/mii.h>
53 #include <linux/skbuff.h>
54 #include <linux/delay.h>
55 #include <linux/crc32.h>
56 #include <linux/phy.h>
58 #include <asm/cpu.h>
59 #include <asm/mipsregs.h>
60 #include <asm/irq.h>
61 #include <asm/io.h>
62 #include <asm/processor.h>
64 #include <au1000.h>
65 #include <prom.h>
67 #include "au1000_eth.h"
69 #ifdef AU1000_ETH_DEBUG
70 static int au1000_debug = 5;
71 #else
72 static int au1000_debug = 3;
73 #endif
75 #define DRV_NAME "au1000_eth"
76 #define DRV_VERSION "1.6"
77 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
78 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION(DRV_DESC);
82 MODULE_LICENSE("GPL");
85 * Theory of operation
87 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
88 * There are four receive and four transmit descriptors. These
89 * descriptors are not in memory; rather, they are just a set of
90 * hardware registers.
92 * Since the Au1000 has a coherent data cache, the receive and
93 * transmit buffers are allocated from the KSEG0 segment. The
94 * hardware registers, however, are still mapped at KSEG1 to
95 * make sure there's no out-of-order writes, and that all writes
96 * complete immediately.
99 /* These addresses are only used if yamon doesn't tell us what
100 * the mac address is, and the mac address is not passed on the
101 * command line.
103 static unsigned char au1000_mac_addr[6] __devinitdata = {
104 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
107 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
110 * board-specific configurations
112 * PHY detection algorithm
114 * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is
115 * autodetected:
117 * mii_probe() first searches the current MAC's MII bus for a PHY,
118 * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is
119 * defined) PHY address not already claimed by another netdev.
121 * If nothing was found that way when searching for the 2nd ethernet
122 * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then
123 * the first MII bus is searched as well for an unclaimed PHY; this is
124 * needed in case of a dual-PHY accessible only through the MAC0's MII
125 * bus.
127 * Finally, if no PHY is found, then the corresponding ethernet
128 * controller is not registered to the network subsystem.
131 /* autodetection defaults */
132 #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR
133 #define AU1XXX_PHY1_SEARCH_ON_MAC0
135 /* static PHY setup
137 * most boards PHY setup should be detectable properly with the
138 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
139 * you have a switch attached, or want to use the PHY's interrupt
140 * notification capabilities) you can provide a static PHY
141 * configuration here
143 * IRQs may only be set, if a PHY address was configured
144 * If a PHY address is given, also a bus id is required to be set
146 * ps: make sure the used irqs are configured properly in the board
147 * specific irq-map
150 #if defined(CONFIG_MIPS_BOSPORUS)
152 * Micrel/Kendin 5 port switch attached to MAC0,
153 * MAC0 is associated with PHY address 5 (== WAN port)
154 * MAC1 is not associated with any PHY, since it's connected directly
155 * to the switch.
156 * no interrupts are used
158 # define AU1XXX_PHY_STATIC_CONFIG
160 # define AU1XXX_PHY0_ADDR 5
161 # define AU1XXX_PHY0_BUSID 0
162 # undef AU1XXX_PHY0_IRQ
164 # undef AU1XXX_PHY1_ADDR
165 # undef AU1XXX_PHY1_BUSID
166 # undef AU1XXX_PHY1_IRQ
167 #endif
169 #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
170 # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
171 #endif
173 static void enable_mac(struct net_device *dev, int force_reset)
175 unsigned long flags;
176 struct au1000_private *aup = netdev_priv(dev);
178 spin_lock_irqsave(&aup->lock, flags);
180 if(force_reset || (!aup->mac_enabled)) {
181 *aup->enable = MAC_EN_CLOCK_ENABLE;
182 au_sync_delay(2);
183 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
184 | MAC_EN_CLOCK_ENABLE);
185 au_sync_delay(2);
187 aup->mac_enabled = 1;
190 spin_unlock_irqrestore(&aup->lock, flags);
194 * MII operations
196 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
198 struct au1000_private *aup = netdev_priv(dev);
199 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
200 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
201 u32 timedout = 20;
202 u32 mii_control;
204 while (*mii_control_reg & MAC_MII_BUSY) {
205 mdelay(1);
206 if (--timedout == 0) {
207 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
208 dev->name);
209 return -1;
213 mii_control = MAC_SET_MII_SELECT_REG(reg) |
214 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
216 *mii_control_reg = mii_control;
218 timedout = 20;
219 while (*mii_control_reg & MAC_MII_BUSY) {
220 mdelay(1);
221 if (--timedout == 0) {
222 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
223 dev->name);
224 return -1;
227 return (int)*mii_data_reg;
230 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
231 int reg, u16 value)
233 struct au1000_private *aup = netdev_priv(dev);
234 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
235 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
236 u32 timedout = 20;
237 u32 mii_control;
239 while (*mii_control_reg & MAC_MII_BUSY) {
240 mdelay(1);
241 if (--timedout == 0) {
242 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
243 dev->name);
244 return;
248 mii_control = MAC_SET_MII_SELECT_REG(reg) |
249 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
251 *mii_data_reg = value;
252 *mii_control_reg = mii_control;
255 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
257 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
258 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
259 struct net_device *const dev = bus->priv;
261 enable_mac(dev, 0); /* make sure the MAC associated with this
262 * mii_bus is enabled */
263 return au1000_mdio_read(dev, phy_addr, regnum);
266 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
267 u16 value)
269 struct net_device *const dev = bus->priv;
271 enable_mac(dev, 0); /* make sure the MAC associated with this
272 * mii_bus is enabled */
273 au1000_mdio_write(dev, phy_addr, regnum, value);
274 return 0;
277 static int au1000_mdiobus_reset(struct mii_bus *bus)
279 struct net_device *const dev = bus->priv;
281 enable_mac(dev, 0); /* make sure the MAC associated with this
282 * mii_bus is enabled */
283 return 0;
286 static void hard_stop(struct net_device *dev)
288 struct au1000_private *aup = netdev_priv(dev);
290 if (au1000_debug > 4)
291 printk(KERN_INFO "%s: hard stop\n", dev->name);
293 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
294 au_sync_delay(10);
297 static void enable_rx_tx(struct net_device *dev)
299 struct au1000_private *aup = netdev_priv(dev);
301 if (au1000_debug > 4)
302 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
304 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
305 au_sync_delay(10);
308 static void
309 au1000_adjust_link(struct net_device *dev)
311 struct au1000_private *aup = netdev_priv(dev);
312 struct phy_device *phydev = aup->phy_dev;
313 unsigned long flags;
315 int status_change = 0;
317 BUG_ON(!aup->phy_dev);
319 spin_lock_irqsave(&aup->lock, flags);
321 if (phydev->link && (aup->old_speed != phydev->speed)) {
322 // speed changed
324 switch(phydev->speed) {
325 case SPEED_10:
326 case SPEED_100:
327 break;
328 default:
329 printk(KERN_WARNING
330 "%s: Speed (%d) is not 10/100 ???\n",
331 dev->name, phydev->speed);
332 break;
335 aup->old_speed = phydev->speed;
337 status_change = 1;
340 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
341 // duplex mode changed
343 /* switching duplex mode requires to disable rx and tx! */
344 hard_stop(dev);
346 if (DUPLEX_FULL == phydev->duplex)
347 aup->mac->control = ((aup->mac->control
348 | MAC_FULL_DUPLEX)
349 & ~MAC_DISABLE_RX_OWN);
350 else
351 aup->mac->control = ((aup->mac->control
352 & ~MAC_FULL_DUPLEX)
353 | MAC_DISABLE_RX_OWN);
354 au_sync_delay(1);
356 enable_rx_tx(dev);
357 aup->old_duplex = phydev->duplex;
359 status_change = 1;
362 if(phydev->link != aup->old_link) {
363 // link state changed
365 if (!phydev->link) {
366 /* link went down */
367 aup->old_speed = 0;
368 aup->old_duplex = -1;
371 aup->old_link = phydev->link;
372 status_change = 1;
375 spin_unlock_irqrestore(&aup->lock, flags);
377 if (status_change) {
378 if (phydev->link)
379 printk(KERN_INFO "%s: link up (%d/%s)\n",
380 dev->name, phydev->speed,
381 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
382 else
383 printk(KERN_INFO "%s: link down\n", dev->name);
387 static int mii_probe (struct net_device *dev)
389 struct au1000_private *const aup = netdev_priv(dev);
390 struct phy_device *phydev = NULL;
392 #if defined(AU1XXX_PHY_STATIC_CONFIG)
393 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
395 if(aup->mac_id == 0) { /* get PHY0 */
396 # if defined(AU1XXX_PHY0_ADDR)
397 phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR];
398 # else
399 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
400 dev->name);
401 return 0;
402 # endif /* defined(AU1XXX_PHY0_ADDR) */
403 } else if (aup->mac_id == 1) { /* get PHY1 */
404 # if defined(AU1XXX_PHY1_ADDR)
405 phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR];
406 # else
407 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
408 dev->name);
409 return 0;
410 # endif /* defined(AU1XXX_PHY1_ADDR) */
413 #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */
414 int phy_addr;
416 /* find the first (lowest address) PHY on the current MAC's MII bus */
417 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
418 if (aup->mii_bus->phy_map[phy_addr]) {
419 phydev = aup->mii_bus->phy_map[phy_addr];
420 # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR)
421 break; /* break out with first one found */
422 # endif
425 # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0)
426 /* try harder to find a PHY */
427 if (!phydev && (aup->mac_id == 1)) {
428 /* no PHY found, maybe we have a dual PHY? */
429 printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
430 "let's see if it's attached to MAC0...\n");
432 BUG_ON(!au_macs[0]);
434 /* find the first (lowest address) non-attached PHY on
435 * the MAC0 MII bus */
436 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
437 struct phy_device *const tmp_phydev =
438 au_macs[0]->mii_bus->phy_map[phy_addr];
440 if (!tmp_phydev)
441 continue; /* no PHY here... */
443 if (tmp_phydev->attached_dev)
444 continue; /* already claimed by MAC0 */
446 phydev = tmp_phydev;
447 break; /* found it */
450 # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */
452 #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */
453 if (!phydev) {
454 printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
455 return -1;
458 /* now we are supposed to have a proper phydev, to attach to... */
459 BUG_ON(phydev->attached_dev);
461 phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
462 0, PHY_INTERFACE_MODE_MII);
464 if (IS_ERR(phydev)) {
465 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
466 return PTR_ERR(phydev);
469 /* mask with MAC supported features */
470 phydev->supported &= (SUPPORTED_10baseT_Half
471 | SUPPORTED_10baseT_Full
472 | SUPPORTED_100baseT_Half
473 | SUPPORTED_100baseT_Full
474 | SUPPORTED_Autoneg
475 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
476 | SUPPORTED_MII
477 | SUPPORTED_TP);
479 phydev->advertising = phydev->supported;
481 aup->old_link = 0;
482 aup->old_speed = 0;
483 aup->old_duplex = -1;
484 aup->phy_dev = phydev;
486 printk(KERN_INFO "%s: attached PHY driver [%s] "
487 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
488 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
490 return 0;
495 * Buffer allocation/deallocation routines. The buffer descriptor returned
496 * has the virtual and dma address of a buffer suitable for
497 * both, receive and transmit operations.
499 static db_dest_t *GetFreeDB(struct au1000_private *aup)
501 db_dest_t *pDB;
502 pDB = aup->pDBfree;
504 if (pDB) {
505 aup->pDBfree = pDB->pnext;
507 return pDB;
510 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
512 db_dest_t *pDBfree = aup->pDBfree;
513 if (pDBfree)
514 pDBfree->pnext = pDB;
515 aup->pDBfree = pDB;
518 static void reset_mac_unlocked(struct net_device *dev)
520 struct au1000_private *const aup = netdev_priv(dev);
521 int i;
523 hard_stop(dev);
525 *aup->enable = MAC_EN_CLOCK_ENABLE;
526 au_sync_delay(2);
527 *aup->enable = 0;
528 au_sync_delay(2);
530 aup->tx_full = 0;
531 for (i = 0; i < NUM_RX_DMA; i++) {
532 /* reset control bits */
533 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
535 for (i = 0; i < NUM_TX_DMA; i++) {
536 /* reset control bits */
537 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
540 aup->mac_enabled = 0;
544 static void reset_mac(struct net_device *dev)
546 struct au1000_private *const aup = netdev_priv(dev);
547 unsigned long flags;
549 if (au1000_debug > 4)
550 printk(KERN_INFO "%s: reset mac, aup %x\n",
551 dev->name, (unsigned)aup);
553 spin_lock_irqsave(&aup->lock, flags);
555 reset_mac_unlocked (dev);
557 spin_unlock_irqrestore(&aup->lock, flags);
561 * Setup the receive and transmit "rings". These pointers are the addresses
562 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
563 * these are not descriptors sitting in memory.
565 static void
566 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
568 int i;
570 for (i = 0; i < NUM_RX_DMA; i++) {
571 aup->rx_dma_ring[i] =
572 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
574 for (i = 0; i < NUM_TX_DMA; i++) {
575 aup->tx_dma_ring[i] =
576 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
580 static struct {
581 u32 base_addr;
582 u32 macen_addr;
583 int irq;
584 struct net_device *dev;
585 } iflist[2] = {
586 #ifdef CONFIG_SOC_AU1000
587 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
588 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
589 #endif
590 #ifdef CONFIG_SOC_AU1100
591 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
592 #endif
593 #ifdef CONFIG_SOC_AU1500
594 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
595 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
596 #endif
597 #ifdef CONFIG_SOC_AU1550
598 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
599 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
600 #endif
603 static int num_ifs;
606 * ethtool operations
609 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
611 struct au1000_private *aup = netdev_priv(dev);
613 if (aup->phy_dev)
614 return phy_ethtool_gset(aup->phy_dev, cmd);
616 return -EINVAL;
619 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
621 struct au1000_private *aup = netdev_priv(dev);
623 if (!capable(CAP_NET_ADMIN))
624 return -EPERM;
626 if (aup->phy_dev)
627 return phy_ethtool_sset(aup->phy_dev, cmd);
629 return -EINVAL;
632 static void
633 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
635 struct au1000_private *aup = netdev_priv(dev);
637 strcpy(info->driver, DRV_NAME);
638 strcpy(info->version, DRV_VERSION);
639 info->fw_version[0] = '\0';
640 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
641 info->regdump_len = 0;
644 static const struct ethtool_ops au1000_ethtool_ops = {
645 .get_settings = au1000_get_settings,
646 .set_settings = au1000_set_settings,
647 .get_drvinfo = au1000_get_drvinfo,
648 .get_link = ethtool_op_get_link,
653 * Initialize the interface.
655 * When the device powers up, the clocks are disabled and the
656 * mac is in reset state. When the interface is closed, we
657 * do the same -- reset the device and disable the clocks to
658 * conserve power. Thus, whenever au1000_init() is called,
659 * the device should already be in reset state.
661 static int au1000_init(struct net_device *dev)
663 struct au1000_private *aup = netdev_priv(dev);
664 unsigned long flags;
665 int i;
666 u32 control;
668 if (au1000_debug > 4)
669 printk("%s: au1000_init\n", dev->name);
671 /* bring the device out of reset */
672 enable_mac(dev, 1);
674 spin_lock_irqsave(&aup->lock, flags);
676 aup->mac->control = 0;
677 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
678 aup->tx_tail = aup->tx_head;
679 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
681 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
682 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
683 dev->dev_addr[1]<<8 | dev->dev_addr[0];
685 for (i = 0; i < NUM_RX_DMA; i++) {
686 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
688 au_sync();
690 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
691 #ifndef CONFIG_CPU_LITTLE_ENDIAN
692 control |= MAC_BIG_ENDIAN;
693 #endif
694 if (aup->phy_dev) {
695 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
696 control |= MAC_FULL_DUPLEX;
697 else
698 control |= MAC_DISABLE_RX_OWN;
699 } else { /* PHY-less op, assume full-duplex */
700 control |= MAC_FULL_DUPLEX;
703 aup->mac->control = control;
704 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
705 au_sync();
707 spin_unlock_irqrestore(&aup->lock, flags);
708 return 0;
711 static inline void update_rx_stats(struct net_device *dev, u32 status)
713 struct au1000_private *aup = netdev_priv(dev);
714 struct net_device_stats *ps = &dev->stats;
716 ps->rx_packets++;
717 if (status & RX_MCAST_FRAME)
718 ps->multicast++;
720 if (status & RX_ERROR) {
721 ps->rx_errors++;
722 if (status & RX_MISSED_FRAME)
723 ps->rx_missed_errors++;
724 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
725 ps->rx_length_errors++;
726 if (status & RX_CRC_ERROR)
727 ps->rx_crc_errors++;
728 if (status & RX_COLL)
729 ps->collisions++;
731 else
732 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
737 * Au1000 receive routine.
739 static int au1000_rx(struct net_device *dev)
741 struct au1000_private *aup = netdev_priv(dev);
742 struct sk_buff *skb;
743 volatile rx_dma_t *prxd;
744 u32 buff_stat, status;
745 db_dest_t *pDB;
746 u32 frmlen;
748 if (au1000_debug > 5)
749 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
751 prxd = aup->rx_dma_ring[aup->rx_head];
752 buff_stat = prxd->buff_stat;
753 while (buff_stat & RX_T_DONE) {
754 status = prxd->status;
755 pDB = aup->rx_db_inuse[aup->rx_head];
756 update_rx_stats(dev, status);
757 if (!(status & RX_ERROR)) {
759 /* good frame */
760 frmlen = (status & RX_FRAME_LEN_MASK);
761 frmlen -= 4; /* Remove FCS */
762 skb = dev_alloc_skb(frmlen + 2);
763 if (skb == NULL) {
764 printk(KERN_ERR
765 "%s: Memory squeeze, dropping packet.\n",
766 dev->name);
767 dev->stats.rx_dropped++;
768 continue;
770 skb_reserve(skb, 2); /* 16 byte IP header align */
771 skb_copy_to_linear_data(skb,
772 (unsigned char *)pDB->vaddr, frmlen);
773 skb_put(skb, frmlen);
774 skb->protocol = eth_type_trans(skb, dev);
775 netif_rx(skb); /* pass the packet to upper layers */
777 else {
778 if (au1000_debug > 4) {
779 if (status & RX_MISSED_FRAME)
780 printk("rx miss\n");
781 if (status & RX_WDOG_TIMER)
782 printk("rx wdog\n");
783 if (status & RX_RUNT)
784 printk("rx runt\n");
785 if (status & RX_OVERLEN)
786 printk("rx overlen\n");
787 if (status & RX_COLL)
788 printk("rx coll\n");
789 if (status & RX_MII_ERROR)
790 printk("rx mii error\n");
791 if (status & RX_CRC_ERROR)
792 printk("rx crc error\n");
793 if (status & RX_LEN_ERROR)
794 printk("rx len error\n");
795 if (status & RX_U_CNTRL_FRAME)
796 printk("rx u control frame\n");
799 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
800 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
801 au_sync();
803 /* next descriptor */
804 prxd = aup->rx_dma_ring[aup->rx_head];
805 buff_stat = prxd->buff_stat;
807 return 0;
810 static void update_tx_stats(struct net_device *dev, u32 status)
812 struct au1000_private *aup = netdev_priv(dev);
813 struct net_device_stats *ps = &dev->stats;
815 if (status & TX_FRAME_ABORTED) {
816 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
817 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
818 /* any other tx errors are only valid
819 * in half duplex mode */
820 ps->tx_errors++;
821 ps->tx_aborted_errors++;
824 else {
825 ps->tx_errors++;
826 ps->tx_aborted_errors++;
827 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
828 ps->tx_carrier_errors++;
834 * Called from the interrupt service routine to acknowledge
835 * the TX DONE bits. This is a must if the irq is setup as
836 * edge triggered.
838 static void au1000_tx_ack(struct net_device *dev)
840 struct au1000_private *aup = netdev_priv(dev);
841 volatile tx_dma_t *ptxd;
843 ptxd = aup->tx_dma_ring[aup->tx_tail];
845 while (ptxd->buff_stat & TX_T_DONE) {
846 update_tx_stats(dev, ptxd->status);
847 ptxd->buff_stat &= ~TX_T_DONE;
848 ptxd->len = 0;
849 au_sync();
851 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
852 ptxd = aup->tx_dma_ring[aup->tx_tail];
854 if (aup->tx_full) {
855 aup->tx_full = 0;
856 netif_wake_queue(dev);
862 * Au1000 interrupt service routine.
864 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
866 struct net_device *dev = dev_id;
868 /* Handle RX interrupts first to minimize chance of overrun */
870 au1000_rx(dev);
871 au1000_tx_ack(dev);
872 return IRQ_RETVAL(1);
875 static int au1000_open(struct net_device *dev)
877 int retval;
878 struct au1000_private *aup = netdev_priv(dev);
880 if (au1000_debug > 4)
881 printk("%s: open: dev=%p\n", dev->name, dev);
883 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
884 dev->name, dev))) {
885 printk(KERN_ERR "%s: unable to get IRQ %d\n",
886 dev->name, dev->irq);
887 return retval;
890 if ((retval = au1000_init(dev))) {
891 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
892 free_irq(dev->irq, dev);
893 return retval;
896 if (aup->phy_dev) {
897 /* cause the PHY state machine to schedule a link state check */
898 aup->phy_dev->state = PHY_CHANGELINK;
899 phy_start(aup->phy_dev);
902 netif_start_queue(dev);
904 if (au1000_debug > 4)
905 printk("%s: open: Initialization done.\n", dev->name);
907 return 0;
910 static int au1000_close(struct net_device *dev)
912 unsigned long flags;
913 struct au1000_private *const aup = netdev_priv(dev);
915 if (au1000_debug > 4)
916 printk("%s: close: dev=%p\n", dev->name, dev);
918 if (aup->phy_dev)
919 phy_stop(aup->phy_dev);
921 spin_lock_irqsave(&aup->lock, flags);
923 reset_mac_unlocked (dev);
925 /* stop the device */
926 netif_stop_queue(dev);
928 /* disable the interrupt */
929 free_irq(dev->irq, dev);
930 spin_unlock_irqrestore(&aup->lock, flags);
932 return 0;
936 * Au1000 transmit routine.
938 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
940 struct au1000_private *aup = netdev_priv(dev);
941 struct net_device_stats *ps = &dev->stats;
942 volatile tx_dma_t *ptxd;
943 u32 buff_stat;
944 db_dest_t *pDB;
945 int i;
947 if (au1000_debug > 5)
948 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
949 dev->name, (unsigned)aup, skb->len,
950 skb->data, aup->tx_head);
952 ptxd = aup->tx_dma_ring[aup->tx_head];
953 buff_stat = ptxd->buff_stat;
954 if (buff_stat & TX_DMA_ENABLE) {
955 /* We've wrapped around and the transmitter is still busy */
956 netif_stop_queue(dev);
957 aup->tx_full = 1;
958 return NETDEV_TX_BUSY;
960 else if (buff_stat & TX_T_DONE) {
961 update_tx_stats(dev, ptxd->status);
962 ptxd->len = 0;
965 if (aup->tx_full) {
966 aup->tx_full = 0;
967 netif_wake_queue(dev);
970 pDB = aup->tx_db_inuse[aup->tx_head];
971 skb_copy_from_linear_data(skb, pDB->vaddr, skb->len);
972 if (skb->len < ETH_ZLEN) {
973 for (i=skb->len; i<ETH_ZLEN; i++) {
974 ((char *)pDB->vaddr)[i] = 0;
976 ptxd->len = ETH_ZLEN;
978 else
979 ptxd->len = skb->len;
981 ps->tx_packets++;
982 ps->tx_bytes += ptxd->len;
984 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
985 au_sync();
986 dev_kfree_skb(skb);
987 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
988 dev->trans_start = jiffies;
989 return NETDEV_TX_OK;
993 * The Tx ring has been full longer than the watchdog timeout
994 * value. The transmitter must be hung?
996 static void au1000_tx_timeout(struct net_device *dev)
998 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
999 reset_mac(dev);
1000 au1000_init(dev);
1001 dev->trans_start = jiffies;
1002 netif_wake_queue(dev);
1005 static void au1000_multicast_list(struct net_device *dev)
1007 struct au1000_private *aup = netdev_priv(dev);
1009 if (au1000_debug > 4)
1010 printk("%s: au1000_multicast_list: flags=%x\n", dev->name, dev->flags);
1012 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1013 aup->mac->control |= MAC_PROMISCUOUS;
1014 } else if ((dev->flags & IFF_ALLMULTI) ||
1015 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1016 aup->mac->control |= MAC_PASS_ALL_MULTI;
1017 aup->mac->control &= ~MAC_PROMISCUOUS;
1018 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1019 } else {
1020 int i;
1021 struct dev_mc_list *mclist;
1022 u32 mc_filter[2]; /* Multicast hash filter */
1024 mc_filter[1] = mc_filter[0] = 0;
1025 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1026 i++, mclist = mclist->next) {
1027 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
1028 (long *)mc_filter);
1030 aup->mac->multi_hash_high = mc_filter[1];
1031 aup->mac->multi_hash_low = mc_filter[0];
1032 aup->mac->control &= ~MAC_PROMISCUOUS;
1033 aup->mac->control |= MAC_HASH_MODE;
1037 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1039 struct au1000_private *aup = netdev_priv(dev);
1041 if (!netif_running(dev)) return -EINVAL;
1043 if (!aup->phy_dev) return -EINVAL; // PHY not controllable
1045 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1048 static const struct net_device_ops au1000_netdev_ops = {
1049 .ndo_open = au1000_open,
1050 .ndo_stop = au1000_close,
1051 .ndo_start_xmit = au1000_tx,
1052 .ndo_set_multicast_list = au1000_multicast_list,
1053 .ndo_do_ioctl = au1000_ioctl,
1054 .ndo_tx_timeout = au1000_tx_timeout,
1055 .ndo_set_mac_address = eth_mac_addr,
1056 .ndo_validate_addr = eth_validate_addr,
1057 .ndo_change_mtu = eth_change_mtu,
1060 static struct net_device * au1000_probe(int port_num)
1062 static unsigned version_printed = 0;
1063 struct au1000_private *aup = NULL;
1064 struct net_device *dev = NULL;
1065 db_dest_t *pDB, *pDBfree;
1066 char ethaddr[6];
1067 int irq, i, err;
1068 u32 base, macen;
1070 if (port_num >= NUM_ETH_INTERFACES)
1071 return NULL;
1073 base = CPHYSADDR(iflist[port_num].base_addr );
1074 macen = CPHYSADDR(iflist[port_num].macen_addr);
1075 irq = iflist[port_num].irq;
1077 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
1078 !request_mem_region(macen, 4, "Au1x00 ENET"))
1079 return NULL;
1081 if (version_printed++ == 0)
1082 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1084 dev = alloc_etherdev(sizeof(struct au1000_private));
1085 if (!dev) {
1086 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
1087 return NULL;
1090 if ((err = register_netdev(dev)) != 0) {
1091 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
1092 DRV_NAME, err);
1093 free_netdev(dev);
1094 return NULL;
1097 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
1098 dev->name, base, irq);
1100 aup = netdev_priv(dev);
1102 spin_lock_init(&aup->lock);
1104 /* Allocate the data buffers */
1105 /* Snooping works fine with eth on all au1xxx */
1106 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1107 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1108 &aup->dma_addr, 0);
1109 if (!aup->vaddr) {
1110 free_netdev(dev);
1111 release_mem_region( base, MAC_IOSIZE);
1112 release_mem_region(macen, 4);
1113 return NULL;
1116 /* aup->mac is the base address of the MAC's registers */
1117 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
1119 /* Setup some variables for quick register address access */
1120 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
1121 aup->mac_id = port_num;
1122 au_macs[port_num] = aup;
1124 if (port_num == 0) {
1125 if (prom_get_ethernet_addr(ethaddr) == 0)
1126 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
1127 else {
1128 printk(KERN_INFO "%s: No MAC address found\n",
1129 dev->name);
1130 /* Use the hard coded MAC addresses */
1133 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
1134 } else if (port_num == 1)
1135 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1138 * Assign to the Ethernet ports two consecutive MAC addresses
1139 * to match those that are printed on their stickers
1141 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
1142 dev->dev_addr[5] += port_num;
1144 *aup->enable = 0;
1145 aup->mac_enabled = 0;
1147 aup->mii_bus = mdiobus_alloc();
1148 if (aup->mii_bus == NULL)
1149 goto err_out;
1151 aup->mii_bus->priv = dev;
1152 aup->mii_bus->read = au1000_mdiobus_read;
1153 aup->mii_bus->write = au1000_mdiobus_write;
1154 aup->mii_bus->reset = au1000_mdiobus_reset;
1155 aup->mii_bus->name = "au1000_eth_mii";
1156 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
1157 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1158 if (aup->mii_bus->irq == NULL)
1159 goto err_out;
1161 for(i = 0; i < PHY_MAX_ADDR; ++i)
1162 aup->mii_bus->irq[i] = PHY_POLL;
1164 /* if known, set corresponding PHY IRQs */
1165 #if defined(AU1XXX_PHY_STATIC_CONFIG)
1166 # if defined(AU1XXX_PHY0_IRQ)
1167 if (AU1XXX_PHY0_BUSID == aup->mac_id)
1168 aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
1169 # endif
1170 # if defined(AU1XXX_PHY1_IRQ)
1171 if (AU1XXX_PHY1_BUSID == aup->mac_id)
1172 aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
1173 # endif
1174 #endif
1175 mdiobus_register(aup->mii_bus);
1177 if (mii_probe(dev) != 0) {
1178 goto err_out;
1181 pDBfree = NULL;
1182 /* setup the data buffer descriptors and attach a buffer to each one */
1183 pDB = aup->db;
1184 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1185 pDB->pnext = pDBfree;
1186 pDBfree = pDB;
1187 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1188 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1189 pDB++;
1191 aup->pDBfree = pDBfree;
1193 for (i = 0; i < NUM_RX_DMA; i++) {
1194 pDB = GetFreeDB(aup);
1195 if (!pDB) {
1196 goto err_out;
1198 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1199 aup->rx_db_inuse[i] = pDB;
1201 for (i = 0; i < NUM_TX_DMA; i++) {
1202 pDB = GetFreeDB(aup);
1203 if (!pDB) {
1204 goto err_out;
1206 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1207 aup->tx_dma_ring[i]->len = 0;
1208 aup->tx_db_inuse[i] = pDB;
1211 dev->base_addr = base;
1212 dev->irq = irq;
1213 dev->netdev_ops = &au1000_netdev_ops;
1214 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1215 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1218 * The boot code uses the ethernet controller, so reset it to start
1219 * fresh. au1000_init() expects that the device is in reset state.
1221 reset_mac(dev);
1223 return dev;
1225 err_out:
1226 if (aup->mii_bus != NULL) {
1227 mdiobus_unregister(aup->mii_bus);
1228 mdiobus_free(aup->mii_bus);
1231 /* here we should have a valid dev plus aup-> register addresses
1232 * so we can reset the mac properly.*/
1233 reset_mac(dev);
1235 for (i = 0; i < NUM_RX_DMA; i++) {
1236 if (aup->rx_db_inuse[i])
1237 ReleaseDB(aup, aup->rx_db_inuse[i]);
1239 for (i = 0; i < NUM_TX_DMA; i++) {
1240 if (aup->tx_db_inuse[i])
1241 ReleaseDB(aup, aup->tx_db_inuse[i]);
1243 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1244 (void *)aup->vaddr, aup->dma_addr);
1245 unregister_netdev(dev);
1246 free_netdev(dev);
1247 release_mem_region( base, MAC_IOSIZE);
1248 release_mem_region(macen, 4);
1249 return NULL;
1253 * Setup the base address and interrupt of the Au1xxx ethernet macs
1254 * based on cpu type and whether the interface is enabled in sys_pinfunc
1255 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
1257 static int __init au1000_init_module(void)
1259 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
1260 struct net_device *dev;
1261 int i, found_one = 0;
1263 num_ifs = NUM_ETH_INTERFACES - ni;
1265 for(i = 0; i < num_ifs; i++) {
1266 dev = au1000_probe(i);
1267 iflist[i].dev = dev;
1268 if (dev)
1269 found_one++;
1271 if (!found_one)
1272 return -ENODEV;
1273 return 0;
1276 static void __exit au1000_cleanup_module(void)
1278 int i, j;
1279 struct net_device *dev;
1280 struct au1000_private *aup;
1282 for (i = 0; i < num_ifs; i++) {
1283 dev = iflist[i].dev;
1284 if (dev) {
1285 aup = netdev_priv(dev);
1286 unregister_netdev(dev);
1287 mdiobus_unregister(aup->mii_bus);
1288 mdiobus_free(aup->mii_bus);
1289 for (j = 0; j < NUM_RX_DMA; j++)
1290 if (aup->rx_db_inuse[j])
1291 ReleaseDB(aup, aup->rx_db_inuse[j]);
1292 for (j = 0; j < NUM_TX_DMA; j++)
1293 if (aup->tx_db_inuse[j])
1294 ReleaseDB(aup, aup->tx_db_inuse[j]);
1295 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1296 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1297 (void *)aup->vaddr, aup->dma_addr);
1298 release_mem_region(dev->base_addr, MAC_IOSIZE);
1299 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1300 free_netdev(dev);
1305 module_init(au1000_init_module);
1306 module_exit(au1000_cleanup_module);