2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/irq.h>
31 #include <linux/time.h>
32 #include <linux/gpio.h>
34 #include <asm/mach/time.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach-types.h>
38 #include <mach/irqs.h>
39 #include <mach/clock.h>
40 #include <mach/sram.h>
41 #include <mach/control.h>
44 #include <mach/board.h>
47 #include "prm-regbits-24xx.h"
49 #include "cm-regbits-24xx.h"
53 #include <mach/powerdomain.h>
54 #include <mach/clockdomain.h>
56 static void (*omap2_sram_idle
)(void);
57 static void (*omap2_sram_suspend
)(u32 dllctrl
, void __iomem
*sdrc_dlla_ctrl
,
58 void __iomem
*sdrc_power
);
60 static struct powerdomain
*mpu_pwrdm
;
61 static struct powerdomain
*core_pwrdm
;
63 static struct clockdomain
*dsp_clkdm
;
64 static struct clockdomain
*gfx_clkdm
;
66 static struct clk
*osc_ck
, *emul_ck
;
68 static int omap2_fclks_active(void)
72 f1
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
73 f2
= cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
75 /* Ignore UART clocks. These are handled by UART core (serial.c) */
76 f1
&= ~(OMAP24XX_EN_UART1
| OMAP24XX_EN_UART2
);
77 f2
&= ~OMAP24XX_EN_UART3
;
84 static void omap2_enter_full_retention(void)
87 struct timespec ts_preidle
, ts_postidle
, ts_idle
;
89 /* There is 1 reference hold for all children of the oscillator
90 * clock, the following will remove it. If no one else uses the
91 * oscillator itself it will be disabled if/when we enter retention
96 /* Clear old wake-up events */
97 /* REVISIT: These write to reserved bits? */
98 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
99 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
100 prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
103 * Set MPU powerdomain's next power state to RETENTION;
104 * preserve logic state during retention
106 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
107 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
109 /* Workaround to kill USB */
110 l
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
) | OMAP24XX_USBSTANDBYCTRL
;
111 omap_ctrl_writel(l
, OMAP2_CONTROL_DEVCONF0
);
113 omap2_gpio_prepare_for_retention();
115 if (omap2_pm_debug
) {
116 omap2_pm_dump(0, 0, 0);
117 getnstimeofday(&ts_preidle
);
120 /* One last check for pending IRQs to avoid extra latency due
121 * to sleeping unnecessarily. */
122 if (omap_irq_pending())
125 omap_uart_prepare_idle(0);
126 omap_uart_prepare_idle(1);
127 omap_uart_prepare_idle(2);
129 /* Jump to SRAM suspend code */
130 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL
),
131 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL
),
132 OMAP_SDRC_REGADDR(SDRC_POWER
));
134 omap_uart_resume_idle(2);
135 omap_uart_resume_idle(1);
136 omap_uart_resume_idle(0);
139 if (omap2_pm_debug
) {
140 unsigned long long tmp
;
142 getnstimeofday(&ts_postidle
);
143 ts_idle
= timespec_sub(ts_postidle
, ts_preidle
);
144 tmp
= timespec_to_ns(&ts_idle
) * NSEC_PER_USEC
;
145 omap2_pm_dump(0, 1, tmp
);
147 omap2_gpio_resume_after_retention();
151 /* clear CORE wake-up events */
152 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
153 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
155 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
156 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD
, PM_WKST
);
158 /* MPU domain wake events */
159 l
= prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
161 prm_write_mod_reg(0x01, OCP_MOD
,
162 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
164 prm_write_mod_reg(0x20, OCP_MOD
,
165 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
167 /* Mask future PRCM-to-MPU interrupts */
168 prm_write_mod_reg(0x0, OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
171 static int omap2_i2c_active(void)
175 l
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
176 return l
& (OMAP2420_EN_I2C2
| OMAP2420_EN_I2C1
);
179 static int sti_console_enabled
;
181 static int omap2_allow_mpu_retention(void)
185 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
186 l
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
187 if (l
& (OMAP2420_EN_MMC
| OMAP24XX_EN_UART2
|
188 OMAP24XX_EN_UART1
| OMAP24XX_EN_MCSPI2
|
189 OMAP24XX_EN_MCSPI1
| OMAP24XX_EN_DSS1
))
191 /* Check for UART3. */
192 l
= cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
193 if (l
& OMAP24XX_EN_UART3
)
195 if (sti_console_enabled
)
201 static void omap2_enter_mpu_retention(void)
204 struct timespec ts_preidle
, ts_postidle
, ts_idle
;
206 /* Putting MPU into the WFI state while a transfer is active
207 * seems to cause the I2C block to timeout. Why? Good question. */
208 if (omap2_i2c_active())
211 /* The peripherals seem not to be able to wake up the MPU when
212 * it is in retention mode. */
213 if (omap2_allow_mpu_retention()) {
214 /* REVISIT: These write to reserved bits? */
215 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
216 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
217 prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
219 /* Try to enter MPU retention */
220 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT
) |
222 MPU_MOD
, PM_PWSTCTRL
);
224 /* Block MPU retention */
226 prm_write_mod_reg(OMAP_LOGICRETSTATE
, MPU_MOD
, PM_PWSTCTRL
);
230 if (omap2_pm_debug
) {
231 omap2_pm_dump(only_idle
? 2 : 1, 0, 0);
232 getnstimeofday(&ts_preidle
);
237 if (omap2_pm_debug
) {
238 unsigned long long tmp
;
240 getnstimeofday(&ts_postidle
);
241 ts_idle
= timespec_sub(ts_postidle
, ts_preidle
);
242 tmp
= timespec_to_ns(&ts_idle
) * NSEC_PER_USEC
;
243 omap2_pm_dump(only_idle
? 2 : 1, 1, tmp
);
247 static int omap2_can_sleep(void)
249 if (omap2_fclks_active())
251 if (osc_ck
->usecount
> 1)
253 if (omap_dma_running())
259 static void omap2_pm_idle(void)
264 if (!omap2_can_sleep()) {
265 if (omap_irq_pending())
267 omap2_enter_mpu_retention();
271 if (omap_irq_pending())
274 omap2_enter_full_retention();
281 static int omap2_pm_prepare(void)
283 /* We cannot sleep in idle until we have resumed */
288 static int omap2_pm_suspend(void)
292 wken_wkup
= prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
293 prm_write_mod_reg(wken_wkup
& ~OMAP24XX_EN_GPT1
, WKUP_MOD
, PM_WKEN
);
296 mir1
= omap_readl(0x480fe0a4);
297 omap_writel(1 << 5, 0x480fe0ac);
299 omap_uart_prepare_suspend();
300 omap2_enter_full_retention();
302 omap_writel(mir1
, 0x480fe0a4);
303 prm_write_mod_reg(wken_wkup
, WKUP_MOD
, PM_WKEN
);
308 static int omap2_pm_enter(suspend_state_t state
)
313 case PM_SUSPEND_STANDBY
:
315 ret
= omap2_pm_suspend();
324 static void omap2_pm_finish(void)
329 static struct platform_suspend_ops omap_pm_ops
= {
330 .prepare
= omap2_pm_prepare
,
331 .enter
= omap2_pm_enter
,
332 .finish
= omap2_pm_finish
,
333 .valid
= suspend_valid_only_mem
,
336 static int _pm_clkdm_enable_hwsup(struct clockdomain
*clkdm
, void *unused
)
338 omap2_clkdm_allow_idle(clkdm
);
342 static void __init
prcm_setup_regs(void)
344 int i
, num_mem_banks
;
345 struct powerdomain
*pwrdm
;
347 /* Enable autoidle */
348 prm_write_mod_reg(OMAP24XX_AUTOIDLE
, OCP_MOD
,
349 OMAP2_PRCM_SYSCONFIG_OFFSET
);
351 /* Set all domain wakeup dependencies */
352 prm_write_mod_reg(OMAP_EN_WKUP_MASK
, MPU_MOD
, PM_WKDEP
);
353 prm_write_mod_reg(0, OMAP24XX_DSP_MOD
, PM_WKDEP
);
354 prm_write_mod_reg(0, GFX_MOD
, PM_WKDEP
);
355 prm_write_mod_reg(0, CORE_MOD
, PM_WKDEP
);
356 if (cpu_is_omap2430())
357 prm_write_mod_reg(0, OMAP2430_MDM_MOD
, PM_WKDEP
);
360 * Set CORE powerdomain memory banks to retain their contents
363 num_mem_banks
= pwrdm_get_mem_bank_count(core_pwrdm
);
364 for (i
= 0; i
< num_mem_banks
; i
++)
365 pwrdm_set_mem_retst(core_pwrdm
, i
, PWRDM_POWER_RET
);
367 /* Set CORE powerdomain's next power state to RETENTION */
368 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_RET
);
371 * Set MPU powerdomain's next power state to RETENTION;
372 * preserve logic state during retention
374 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
375 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
377 /* Force-power down DSP, GFX powerdomains */
379 pwrdm
= clkdm_get_pwrdm(dsp_clkdm
);
380 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
381 omap2_clkdm_sleep(dsp_clkdm
);
383 pwrdm
= clkdm_get_pwrdm(gfx_clkdm
);
384 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
385 omap2_clkdm_sleep(gfx_clkdm
);
387 /* Enable clockdomain hardware-supervised control for all clkdms */
388 clkdm_for_each(_pm_clkdm_enable_hwsup
, NULL
);
390 /* Enable clock autoidle for all domains */
391 cm_write_mod_reg(OMAP24XX_AUTO_CAM
|
392 OMAP24XX_AUTO_MAILBOXES
|
395 OMAP24XX_AUTO_MSPRO
|
400 OMAP24XX_AUTO_UART2
|
401 OMAP24XX_AUTO_UART1
|
404 OMAP24XX_AUTO_MCSPI2
|
405 OMAP24XX_AUTO_MCSPI1
|
406 OMAP24XX_AUTO_MCBSP2
|
407 OMAP24XX_AUTO_MCBSP1
|
408 OMAP24XX_AUTO_GPT12
|
409 OMAP24XX_AUTO_GPT11
|
410 OMAP24XX_AUTO_GPT10
|
419 OMAP2420_AUTO_VLYNQ
|
421 CORE_MOD
, CM_AUTOIDLE1
);
422 cm_write_mod_reg(OMAP24XX_AUTO_UART3
|
425 CORE_MOD
, CM_AUTOIDLE2
);
426 cm_write_mod_reg(OMAP24XX_AUTO_SDRC
|
429 CORE_MOD
, CM_AUTOIDLE3
);
430 cm_write_mod_reg(OMAP24XX_AUTO_PKA
|
435 CORE_MOD
, OMAP24XX_CM_AUTOIDLE4
);
437 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI
, OMAP24XX_DSP_MOD
, CM_AUTOIDLE
);
439 /* Put DPLL and both APLLs into autoidle mode */
440 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT
) |
441 (0x03 << OMAP24XX_AUTO_96M_SHIFT
) |
442 (0x03 << OMAP24XX_AUTO_54M_SHIFT
),
443 PLL_MOD
, CM_AUTOIDLE
);
445 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL
|
447 OMAP24XX_AUTO_MPU_WDT
|
448 OMAP24XX_AUTO_GPIOS
|
449 OMAP24XX_AUTO_32KSYNC
|
451 WKUP_MOD
, CM_AUTOIDLE
);
453 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
455 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
456 OMAP2_PRCM_CLKSSETUP_OFFSET
);
458 /* Configure automatic voltage transition */
459 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
460 OMAP2_PRCM_VOLTSETUP_OFFSET
);
461 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT
|
462 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT
) |
463 OMAP24XX_MEMRETCTRL
|
464 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT
) |
465 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT
),
466 OMAP24XX_GR_MOD
, OMAP2_PRCM_VOLTCTRL_OFFSET
);
468 /* Enable wake-up events */
469 prm_write_mod_reg(OMAP24XX_EN_GPIOS
| OMAP24XX_EN_GPT1
,
473 static int __init
omap2_pm_init(void)
477 if (!cpu_is_omap24xx())
480 printk(KERN_INFO
"Power Management for OMAP2 initializing\n");
481 l
= prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_REVISION_OFFSET
);
482 printk(KERN_INFO
"PRCM revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
484 /* Look up important powerdomains, clockdomains */
486 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
488 pr_err("PM: mpu_pwrdm not found\n");
490 core_pwrdm
= pwrdm_lookup("core_pwrdm");
492 pr_err("PM: core_pwrdm not found\n");
494 dsp_clkdm
= clkdm_lookup("dsp_clkdm");
496 pr_err("PM: mpu_clkdm not found\n");
498 gfx_clkdm
= clkdm_lookup("gfx_clkdm");
500 pr_err("PM: gfx_clkdm not found\n");
503 osc_ck
= clk_get(NULL
, "osc_ck");
504 if (IS_ERR(osc_ck
)) {
505 printk(KERN_ERR
"could not get osc_ck\n");
509 if (cpu_is_omap242x()) {
510 emul_ck
= clk_get(NULL
, "emul_ck");
511 if (IS_ERR(emul_ck
)) {
512 printk(KERN_ERR
"could not get emul_ck\n");
520 /* Hack to prevent MPU retention when STI console is enabled. */
522 const struct omap_sti_console_config
*sti
;
524 sti
= omap_get_config(OMAP_TAG_STI_CONSOLE
,
525 struct omap_sti_console_config
);
526 if (sti
!= NULL
&& sti
->enable
)
527 sti_console_enabled
= 1;
531 * We copy the assembler sleep/wakeup routines to SRAM.
532 * These routines need to be in SRAM as that's the only
533 * memory the MPU can see when it wakes up.
535 if (cpu_is_omap24xx()) {
536 omap2_sram_idle
= omap_sram_push(omap24xx_idle_loop_suspend
,
537 omap24xx_idle_loop_suspend_sz
);
539 omap2_sram_suspend
= omap_sram_push(omap24xx_cpu_suspend
,
540 omap24xx_cpu_suspend_sz
);
543 suspend_set_ops(&omap_pm_ops
);
544 pm_idle
= omap2_pm_idle
;
549 late_initcall(omap2_pm_init
);