arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <mach/clock.h>
  40 #include <mach/sram.h>
  41 #include <mach/control.h>
  42 #include <mach/mux.h>
  43 #include <mach/dma.h>
  44 #include <mach/board.h>
  45
  46 #include "prm.h"
  47 #include "prm-regbits-24xx.h"
  48 #include "cm.h"
  49 #include "cm-regbits-24xx.h"
  50 #include "sdrc.h"
  51 #include "pm.h"
  52
  53 #include <mach/powerdomain.h>
  54 #include <mach/clockdomain.h>
  55
  56 static void (*omap2_sram_idle)(void);
  57 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  58                                   void __iomem *sdrc_power);
  59
  60 static struct powerdomain *mpu_pwrdm;
  61 static struct powerdomain *core_pwrdm;
  62
  63 static struct clockdomain *dsp_clkdm;
  64 static struct clockdomain *gfx_clkdm;
  65
  66 static struct clk *osc_ck, *emul_ck;
  67
  68 static int omap2_fclks_active(void)
  69 {
  70         u32 f1, f2;
  71
  72         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  73         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  74
  75         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  76         f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
  77         f2 &= ~OMAP24XX_EN_UART3;
  78
  79         if (f1 | f2)
  80                 return 1;
  81         return 0;
  82 }
  83
  84 static void omap2_enter_full_retention(void)
  85 {
  86         u32 l;
  87         struct timespec ts_preidle, ts_postidle, ts_idle;
  88
  89         /* There is 1 reference hold for all children of the oscillator
  90          * clock, the following will remove it. If no one else uses the
  91          * oscillator itself it will be disabled if/when we enter retention
  92          * mode.
  93          */
  94         clk_disable(osc_ck);
  95
  96         /* Clear old wake-up events */
  97         /* REVISIT: These write to reserved bits? */
  98         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  99         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 100         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 101
 102         /*
 103          * Set MPU powerdomain's next power state to RETENTION;
 104          * preserve logic state during retention
 105          */
 106         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 107         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 108
 109         /* Workaround to kill USB */
 110         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 111         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 112
 113         omap2_gpio_prepare_for_retention();
 114
 115         if (omap2_pm_debug) {
 116                 omap2_pm_dump(0, 0, 0);
 117                 getnstimeofday(&ts_preidle);
 118         }
 119
 120         /* One last check for pending IRQs to avoid extra latency due
 121          * to sleeping unnecessarily. */
 122         if (omap_irq_pending())
 123                 goto no_sleep;
 124
 125         omap_uart_prepare_idle(0);
 126         omap_uart_prepare_idle(1);
 127         omap_uart_prepare_idle(2);
 128
 129         /* Jump to SRAM suspend code */
 130         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 131                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 132                            OMAP_SDRC_REGADDR(SDRC_POWER));
 133
 134         omap_uart_resume_idle(2);
 135         omap_uart_resume_idle(1);
 136         omap_uart_resume_idle(0);
 137
 138 no_sleep:
 139         if (omap2_pm_debug) {
 140                 unsigned long long tmp;
 141
 142                 getnstimeofday(&ts_postidle);
 143                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 144                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 145                 omap2_pm_dump(0, 1, tmp);
 146         }
 147         omap2_gpio_resume_after_retention();
 148
 149         clk_enable(osc_ck);
 150
 151         /* clear CORE wake-up events */
 152         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 153         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 154
 155         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 156         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 157
 158         /* MPU domain wake events */
 159         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 160         if (l & 0x01)
 161                 prm_write_mod_reg(0x01, OCP_MOD,
 162                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 163         if (l & 0x20)
 164                 prm_write_mod_reg(0x20, OCP_MOD,
 165                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 166
 167         /* Mask future PRCM-to-MPU interrupts */
 168         prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 169 }
 170
 171 static int omap2_i2c_active(void)
 172 {
 173         u32 l;
 174
 175         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 176         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 177 }
 178
 179 static int sti_console_enabled;
 180
 181 static int omap2_allow_mpu_retention(void)
 182 {
 183         u32 l;
 184
 185         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 186         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 187         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 188                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 189                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 190                 return 0;
 191         /* Check for UART3. */
 192         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 193         if (l & OMAP24XX_EN_UART3)
 194                 return 0;
 195         if (sti_console_enabled)
 196                 return 0;
 197
 198         return 1;
 199 }
 200
 201 static void omap2_enter_mpu_retention(void)
 202 {
 203         int only_idle = 0;
 204         struct timespec ts_preidle, ts_postidle, ts_idle;
 205
 206         /* Putting MPU into the WFI state while a transfer is active
 207          * seems to cause the I2C block to timeout. Why? Good question. */
 208         if (omap2_i2c_active())
 209                 return;
 210
 211         /* The peripherals seem not to be able to wake up the MPU when
 212          * it is in retention mode. */
 213         if (omap2_allow_mpu_retention()) {
 214                 /* REVISIT: These write to reserved bits? */
 215                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 216                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 217                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 218
 219                 /* Try to enter MPU retention */
 220                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 221                                   OMAP_LOGICRETSTATE,
 222                                   MPU_MOD, PM_PWSTCTRL);
 223         } else {
 224                 /* Block MPU retention */
 225
 226                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 227                 only_idle = 1;
 228         }
 229
 230         if (omap2_pm_debug) {
 231                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 232                 getnstimeofday(&ts_preidle);
 233         }
 234
 235         omap2_sram_idle();
 236
 237         if (omap2_pm_debug) {
 238                 unsigned long long tmp;
 239
 240                 getnstimeofday(&ts_postidle);
 241                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 242                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 243                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
 244         }
 245 }
 246
 247 static int omap2_can_sleep(void)
 248 {
 249         if (omap2_fclks_active())
 250                 return 0;
 251         if (osc_ck->usecount > 1)
 252                 return 0;
 253         if (omap_dma_running())
 254                 return 0;
 255
 256         return 1;
 257 }
 258
 259 static void omap2_pm_idle(void)
 260 {
 261         local_irq_disable();
 262         local_fiq_disable();
 263
 264         if (!omap2_can_sleep()) {
 265                 if (omap_irq_pending())
 266                         goto out;
 267                 omap2_enter_mpu_retention();
 268                 goto out;
 269         }
 270
 271         if (omap_irq_pending())
 272                 goto out;
 273
 274         omap2_enter_full_retention();
 275
 276 out:
 277         local_fiq_enable();
 278         local_irq_enable();
 279 }
 280
 281 static int omap2_pm_prepare(void)
 282 {
 283         /* We cannot sleep in idle until we have resumed */
 284         disable_hlt();
 285         return 0;
 286 }
 287
 288 static int omap2_pm_suspend(void)
 289 {
 290         u32 wken_wkup, mir1;
 291
 292         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 293         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 294
 295         /* Mask GPT1 */
 296         mir1 = omap_readl(0x480fe0a4);
 297         omap_writel(1 << 5, 0x480fe0ac);
 298
 299         omap_uart_prepare_suspend();
 300         omap2_enter_full_retention();
 301
 302         omap_writel(mir1, 0x480fe0a4);
 303         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 304
 305         return 0;
 306 }
 307
 308 static int omap2_pm_enter(suspend_state_t state)
 309 {
 310         int ret = 0;
 311
 312         switch (state) {
 313         case PM_SUSPEND_STANDBY:
 314         case PM_SUSPEND_MEM:
 315                 ret = omap2_pm_suspend();
 316                 break;
 317         default:
 318                 ret = -EINVAL;
 319         }
 320
 321         return ret;
 322 }
 323
 324 static void omap2_pm_finish(void)
 325 {
 326         enable_hlt();
 327 }
 328
 329 static struct platform_suspend_ops omap_pm_ops = {
 330         .prepare        = omap2_pm_prepare,
 331         .enter          = omap2_pm_enter,
 332         .finish         = omap2_pm_finish,
 333         .valid          = suspend_valid_only_mem,
 334 };
 335
 336 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
 337 {
 338         omap2_clkdm_allow_idle(clkdm);
 339         return 0;
 340 }
 341
 342 static void __init prcm_setup_regs(void)
 343 {
 344         int i, num_mem_banks;
 345         struct powerdomain *pwrdm;
 346
 347         /* Enable autoidle */
 348         prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
 349                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 350
 351         /* Set all domain wakeup dependencies */
 352         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 353         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 354         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 355         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 356         if (cpu_is_omap2430())
 357                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 358
 359         /*
 360          * Set CORE powerdomain memory banks to retain their contents
 361          * during RETENTION
 362          */
 363         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 364         for (i = 0; i < num_mem_banks; i++)
 365                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 366
 367         /* Set CORE powerdomain's next power state to RETENTION */
 368         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 369
 370         /*
 371          * Set MPU powerdomain's next power state to RETENTION;
 372          * preserve logic state during retention
 373          */
 374         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 375         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 376
 377         /* Force-power down DSP, GFX powerdomains */
 378
 379         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 380         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 381         omap2_clkdm_sleep(dsp_clkdm);
 382
 383         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 384         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 385         omap2_clkdm_sleep(gfx_clkdm);
 386
 387         /* Enable clockdomain hardware-supervised control for all clkdms */
 388         clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
 389
 390         /* Enable clock autoidle for all domains */
 391         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 392                          OMAP24XX_AUTO_MAILBOXES |
 393                          OMAP24XX_AUTO_WDT4 |
 394                          OMAP2420_AUTO_WDT3 |
 395                          OMAP24XX_AUTO_MSPRO |
 396                          OMAP2420_AUTO_MMC |
 397                          OMAP24XX_AUTO_FAC |
 398                          OMAP2420_AUTO_EAC |
 399                          OMAP24XX_AUTO_HDQ |
 400                          OMAP24XX_AUTO_UART2 |
 401                          OMAP24XX_AUTO_UART1 |
 402                          OMAP24XX_AUTO_I2C2 |
 403                          OMAP24XX_AUTO_I2C1 |
 404                          OMAP24XX_AUTO_MCSPI2 |
 405                          OMAP24XX_AUTO_MCSPI1 |
 406                          OMAP24XX_AUTO_MCBSP2 |
 407                          OMAP24XX_AUTO_MCBSP1 |
 408                          OMAP24XX_AUTO_GPT12 |
 409                          OMAP24XX_AUTO_GPT11 |
 410                          OMAP24XX_AUTO_GPT10 |
 411                          OMAP24XX_AUTO_GPT9 |
 412                          OMAP24XX_AUTO_GPT8 |
 413                          OMAP24XX_AUTO_GPT7 |
 414                          OMAP24XX_AUTO_GPT6 |
 415                          OMAP24XX_AUTO_GPT5 |
 416                          OMAP24XX_AUTO_GPT4 |
 417                          OMAP24XX_AUTO_GPT3 |
 418                          OMAP24XX_AUTO_GPT2 |
 419                          OMAP2420_AUTO_VLYNQ |
 420                          OMAP24XX_AUTO_DSS,
 421                          CORE_MOD, CM_AUTOIDLE1);
 422         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 423                          OMAP24XX_AUTO_SSI |
 424                          OMAP24XX_AUTO_USB,
 425                          CORE_MOD, CM_AUTOIDLE2);
 426         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 427                          OMAP24XX_AUTO_GPMC |
 428                          OMAP24XX_AUTO_SDMA,
 429                          CORE_MOD, CM_AUTOIDLE3);
 430         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 431                          OMAP24XX_AUTO_AES |
 432                          OMAP24XX_AUTO_RNG |
 433                          OMAP24XX_AUTO_SHA |
 434                          OMAP24XX_AUTO_DES,
 435                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 436
 437         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 438
 439         /* Put DPLL and both APLLs into autoidle mode */
 440         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 441                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 442                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 443                          PLL_MOD, CM_AUTOIDLE);
 444
 445         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 446                          OMAP24XX_AUTO_WDT1 |
 447                          OMAP24XX_AUTO_MPU_WDT |
 448                          OMAP24XX_AUTO_GPIOS |
 449                          OMAP24XX_AUTO_32KSYNC |
 450                          OMAP24XX_AUTO_GPT1,
 451                          WKUP_MOD, CM_AUTOIDLE);
 452
 453         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 454          * stabilisation */
 455         prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 456                           OMAP2_PRCM_CLKSSETUP_OFFSET);
 457
 458         /* Configure automatic voltage transition */
 459         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 460                           OMAP2_PRCM_VOLTSETUP_OFFSET);
 461         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
 462                           (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 463                           OMAP24XX_MEMRETCTRL |
 464                           (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 465                           (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 466                           OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 467
 468         /* Enable wake-up events */
 469         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 470                           WKUP_MOD, PM_WKEN);
 471 }
 472
 473 static int __init omap2_pm_init(void)
 474 {
 475         u32 l;
 476
 477         if (!cpu_is_omap24xx())
 478                 return -ENODEV;
 479
 480         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 481         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 482         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 483
 484         /* Look up important powerdomains, clockdomains */
 485
 486         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 487         if (!mpu_pwrdm)
 488                 pr_err("PM: mpu_pwrdm not found\n");
 489
 490         core_pwrdm = pwrdm_lookup("core_pwrdm");
 491         if (!core_pwrdm)
 492                 pr_err("PM: core_pwrdm not found\n");
 493
 494         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 495         if (!dsp_clkdm)
 496                 pr_err("PM: mpu_clkdm not found\n");
 497
 498         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 499         if (!gfx_clkdm)
 500                 pr_err("PM: gfx_clkdm not found\n");
 501
 502
 503         osc_ck = clk_get(NULL, "osc_ck");
 504         if (IS_ERR(osc_ck)) {
 505                 printk(KERN_ERR "could not get osc_ck\n");
 506                 return -ENODEV;
 507         }
 508
 509         if (cpu_is_omap242x()) {
 510                 emul_ck = clk_get(NULL, "emul_ck");
 511                 if (IS_ERR(emul_ck)) {
 512                         printk(KERN_ERR "could not get emul_ck\n");
 513                         clk_put(osc_ck);
 514                         return -ENODEV;
 515                 }
 516         }
 517
 518         prcm_setup_regs();
 519
 520         /* Hack to prevent MPU retention when STI console is enabled. */
 521         {
 522                 const struct omap_sti_console_config *sti;
 523
 524                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 525                                       struct omap_sti_console_config);
 526                 if (sti != NULL && sti->enable)
 527                         sti_console_enabled = 1;
 528         }
 529
 530         /*
 531          * We copy the assembler sleep/wakeup routines to SRAM.
 532          * These routines need to be in SRAM as that's the only
 533          * memory the MPU can see when it wakes up.
 534          */
 535         if (cpu_is_omap24xx()) {
 536                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 537                                                  omap24xx_idle_loop_suspend_sz);
 538
 539                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 540                                                     omap24xx_cpu_suspend_sz);
 541         }
 542
 543         suspend_set_ops(&omap_pm_ops);
 544         pm_idle = omap2_pm_idle;
 545
 546         return 0;
 547 }
 548
 549 late_initcall(omap2_pm_init);