cfg80211: fix looping soft lockup in find_ie()
[linux-2.6/verdex.git] / drivers / serial / s3c6400.c
blob4be92ab50058284f0cf823bf4ed4ab10b5c80be9
1 /* linux/drivers/serial/s3c6400.c
3 * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/init.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
23 #include <asm/irq.h>
24 #include <mach/hardware.h>
26 #include <plat/regs-serial.h>
28 #include "samsung.h"
30 static int s3c6400_serial_setsource(struct uart_port *port,
31 struct s3c24xx_uart_clksrc *clk)
33 unsigned long ucon = rd_regl(port, S3C2410_UCON);
35 if (strcmp(clk->name, "uclk0") == 0) {
36 ucon &= ~S3C6400_UCON_CLKMASK;
37 ucon |= S3C6400_UCON_UCLK0;
38 } else if (strcmp(clk->name, "uclk1") == 0)
39 ucon |= S3C6400_UCON_UCLK1;
40 else if (strcmp(clk->name, "pclk") == 0) {
41 /* See notes about transitioning from UCLK to PCLK */
42 ucon &= ~S3C6400_UCON_UCLK0;
43 } else {
44 printk(KERN_ERR "unknown clock source %s\n", clk->name);
45 return -EINVAL;
48 wr_regl(port, S3C2410_UCON, ucon);
49 return 0;
53 static int s3c6400_serial_getsource(struct uart_port *port,
54 struct s3c24xx_uart_clksrc *clk)
56 u32 ucon = rd_regl(port, S3C2410_UCON);
58 clk->divisor = 1;
60 switch (ucon & S3C6400_UCON_CLKMASK) {
61 case S3C6400_UCON_UCLK0:
62 clk->name = "uclk0";
63 break;
65 case S3C6400_UCON_UCLK1:
66 clk->name = "uclk1";
67 break;
69 case S3C6400_UCON_PCLK:
70 case S3C6400_UCON_PCLK2:
71 clk->name = "pclk";
72 break;
75 return 0;
78 static int s3c6400_serial_resetport(struct uart_port *port,
79 struct s3c2410_uartcfg *cfg)
81 unsigned long ucon = rd_regl(port, S3C2410_UCON);
83 dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
84 port, port->mapbase, cfg);
86 /* ensure we don't change the clock settings... */
88 ucon &= S3C6400_UCON_CLKMASK;
90 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
91 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
93 /* reset both fifos */
95 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
96 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
98 return 0;
101 static struct s3c24xx_uart_info s3c6400_uart_inf = {
102 .name = "Samsung S3C6400 UART",
103 .type = PORT_S3C6400,
104 .fifosize = 64,
105 .has_divslot = 1,
106 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
107 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
108 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
109 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
110 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
111 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
112 .get_clksrc = s3c6400_serial_getsource,
113 .set_clksrc = s3c6400_serial_setsource,
114 .reset_port = s3c6400_serial_resetport,
117 /* device management */
119 static int s3c6400_serial_probe(struct platform_device *dev)
121 dbg("s3c6400_serial_probe: dev=%p\n", dev);
122 return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
125 static struct platform_driver s3c6400_serial_driver = {
126 .probe = s3c6400_serial_probe,
127 .remove = __devexit_p(s3c24xx_serial_remove),
128 .driver = {
129 .name = "s3c6400-uart",
130 .owner = THIS_MODULE,
134 s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
136 static int __init s3c6400_serial_init(void)
138 return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
141 static void __exit s3c6400_serial_exit(void)
143 platform_driver_unregister(&s3c6400_serial_driver);
146 module_init(s3c6400_serial_init);
147 module_exit(s3c6400_serial_exit);
149 MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
150 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
151 MODULE_LICENSE("GPL v2");
152 MODULE_ALIAS("platform:s3c6400-uart");