2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name
[] = DRV_NAME
;
47 const char qlge_driver_version
[] = DRV_VERSION
;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING
" ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION
);
54 static const u32 default_msg
=
55 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
|
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR
| NETIF_MSG_TX_DONE
| NETIF_MSG_RX_STATUS
|
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW
| NETIF_MSG_WOL
| 0;
66 static int debug
= 0x00007fff; /* defaults above */
67 module_param(debug
, int, 0);
68 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
73 static int irq_type
= MSIX_IRQ
;
74 module_param(irq_type
, int, MSIX_IRQ
);
75 MODULE_PARM_DESC(irq_type
, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl
[] __devinitdata
= {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QLGE_DEVICE_ID
)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QLGE_DEVICE_ID1
)},
80 /* required last entry */
84 MODULE_DEVICE_TABLE(pci
, qlge_pci_tbl
);
86 /* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
90 static int ql_sem_trylock(struct ql_adapter
*qdev
, u32 sem_mask
)
96 sem_bits
= SEM_SET
<< SEM_XGMAC0_SHIFT
;
99 sem_bits
= SEM_SET
<< SEM_XGMAC1_SHIFT
;
102 sem_bits
= SEM_SET
<< SEM_ICB_SHIFT
;
104 case SEM_MAC_ADDR_MASK
:
105 sem_bits
= SEM_SET
<< SEM_MAC_ADDR_SHIFT
;
108 sem_bits
= SEM_SET
<< SEM_FLASH_SHIFT
;
111 sem_bits
= SEM_SET
<< SEM_PROBE_SHIFT
;
113 case SEM_RT_IDX_MASK
:
114 sem_bits
= SEM_SET
<< SEM_RT_IDX_SHIFT
;
116 case SEM_PROC_REG_MASK
:
117 sem_bits
= SEM_SET
<< SEM_PROC_REG_SHIFT
;
120 QPRINTK(qdev
, PROBE
, ALERT
, "Bad Semaphore mask!.\n");
124 ql_write32(qdev
, SEM
, sem_bits
| sem_mask
);
125 return !(ql_read32(qdev
, SEM
) & sem_bits
);
128 int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
)
130 unsigned int seconds
= 3;
132 if (!ql_sem_trylock(qdev
, sem_mask
))
139 void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
)
141 ql_write32(qdev
, SEM
, sem_mask
);
142 ql_read32(qdev
, SEM
); /* flush */
145 /* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
150 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 err_bit
)
153 int count
= UDELAY_COUNT
;
156 temp
= ql_read32(qdev
, reg
);
158 /* check for errors */
159 if (temp
& err_bit
) {
160 QPRINTK(qdev
, PROBE
, ALERT
,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
164 } else if (temp
& bit
)
166 udelay(UDELAY_DELAY
);
169 QPRINTK(qdev
, PROBE
, ALERT
,
170 "Timed out waiting for reg %x to come ready.\n", reg
);
174 /* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
177 static int ql_wait_cfg(struct ql_adapter
*qdev
, u32 bit
)
179 int count
= UDELAY_COUNT
;
183 temp
= ql_read32(qdev
, CFG
);
188 udelay(UDELAY_DELAY
);
195 /* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
198 int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
208 (bit
& (CFG_LRQ
| CFG_LR
| CFG_LCQ
)) ? PCI_DMA_TODEVICE
:
211 map
= pci_map_single(qdev
->pdev
, ptr
, size
, direction
);
212 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
213 QPRINTK(qdev
, IFUP
, ERR
, "Couldn't map DMA area.\n");
217 status
= ql_wait_cfg(qdev
, bit
);
219 QPRINTK(qdev
, IFUP
, ERR
,
220 "Timed out waiting for CFG to come ready.\n");
224 status
= ql_sem_spinlock(qdev
, SEM_ICB_MASK
);
227 ql_write32(qdev
, ICB_L
, (u32
) map
);
228 ql_write32(qdev
, ICB_H
, (u32
) (map
>> 32));
229 ql_sem_unlock(qdev
, SEM_ICB_MASK
); /* does flush too */
231 mask
= CFG_Q_MASK
| (bit
<< 16);
232 value
= bit
| (q_id
<< CFG_Q_SHIFT
);
233 ql_write32(qdev
, CFG
, (mask
| value
));
236 * Wait for the bit to clear after signaling hw.
238 status
= ql_wait_cfg(qdev
, bit
);
240 pci_unmap_single(qdev
->pdev
, map
, size
, direction
);
244 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
251 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
255 case MAC_ADDR_TYPE_MULTI_MAC
:
256 case MAC_ADDR_TYPE_CAM_MAC
:
259 ql_wait_reg_rdy(qdev
,
260 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
263 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
264 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
265 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
267 ql_wait_reg_rdy(qdev
,
268 MAC_ADDR_IDX
, MAC_ADDR_MR
, MAC_ADDR_E
);
271 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
273 ql_wait_reg_rdy(qdev
,
274 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
277 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
278 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
279 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
281 ql_wait_reg_rdy(qdev
,
282 MAC_ADDR_IDX
, MAC_ADDR_MR
, MAC_ADDR_E
);
285 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
286 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
288 ql_wait_reg_rdy(qdev
,
289 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
292 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
293 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
294 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
296 ql_wait_reg_rdy(qdev
, MAC_ADDR_IDX
,
297 MAC_ADDR_MR
, MAC_ADDR_E
);
300 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
304 case MAC_ADDR_TYPE_VLAN
:
305 case MAC_ADDR_TYPE_MULTI_FLTR
:
307 QPRINTK(qdev
, IFUP
, CRIT
,
308 "Address type %d not yet supported.\n", type
);
312 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
316 /* Set up a MAC, multicast or VLAN address for the
317 * inbound frame matching.
319 static int ql_set_mac_addr_reg(struct ql_adapter
*qdev
, u8
*addr
, u32 type
,
325 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
329 case MAC_ADDR_TYPE_MULTI_MAC
:
330 case MAC_ADDR_TYPE_CAM_MAC
:
333 u32 upper
= (addr
[0] << 8) | addr
[1];
335 (addr
[2] << 24) | (addr
[3] << 16) | (addr
[4] << 8) |
338 QPRINTK(qdev
, IFUP
, INFO
,
339 "Adding %s address %pM"
340 " at index %d in the CAM.\n",
342 MAC_ADDR_TYPE_MULTI_MAC
) ? "MULTICAST" :
343 "UNICAST"), addr
, index
);
346 ql_wait_reg_rdy(qdev
,
347 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
350 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
351 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
353 ql_write32(qdev
, MAC_ADDR_DATA
, lower
);
355 ql_wait_reg_rdy(qdev
,
356 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
359 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
360 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
362 ql_write32(qdev
, MAC_ADDR_DATA
, upper
);
364 ql_wait_reg_rdy(qdev
,
365 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
368 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
) | /* offset */
369 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
371 /* This field should also include the queue id
372 and possibly the function id. Right now we hardcode
373 the route field to NIC core.
375 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
376 cam_output
= (CAM_OUT_ROUTE_NIC
|
378 func
<< CAM_OUT_FUNC_SHIFT
) |
380 rss_ring_first_cq_id
<<
381 CAM_OUT_CQ_ID_SHIFT
));
383 cam_output
|= CAM_OUT_RV
;
384 /* route to NIC core */
385 ql_write32(qdev
, MAC_ADDR_DATA
, cam_output
);
389 case MAC_ADDR_TYPE_VLAN
:
391 u32 enable_bit
= *((u32
*) &addr
[0]);
392 /* For VLAN, the addr actually holds a bit that
393 * either enables or disables the vlan id we are
394 * addressing. It's either MAC_ADDR_E on or off.
395 * That's bit-27 we're talking about.
397 QPRINTK(qdev
, IFUP
, INFO
, "%s VLAN ID %d %s the CAM.\n",
398 (enable_bit
? "Adding" : "Removing"),
399 index
, (enable_bit
? "to" : "from"));
402 ql_wait_reg_rdy(qdev
,
403 MAC_ADDR_IDX
, MAC_ADDR_MW
, MAC_ADDR_E
);
406 ql_write32(qdev
, MAC_ADDR_IDX
, offset
| /* offset */
407 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
409 enable_bit
); /* enable/disable */
412 case MAC_ADDR_TYPE_MULTI_FLTR
:
414 QPRINTK(qdev
, IFUP
, CRIT
,
415 "Address type %d not yet supported.\n", type
);
419 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
423 /* Get a specific frame routing value from the CAM.
424 * Used for debug and reg dump.
426 int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
)
430 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
434 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, RT_IDX_E
);
438 ql_write32(qdev
, RT_IDX
,
439 RT_IDX_TYPE_NICQ
| RT_IDX_RS
| (index
<< RT_IDX_IDX_SHIFT
));
440 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MR
, RT_IDX_E
);
443 *value
= ql_read32(qdev
, RT_DATA
);
445 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
449 /* The NIC function for this chip has 16 routing indexes. Each one can be used
450 * to route different frame types to various inbound queues. We send broadcast/
451 * multicast/error frames to the default queue for slow handling,
452 * and CAM hit/RSS frames to the fast handling queues.
454 static int ql_set_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32 mask
,
460 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
464 QPRINTK(qdev
, IFUP
, DEBUG
,
465 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
466 (enable
? "Adding" : "Removing"),
467 ((index
== RT_IDX_ALL_ERR_SLOT
) ? "MAC ERROR/ALL ERROR" : ""),
468 ((index
== RT_IDX_IP_CSUM_ERR_SLOT
) ? "IP CSUM ERROR" : ""),
470 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
) ? "TCP/UDP CSUM ERROR" : ""),
471 ((index
== RT_IDX_BCAST_SLOT
) ? "BROADCAST" : ""),
472 ((index
== RT_IDX_MCAST_MATCH_SLOT
) ? "MULTICAST MATCH" : ""),
473 ((index
== RT_IDX_ALLMULTI_SLOT
) ? "ALL MULTICAST MATCH" : ""),
474 ((index
== RT_IDX_UNUSED6_SLOT
) ? "UNUSED6" : ""),
475 ((index
== RT_IDX_UNUSED7_SLOT
) ? "UNUSED7" : ""),
476 ((index
== RT_IDX_RSS_MATCH_SLOT
) ? "RSS ALL/IPV4 MATCH" : ""),
477 ((index
== RT_IDX_RSS_IPV6_SLOT
) ? "RSS IPV6" : ""),
478 ((index
== RT_IDX_RSS_TCP4_SLOT
) ? "RSS TCP4" : ""),
479 ((index
== RT_IDX_RSS_TCP6_SLOT
) ? "RSS TCP6" : ""),
480 ((index
== RT_IDX_CAM_HIT_SLOT
) ? "CAM HIT" : ""),
481 ((index
== RT_IDX_UNUSED013
) ? "UNUSED13" : ""),
482 ((index
== RT_IDX_UNUSED014
) ? "UNUSED14" : ""),
483 ((index
== RT_IDX_PROMISCUOUS_SLOT
) ? "PROMISCUOUS" : ""),
484 (enable
? "to" : "from"));
489 value
= RT_IDX_DST_CAM_Q
| /* dest */
490 RT_IDX_TYPE_NICQ
| /* type */
491 (RT_IDX_CAM_HIT_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
494 case RT_IDX_VALID
: /* Promiscuous Mode frames. */
496 value
= RT_IDX_DST_DFLT_Q
| /* dest */
497 RT_IDX_TYPE_NICQ
| /* type */
498 (RT_IDX_PROMISCUOUS_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
501 case RT_IDX_ERR
: /* Pass up MAC,IP,TCP/UDP error frames. */
503 value
= RT_IDX_DST_DFLT_Q
| /* dest */
504 RT_IDX_TYPE_NICQ
| /* type */
505 (RT_IDX_ALL_ERR_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
508 case RT_IDX_BCAST
: /* Pass up Broadcast frames to default Q. */
510 value
= RT_IDX_DST_DFLT_Q
| /* dest */
511 RT_IDX_TYPE_NICQ
| /* type */
512 (RT_IDX_BCAST_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
515 case RT_IDX_MCAST
: /* Pass up All Multicast frames. */
517 value
= RT_IDX_DST_CAM_Q
| /* dest */
518 RT_IDX_TYPE_NICQ
| /* type */
519 (RT_IDX_ALLMULTI_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
522 case RT_IDX_MCAST_MATCH
: /* Pass up matched Multicast frames. */
524 value
= RT_IDX_DST_CAM_Q
| /* dest */
525 RT_IDX_TYPE_NICQ
| /* type */
526 (RT_IDX_MCAST_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
529 case RT_IDX_RSS_MATCH
: /* Pass up matched RSS frames. */
531 value
= RT_IDX_DST_RSS
| /* dest */
532 RT_IDX_TYPE_NICQ
| /* type */
533 (RT_IDX_RSS_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
536 case 0: /* Clear the E-bit on an entry. */
538 value
= RT_IDX_DST_DFLT_Q
| /* dest */
539 RT_IDX_TYPE_NICQ
| /* type */
540 (index
<< RT_IDX_IDX_SHIFT
);/* index */
544 QPRINTK(qdev
, IFUP
, ERR
, "Mask type %d not yet supported.\n",
551 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
554 value
|= (enable
? RT_IDX_E
: 0);
555 ql_write32(qdev
, RT_IDX
, value
);
556 ql_write32(qdev
, RT_DATA
, enable
? mask
: 0);
559 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
563 static void ql_enable_interrupts(struct ql_adapter
*qdev
)
565 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16) | INTR_EN_EI
);
568 static void ql_disable_interrupts(struct ql_adapter
*qdev
)
570 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16));
573 /* If we're running with multiple MSI-X vectors then we enable on the fly.
574 * Otherwise, we may have multiple outstanding workers and don't want to
575 * enable until the last one finishes. In this case, the irq_cnt gets
576 * incremented everytime we queue a worker and decremented everytime
577 * a worker finishes. Once it hits zero we enable the interrupt.
579 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
582 unsigned long hw_flags
= 0;
583 struct intr_context
*ctx
= qdev
->intr_context
+ intr
;
585 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
)) {
586 /* Always enable if we're MSIX multi interrupts and
587 * it's not the default (zeroeth) interrupt.
589 ql_write32(qdev
, INTR_EN
,
591 var
= ql_read32(qdev
, STS
);
595 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
596 if (atomic_dec_and_test(&ctx
->irq_cnt
)) {
597 ql_write32(qdev
, INTR_EN
,
599 var
= ql_read32(qdev
, STS
);
601 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
605 static u32
ql_disable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
608 unsigned long hw_flags
;
609 struct intr_context
*ctx
;
611 /* HW disables for us if we're MSIX multi interrupts and
612 * it's not the default (zeroeth) interrupt.
614 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
))
617 ctx
= qdev
->intr_context
+ intr
;
618 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
619 if (!atomic_read(&ctx
->irq_cnt
)) {
620 ql_write32(qdev
, INTR_EN
,
622 var
= ql_read32(qdev
, STS
);
624 atomic_inc(&ctx
->irq_cnt
);
625 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
629 static void ql_enable_all_completion_interrupts(struct ql_adapter
*qdev
)
632 for (i
= 0; i
< qdev
->intr_count
; i
++) {
633 /* The enable call does a atomic_dec_and_test
634 * and enables only if the result is zero.
635 * So we precharge it here.
637 if (unlikely(!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) ||
639 atomic_set(&qdev
->intr_context
[i
].irq_cnt
, 1);
640 ql_enable_completion_interrupt(qdev
, i
);
645 static int ql_read_flash_word(struct ql_adapter
*qdev
, int offset
, u32
*data
)
648 /* wait for reg to come ready */
649 status
= ql_wait_reg_rdy(qdev
,
650 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
653 /* set up for reg read */
654 ql_write32(qdev
, FLASH_ADDR
, FLASH_ADDR_R
| offset
);
655 /* wait for reg to come ready */
656 status
= ql_wait_reg_rdy(qdev
,
657 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
661 *data
= ql_read32(qdev
, FLASH_DATA
);
666 static int ql_get_flash_params(struct ql_adapter
*qdev
)
670 u32
*p
= (u32
*)&qdev
->flash
;
672 if (ql_sem_spinlock(qdev
, SEM_FLASH_MASK
))
675 for (i
= 0; i
< sizeof(qdev
->flash
) / sizeof(u32
); i
++, p
++) {
676 status
= ql_read_flash_word(qdev
, i
, p
);
678 QPRINTK(qdev
, IFUP
, ERR
, "Error reading flash.\n");
684 ql_sem_unlock(qdev
, SEM_FLASH_MASK
);
688 /* xgmac register are located behind the xgmac_addr and xgmac_data
689 * register pair. Each read/write requires us to wait for the ready
690 * bit before reading/writing the data.
692 static int ql_write_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32 data
)
695 /* wait for reg to come ready */
696 status
= ql_wait_reg_rdy(qdev
,
697 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
700 /* write the data to the data reg */
701 ql_write32(qdev
, XGMAC_DATA
, data
);
702 /* trigger the write */
703 ql_write32(qdev
, XGMAC_ADDR
, reg
);
707 /* xgmac register are located behind the xgmac_addr and xgmac_data
708 * register pair. Each read/write requires us to wait for the ready
709 * bit before reading/writing the data.
711 int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
)
714 /* wait for reg to come ready */
715 status
= ql_wait_reg_rdy(qdev
,
716 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
719 /* set up for reg read */
720 ql_write32(qdev
, XGMAC_ADDR
, reg
| XGMAC_ADDR_R
);
721 /* wait for reg to come ready */
722 status
= ql_wait_reg_rdy(qdev
,
723 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
727 *data
= ql_read32(qdev
, XGMAC_DATA
);
732 /* This is used for reading the 64-bit statistics regs. */
733 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
)
739 status
= ql_read_xgmac_reg(qdev
, reg
, &lo
);
743 status
= ql_read_xgmac_reg(qdev
, reg
+ 4, &hi
);
747 *data
= (u64
) lo
| ((u64
) hi
<< 32);
753 /* Take the MAC Core out of reset.
754 * Enable statistics counting.
755 * Take the transmitter/receiver out of reset.
756 * This functionality may be done in the MPI firmware at a
759 static int ql_port_initialize(struct ql_adapter
*qdev
)
764 if (ql_sem_trylock(qdev
, qdev
->xg_sem_mask
)) {
765 /* Another function has the semaphore, so
766 * wait for the port init bit to come ready.
768 QPRINTK(qdev
, LINK
, INFO
,
769 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
770 status
= ql_wait_reg_rdy(qdev
, STS
, qdev
->port_init
, 0);
772 QPRINTK(qdev
, LINK
, CRIT
,
773 "Port initialize timed out.\n");
778 QPRINTK(qdev
, LINK
, INFO
, "Got xgmac semaphore!.\n");
779 /* Set the core reset. */
780 status
= ql_read_xgmac_reg(qdev
, GLOBAL_CFG
, &data
);
783 data
|= GLOBAL_CFG_RESET
;
784 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
788 /* Clear the core reset and turn on jumbo for receiver. */
789 data
&= ~GLOBAL_CFG_RESET
; /* Clear core reset. */
790 data
|= GLOBAL_CFG_JUMBO
; /* Turn on jumbo. */
791 data
|= GLOBAL_CFG_TX_STAT_EN
;
792 data
|= GLOBAL_CFG_RX_STAT_EN
;
793 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
797 /* Enable transmitter, and clear it's reset. */
798 status
= ql_read_xgmac_reg(qdev
, TX_CFG
, &data
);
801 data
&= ~TX_CFG_RESET
; /* Clear the TX MAC reset. */
802 data
|= TX_CFG_EN
; /* Enable the transmitter. */
803 status
= ql_write_xgmac_reg(qdev
, TX_CFG
, data
);
807 /* Enable receiver and clear it's reset. */
808 status
= ql_read_xgmac_reg(qdev
, RX_CFG
, &data
);
811 data
&= ~RX_CFG_RESET
; /* Clear the RX MAC reset. */
812 data
|= RX_CFG_EN
; /* Enable the receiver. */
813 status
= ql_write_xgmac_reg(qdev
, RX_CFG
, data
);
819 ql_write_xgmac_reg(qdev
, MAC_TX_PARAMS
, MAC_TX_PARAMS_JUMBO
| (0x2580 << 16));
823 ql_write_xgmac_reg(qdev
, MAC_RX_PARAMS
, 0x2580);
827 /* Signal to the world that the port is enabled. */
828 ql_write32(qdev
, STS
, ((qdev
->port_init
<< 16) | qdev
->port_init
));
830 ql_sem_unlock(qdev
, qdev
->xg_sem_mask
);
834 /* Get the next large buffer. */
835 static struct bq_desc
*ql_get_curr_lbuf(struct rx_ring
*rx_ring
)
837 struct bq_desc
*lbq_desc
= &rx_ring
->lbq
[rx_ring
->lbq_curr_idx
];
838 rx_ring
->lbq_curr_idx
++;
839 if (rx_ring
->lbq_curr_idx
== rx_ring
->lbq_len
)
840 rx_ring
->lbq_curr_idx
= 0;
841 rx_ring
->lbq_free_cnt
++;
845 /* Get the next small buffer. */
846 static struct bq_desc
*ql_get_curr_sbuf(struct rx_ring
*rx_ring
)
848 struct bq_desc
*sbq_desc
= &rx_ring
->sbq
[rx_ring
->sbq_curr_idx
];
849 rx_ring
->sbq_curr_idx
++;
850 if (rx_ring
->sbq_curr_idx
== rx_ring
->sbq_len
)
851 rx_ring
->sbq_curr_idx
= 0;
852 rx_ring
->sbq_free_cnt
++;
856 /* Update an rx ring index. */
857 static void ql_update_cq(struct rx_ring
*rx_ring
)
859 rx_ring
->cnsmr_idx
++;
860 rx_ring
->curr_entry
++;
861 if (unlikely(rx_ring
->cnsmr_idx
== rx_ring
->cq_len
)) {
862 rx_ring
->cnsmr_idx
= 0;
863 rx_ring
->curr_entry
= rx_ring
->cq_base
;
867 static void ql_write_cq_idx(struct rx_ring
*rx_ring
)
869 ql_write_db_reg(rx_ring
->cnsmr_idx
, rx_ring
->cnsmr_idx_db_reg
);
872 /* Process (refill) a large buffer queue. */
873 static void ql_update_lbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
875 int clean_idx
= rx_ring
->lbq_clean_idx
;
876 struct bq_desc
*lbq_desc
;
877 struct bq_element
*bq
;
881 while (rx_ring
->lbq_free_cnt
> 16) {
882 for (i
= 0; i
< 16; i
++) {
883 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
884 "lbq: try cleaning clean_idx = %d.\n",
886 lbq_desc
= &rx_ring
->lbq
[clean_idx
];
888 if (lbq_desc
->p
.lbq_page
== NULL
) {
889 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
890 "lbq: getting new page for index %d.\n",
892 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
893 if (lbq_desc
->p
.lbq_page
== NULL
) {
894 QPRINTK(qdev
, RX_STATUS
, ERR
,
895 "Couldn't get a page.\n");
898 map
= pci_map_page(qdev
->pdev
,
899 lbq_desc
->p
.lbq_page
,
902 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
903 QPRINTK(qdev
, RX_STATUS
, ERR
,
904 "PCI mapping failed.\n");
907 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
908 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
909 bq
->addr_lo
= /*lbq_desc->addr_lo = */
911 bq
->addr_hi
= /*lbq_desc->addr_hi = */
912 cpu_to_le32(map
>> 32);
915 if (clean_idx
== rx_ring
->lbq_len
)
919 rx_ring
->lbq_clean_idx
= clean_idx
;
920 rx_ring
->lbq_prod_idx
+= 16;
921 if (rx_ring
->lbq_prod_idx
== rx_ring
->lbq_len
)
922 rx_ring
->lbq_prod_idx
= 0;
923 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
924 "lbq: updating prod idx = %d.\n",
925 rx_ring
->lbq_prod_idx
);
926 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
927 rx_ring
->lbq_prod_idx_db_reg
);
928 rx_ring
->lbq_free_cnt
-= 16;
932 /* Process (refill) a small buffer queue. */
933 static void ql_update_sbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
935 int clean_idx
= rx_ring
->sbq_clean_idx
;
936 struct bq_desc
*sbq_desc
;
937 struct bq_element
*bq
;
941 while (rx_ring
->sbq_free_cnt
> 16) {
942 for (i
= 0; i
< 16; i
++) {
943 sbq_desc
= &rx_ring
->sbq
[clean_idx
];
944 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
945 "sbq: try cleaning clean_idx = %d.\n",
948 if (sbq_desc
->p
.skb
== NULL
) {
949 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
950 "sbq: getting new skb for index %d.\n",
953 netdev_alloc_skb(qdev
->ndev
,
954 rx_ring
->sbq_buf_size
);
955 if (sbq_desc
->p
.skb
== NULL
) {
956 QPRINTK(qdev
, PROBE
, ERR
,
957 "Couldn't get an skb.\n");
958 rx_ring
->sbq_clean_idx
= clean_idx
;
961 skb_reserve(sbq_desc
->p
.skb
, QLGE_SB_PAD
);
962 map
= pci_map_single(qdev
->pdev
,
963 sbq_desc
->p
.skb
->data
,
964 rx_ring
->sbq_buf_size
/
965 2, PCI_DMA_FROMDEVICE
);
966 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
967 pci_unmap_len_set(sbq_desc
, maplen
,
968 rx_ring
->sbq_buf_size
/ 2);
969 bq
->addr_lo
= cpu_to_le32(map
);
970 bq
->addr_hi
= cpu_to_le32(map
>> 32);
974 if (clean_idx
== rx_ring
->sbq_len
)
977 rx_ring
->sbq_clean_idx
= clean_idx
;
978 rx_ring
->sbq_prod_idx
+= 16;
979 if (rx_ring
->sbq_prod_idx
== rx_ring
->sbq_len
)
980 rx_ring
->sbq_prod_idx
= 0;
981 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
982 "sbq: updating prod idx = %d.\n",
983 rx_ring
->sbq_prod_idx
);
984 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
985 rx_ring
->sbq_prod_idx_db_reg
);
987 rx_ring
->sbq_free_cnt
-= 16;
991 static void ql_update_buffer_queues(struct ql_adapter
*qdev
,
992 struct rx_ring
*rx_ring
)
994 ql_update_sbq(qdev
, rx_ring
);
995 ql_update_lbq(qdev
, rx_ring
);
998 /* Unmaps tx buffers. Can be called from send() if a pci mapping
999 * fails at some stage, or from the interrupt when a tx completes.
1001 static void ql_unmap_send(struct ql_adapter
*qdev
,
1002 struct tx_ring_desc
*tx_ring_desc
, int mapped
)
1005 for (i
= 0; i
< mapped
; i
++) {
1006 if (i
== 0 || (i
== 7 && mapped
> 7)) {
1008 * Unmap the skb->data area, or the
1009 * external sglist (AKA the Outbound
1010 * Address List (OAL)).
1011 * If its the zeroeth element, then it's
1012 * the skb->data area. If it's the 7th
1013 * element and there is more than 6 frags,
1017 QPRINTK(qdev
, TX_DONE
, DEBUG
,
1018 "unmapping OAL area.\n");
1020 pci_unmap_single(qdev
->pdev
,
1021 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1023 pci_unmap_len(&tx_ring_desc
->map
[i
],
1027 QPRINTK(qdev
, TX_DONE
, DEBUG
, "unmapping frag %d.\n",
1029 pci_unmap_page(qdev
->pdev
,
1030 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1032 pci_unmap_len(&tx_ring_desc
->map
[i
],
1033 maplen
), PCI_DMA_TODEVICE
);
1039 /* Map the buffers for this transmit. This will return
1040 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1042 static int ql_map_send(struct ql_adapter
*qdev
,
1043 struct ob_mac_iocb_req
*mac_iocb_ptr
,
1044 struct sk_buff
*skb
, struct tx_ring_desc
*tx_ring_desc
)
1046 int len
= skb_headlen(skb
);
1048 int frag_idx
, err
, map_idx
= 0;
1049 struct tx_buf_desc
*tbd
= mac_iocb_ptr
->tbd
;
1050 int frag_cnt
= skb_shinfo(skb
)->nr_frags
;
1053 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "frag_cnt = %d.\n", frag_cnt
);
1056 * Map the skb buffer first.
1058 map
= pci_map_single(qdev
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1060 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1062 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1063 "PCI mapping failed with error: %d\n", err
);
1065 return NETDEV_TX_BUSY
;
1068 tbd
->len
= cpu_to_le32(len
);
1069 tbd
->addr
= cpu_to_le64(map
);
1070 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1071 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
, len
);
1075 * This loop fills the remainder of the 8 address descriptors
1076 * in the IOCB. If there are more than 7 fragments, then the
1077 * eighth address desc will point to an external list (OAL).
1078 * When this happens, the remainder of the frags will be stored
1081 for (frag_idx
= 0; frag_idx
< frag_cnt
; frag_idx
++, map_idx
++) {
1082 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[frag_idx
];
1084 if (frag_idx
== 6 && frag_cnt
> 7) {
1085 /* Let's tack on an sglist.
1086 * Our control block will now
1088 * iocb->seg[0] = skb->data
1089 * iocb->seg[1] = frag[0]
1090 * iocb->seg[2] = frag[1]
1091 * iocb->seg[3] = frag[2]
1092 * iocb->seg[4] = frag[3]
1093 * iocb->seg[5] = frag[4]
1094 * iocb->seg[6] = frag[5]
1095 * iocb->seg[7] = ptr to OAL (external sglist)
1096 * oal->seg[0] = frag[6]
1097 * oal->seg[1] = frag[7]
1098 * oal->seg[2] = frag[8]
1099 * oal->seg[3] = frag[9]
1100 * oal->seg[4] = frag[10]
1103 /* Tack on the OAL in the eighth segment of IOCB. */
1104 map
= pci_map_single(qdev
->pdev
, &tx_ring_desc
->oal
,
1107 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1109 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1110 "PCI mapping outbound address list with error: %d\n",
1115 tbd
->addr
= cpu_to_le64(map
);
1117 * The length is the number of fragments
1118 * that remain to be mapped times the length
1119 * of our sglist (OAL).
1122 cpu_to_le32((sizeof(struct tx_buf_desc
) *
1123 (frag_cnt
- frag_idx
)) | TX_DESC_C
);
1124 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
,
1126 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1127 sizeof(struct oal
));
1128 tbd
= (struct tx_buf_desc
*)&tx_ring_desc
->oal
;
1133 pci_map_page(qdev
->pdev
, frag
->page
,
1134 frag
->page_offset
, frag
->size
,
1137 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1139 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1140 "PCI mapping frags failed with error: %d.\n",
1145 tbd
->addr
= cpu_to_le64(map
);
1146 tbd
->len
= cpu_to_le32(frag
->size
);
1147 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1148 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1152 /* Save the number of segments we've mapped. */
1153 tx_ring_desc
->map_cnt
= map_idx
;
1154 /* Terminate the last segment. */
1155 tbd
->len
= cpu_to_le32(le32_to_cpu(tbd
->len
) | TX_DESC_E
);
1156 return NETDEV_TX_OK
;
1160 * If the first frag mapping failed, then i will be zero.
1161 * This causes the unmap of the skb->data area. Otherwise
1162 * we pass in the number of frags that mapped successfully
1163 * so they can be umapped.
1165 ql_unmap_send(qdev
, tx_ring_desc
, map_idx
);
1166 return NETDEV_TX_BUSY
;
1169 static void ql_realign_skb(struct sk_buff
*skb
, int len
)
1171 void *temp_addr
= skb
->data
;
1173 /* Undo the skb_reserve(skb,32) we did before
1174 * giving to hardware, and realign data on
1175 * a 2-byte boundary.
1177 skb
->data
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1178 skb
->tail
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1179 skb_copy_to_linear_data(skb
, temp_addr
,
1184 * This function builds an skb for the given inbound
1185 * completion. It will be rewritten for readability in the near
1186 * future, but for not it works well.
1188 static struct sk_buff
*ql_build_rx_skb(struct ql_adapter
*qdev
,
1189 struct rx_ring
*rx_ring
,
1190 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1192 struct bq_desc
*lbq_desc
;
1193 struct bq_desc
*sbq_desc
;
1194 struct sk_buff
*skb
= NULL
;
1195 u32 length
= le32_to_cpu(ib_mac_rsp
->data_len
);
1196 u32 hdr_len
= le32_to_cpu(ib_mac_rsp
->hdr_len
);
1199 * Handle the header buffer if present.
1201 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HV
&&
1202 ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1203 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Header of %d bytes in small buffer.\n", hdr_len
);
1205 * Headers fit nicely into a small buffer.
1207 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1208 pci_unmap_single(qdev
->pdev
,
1209 pci_unmap_addr(sbq_desc
, mapaddr
),
1210 pci_unmap_len(sbq_desc
, maplen
),
1211 PCI_DMA_FROMDEVICE
);
1212 skb
= sbq_desc
->p
.skb
;
1213 ql_realign_skb(skb
, hdr_len
);
1214 skb_put(skb
, hdr_len
);
1215 sbq_desc
->p
.skb
= NULL
;
1219 * Handle the data buffer(s).
1221 if (unlikely(!length
)) { /* Is there data too? */
1222 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1223 "No Data buffer in this packet.\n");
1227 if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DS
) {
1228 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1229 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1230 "Headers in small, data of %d bytes in small, combine them.\n", length
);
1232 * Data is less than small buffer size so it's
1233 * stuffed in a small buffer.
1234 * For this case we append the data
1235 * from the "data" small buffer to the "header" small
1238 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1239 pci_dma_sync_single_for_cpu(qdev
->pdev
,
1241 (sbq_desc
, mapaddr
),
1244 PCI_DMA_FROMDEVICE
);
1245 memcpy(skb_put(skb
, length
),
1246 sbq_desc
->p
.skb
->data
, length
);
1247 pci_dma_sync_single_for_device(qdev
->pdev
,
1254 PCI_DMA_FROMDEVICE
);
1256 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1257 "%d bytes in a single small buffer.\n", length
);
1258 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1259 skb
= sbq_desc
->p
.skb
;
1260 ql_realign_skb(skb
, length
);
1261 skb_put(skb
, length
);
1262 pci_unmap_single(qdev
->pdev
,
1263 pci_unmap_addr(sbq_desc
,
1265 pci_unmap_len(sbq_desc
,
1267 PCI_DMA_FROMDEVICE
);
1268 sbq_desc
->p
.skb
= NULL
;
1270 } else if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DL
) {
1271 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1272 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1273 "Header in small, %d bytes in large. Chain large to small!\n", length
);
1275 * The data is in a single large buffer. We
1276 * chain it to the header buffer's skb and let
1279 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1280 pci_unmap_page(qdev
->pdev
,
1281 pci_unmap_addr(lbq_desc
,
1283 pci_unmap_len(lbq_desc
, maplen
),
1284 PCI_DMA_FROMDEVICE
);
1285 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1286 "Chaining page to skb.\n");
1287 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1290 skb
->data_len
+= length
;
1291 skb
->truesize
+= length
;
1292 lbq_desc
->p
.lbq_page
= NULL
;
1295 * The headers and data are in a single large buffer. We
1296 * copy it to a new skb and let it go. This can happen with
1297 * jumbo mtu on a non-TCP/UDP frame.
1299 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1300 skb
= netdev_alloc_skb(qdev
->ndev
, length
);
1302 QPRINTK(qdev
, PROBE
, DEBUG
,
1303 "No skb available, drop the packet.\n");
1306 skb_reserve(skb
, NET_IP_ALIGN
);
1307 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1308 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length
);
1309 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1312 skb
->data_len
+= length
;
1313 skb
->truesize
+= length
;
1315 lbq_desc
->p
.lbq_page
= NULL
;
1316 __pskb_pull_tail(skb
,
1317 (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1318 VLAN_ETH_HLEN
: ETH_HLEN
);
1322 * The data is in a chain of large buffers
1323 * pointed to by a small buffer. We loop
1324 * thru and chain them to the our small header
1326 * frags: There are 18 max frags and our small
1327 * buffer will hold 32 of them. The thing is,
1328 * we'll use 3 max for our 9000 byte jumbo
1329 * frames. If the MTU goes up we could
1330 * eventually be in trouble.
1332 int size
, offset
, i
= 0;
1333 struct bq_element
*bq
, bq_array
[8];
1334 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1335 pci_unmap_single(qdev
->pdev
,
1336 pci_unmap_addr(sbq_desc
, mapaddr
),
1337 pci_unmap_len(sbq_desc
, maplen
),
1338 PCI_DMA_FROMDEVICE
);
1339 if (!(ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
)) {
1341 * This is an non TCP/UDP IP frame, so
1342 * the headers aren't split into a small
1343 * buffer. We have to use the small buffer
1344 * that contains our sg list as our skb to
1345 * send upstairs. Copy the sg list here to
1346 * a local buffer and use it to find the
1349 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1350 "%d bytes of headers & data in chain of large.\n", length
);
1351 skb
= sbq_desc
->p
.skb
;
1353 memcpy(bq
, skb
->data
, sizeof(bq_array
));
1354 sbq_desc
->p
.skb
= NULL
;
1355 skb_reserve(skb
, NET_IP_ALIGN
);
1357 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1358 "Headers in small, %d bytes of data in chain of large.\n", length
);
1359 bq
= (struct bq_element
*)sbq_desc
->p
.skb
->data
;
1361 while (length
> 0) {
1362 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1363 if ((bq
->addr_lo
& ~BQ_MASK
) != lbq_desc
->bq
->addr_lo
) {
1364 QPRINTK(qdev
, RX_STATUS
, ERR
,
1365 "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1366 lbq_desc
->bq
->addr_lo
, bq
->addr_lo
);
1369 pci_unmap_page(qdev
->pdev
,
1370 pci_unmap_addr(lbq_desc
,
1372 pci_unmap_len(lbq_desc
,
1374 PCI_DMA_FROMDEVICE
);
1375 size
= (length
< PAGE_SIZE
) ? length
: PAGE_SIZE
;
1378 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1379 "Adding page %d to skb for %d bytes.\n",
1381 skb_fill_page_desc(skb
, i
, lbq_desc
->p
.lbq_page
,
1384 skb
->data_len
+= size
;
1385 skb
->truesize
+= size
;
1387 lbq_desc
->p
.lbq_page
= NULL
;
1391 __pskb_pull_tail(skb
, (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1392 VLAN_ETH_HLEN
: ETH_HLEN
);
1397 /* Process an inbound completion from an rx ring. */
1398 static void ql_process_mac_rx_intr(struct ql_adapter
*qdev
,
1399 struct rx_ring
*rx_ring
,
1400 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1402 struct net_device
*ndev
= qdev
->ndev
;
1403 struct sk_buff
*skb
= NULL
;
1405 QL_DUMP_IB_MAC_RSP(ib_mac_rsp
);
1407 skb
= ql_build_rx_skb(qdev
, rx_ring
, ib_mac_rsp
);
1408 if (unlikely(!skb
)) {
1409 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1410 "No skb available, drop packet.\n");
1414 prefetch(skb
->data
);
1416 if (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) {
1417 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "%s%s%s Multicast.\n",
1418 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1419 IB_MAC_IOCB_RSP_M_HASH
? "Hash" : "",
1420 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1421 IB_MAC_IOCB_RSP_M_REG
? "Registered" : "",
1422 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1423 IB_MAC_IOCB_RSP_M_PROM
? "Promiscuous" : "");
1425 if (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_P
) {
1426 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Promiscuous Packet.\n");
1428 if (ib_mac_rsp
->flags1
& (IB_MAC_IOCB_RSP_IE
| IB_MAC_IOCB_RSP_TE
)) {
1429 QPRINTK(qdev
, RX_STATUS
, ERR
,
1430 "Bad checksum for this %s packet.\n",
1432 flags2
& IB_MAC_IOCB_RSP_T
) ? "TCP" : "UDP"));
1433 skb
->ip_summed
= CHECKSUM_NONE
;
1434 } else if (qdev
->rx_csum
&&
1435 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_T
) ||
1436 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_U
) &&
1437 !(ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_NU
)))) {
1438 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "RX checksum done!\n");
1439 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1441 qdev
->stats
.rx_packets
++;
1442 qdev
->stats
.rx_bytes
+= skb
->len
;
1443 skb
->protocol
= eth_type_trans(skb
, ndev
);
1444 if (qdev
->vlgrp
&& (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
)) {
1445 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1446 "Passing a VLAN packet upstream.\n");
1447 vlan_hwaccel_rx(skb
, qdev
->vlgrp
,
1448 le16_to_cpu(ib_mac_rsp
->vlan_id
));
1450 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1451 "Passing a normal packet upstream.\n");
1456 /* Process an outbound completion from an rx ring. */
1457 static void ql_process_mac_tx_intr(struct ql_adapter
*qdev
,
1458 struct ob_mac_iocb_rsp
*mac_rsp
)
1460 struct tx_ring
*tx_ring
;
1461 struct tx_ring_desc
*tx_ring_desc
;
1463 QL_DUMP_OB_MAC_RSP(mac_rsp
);
1464 tx_ring
= &qdev
->tx_ring
[mac_rsp
->txq_idx
];
1465 tx_ring_desc
= &tx_ring
->q
[mac_rsp
->tid
];
1466 ql_unmap_send(qdev
, tx_ring_desc
, tx_ring_desc
->map_cnt
);
1467 qdev
->stats
.tx_bytes
+= tx_ring_desc
->map_cnt
;
1468 qdev
->stats
.tx_packets
++;
1469 dev_kfree_skb(tx_ring_desc
->skb
);
1470 tx_ring_desc
->skb
= NULL
;
1472 if (unlikely(mac_rsp
->flags1
& (OB_MAC_IOCB_RSP_E
|
1475 OB_MAC_IOCB_RSP_P
| OB_MAC_IOCB_RSP_B
))) {
1476 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_E
) {
1477 QPRINTK(qdev
, TX_DONE
, WARNING
,
1478 "Total descriptor length did not match transfer length.\n");
1480 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_S
) {
1481 QPRINTK(qdev
, TX_DONE
, WARNING
,
1482 "Frame too short to be legal, not sent.\n");
1484 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_L
) {
1485 QPRINTK(qdev
, TX_DONE
, WARNING
,
1486 "Frame too long, but sent anyway.\n");
1488 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_B
) {
1489 QPRINTK(qdev
, TX_DONE
, WARNING
,
1490 "PCI backplane error. Frame not sent.\n");
1493 atomic_inc(&tx_ring
->tx_count
);
1496 /* Fire up a handler to reset the MPI processor. */
1497 void ql_queue_fw_error(struct ql_adapter
*qdev
)
1499 netif_stop_queue(qdev
->ndev
);
1500 netif_carrier_off(qdev
->ndev
);
1501 queue_delayed_work(qdev
->workqueue
, &qdev
->mpi_reset_work
, 0);
1504 void ql_queue_asic_error(struct ql_adapter
*qdev
)
1506 netif_stop_queue(qdev
->ndev
);
1507 netif_carrier_off(qdev
->ndev
);
1508 ql_disable_interrupts(qdev
);
1509 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
1512 static void ql_process_chip_ae_intr(struct ql_adapter
*qdev
,
1513 struct ib_ae_iocb_rsp
*ib_ae_rsp
)
1515 switch (ib_ae_rsp
->event
) {
1516 case MGMT_ERR_EVENT
:
1517 QPRINTK(qdev
, RX_ERR
, ERR
,
1518 "Management Processor Fatal Error.\n");
1519 ql_queue_fw_error(qdev
);
1522 case CAM_LOOKUP_ERR_EVENT
:
1523 QPRINTK(qdev
, LINK
, ERR
,
1524 "Multiple CAM hits lookup occurred.\n");
1525 QPRINTK(qdev
, DRV
, ERR
, "This event shouldn't occur.\n");
1526 ql_queue_asic_error(qdev
);
1529 case SOFT_ECC_ERROR_EVENT
:
1530 QPRINTK(qdev
, RX_ERR
, ERR
, "Soft ECC error detected.\n");
1531 ql_queue_asic_error(qdev
);
1534 case PCI_ERR_ANON_BUF_RD
:
1535 QPRINTK(qdev
, RX_ERR
, ERR
,
1536 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1538 ql_queue_asic_error(qdev
);
1542 QPRINTK(qdev
, DRV
, ERR
, "Unexpected event %d.\n",
1544 ql_queue_asic_error(qdev
);
1549 static int ql_clean_outbound_rx_ring(struct rx_ring
*rx_ring
)
1551 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1552 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1553 struct ob_mac_iocb_rsp
*net_rsp
= NULL
;
1556 /* While there are entries in the completion queue. */
1557 while (prod
!= rx_ring
->cnsmr_idx
) {
1559 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1560 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1561 prod
, rx_ring
->cnsmr_idx
);
1563 net_rsp
= (struct ob_mac_iocb_rsp
*)rx_ring
->curr_entry
;
1565 switch (net_rsp
->opcode
) {
1567 case OPCODE_OB_MAC_TSO_IOCB
:
1568 case OPCODE_OB_MAC_IOCB
:
1569 ql_process_mac_tx_intr(qdev
, net_rsp
);
1572 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1573 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1577 ql_update_cq(rx_ring
);
1578 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1580 ql_write_cq_idx(rx_ring
);
1581 if (netif_queue_stopped(qdev
->ndev
) && net_rsp
!= NULL
) {
1582 struct tx_ring
*tx_ring
= &qdev
->tx_ring
[net_rsp
->txq_idx
];
1583 if (atomic_read(&tx_ring
->queue_stopped
) &&
1584 (atomic_read(&tx_ring
->tx_count
) > (tx_ring
->wq_len
/ 4)))
1586 * The queue got stopped because the tx_ring was full.
1587 * Wake it up, because it's now at least 25% empty.
1589 netif_wake_queue(qdev
->ndev
);
1595 static int ql_clean_inbound_rx_ring(struct rx_ring
*rx_ring
, int budget
)
1597 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1598 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1599 struct ql_net_rsp_iocb
*net_rsp
;
1602 /* While there are entries in the completion queue. */
1603 while (prod
!= rx_ring
->cnsmr_idx
) {
1605 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1606 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1607 prod
, rx_ring
->cnsmr_idx
);
1609 net_rsp
= rx_ring
->curr_entry
;
1611 switch (net_rsp
->opcode
) {
1612 case OPCODE_IB_MAC_IOCB
:
1613 ql_process_mac_rx_intr(qdev
, rx_ring
,
1614 (struct ib_mac_iocb_rsp
*)
1618 case OPCODE_IB_AE_IOCB
:
1619 ql_process_chip_ae_intr(qdev
, (struct ib_ae_iocb_rsp
*)
1624 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1625 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1630 ql_update_cq(rx_ring
);
1631 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1632 if (count
== budget
)
1635 ql_update_buffer_queues(qdev
, rx_ring
);
1636 ql_write_cq_idx(rx_ring
);
1640 static int ql_napi_poll_msix(struct napi_struct
*napi
, int budget
)
1642 struct rx_ring
*rx_ring
= container_of(napi
, struct rx_ring
, napi
);
1643 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1644 int work_done
= ql_clean_inbound_rx_ring(rx_ring
, budget
);
1646 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Enter, NAPI POLL cq_id = %d.\n",
1649 if (work_done
< budget
) {
1650 __netif_rx_complete(napi
);
1651 ql_enable_completion_interrupt(qdev
, rx_ring
->irq
);
1656 static void ql_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
1658 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1662 QPRINTK(qdev
, IFUP
, DEBUG
, "Turning on VLAN in NIC_RCV_CFG.\n");
1663 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
|
1664 NIC_RCV_CFG_VLAN_MATCH_AND_NON
);
1666 QPRINTK(qdev
, IFUP
, DEBUG
,
1667 "Turning off VLAN in NIC_RCV_CFG.\n");
1668 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
);
1672 static void ql_vlan_rx_add_vid(struct net_device
*ndev
, u16 vid
)
1674 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1675 u32 enable_bit
= MAC_ADDR_E
;
1677 spin_lock(&qdev
->hw_lock
);
1678 if (ql_set_mac_addr_reg
1679 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1680 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init vlan address.\n");
1682 spin_unlock(&qdev
->hw_lock
);
1685 static void ql_vlan_rx_kill_vid(struct net_device
*ndev
, u16 vid
)
1687 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1690 spin_lock(&qdev
->hw_lock
);
1691 if (ql_set_mac_addr_reg
1692 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1693 QPRINTK(qdev
, IFUP
, ERR
, "Failed to clear vlan address.\n");
1695 spin_unlock(&qdev
->hw_lock
);
1699 /* Worker thread to process a given rx_ring that is dedicated
1700 * to outbound completions.
1702 static void ql_tx_clean(struct work_struct
*work
)
1704 struct rx_ring
*rx_ring
=
1705 container_of(work
, struct rx_ring
, rx_work
.work
);
1706 ql_clean_outbound_rx_ring(rx_ring
);
1707 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1711 /* Worker thread to process a given rx_ring that is dedicated
1712 * to inbound completions.
1714 static void ql_rx_clean(struct work_struct
*work
)
1716 struct rx_ring
*rx_ring
=
1717 container_of(work
, struct rx_ring
, rx_work
.work
);
1718 ql_clean_inbound_rx_ring(rx_ring
, 64);
1719 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1722 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1723 static irqreturn_t
qlge_msix_tx_isr(int irq
, void *dev_id
)
1725 struct rx_ring
*rx_ring
= dev_id
;
1726 queue_delayed_work_on(rx_ring
->cpu
, rx_ring
->qdev
->q_workqueue
,
1727 &rx_ring
->rx_work
, 0);
1731 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1732 static irqreturn_t
qlge_msix_rx_isr(int irq
, void *dev_id
)
1734 struct rx_ring
*rx_ring
= dev_id
;
1735 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1736 netif_rx_schedule(&rx_ring
->napi
);
1740 /* This handles a fatal error, MPI activity, and the default
1741 * rx_ring in an MSI-X multiple vector environment.
1742 * In MSI/Legacy environment it also process the rest of
1745 static irqreturn_t
qlge_isr(int irq
, void *dev_id
)
1747 struct rx_ring
*rx_ring
= dev_id
;
1748 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1749 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
1754 spin_lock(&qdev
->hw_lock
);
1755 if (atomic_read(&qdev
->intr_context
[0].irq_cnt
)) {
1756 QPRINTK(qdev
, INTR
, DEBUG
, "Shared Interrupt, Not ours!\n");
1757 spin_unlock(&qdev
->hw_lock
);
1760 spin_unlock(&qdev
->hw_lock
);
1762 var
= ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1765 * Check for fatal error.
1768 ql_queue_asic_error(qdev
);
1769 QPRINTK(qdev
, INTR
, ERR
, "Got fatal error, STS = %x.\n", var
);
1770 var
= ql_read32(qdev
, ERR_STS
);
1771 QPRINTK(qdev
, INTR
, ERR
,
1772 "Resetting chip. Error Status Register = 0x%x\n", var
);
1777 * Check MPI processor activity.
1781 * We've got an async event or mailbox completion.
1782 * Handle it and clear the source of the interrupt.
1784 QPRINTK(qdev
, INTR
, ERR
, "Got MPI processor interrupt.\n");
1785 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1786 queue_delayed_work_on(smp_processor_id(), qdev
->workqueue
,
1787 &qdev
->mpi_work
, 0);
1792 * Check the default queue and wake handler if active.
1794 rx_ring
= &qdev
->rx_ring
[0];
1795 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) != rx_ring
->cnsmr_idx
) {
1796 QPRINTK(qdev
, INTR
, INFO
, "Waking handler for rx_ring[0].\n");
1797 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1798 queue_delayed_work_on(smp_processor_id(), qdev
->q_workqueue
,
1799 &rx_ring
->rx_work
, 0);
1803 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
1805 * Start the DPC for each active queue.
1807 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
1808 rx_ring
= &qdev
->rx_ring
[i
];
1809 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) !=
1810 rx_ring
->cnsmr_idx
) {
1811 QPRINTK(qdev
, INTR
, INFO
,
1812 "Waking handler for rx_ring[%d].\n", i
);
1813 ql_disable_completion_interrupt(qdev
,
1816 if (i
< qdev
->rss_ring_first_cq_id
)
1817 queue_delayed_work_on(rx_ring
->cpu
,
1822 netif_rx_schedule(&rx_ring
->napi
);
1827 ql_enable_completion_interrupt(qdev
, intr_context
->intr
);
1828 return work_done
? IRQ_HANDLED
: IRQ_NONE
;
1831 static int ql_tso(struct sk_buff
*skb
, struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1834 if (skb_is_gso(skb
)) {
1836 if (skb_header_cloned(skb
)) {
1837 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
1842 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1843 mac_iocb_ptr
->flags3
|= OB_MAC_TSO_IOCB_IC
;
1844 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1845 mac_iocb_ptr
->total_hdrs_len
=
1846 cpu_to_le16(skb_transport_offset(skb
) + tcp_hdrlen(skb
));
1847 mac_iocb_ptr
->net_trans_offset
=
1848 cpu_to_le16(skb_network_offset(skb
) |
1849 skb_transport_offset(skb
)
1850 << OB_MAC_TRANSPORT_HDR_SHIFT
);
1851 mac_iocb_ptr
->mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
);
1852 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_LSO
;
1853 if (likely(skb
->protocol
== htons(ETH_P_IP
))) {
1854 struct iphdr
*iph
= ip_hdr(skb
);
1856 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1857 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1861 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
1862 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP6
;
1863 tcp_hdr(skb
)->check
=
1864 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
1865 &ipv6_hdr(skb
)->daddr
,
1873 static void ql_hw_csum_setup(struct sk_buff
*skb
,
1874 struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1877 struct iphdr
*iph
= ip_hdr(skb
);
1879 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1880 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1881 mac_iocb_ptr
->net_trans_offset
=
1882 cpu_to_le16(skb_network_offset(skb
) |
1883 skb_transport_offset(skb
) << OB_MAC_TRANSPORT_HDR_SHIFT
);
1885 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1886 len
= (ntohs(iph
->tot_len
) - (iph
->ihl
<< 2));
1887 if (likely(iph
->protocol
== IPPROTO_TCP
)) {
1888 check
= &(tcp_hdr(skb
)->check
);
1889 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_TC
;
1890 mac_iocb_ptr
->total_hdrs_len
=
1891 cpu_to_le16(skb_transport_offset(skb
) +
1892 (tcp_hdr(skb
)->doff
<< 2));
1894 check
= &(udp_hdr(skb
)->check
);
1895 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_UC
;
1896 mac_iocb_ptr
->total_hdrs_len
=
1897 cpu_to_le16(skb_transport_offset(skb
) +
1898 sizeof(struct udphdr
));
1900 *check
= ~csum_tcpudp_magic(iph
->saddr
,
1901 iph
->daddr
, len
, iph
->protocol
, 0);
1904 static int qlge_send(struct sk_buff
*skb
, struct net_device
*ndev
)
1906 struct tx_ring_desc
*tx_ring_desc
;
1907 struct ob_mac_iocb_req
*mac_iocb_ptr
;
1908 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1910 struct tx_ring
*tx_ring
;
1911 u32 tx_ring_idx
= (u32
) QL_TXQ_IDX(qdev
, skb
);
1913 tx_ring
= &qdev
->tx_ring
[tx_ring_idx
];
1915 if (unlikely(atomic_read(&tx_ring
->tx_count
) < 2)) {
1916 QPRINTK(qdev
, TX_QUEUED
, INFO
,
1917 "%s: shutting down tx queue %d du to lack of resources.\n",
1918 __func__
, tx_ring_idx
);
1919 netif_stop_queue(ndev
);
1920 atomic_inc(&tx_ring
->queue_stopped
);
1921 return NETDEV_TX_BUSY
;
1923 tx_ring_desc
= &tx_ring
->q
[tx_ring
->prod_idx
];
1924 mac_iocb_ptr
= tx_ring_desc
->queue_entry
;
1925 memset((void *)mac_iocb_ptr
, 0, sizeof(mac_iocb_ptr
));
1926 if (ql_map_send(qdev
, mac_iocb_ptr
, skb
, tx_ring_desc
) != NETDEV_TX_OK
) {
1927 QPRINTK(qdev
, TX_QUEUED
, ERR
, "Could not map the segments.\n");
1928 return NETDEV_TX_BUSY
;
1931 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_IOCB
;
1932 mac_iocb_ptr
->tid
= tx_ring_desc
->index
;
1933 /* We use the upper 32-bits to store the tx queue for this IO.
1934 * When we get the completion we can use it to establish the context.
1936 mac_iocb_ptr
->txq_idx
= tx_ring_idx
;
1937 tx_ring_desc
->skb
= skb
;
1939 mac_iocb_ptr
->frame_len
= cpu_to_le16((u16
) skb
->len
);
1941 if (qdev
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1942 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "Adding a vlan tag %d.\n",
1943 vlan_tx_tag_get(skb
));
1944 mac_iocb_ptr
->flags3
|= OB_MAC_IOCB_V
;
1945 mac_iocb_ptr
->vlan_tci
= cpu_to_le16(vlan_tx_tag_get(skb
));
1947 tso
= ql_tso(skb
, (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1949 dev_kfree_skb_any(skb
);
1950 return NETDEV_TX_OK
;
1951 } else if (unlikely(!tso
) && (skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
1952 ql_hw_csum_setup(skb
,
1953 (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1955 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr
);
1956 tx_ring
->prod_idx
++;
1957 if (tx_ring
->prod_idx
== tx_ring
->wq_len
)
1958 tx_ring
->prod_idx
= 0;
1961 ql_write_db_reg(tx_ring
->prod_idx
, tx_ring
->prod_idx_db_reg
);
1962 ndev
->trans_start
= jiffies
;
1963 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "tx queued, slot %d, len %d\n",
1964 tx_ring
->prod_idx
, skb
->len
);
1966 atomic_dec(&tx_ring
->tx_count
);
1967 return NETDEV_TX_OK
;
1970 static void ql_free_shadow_space(struct ql_adapter
*qdev
)
1972 if (qdev
->rx_ring_shadow_reg_area
) {
1973 pci_free_consistent(qdev
->pdev
,
1975 qdev
->rx_ring_shadow_reg_area
,
1976 qdev
->rx_ring_shadow_reg_dma
);
1977 qdev
->rx_ring_shadow_reg_area
= NULL
;
1979 if (qdev
->tx_ring_shadow_reg_area
) {
1980 pci_free_consistent(qdev
->pdev
,
1982 qdev
->tx_ring_shadow_reg_area
,
1983 qdev
->tx_ring_shadow_reg_dma
);
1984 qdev
->tx_ring_shadow_reg_area
= NULL
;
1988 static int ql_alloc_shadow_space(struct ql_adapter
*qdev
)
1990 qdev
->rx_ring_shadow_reg_area
=
1991 pci_alloc_consistent(qdev
->pdev
,
1992 PAGE_SIZE
, &qdev
->rx_ring_shadow_reg_dma
);
1993 if (qdev
->rx_ring_shadow_reg_area
== NULL
) {
1994 QPRINTK(qdev
, IFUP
, ERR
,
1995 "Allocation of RX shadow space failed.\n");
1998 qdev
->tx_ring_shadow_reg_area
=
1999 pci_alloc_consistent(qdev
->pdev
, PAGE_SIZE
,
2000 &qdev
->tx_ring_shadow_reg_dma
);
2001 if (qdev
->tx_ring_shadow_reg_area
== NULL
) {
2002 QPRINTK(qdev
, IFUP
, ERR
,
2003 "Allocation of TX shadow space failed.\n");
2004 goto err_wqp_sh_area
;
2009 pci_free_consistent(qdev
->pdev
,
2011 qdev
->rx_ring_shadow_reg_area
,
2012 qdev
->rx_ring_shadow_reg_dma
);
2016 static void ql_init_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2018 struct tx_ring_desc
*tx_ring_desc
;
2020 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2022 mac_iocb_ptr
= tx_ring
->wq_base
;
2023 tx_ring_desc
= tx_ring
->q
;
2024 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2025 tx_ring_desc
->index
= i
;
2026 tx_ring_desc
->skb
= NULL
;
2027 tx_ring_desc
->queue_entry
= mac_iocb_ptr
;
2031 atomic_set(&tx_ring
->tx_count
, tx_ring
->wq_len
);
2032 atomic_set(&tx_ring
->queue_stopped
, 0);
2035 static void ql_free_tx_resources(struct ql_adapter
*qdev
,
2036 struct tx_ring
*tx_ring
)
2038 if (tx_ring
->wq_base
) {
2039 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2040 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2041 tx_ring
->wq_base
= NULL
;
2047 static int ql_alloc_tx_resources(struct ql_adapter
*qdev
,
2048 struct tx_ring
*tx_ring
)
2051 pci_alloc_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2052 &tx_ring
->wq_base_dma
);
2054 if ((tx_ring
->wq_base
== NULL
)
2055 || tx_ring
->wq_base_dma
& (tx_ring
->wq_size
- 1)) {
2056 QPRINTK(qdev
, IFUP
, ERR
, "tx_ring alloc failed.\n");
2060 kmalloc(tx_ring
->wq_len
* sizeof(struct tx_ring_desc
), GFP_KERNEL
);
2061 if (tx_ring
->q
== NULL
)
2066 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2067 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2071 static void ql_free_lbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2074 struct bq_desc
*lbq_desc
;
2076 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2077 lbq_desc
= &rx_ring
->lbq
[i
];
2078 if (lbq_desc
->p
.lbq_page
) {
2079 pci_unmap_page(qdev
->pdev
,
2080 pci_unmap_addr(lbq_desc
, mapaddr
),
2081 pci_unmap_len(lbq_desc
, maplen
),
2082 PCI_DMA_FROMDEVICE
);
2084 put_page(lbq_desc
->p
.lbq_page
);
2085 lbq_desc
->p
.lbq_page
= NULL
;
2087 lbq_desc
->bq
->addr_lo
= 0;
2088 lbq_desc
->bq
->addr_hi
= 0;
2093 * Allocate and map a page for each element of the lbq.
2095 static int ql_alloc_lbq_buffers(struct ql_adapter
*qdev
,
2096 struct rx_ring
*rx_ring
)
2099 struct bq_desc
*lbq_desc
;
2101 struct bq_element
*bq
= rx_ring
->lbq_base
;
2103 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2104 lbq_desc
= &rx_ring
->lbq
[i
];
2105 memset(lbq_desc
, 0, sizeof(lbq_desc
));
2107 lbq_desc
->index
= i
;
2108 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
2109 if (unlikely(!lbq_desc
->p
.lbq_page
)) {
2110 QPRINTK(qdev
, IFUP
, ERR
, "failed alloc_page().\n");
2113 map
= pci_map_page(qdev
->pdev
,
2114 lbq_desc
->p
.lbq_page
,
2115 0, PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2116 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2117 QPRINTK(qdev
, IFUP
, ERR
,
2118 "PCI mapping failed.\n");
2121 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
2122 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
2123 bq
->addr_lo
= cpu_to_le32(map
);
2124 bq
->addr_hi
= cpu_to_le32(map
>> 32);
2130 ql_free_lbq_buffers(qdev
, rx_ring
);
2134 static void ql_free_sbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2137 struct bq_desc
*sbq_desc
;
2139 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2140 sbq_desc
= &rx_ring
->sbq
[i
];
2141 if (sbq_desc
== NULL
) {
2142 QPRINTK(qdev
, IFUP
, ERR
, "sbq_desc %d is NULL.\n", i
);
2145 if (sbq_desc
->p
.skb
) {
2146 pci_unmap_single(qdev
->pdev
,
2147 pci_unmap_addr(sbq_desc
, mapaddr
),
2148 pci_unmap_len(sbq_desc
, maplen
),
2149 PCI_DMA_FROMDEVICE
);
2150 dev_kfree_skb(sbq_desc
->p
.skb
);
2151 sbq_desc
->p
.skb
= NULL
;
2153 if (sbq_desc
->bq
== NULL
) {
2154 QPRINTK(qdev
, IFUP
, ERR
, "sbq_desc->bq %d is NULL.\n",
2158 sbq_desc
->bq
->addr_lo
= 0;
2159 sbq_desc
->bq
->addr_hi
= 0;
2163 /* Allocate and map an skb for each element of the sbq. */
2164 static int ql_alloc_sbq_buffers(struct ql_adapter
*qdev
,
2165 struct rx_ring
*rx_ring
)
2168 struct bq_desc
*sbq_desc
;
2169 struct sk_buff
*skb
;
2171 struct bq_element
*bq
= rx_ring
->sbq_base
;
2173 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2174 sbq_desc
= &rx_ring
->sbq
[i
];
2175 memset(sbq_desc
, 0, sizeof(sbq_desc
));
2176 sbq_desc
->index
= i
;
2178 skb
= netdev_alloc_skb(qdev
->ndev
, rx_ring
->sbq_buf_size
);
2179 if (unlikely(!skb
)) {
2180 /* Better luck next round */
2181 QPRINTK(qdev
, IFUP
, ERR
,
2182 "small buff alloc failed for %d bytes at index %d.\n",
2183 rx_ring
->sbq_buf_size
, i
);
2186 skb_reserve(skb
, QLGE_SB_PAD
);
2187 sbq_desc
->p
.skb
= skb
;
2189 * Map only half the buffer. Because the
2190 * other half may get some data copied to it
2191 * when the completion arrives.
2193 map
= pci_map_single(qdev
->pdev
,
2195 rx_ring
->sbq_buf_size
/ 2,
2196 PCI_DMA_FROMDEVICE
);
2197 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2198 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
2201 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
2202 pci_unmap_len_set(sbq_desc
, maplen
, rx_ring
->sbq_buf_size
/ 2);
2203 bq
->addr_lo
= /*sbq_desc->addr_lo = */
2205 bq
->addr_hi
= /*sbq_desc->addr_hi = */
2206 cpu_to_le32(map
>> 32);
2211 ql_free_sbq_buffers(qdev
, rx_ring
);
2215 static void ql_free_rx_resources(struct ql_adapter
*qdev
,
2216 struct rx_ring
*rx_ring
)
2218 if (rx_ring
->sbq_len
)
2219 ql_free_sbq_buffers(qdev
, rx_ring
);
2220 if (rx_ring
->lbq_len
)
2221 ql_free_lbq_buffers(qdev
, rx_ring
);
2223 /* Free the small buffer queue. */
2224 if (rx_ring
->sbq_base
) {
2225 pci_free_consistent(qdev
->pdev
,
2227 rx_ring
->sbq_base
, rx_ring
->sbq_base_dma
);
2228 rx_ring
->sbq_base
= NULL
;
2231 /* Free the small buffer queue control blocks. */
2232 kfree(rx_ring
->sbq
);
2233 rx_ring
->sbq
= NULL
;
2235 /* Free the large buffer queue. */
2236 if (rx_ring
->lbq_base
) {
2237 pci_free_consistent(qdev
->pdev
,
2239 rx_ring
->lbq_base
, rx_ring
->lbq_base_dma
);
2240 rx_ring
->lbq_base
= NULL
;
2243 /* Free the large buffer queue control blocks. */
2244 kfree(rx_ring
->lbq
);
2245 rx_ring
->lbq
= NULL
;
2247 /* Free the rx queue. */
2248 if (rx_ring
->cq_base
) {
2249 pci_free_consistent(qdev
->pdev
,
2251 rx_ring
->cq_base
, rx_ring
->cq_base_dma
);
2252 rx_ring
->cq_base
= NULL
;
2256 /* Allocate queues and buffers for this completions queue based
2257 * on the values in the parameter structure. */
2258 static int ql_alloc_rx_resources(struct ql_adapter
*qdev
,
2259 struct rx_ring
*rx_ring
)
2263 * Allocate the completion queue for this rx_ring.
2266 pci_alloc_consistent(qdev
->pdev
, rx_ring
->cq_size
,
2267 &rx_ring
->cq_base_dma
);
2269 if (rx_ring
->cq_base
== NULL
) {
2270 QPRINTK(qdev
, IFUP
, ERR
, "rx_ring alloc failed.\n");
2274 if (rx_ring
->sbq_len
) {
2276 * Allocate small buffer queue.
2279 pci_alloc_consistent(qdev
->pdev
, rx_ring
->sbq_size
,
2280 &rx_ring
->sbq_base_dma
);
2282 if (rx_ring
->sbq_base
== NULL
) {
2283 QPRINTK(qdev
, IFUP
, ERR
,
2284 "Small buffer queue allocation failed.\n");
2289 * Allocate small buffer queue control blocks.
2292 kmalloc(rx_ring
->sbq_len
* sizeof(struct bq_desc
),
2294 if (rx_ring
->sbq
== NULL
) {
2295 QPRINTK(qdev
, IFUP
, ERR
,
2296 "Small buffer queue control block allocation failed.\n");
2300 if (ql_alloc_sbq_buffers(qdev
, rx_ring
)) {
2301 QPRINTK(qdev
, IFUP
, ERR
,
2302 "Small buffer allocation failed.\n");
2307 if (rx_ring
->lbq_len
) {
2309 * Allocate large buffer queue.
2312 pci_alloc_consistent(qdev
->pdev
, rx_ring
->lbq_size
,
2313 &rx_ring
->lbq_base_dma
);
2315 if (rx_ring
->lbq_base
== NULL
) {
2316 QPRINTK(qdev
, IFUP
, ERR
,
2317 "Large buffer queue allocation failed.\n");
2321 * Allocate large buffer queue control blocks.
2324 kmalloc(rx_ring
->lbq_len
* sizeof(struct bq_desc
),
2326 if (rx_ring
->lbq
== NULL
) {
2327 QPRINTK(qdev
, IFUP
, ERR
,
2328 "Large buffer queue control block allocation failed.\n");
2333 * Allocate the buffers.
2335 if (ql_alloc_lbq_buffers(qdev
, rx_ring
)) {
2336 QPRINTK(qdev
, IFUP
, ERR
,
2337 "Large buffer allocation failed.\n");
2345 ql_free_rx_resources(qdev
, rx_ring
);
2349 static void ql_tx_ring_clean(struct ql_adapter
*qdev
)
2351 struct tx_ring
*tx_ring
;
2352 struct tx_ring_desc
*tx_ring_desc
;
2356 * Loop through all queues and free
2359 for (j
= 0; j
< qdev
->tx_ring_count
; j
++) {
2360 tx_ring
= &qdev
->tx_ring
[j
];
2361 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2362 tx_ring_desc
= &tx_ring
->q
[i
];
2363 if (tx_ring_desc
&& tx_ring_desc
->skb
) {
2364 QPRINTK(qdev
, IFDOWN
, ERR
,
2365 "Freeing lost SKB %p, from queue %d, index %d.\n",
2366 tx_ring_desc
->skb
, j
,
2367 tx_ring_desc
->index
);
2368 ql_unmap_send(qdev
, tx_ring_desc
,
2369 tx_ring_desc
->map_cnt
);
2370 dev_kfree_skb(tx_ring_desc
->skb
);
2371 tx_ring_desc
->skb
= NULL
;
2377 static void ql_free_ring_cb(struct ql_adapter
*qdev
)
2379 kfree(qdev
->ring_mem
);
2382 static int ql_alloc_ring_cb(struct ql_adapter
*qdev
)
2384 /* Allocate space for tx/rx ring control blocks. */
2385 qdev
->ring_mem_size
=
2386 (qdev
->tx_ring_count
* sizeof(struct tx_ring
)) +
2387 (qdev
->rx_ring_count
* sizeof(struct rx_ring
));
2388 qdev
->ring_mem
= kmalloc(qdev
->ring_mem_size
, GFP_KERNEL
);
2389 if (qdev
->ring_mem
== NULL
) {
2392 qdev
->rx_ring
= qdev
->ring_mem
;
2393 qdev
->tx_ring
= qdev
->ring_mem
+
2394 (qdev
->rx_ring_count
* sizeof(struct rx_ring
));
2399 static void ql_free_mem_resources(struct ql_adapter
*qdev
)
2403 for (i
= 0; i
< qdev
->tx_ring_count
; i
++)
2404 ql_free_tx_resources(qdev
, &qdev
->tx_ring
[i
]);
2405 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2406 ql_free_rx_resources(qdev
, &qdev
->rx_ring
[i
]);
2407 ql_free_shadow_space(qdev
);
2410 static int ql_alloc_mem_resources(struct ql_adapter
*qdev
)
2414 /* Allocate space for our shadow registers and such. */
2415 if (ql_alloc_shadow_space(qdev
))
2418 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2419 if (ql_alloc_rx_resources(qdev
, &qdev
->rx_ring
[i
]) != 0) {
2420 QPRINTK(qdev
, IFUP
, ERR
,
2421 "RX resource allocation failed.\n");
2425 /* Allocate tx queue resources */
2426 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2427 if (ql_alloc_tx_resources(qdev
, &qdev
->tx_ring
[i
]) != 0) {
2428 QPRINTK(qdev
, IFUP
, ERR
,
2429 "TX resource allocation failed.\n");
2436 ql_free_mem_resources(qdev
);
2440 /* Set up the rx ring control block and pass it to the chip.
2441 * The control block is defined as
2442 * "Completion Queue Initialization Control Block", or cqicb.
2444 static int ql_start_rx_ring(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2446 struct cqicb
*cqicb
= &rx_ring
->cqicb
;
2447 void *shadow_reg
= qdev
->rx_ring_shadow_reg_area
+
2448 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2449 u64 shadow_reg_dma
= qdev
->rx_ring_shadow_reg_dma
+
2450 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2451 void __iomem
*doorbell_area
=
2452 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* (128 + rx_ring
->cq_id
));
2456 /* Set up the shadow registers for this ring. */
2457 rx_ring
->prod_idx_sh_reg
= shadow_reg
;
2458 rx_ring
->prod_idx_sh_reg_dma
= shadow_reg_dma
;
2459 shadow_reg
+= sizeof(u64
);
2460 shadow_reg_dma
+= sizeof(u64
);
2461 rx_ring
->lbq_base_indirect
= shadow_reg
;
2462 rx_ring
->lbq_base_indirect_dma
= shadow_reg_dma
;
2463 shadow_reg
+= sizeof(u64
);
2464 shadow_reg_dma
+= sizeof(u64
);
2465 rx_ring
->sbq_base_indirect
= shadow_reg
;
2466 rx_ring
->sbq_base_indirect_dma
= shadow_reg_dma
;
2468 /* PCI doorbell mem area + 0x00 for consumer index register */
2469 rx_ring
->cnsmr_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2470 rx_ring
->cnsmr_idx
= 0;
2471 rx_ring
->curr_entry
= rx_ring
->cq_base
;
2473 /* PCI doorbell mem area + 0x04 for valid register */
2474 rx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2476 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2477 rx_ring
->lbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x18);
2479 /* PCI doorbell mem area + 0x1c */
2480 rx_ring
->sbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x1c);
2482 memset((void *)cqicb
, 0, sizeof(struct cqicb
));
2483 cqicb
->msix_vect
= rx_ring
->irq
;
2485 cqicb
->len
= cpu_to_le16(rx_ring
->cq_len
| LEN_V
| LEN_CPP_CONT
);
2487 cqicb
->addr_lo
= cpu_to_le32(rx_ring
->cq_base_dma
);
2488 cqicb
->addr_hi
= cpu_to_le32((u64
) rx_ring
->cq_base_dma
>> 32);
2490 cqicb
->prod_idx_addr_lo
= cpu_to_le32(rx_ring
->prod_idx_sh_reg_dma
);
2491 cqicb
->prod_idx_addr_hi
=
2492 cpu_to_le32((u64
) rx_ring
->prod_idx_sh_reg_dma
>> 32);
2495 * Set up the control block load flags.
2497 cqicb
->flags
= FLAGS_LC
| /* Load queue base address */
2498 FLAGS_LV
| /* Load MSI-X vector */
2499 FLAGS_LI
; /* Load irq delay values */
2500 if (rx_ring
->lbq_len
) {
2501 cqicb
->flags
|= FLAGS_LL
; /* Load lbq values */
2502 *((u64
*) rx_ring
->lbq_base_indirect
) = rx_ring
->lbq_base_dma
;
2503 cqicb
->lbq_addr_lo
=
2504 cpu_to_le32(rx_ring
->lbq_base_indirect_dma
);
2505 cqicb
->lbq_addr_hi
=
2506 cpu_to_le32((u64
) rx_ring
->lbq_base_indirect_dma
>> 32);
2507 cqicb
->lbq_buf_size
= cpu_to_le32(rx_ring
->lbq_buf_size
);
2508 bq_len
= (u16
) rx_ring
->lbq_len
;
2509 cqicb
->lbq_len
= cpu_to_le16(bq_len
);
2510 rx_ring
->lbq_prod_idx
= rx_ring
->lbq_len
- 16;
2511 rx_ring
->lbq_curr_idx
= 0;
2512 rx_ring
->lbq_clean_idx
= rx_ring
->lbq_prod_idx
;
2513 rx_ring
->lbq_free_cnt
= 16;
2515 if (rx_ring
->sbq_len
) {
2516 cqicb
->flags
|= FLAGS_LS
; /* Load sbq values */
2517 *((u64
*) rx_ring
->sbq_base_indirect
) = rx_ring
->sbq_base_dma
;
2518 cqicb
->sbq_addr_lo
=
2519 cpu_to_le32(rx_ring
->sbq_base_indirect_dma
);
2520 cqicb
->sbq_addr_hi
=
2521 cpu_to_le32((u64
) rx_ring
->sbq_base_indirect_dma
>> 32);
2522 cqicb
->sbq_buf_size
=
2523 cpu_to_le16(((rx_ring
->sbq_buf_size
/ 2) + 8) & 0xfffffff8);
2524 bq_len
= (u16
) rx_ring
->sbq_len
;
2525 cqicb
->sbq_len
= cpu_to_le16(bq_len
);
2526 rx_ring
->sbq_prod_idx
= rx_ring
->sbq_len
- 16;
2527 rx_ring
->sbq_curr_idx
= 0;
2528 rx_ring
->sbq_clean_idx
= rx_ring
->sbq_prod_idx
;
2529 rx_ring
->sbq_free_cnt
= 16;
2531 switch (rx_ring
->type
) {
2533 /* If there's only one interrupt, then we use
2534 * worker threads to process the outbound
2535 * completion handling rx_rings. We do this so
2536 * they can be run on multiple CPUs. There is
2537 * room to play with this more where we would only
2538 * run in a worker if there are more than x number
2539 * of outbound completions on the queue and more
2540 * than one queue active. Some threshold that
2541 * would indicate a benefit in spite of the cost
2542 * of a context switch.
2543 * If there's more than one interrupt, then the
2544 * outbound completions are processed in the ISR.
2546 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))
2547 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2549 /* With all debug warnings on we see a WARN_ON message
2550 * when we free the skb in the interrupt context.
2552 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2554 cqicb
->irq_delay
= cpu_to_le16(qdev
->tx_coalesce_usecs
);
2555 cqicb
->pkt_delay
= cpu_to_le16(qdev
->tx_max_coalesced_frames
);
2558 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_rx_clean
);
2559 cqicb
->irq_delay
= 0;
2560 cqicb
->pkt_delay
= 0;
2563 /* Inbound completion handling rx_rings run in
2564 * separate NAPI contexts.
2566 netif_napi_add(qdev
->ndev
, &rx_ring
->napi
, ql_napi_poll_msix
,
2568 cqicb
->irq_delay
= cpu_to_le16(qdev
->rx_coalesce_usecs
);
2569 cqicb
->pkt_delay
= cpu_to_le16(qdev
->rx_max_coalesced_frames
);
2572 QPRINTK(qdev
, IFUP
, DEBUG
, "Invalid rx_ring->type = %d.\n",
2575 QPRINTK(qdev
, IFUP
, INFO
, "Initializing rx work queue.\n");
2576 err
= ql_write_cfg(qdev
, cqicb
, sizeof(struct cqicb
),
2577 CFG_LCQ
, rx_ring
->cq_id
);
2579 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load CQICB.\n");
2582 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded CQICB.\n");
2584 * Advance the producer index for the buffer queues.
2587 if (rx_ring
->lbq_len
)
2588 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
2589 rx_ring
->lbq_prod_idx_db_reg
);
2590 if (rx_ring
->sbq_len
)
2591 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
2592 rx_ring
->sbq_prod_idx_db_reg
);
2596 static int ql_start_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2598 struct wqicb
*wqicb
= (struct wqicb
*)tx_ring
;
2599 void __iomem
*doorbell_area
=
2600 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* tx_ring
->wq_id
);
2601 void *shadow_reg
= qdev
->tx_ring_shadow_reg_area
+
2602 (tx_ring
->wq_id
* sizeof(u64
));
2603 u64 shadow_reg_dma
= qdev
->tx_ring_shadow_reg_dma
+
2604 (tx_ring
->wq_id
* sizeof(u64
));
2608 * Assign doorbell registers for this tx_ring.
2610 /* TX PCI doorbell mem area for tx producer index */
2611 tx_ring
->prod_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2612 tx_ring
->prod_idx
= 0;
2613 /* TX PCI doorbell mem area + 0x04 */
2614 tx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2617 * Assign shadow registers for this tx_ring.
2619 tx_ring
->cnsmr_idx_sh_reg
= shadow_reg
;
2620 tx_ring
->cnsmr_idx_sh_reg_dma
= shadow_reg_dma
;
2622 wqicb
->len
= cpu_to_le16(tx_ring
->wq_len
| Q_LEN_V
| Q_LEN_CPP_CONT
);
2623 wqicb
->flags
= cpu_to_le16(Q_FLAGS_LC
|
2624 Q_FLAGS_LB
| Q_FLAGS_LI
| Q_FLAGS_LO
);
2625 wqicb
->cq_id_rss
= cpu_to_le16(tx_ring
->cq_id
);
2627 wqicb
->addr_lo
= cpu_to_le32(tx_ring
->wq_base_dma
);
2628 wqicb
->addr_hi
= cpu_to_le32((u64
) tx_ring
->wq_base_dma
>> 32);
2630 wqicb
->cnsmr_idx_addr_lo
= cpu_to_le32(tx_ring
->cnsmr_idx_sh_reg_dma
);
2631 wqicb
->cnsmr_idx_addr_hi
=
2632 cpu_to_le32((u64
) tx_ring
->cnsmr_idx_sh_reg_dma
>> 32);
2634 ql_init_tx_ring(qdev
, tx_ring
);
2636 err
= ql_write_cfg(qdev
, wqicb
, sizeof(wqicb
), CFG_LRQ
,
2637 (u16
) tx_ring
->wq_id
);
2639 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load tx_ring.\n");
2642 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded WQICB.\n");
2646 static void ql_disable_msix(struct ql_adapter
*qdev
)
2648 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2649 pci_disable_msix(qdev
->pdev
);
2650 clear_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2651 kfree(qdev
->msi_x_entry
);
2652 qdev
->msi_x_entry
= NULL
;
2653 } else if (test_bit(QL_MSI_ENABLED
, &qdev
->flags
)) {
2654 pci_disable_msi(qdev
->pdev
);
2655 clear_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2659 static void ql_enable_msix(struct ql_adapter
*qdev
)
2663 qdev
->intr_count
= 1;
2664 /* Get the MSIX vectors. */
2665 if (irq_type
== MSIX_IRQ
) {
2666 /* Try to alloc space for the msix struct,
2667 * if it fails then go to MSI/legacy.
2669 qdev
->msi_x_entry
= kcalloc(qdev
->rx_ring_count
,
2670 sizeof(struct msix_entry
),
2672 if (!qdev
->msi_x_entry
) {
2677 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2678 qdev
->msi_x_entry
[i
].entry
= i
;
2680 if (!pci_enable_msix
2681 (qdev
->pdev
, qdev
->msi_x_entry
, qdev
->rx_ring_count
)) {
2682 set_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2683 qdev
->intr_count
= qdev
->rx_ring_count
;
2684 QPRINTK(qdev
, IFUP
, INFO
,
2685 "MSI-X Enabled, got %d vectors.\n",
2689 kfree(qdev
->msi_x_entry
);
2690 qdev
->msi_x_entry
= NULL
;
2691 QPRINTK(qdev
, IFUP
, WARNING
,
2692 "MSI-X Enable failed, trying MSI.\n");
2697 if (irq_type
== MSI_IRQ
) {
2698 if (!pci_enable_msi(qdev
->pdev
)) {
2699 set_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2700 QPRINTK(qdev
, IFUP
, INFO
,
2701 "Running with MSI interrupts.\n");
2706 QPRINTK(qdev
, IFUP
, DEBUG
, "Running with legacy interrupts.\n");
2710 * Here we build the intr_context structures based on
2711 * our rx_ring count and intr vector count.
2712 * The intr_context structure is used to hook each vector
2713 * to possibly different handlers.
2715 static void ql_resolve_queues_to_irqs(struct ql_adapter
*qdev
)
2718 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2720 ql_enable_msix(qdev
);
2722 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))) {
2723 /* Each rx_ring has it's
2724 * own intr_context since we have separate
2725 * vectors for each queue.
2726 * This only true when MSI-X is enabled.
2728 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2729 qdev
->rx_ring
[i
].irq
= i
;
2730 intr_context
->intr
= i
;
2731 intr_context
->qdev
= qdev
;
2733 * We set up each vectors enable/disable/read bits so
2734 * there's no bit/mask calculations in the critical path.
2736 intr_context
->intr_en_mask
=
2737 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2738 INTR_EN_TYPE_ENABLE
| INTR_EN_IHD_MASK
| INTR_EN_IHD
2740 intr_context
->intr_dis_mask
=
2741 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2742 INTR_EN_TYPE_DISABLE
| INTR_EN_IHD_MASK
|
2744 intr_context
->intr_read_mask
=
2745 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2746 INTR_EN_TYPE_READ
| INTR_EN_IHD_MASK
| INTR_EN_IHD
|
2751 * Default queue handles bcast/mcast plus
2752 * async events. Needs buffers.
2754 intr_context
->handler
= qlge_isr
;
2755 sprintf(intr_context
->name
, "%s-default-queue",
2757 } else if (i
< qdev
->rss_ring_first_cq_id
) {
2759 * Outbound queue is for outbound completions only.
2761 intr_context
->handler
= qlge_msix_tx_isr
;
2762 sprintf(intr_context
->name
, "%s-txq-%d",
2763 qdev
->ndev
->name
, i
);
2766 * Inbound queues handle unicast frames only.
2768 intr_context
->handler
= qlge_msix_rx_isr
;
2769 sprintf(intr_context
->name
, "%s-rxq-%d",
2770 qdev
->ndev
->name
, i
);
2775 * All rx_rings use the same intr_context since
2776 * there is only one vector.
2778 intr_context
->intr
= 0;
2779 intr_context
->qdev
= qdev
;
2781 * We set up each vectors enable/disable/read bits so
2782 * there's no bit/mask calculations in the critical path.
2784 intr_context
->intr_en_mask
=
2785 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_ENABLE
;
2786 intr_context
->intr_dis_mask
=
2787 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2788 INTR_EN_TYPE_DISABLE
;
2789 intr_context
->intr_read_mask
=
2790 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_READ
;
2792 * Single interrupt means one handler for all rings.
2794 intr_context
->handler
= qlge_isr
;
2795 sprintf(intr_context
->name
, "%s-single_irq", qdev
->ndev
->name
);
2796 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2797 qdev
->rx_ring
[i
].irq
= 0;
2801 static void ql_free_irq(struct ql_adapter
*qdev
)
2804 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2806 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2807 if (intr_context
->hooked
) {
2808 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2809 free_irq(qdev
->msi_x_entry
[i
].vector
,
2811 QPRINTK(qdev
, IFDOWN
, ERR
,
2812 "freeing msix interrupt %d.\n", i
);
2814 free_irq(qdev
->pdev
->irq
, &qdev
->rx_ring
[0]);
2815 QPRINTK(qdev
, IFDOWN
, ERR
,
2816 "freeing msi interrupt %d.\n", i
);
2820 ql_disable_msix(qdev
);
2823 static int ql_request_irq(struct ql_adapter
*qdev
)
2827 struct pci_dev
*pdev
= qdev
->pdev
;
2828 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2830 ql_resolve_queues_to_irqs(qdev
);
2832 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2833 atomic_set(&intr_context
->irq_cnt
, 0);
2834 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2835 status
= request_irq(qdev
->msi_x_entry
[i
].vector
,
2836 intr_context
->handler
,
2841 QPRINTK(qdev
, IFUP
, ERR
,
2842 "Failed request for MSIX interrupt %d.\n",
2846 QPRINTK(qdev
, IFUP
, INFO
,
2847 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2849 qdev
->rx_ring
[i
].type
==
2850 DEFAULT_Q
? "DEFAULT_Q" : "",
2851 qdev
->rx_ring
[i
].type
==
2853 qdev
->rx_ring
[i
].type
==
2854 RX_Q
? "RX_Q" : "", intr_context
->name
);
2857 QPRINTK(qdev
, IFUP
, DEBUG
,
2858 "trying msi or legacy interrupts.\n");
2859 QPRINTK(qdev
, IFUP
, DEBUG
,
2860 "%s: irq = %d.\n", __func__
, pdev
->irq
);
2861 QPRINTK(qdev
, IFUP
, DEBUG
,
2862 "%s: context->name = %s.\n", __func__
,
2863 intr_context
->name
);
2864 QPRINTK(qdev
, IFUP
, DEBUG
,
2865 "%s: dev_id = 0x%p.\n", __func__
,
2868 request_irq(pdev
->irq
, qlge_isr
,
2869 test_bit(QL_MSI_ENABLED
,
2871 flags
) ? 0 : IRQF_SHARED
,
2872 intr_context
->name
, &qdev
->rx_ring
[0]);
2876 QPRINTK(qdev
, IFUP
, ERR
,
2877 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2879 qdev
->rx_ring
[0].type
==
2880 DEFAULT_Q
? "DEFAULT_Q" : "",
2881 qdev
->rx_ring
[0].type
== TX_Q
? "TX_Q" : "",
2882 qdev
->rx_ring
[0].type
== RX_Q
? "RX_Q" : "",
2883 intr_context
->name
);
2885 intr_context
->hooked
= 1;
2889 QPRINTK(qdev
, IFUP
, ERR
, "Failed to get the interrupts!!!/n");
2894 static int ql_start_rss(struct ql_adapter
*qdev
)
2896 struct ricb
*ricb
= &qdev
->ricb
;
2899 u8
*hash_id
= (u8
*) ricb
->hash_cq_id
;
2901 memset((void *)ricb
, 0, sizeof(ricb
));
2903 ricb
->base_cq
= qdev
->rss_ring_first_cq_id
| RSS_L4K
;
2905 (RSS_L6K
| RSS_LI
| RSS_LB
| RSS_LM
| RSS_RI4
| RSS_RI6
| RSS_RT4
|
2907 ricb
->mask
= cpu_to_le16(qdev
->rss_ring_count
- 1);
2910 * Fill out the Indirection Table.
2912 for (i
= 0; i
< 32; i
++)
2916 * Random values for the IPv6 and IPv4 Hash Keys.
2918 get_random_bytes((void *)&ricb
->ipv6_hash_key
[0], 40);
2919 get_random_bytes((void *)&ricb
->ipv4_hash_key
[0], 16);
2921 QPRINTK(qdev
, IFUP
, INFO
, "Initializing RSS.\n");
2923 status
= ql_write_cfg(qdev
, ricb
, sizeof(ricb
), CFG_LR
, 0);
2925 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load RICB.\n");
2928 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded RICB.\n");
2932 /* Initialize the frame-to-queue routing. */
2933 static int ql_route_initialize(struct ql_adapter
*qdev
)
2938 /* Clear all the entries in the routing table. */
2939 for (i
= 0; i
< 16; i
++) {
2940 status
= ql_set_routing_reg(qdev
, i
, 0, 0);
2942 QPRINTK(qdev
, IFUP
, ERR
,
2943 "Failed to init routing register for CAM packets.\n");
2948 status
= ql_set_routing_reg(qdev
, RT_IDX_ALL_ERR_SLOT
, RT_IDX_ERR
, 1);
2950 QPRINTK(qdev
, IFUP
, ERR
,
2951 "Failed to init routing register for error packets.\n");
2954 status
= ql_set_routing_reg(qdev
, RT_IDX_BCAST_SLOT
, RT_IDX_BCAST
, 1);
2956 QPRINTK(qdev
, IFUP
, ERR
,
2957 "Failed to init routing register for broadcast packets.\n");
2960 /* If we have more than one inbound queue, then turn on RSS in the
2963 if (qdev
->rss_ring_count
> 1) {
2964 status
= ql_set_routing_reg(qdev
, RT_IDX_RSS_MATCH_SLOT
,
2965 RT_IDX_RSS_MATCH
, 1);
2967 QPRINTK(qdev
, IFUP
, ERR
,
2968 "Failed to init routing register for MATCH RSS packets.\n");
2973 status
= ql_set_routing_reg(qdev
, RT_IDX_CAM_HIT_SLOT
,
2976 QPRINTK(qdev
, IFUP
, ERR
,
2977 "Failed to init routing register for CAM packets.\n");
2983 static int ql_adapter_initialize(struct ql_adapter
*qdev
)
2990 * Set up the System register to halt on errors.
2992 value
= SYS_EFE
| SYS_FAE
;
2994 ql_write32(qdev
, SYS
, mask
| value
);
2996 /* Set the default queue. */
2997 value
= NIC_RCV_CFG_DFQ
;
2998 mask
= NIC_RCV_CFG_DFQ_MASK
;
2999 ql_write32(qdev
, NIC_RCV_CFG
, (mask
| value
));
3001 /* Set the MPI interrupt to enabled. */
3002 ql_write32(qdev
, INTR_MASK
, (INTR_MASK_PI
<< 16) | INTR_MASK_PI
);
3004 /* Enable the function, set pagesize, enable error checking. */
3005 value
= FSC_FE
| FSC_EPC_INBOUND
| FSC_EPC_OUTBOUND
|
3006 FSC_EC
| FSC_VM_PAGE_4K
| FSC_SH
;
3008 /* Set/clear header splitting. */
3009 mask
= FSC_VM_PAGESIZE_MASK
|
3010 FSC_DBL_MASK
| FSC_DBRST_MASK
| (value
<< 16);
3011 ql_write32(qdev
, FSC
, mask
| value
);
3013 ql_write32(qdev
, SPLT_HDR
, SPLT_HDR_EP
|
3014 min(SMALL_BUFFER_SIZE
, MAX_SPLIT_SIZE
));
3016 /* Start up the rx queues. */
3017 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
3018 status
= ql_start_rx_ring(qdev
, &qdev
->rx_ring
[i
]);
3020 QPRINTK(qdev
, IFUP
, ERR
,
3021 "Failed to start rx ring[%d].\n", i
);
3026 /* If there is more than one inbound completion queue
3027 * then download a RICB to configure RSS.
3029 if (qdev
->rss_ring_count
> 1) {
3030 status
= ql_start_rss(qdev
);
3032 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start RSS.\n");
3037 /* Start up the tx queues. */
3038 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3039 status
= ql_start_tx_ring(qdev
, &qdev
->tx_ring
[i
]);
3041 QPRINTK(qdev
, IFUP
, ERR
,
3042 "Failed to start tx ring[%d].\n", i
);
3047 status
= ql_port_initialize(qdev
);
3049 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start port.\n");
3053 status
= ql_set_mac_addr_reg(qdev
, (u8
*) qdev
->ndev
->perm_addr
,
3054 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
);
3056 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init mac address.\n");
3060 status
= ql_route_initialize(qdev
);
3062 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init routing table.\n");
3066 /* Start NAPI for the RSS queues. */
3067 for (i
= qdev
->rss_ring_first_cq_id
; i
< qdev
->rx_ring_count
; i
++) {
3068 QPRINTK(qdev
, IFUP
, INFO
, "Enabling NAPI for rx_ring[%d].\n",
3070 napi_enable(&qdev
->rx_ring
[i
].napi
);
3076 /* Issue soft reset to chip. */
3077 static int ql_adapter_reset(struct ql_adapter
*qdev
)
3084 #define MAX_RESET_CNT 1
3087 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Issue soft reset to chip.\n");
3088 ql_write32(qdev
, RST_FO
, (RST_FO_FR
<< 16) | RST_FO_FR
);
3089 /* Wait for reset to complete. */
3091 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Wait %d seconds for reset to complete.\n",
3094 value
= ql_read32(qdev
, RST_FO
);
3095 if ((value
& RST_FO_FR
) == 0)
3099 } while ((--max_wait_time
));
3100 if (value
& RST_FO_FR
) {
3101 QPRINTK(qdev
, IFDOWN
, ERR
,
3102 "Stuck in SoftReset: FSC_SR:0x%08x\n", value
);
3103 if (resetCnt
< MAX_RESET_CNT
)
3106 if (max_wait_time
== 0) {
3107 status
= -ETIMEDOUT
;
3108 QPRINTK(qdev
, IFDOWN
, ERR
,
3109 "ETIMEOUT!!! errored out of resetting the chip!\n");
3115 static void ql_display_dev_info(struct net_device
*ndev
)
3117 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3119 QPRINTK(qdev
, PROBE
, INFO
,
3120 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3121 "XG Roll = %d, XG Rev = %d.\n",
3123 qdev
->chip_rev_id
& 0x0000000f,
3124 qdev
->chip_rev_id
>> 4 & 0x0000000f,
3125 qdev
->chip_rev_id
>> 8 & 0x0000000f,
3126 qdev
->chip_rev_id
>> 12 & 0x0000000f);
3127 QPRINTK(qdev
, PROBE
, INFO
, "MAC address %pM\n", ndev
->dev_addr
);
3130 static int ql_adapter_down(struct ql_adapter
*qdev
)
3132 struct net_device
*ndev
= qdev
->ndev
;
3134 struct rx_ring
*rx_ring
;
3136 netif_stop_queue(ndev
);
3137 netif_carrier_off(ndev
);
3139 cancel_delayed_work_sync(&qdev
->asic_reset_work
);
3140 cancel_delayed_work_sync(&qdev
->mpi_reset_work
);
3141 cancel_delayed_work_sync(&qdev
->mpi_work
);
3143 /* The default queue at index 0 is always processed in
3146 cancel_delayed_work_sync(&qdev
->rx_ring
[0].rx_work
);
3148 /* The rest of the rx_rings are processed in
3149 * a workqueue only if it's a single interrupt
3150 * environment (MSI/Legacy).
3152 for (i
= 1; i
> qdev
->rx_ring_count
; i
++) {
3153 rx_ring
= &qdev
->rx_ring
[i
];
3154 /* Only the RSS rings use NAPI on multi irq
3155 * environment. Outbound completion processing
3156 * is done in interrupt context.
3158 if (i
>= qdev
->rss_ring_first_cq_id
) {
3159 napi_disable(&rx_ring
->napi
);
3161 cancel_delayed_work_sync(&rx_ring
->rx_work
);
3165 clear_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3167 ql_disable_interrupts(qdev
);
3169 ql_tx_ring_clean(qdev
);
3171 spin_lock(&qdev
->hw_lock
);
3172 status
= ql_adapter_reset(qdev
);
3174 QPRINTK(qdev
, IFDOWN
, ERR
, "reset(func #%d) FAILED!\n",
3176 spin_unlock(&qdev
->hw_lock
);
3180 static int ql_adapter_up(struct ql_adapter
*qdev
)
3184 spin_lock(&qdev
->hw_lock
);
3185 err
= ql_adapter_initialize(qdev
);
3187 QPRINTK(qdev
, IFUP
, INFO
, "Unable to initialize adapter.\n");
3188 spin_unlock(&qdev
->hw_lock
);
3191 spin_unlock(&qdev
->hw_lock
);
3192 set_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3193 ql_enable_interrupts(qdev
);
3194 ql_enable_all_completion_interrupts(qdev
);
3195 if ((ql_read32(qdev
, STS
) & qdev
->port_init
)) {
3196 netif_carrier_on(qdev
->ndev
);
3197 netif_start_queue(qdev
->ndev
);
3202 ql_adapter_reset(qdev
);
3206 static int ql_cycle_adapter(struct ql_adapter
*qdev
)
3210 status
= ql_adapter_down(qdev
);
3214 status
= ql_adapter_up(qdev
);
3220 QPRINTK(qdev
, IFUP
, ALERT
,
3221 "Driver up/down cycle failed, closing device\n");
3223 dev_close(qdev
->ndev
);
3228 static void ql_release_adapter_resources(struct ql_adapter
*qdev
)
3230 ql_free_mem_resources(qdev
);
3234 static int ql_get_adapter_resources(struct ql_adapter
*qdev
)
3238 if (ql_alloc_mem_resources(qdev
)) {
3239 QPRINTK(qdev
, IFUP
, ERR
, "Unable to allocate memory.\n");
3242 status
= ql_request_irq(qdev
);
3247 ql_free_mem_resources(qdev
);
3251 static int qlge_close(struct net_device
*ndev
)
3253 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3256 * Wait for device to recover from a reset.
3257 * (Rarely happens, but possible.)
3259 while (!test_bit(QL_ADAPTER_UP
, &qdev
->flags
))
3261 ql_adapter_down(qdev
);
3262 ql_release_adapter_resources(qdev
);
3263 ql_free_ring_cb(qdev
);
3267 static int ql_configure_rings(struct ql_adapter
*qdev
)
3270 struct rx_ring
*rx_ring
;
3271 struct tx_ring
*tx_ring
;
3272 int cpu_cnt
= num_online_cpus();
3275 * For each processor present we allocate one
3276 * rx_ring for outbound completions, and one
3277 * rx_ring for inbound completions. Plus there is
3278 * always the one default queue. For the CPU
3279 * counts we end up with the following rx_rings:
3281 * one default queue +
3282 * (CPU count * outbound completion rx_ring) +
3283 * (CPU count * inbound (RSS) completion rx_ring)
3284 * To keep it simple we limit the total number of
3285 * queues to < 32, so we truncate CPU to 8.
3286 * This limitation can be removed when requested.
3293 * rx_ring[0] is always the default queue.
3295 /* Allocate outbound completion ring for each CPU. */
3296 qdev
->tx_ring_count
= cpu_cnt
;
3297 /* Allocate inbound completion (RSS) ring for each CPU. */
3298 qdev
->rss_ring_count
= cpu_cnt
;
3299 /* cq_id for the first inbound ring handler. */
3300 qdev
->rss_ring_first_cq_id
= cpu_cnt
+ 1;
3302 * qdev->rx_ring_count:
3303 * Total number of rx_rings. This includes the one
3304 * default queue, a number of outbound completion
3305 * handler rx_rings, and the number of inbound
3306 * completion handler rx_rings.
3308 qdev
->rx_ring_count
= qdev
->tx_ring_count
+ qdev
->rss_ring_count
+ 1;
3310 if (ql_alloc_ring_cb(qdev
))
3313 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3314 tx_ring
= &qdev
->tx_ring
[i
];
3315 memset((void *)tx_ring
, 0, sizeof(tx_ring
));
3316 tx_ring
->qdev
= qdev
;
3318 tx_ring
->wq_len
= qdev
->tx_ring_size
;
3320 tx_ring
->wq_len
* sizeof(struct ob_mac_iocb_req
);
3323 * The completion queue ID for the tx rings start
3324 * immediately after the default Q ID, which is zero.
3326 tx_ring
->cq_id
= i
+ 1;
3329 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
3330 rx_ring
= &qdev
->rx_ring
[i
];
3331 memset((void *)rx_ring
, 0, sizeof(rx_ring
));
3332 rx_ring
->qdev
= qdev
;
3334 rx_ring
->cpu
= i
% cpu_cnt
; /* CPU to run handler on. */
3335 if (i
== 0) { /* Default queue at index 0. */
3337 * Default queue handles bcast/mcast plus
3338 * async events. Needs buffers.
3340 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3342 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3343 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3345 rx_ring
->lbq_len
* sizeof(struct bq_element
);
3346 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3347 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3349 rx_ring
->sbq_len
* sizeof(struct bq_element
);
3350 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3351 rx_ring
->type
= DEFAULT_Q
;
3352 } else if (i
< qdev
->rss_ring_first_cq_id
) {
3354 * Outbound queue handles outbound completions only.
3356 /* outbound cq is same size as tx_ring it services. */
3357 rx_ring
->cq_len
= qdev
->tx_ring_size
;
3359 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3360 rx_ring
->lbq_len
= 0;
3361 rx_ring
->lbq_size
= 0;
3362 rx_ring
->lbq_buf_size
= 0;
3363 rx_ring
->sbq_len
= 0;
3364 rx_ring
->sbq_size
= 0;
3365 rx_ring
->sbq_buf_size
= 0;
3366 rx_ring
->type
= TX_Q
;
3367 } else { /* Inbound completions (RSS) queues */
3369 * Inbound queues handle unicast frames only.
3371 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3373 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3374 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3376 rx_ring
->lbq_len
* sizeof(struct bq_element
);
3377 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3378 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3380 rx_ring
->sbq_len
* sizeof(struct bq_element
);
3381 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3382 rx_ring
->type
= RX_Q
;
3388 static int qlge_open(struct net_device
*ndev
)
3391 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3393 err
= ql_configure_rings(qdev
);
3397 err
= ql_get_adapter_resources(qdev
);
3401 err
= ql_adapter_up(qdev
);
3408 ql_release_adapter_resources(qdev
);
3409 ql_free_ring_cb(qdev
);
3413 static int qlge_change_mtu(struct net_device
*ndev
, int new_mtu
)
3415 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3417 if (ndev
->mtu
== 1500 && new_mtu
== 9000) {
3418 QPRINTK(qdev
, IFUP
, ERR
, "Changing to jumbo MTU.\n");
3419 } else if (ndev
->mtu
== 9000 && new_mtu
== 1500) {
3420 QPRINTK(qdev
, IFUP
, ERR
, "Changing to normal MTU.\n");
3421 } else if ((ndev
->mtu
== 1500 && new_mtu
== 1500) ||
3422 (ndev
->mtu
== 9000 && new_mtu
== 9000)) {
3426 ndev
->mtu
= new_mtu
;
3430 static struct net_device_stats
*qlge_get_stats(struct net_device
3433 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3434 return &qdev
->stats
;
3437 static void qlge_set_multicast_list(struct net_device
*ndev
)
3439 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3440 struct dev_mc_list
*mc_ptr
;
3443 spin_lock(&qdev
->hw_lock
);
3445 * Set or clear promiscuous mode if a
3446 * transition is taking place.
3448 if (ndev
->flags
& IFF_PROMISC
) {
3449 if (!test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3450 if (ql_set_routing_reg
3451 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 1)) {
3452 QPRINTK(qdev
, HW
, ERR
,
3453 "Failed to set promiscous mode.\n");
3455 set_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3459 if (test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3460 if (ql_set_routing_reg
3461 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 0)) {
3462 QPRINTK(qdev
, HW
, ERR
,
3463 "Failed to clear promiscous mode.\n");
3465 clear_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3471 * Set or clear all multicast mode if a
3472 * transition is taking place.
3474 if ((ndev
->flags
& IFF_ALLMULTI
) ||
3475 (ndev
->mc_count
> MAX_MULTICAST_ENTRIES
)) {
3476 if (!test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3477 if (ql_set_routing_reg
3478 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 1)) {
3479 QPRINTK(qdev
, HW
, ERR
,
3480 "Failed to set all-multi mode.\n");
3482 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3486 if (test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3487 if (ql_set_routing_reg
3488 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 0)) {
3489 QPRINTK(qdev
, HW
, ERR
,
3490 "Failed to clear all-multi mode.\n");
3492 clear_bit(QL_ALLMULTI
, &qdev
->flags
);
3497 if (ndev
->mc_count
) {
3498 for (i
= 0, mc_ptr
= ndev
->mc_list
; mc_ptr
;
3499 i
++, mc_ptr
= mc_ptr
->next
)
3500 if (ql_set_mac_addr_reg(qdev
, (u8
*) mc_ptr
->dmi_addr
,
3501 MAC_ADDR_TYPE_MULTI_MAC
, i
)) {
3502 QPRINTK(qdev
, HW
, ERR
,
3503 "Failed to loadmulticast address.\n");
3506 if (ql_set_routing_reg
3507 (qdev
, RT_IDX_MCAST_MATCH_SLOT
, RT_IDX_MCAST_MATCH
, 1)) {
3508 QPRINTK(qdev
, HW
, ERR
,
3509 "Failed to set multicast match mode.\n");
3511 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3515 spin_unlock(&qdev
->hw_lock
);
3518 static int qlge_set_mac_address(struct net_device
*ndev
, void *p
)
3520 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3521 struct sockaddr
*addr
= p
;
3524 if (netif_running(ndev
))
3527 if (!is_valid_ether_addr(addr
->sa_data
))
3528 return -EADDRNOTAVAIL
;
3529 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3531 spin_lock(&qdev
->hw_lock
);
3532 if (ql_set_mac_addr_reg(qdev
, (u8
*) ndev
->dev_addr
,
3533 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
)) {/* Unicast */
3534 QPRINTK(qdev
, HW
, ERR
, "Failed to load MAC address.\n");
3537 spin_unlock(&qdev
->hw_lock
);
3542 static void qlge_tx_timeout(struct net_device
*ndev
)
3544 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3545 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
3548 static void ql_asic_reset_work(struct work_struct
*work
)
3550 struct ql_adapter
*qdev
=
3551 container_of(work
, struct ql_adapter
, asic_reset_work
.work
);
3552 ql_cycle_adapter(qdev
);
3555 static void ql_get_board_info(struct ql_adapter
*qdev
)
3558 (ql_read32(qdev
, STS
) & STS_FUNC_ID_MASK
) >> STS_FUNC_ID_SHIFT
;
3560 qdev
->xg_sem_mask
= SEM_XGMAC1_MASK
;
3561 qdev
->port_link_up
= STS_PL1
;
3562 qdev
->port_init
= STS_PI1
;
3563 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBI
;
3564 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBO
;
3566 qdev
->xg_sem_mask
= SEM_XGMAC0_MASK
;
3567 qdev
->port_link_up
= STS_PL0
;
3568 qdev
->port_init
= STS_PI0
;
3569 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBI
;
3570 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBO
;
3572 qdev
->chip_rev_id
= ql_read32(qdev
, REV_ID
);
3575 static void ql_release_all(struct pci_dev
*pdev
)
3577 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3578 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3580 if (qdev
->workqueue
) {
3581 destroy_workqueue(qdev
->workqueue
);
3582 qdev
->workqueue
= NULL
;
3584 if (qdev
->q_workqueue
) {
3585 destroy_workqueue(qdev
->q_workqueue
);
3586 qdev
->q_workqueue
= NULL
;
3589 iounmap(qdev
->reg_base
);
3590 if (qdev
->doorbell_area
)
3591 iounmap(qdev
->doorbell_area
);
3592 pci_release_regions(pdev
);
3593 pci_set_drvdata(pdev
, NULL
);
3596 static int __devinit
ql_init_device(struct pci_dev
*pdev
,
3597 struct net_device
*ndev
, int cards_found
)
3599 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3603 memset((void *)qdev
, 0, sizeof(qdev
));
3604 err
= pci_enable_device(pdev
);
3606 dev_err(&pdev
->dev
, "PCI device enable failed.\n");
3610 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3612 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
3616 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
3617 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
3618 val16
|= (PCI_EXP_DEVCTL_CERE
|
3619 PCI_EXP_DEVCTL_NFERE
|
3620 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
3621 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
3624 err
= pci_request_regions(pdev
, DRV_NAME
);
3626 dev_err(&pdev
->dev
, "PCI region request failed.\n");
3630 pci_set_master(pdev
);
3631 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3632 set_bit(QL_DMA64
, &qdev
->flags
);
3633 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3635 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3637 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3641 dev_err(&pdev
->dev
, "No usable DMA configuration.\n");
3645 pci_set_drvdata(pdev
, ndev
);
3647 ioremap_nocache(pci_resource_start(pdev
, 1),
3648 pci_resource_len(pdev
, 1));
3649 if (!qdev
->reg_base
) {
3650 dev_err(&pdev
->dev
, "Register mapping failed.\n");
3655 qdev
->doorbell_area_size
= pci_resource_len(pdev
, 3);
3656 qdev
->doorbell_area
=
3657 ioremap_nocache(pci_resource_start(pdev
, 3),
3658 pci_resource_len(pdev
, 3));
3659 if (!qdev
->doorbell_area
) {
3660 dev_err(&pdev
->dev
, "Doorbell register mapping failed.\n");
3665 ql_get_board_info(qdev
);
3668 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3669 spin_lock_init(&qdev
->hw_lock
);
3670 spin_lock_init(&qdev
->stats_lock
);
3672 /* make sure the EEPROM is good */
3673 err
= ql_get_flash_params(qdev
);
3675 dev_err(&pdev
->dev
, "Invalid FLASH.\n");
3679 if (!is_valid_ether_addr(qdev
->flash
.mac_addr
))
3682 memcpy(ndev
->dev_addr
, qdev
->flash
.mac_addr
, ndev
->addr_len
);
3683 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3685 /* Set up the default ring sizes. */
3686 qdev
->tx_ring_size
= NUM_TX_RING_ENTRIES
;
3687 qdev
->rx_ring_size
= NUM_RX_RING_ENTRIES
;
3689 /* Set up the coalescing parameters. */
3690 qdev
->rx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3691 qdev
->tx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3692 qdev
->rx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3693 qdev
->tx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3696 * Set up the operating parameters.
3700 qdev
->q_workqueue
= create_workqueue(ndev
->name
);
3701 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3702 INIT_DELAYED_WORK(&qdev
->asic_reset_work
, ql_asic_reset_work
);
3703 INIT_DELAYED_WORK(&qdev
->mpi_reset_work
, ql_mpi_reset_work
);
3704 INIT_DELAYED_WORK(&qdev
->mpi_work
, ql_mpi_work
);
3707 dev_info(&pdev
->dev
, "%s\n", DRV_STRING
);
3708 dev_info(&pdev
->dev
, "Driver name: %s, Version: %s.\n",
3709 DRV_NAME
, DRV_VERSION
);
3713 ql_release_all(pdev
);
3714 pci_disable_device(pdev
);
3719 static const struct net_device_ops qlge_netdev_ops
= {
3720 .ndo_open
= qlge_open
,
3721 .ndo_stop
= qlge_close
,
3722 .ndo_start_xmit
= qlge_send
,
3723 .ndo_change_mtu
= qlge_change_mtu
,
3724 .ndo_get_stats
= qlge_get_stats
,
3725 .ndo_set_multicast_list
= qlge_set_multicast_list
,
3726 .ndo_set_mac_address
= qlge_set_mac_address
,
3727 .ndo_validate_addr
= eth_validate_addr
,
3728 .ndo_tx_timeout
= qlge_tx_timeout
,
3729 .ndo_vlan_rx_register
= ql_vlan_rx_register
,
3730 .ndo_vlan_rx_add_vid
= ql_vlan_rx_add_vid
,
3731 .ndo_vlan_rx_kill_vid
= ql_vlan_rx_kill_vid
,
3734 static int __devinit
qlge_probe(struct pci_dev
*pdev
,
3735 const struct pci_device_id
*pci_entry
)
3737 struct net_device
*ndev
= NULL
;
3738 struct ql_adapter
*qdev
= NULL
;
3739 static int cards_found
= 0;
3742 ndev
= alloc_etherdev(sizeof(struct ql_adapter
));
3746 err
= ql_init_device(pdev
, ndev
, cards_found
);
3752 qdev
= netdev_priv(ndev
);
3753 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3760 | NETIF_F_HW_VLAN_TX
3761 | NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
);
3763 if (test_bit(QL_DMA64
, &qdev
->flags
))
3764 ndev
->features
|= NETIF_F_HIGHDMA
;
3767 * Set up net_device structure.
3769 ndev
->tx_queue_len
= qdev
->tx_ring_size
;
3770 ndev
->irq
= pdev
->irq
;
3772 ndev
->netdev_ops
= &qlge_netdev_ops
;
3773 SET_ETHTOOL_OPS(ndev
, &qlge_ethtool_ops
);
3774 ndev
->watchdog_timeo
= 10 * HZ
;
3776 err
= register_netdev(ndev
);
3778 dev_err(&pdev
->dev
, "net device registration failed.\n");
3779 ql_release_all(pdev
);
3780 pci_disable_device(pdev
);
3783 netif_carrier_off(ndev
);
3784 netif_stop_queue(ndev
);
3785 ql_display_dev_info(ndev
);
3790 static void __devexit
qlge_remove(struct pci_dev
*pdev
)
3792 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3793 unregister_netdev(ndev
);
3794 ql_release_all(pdev
);
3795 pci_disable_device(pdev
);
3800 * This callback is called by the PCI subsystem whenever
3801 * a PCI bus error is detected.
3803 static pci_ers_result_t
qlge_io_error_detected(struct pci_dev
*pdev
,
3804 enum pci_channel_state state
)
3806 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3807 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3809 if (netif_running(ndev
))
3810 ql_adapter_down(qdev
);
3812 pci_disable_device(pdev
);
3814 /* Request a slot reset. */
3815 return PCI_ERS_RESULT_NEED_RESET
;
3819 * This callback is called after the PCI buss has been reset.
3820 * Basically, this tries to restart the card from scratch.
3821 * This is a shortened version of the device probe/discovery code,
3822 * it resembles the first-half of the () routine.
3824 static pci_ers_result_t
qlge_io_slot_reset(struct pci_dev
*pdev
)
3826 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3827 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3829 if (pci_enable_device(pdev
)) {
3830 QPRINTK(qdev
, IFUP
, ERR
,
3831 "Cannot re-enable PCI device after reset.\n");
3832 return PCI_ERS_RESULT_DISCONNECT
;
3835 pci_set_master(pdev
);
3837 netif_carrier_off(ndev
);
3838 netif_stop_queue(ndev
);
3839 ql_adapter_reset(qdev
);
3841 /* Make sure the EEPROM is good */
3842 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3844 if (!is_valid_ether_addr(ndev
->perm_addr
)) {
3845 QPRINTK(qdev
, IFUP
, ERR
, "After reset, invalid MAC address.\n");
3846 return PCI_ERS_RESULT_DISCONNECT
;
3849 return PCI_ERS_RESULT_RECOVERED
;
3852 static void qlge_io_resume(struct pci_dev
*pdev
)
3854 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3855 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3857 pci_set_master(pdev
);
3859 if (netif_running(ndev
)) {
3860 if (ql_adapter_up(qdev
)) {
3861 QPRINTK(qdev
, IFUP
, ERR
,
3862 "Device initialization failed after reset.\n");
3867 netif_device_attach(ndev
);
3870 static struct pci_error_handlers qlge_err_handler
= {
3871 .error_detected
= qlge_io_error_detected
,
3872 .slot_reset
= qlge_io_slot_reset
,
3873 .resume
= qlge_io_resume
,
3876 static int qlge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3878 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3879 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3882 netif_device_detach(ndev
);
3884 if (netif_running(ndev
)) {
3885 err
= ql_adapter_down(qdev
);
3890 err
= pci_save_state(pdev
);
3894 pci_disable_device(pdev
);
3896 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3902 static int qlge_resume(struct pci_dev
*pdev
)
3904 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3905 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3908 pci_set_power_state(pdev
, PCI_D0
);
3909 pci_restore_state(pdev
);
3910 err
= pci_enable_device(pdev
);
3912 QPRINTK(qdev
, IFUP
, ERR
, "Cannot enable PCI device from suspend\n");
3915 pci_set_master(pdev
);
3917 pci_enable_wake(pdev
, PCI_D3hot
, 0);
3918 pci_enable_wake(pdev
, PCI_D3cold
, 0);
3920 if (netif_running(ndev
)) {
3921 err
= ql_adapter_up(qdev
);
3926 netif_device_attach(ndev
);
3930 #endif /* CONFIG_PM */
3932 static void qlge_shutdown(struct pci_dev
*pdev
)
3934 qlge_suspend(pdev
, PMSG_SUSPEND
);
3937 static struct pci_driver qlge_driver
= {
3939 .id_table
= qlge_pci_tbl
,
3940 .probe
= qlge_probe
,
3941 .remove
= __devexit_p(qlge_remove
),
3943 .suspend
= qlge_suspend
,
3944 .resume
= qlge_resume
,
3946 .shutdown
= qlge_shutdown
,
3947 .err_handler
= &qlge_err_handler
3950 static int __init
qlge_init_module(void)
3952 return pci_register_driver(&qlge_driver
);
3955 static void __exit
qlge_exit(void)
3957 pci_unregister_driver(&qlge_driver
);
3960 module_init(qlge_init_module
);
3961 module_exit(qlge_exit
);