include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/irqflags.h>
   9
  10 #include <asm/hw_irq.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * We have to use the sync instructions for mb(), since lwsync doesn't
  27  * order loads with respect to previous stores.  Lwsync is fine for
  28  * rmb(), though. Note that rmb() actually uses a sync on 32-bit
  29  * architectures.
  30  *
  31  * For wmb(), we use sync since wmb is used in drivers to order
  32  * stores to system memory with respect to writes to the device.
  33  * However, smp_wmb() can be a lighter-weight eieio barrier on
  34  * SMP since it is only used to order updates to system memory.
  35  */
  36 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  37 #define rmb()  __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
  38 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  39 #define read_barrier_depends()  do { } while(0)
  40
  41 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  42
  43 #ifdef __KERNEL__
  44 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
  45 #ifdef CONFIG_SMP
  46 #define smp_mb()        mb()
  47 #define smp_rmb()       rmb()
  48 #define smp_wmb()       eieio()
  49 #define smp_read_barrier_depends()      read_barrier_depends()
  50 #else
  51 #define smp_mb()        barrier()
  52 #define smp_rmb()       barrier()
  53 #define smp_wmb()       barrier()
  54 #define smp_read_barrier_depends()      do { } while(0)
  55 #endif /* CONFIG_SMP */
  56
  57 /*
  58  * This is a barrier which prevents following instructions from being
  59  * started until the value of the argument x is known.  For example, if
  60  * x is a variable loaded from memory, this prevents following
  61  * instructions from being executed until the load has been performed.
  62  */
  63 #define data_barrier(x) \
  64         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  65
  66 struct task_struct;
  67 struct pt_regs;
  68
  69 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  70
  71 extern int (*__debugger)(struct pt_regs *regs);
  72 extern int (*__debugger_ipi)(struct pt_regs *regs);
  73 extern int (*__debugger_bpt)(struct pt_regs *regs);
  74 extern int (*__debugger_sstep)(struct pt_regs *regs);
  75 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  76 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  77 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  78
  79 #define DEBUGGER_BOILERPLATE(__NAME) \
  80 static inline int __NAME(struct pt_regs *regs) \
  81 { \
  82         if (unlikely(__ ## __NAME)) \
  83                 return __ ## __NAME(regs); \
  84         return 0; \
  85 }
  86
  87 DEBUGGER_BOILERPLATE(debugger)
  88 DEBUGGER_BOILERPLATE(debugger_ipi)
  89 DEBUGGER_BOILERPLATE(debugger_bpt)
  90 DEBUGGER_BOILERPLATE(debugger_sstep)
  91 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  92 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  93 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  94
  95 #else
  96 static inline int debugger(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
 100 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 101 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 102 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 103 #endif
 104
 105 extern int set_dabr(unsigned long dabr);
 106 extern void print_backtrace(unsigned long *);
 107 extern void show_regs(struct pt_regs * regs);
 108 extern void flush_instruction_cache(void);
 109 extern void hard_reset_now(void);
 110 extern void poweroff_now(void);
 111
 112 #ifdef CONFIG_6xx
 113 extern long _get_L2CR(void);
 114 extern long _get_L3CR(void);
 115 extern void _set_L2CR(unsigned long);
 116 extern void _set_L3CR(unsigned long);
 117 #else
 118 #define _get_L2CR()     0L
 119 #define _get_L3CR()     0L
 120 #define _set_L2CR(val)  do { } while(0)
 121 #define _set_L3CR(val)  do { } while(0)
 122 #endif
 123
 124 extern void via_cuda_init(void);
 125 extern void read_rtc_time(void);
 126 extern void pmac_find_display(void);
 127 extern void giveup_fpu(struct task_struct *);
 128 extern void disable_kernel_fp(void);
 129 extern void enable_kernel_fp(void);
 130 extern void flush_fp_to_thread(struct task_struct *);
 131 extern void enable_kernel_altivec(void);
 132 extern void giveup_altivec(struct task_struct *);
 133 extern void load_up_altivec(struct task_struct *);
 134 extern int emulate_altivec(struct pt_regs *);
 135 extern void enable_kernel_spe(void);
 136 extern void giveup_spe(struct task_struct *);
 137 extern void load_up_spe(struct task_struct *);
 138 extern int fix_alignment(struct pt_regs *);
 139 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 140 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 141
 142 #ifndef CONFIG_SMP
 143 extern void discard_lazy_cpu_state(void);
 144 #else
 145 static inline void discard_lazy_cpu_state(void)
 146 {
 147 }
 148 #endif
 149
 150 #ifdef CONFIG_ALTIVEC
 151 extern void flush_altivec_to_thread(struct task_struct *);
 152 #else
 153 static inline void flush_altivec_to_thread(struct task_struct *t)
 154 {
 155 }
 156 #endif
 157
 158 #ifdef CONFIG_SPE
 159 extern void flush_spe_to_thread(struct task_struct *);
 160 #else
 161 static inline void flush_spe_to_thread(struct task_struct *t)
 162 {
 163 }
 164 #endif
 165
 166 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 167 extern void cacheable_memzero(void *p, unsigned int nb);
 168 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 169 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 170 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 171 extern int die(const char *, struct pt_regs *, long);
 172 extern void _exception(int, struct pt_regs *, int, unsigned long);
 173 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 174
 175 #ifdef CONFIG_BOOKE_WDT
 176 extern u32 booke_wdt_enabled;
 177 extern u32 booke_wdt_period;
 178 #endif /* CONFIG_BOOKE_WDT */
 179
 180 struct device_node;
 181 extern void note_scsi_host(struct device_node *, void *);
 182
 183 extern struct task_struct *__switch_to(struct task_struct *,
 184         struct task_struct *);
 185 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 186
 187 struct thread_struct;
 188 extern struct task_struct *_switch(struct thread_struct *prev,
 189                                    struct thread_struct *next);
 190
 191 extern unsigned int rtas_data;
 192 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 193 extern unsigned long memory_limit;
 194 extern unsigned long klimit;
 195
 196 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
 197 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 198
 199 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 200
 201 /*
 202  * Atomic exchange
 203  *
 204  * Changes the memory location '*ptr' to be val and returns
 205  * the previous value stored there.
 206  */
 207 static __always_inline unsigned long
 208 __xchg_u32(volatile void *p, unsigned long val)
 209 {
 210         unsigned long prev;
 211
 212         __asm__ __volatile__(
 213         LWSYNC_ON_SMP
 214 "1:     lwarx   %0,0,%2 \n"
 215         PPC405_ERR77(0,%2)
 216 "       stwcx.  %3,0,%2 \n\
 217         bne-    1b"
 218         ISYNC_ON_SMP
 219         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 220         : "r" (p), "r" (val)
 221         : "cc", "memory");
 222
 223         return prev;
 224 }
 225
 226 /*
 227  * Atomic exchange
 228  *
 229  * Changes the memory location '*ptr' to be val and returns
 230  * the previous value stored there.
 231  */
 232 static __always_inline unsigned long
 233 __xchg_u32_local(volatile void *p, unsigned long val)
 234 {
 235         unsigned long prev;
 236
 237         __asm__ __volatile__(
 238 "1:     lwarx   %0,0,%2 \n"
 239         PPC405_ERR77(0,%2)
 240 "       stwcx.  %3,0,%2 \n\
 241         bne-    1b"
 242         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 243         : "r" (p), "r" (val)
 244         : "cc", "memory");
 245
 246         return prev;
 247 }
 248
 249 #ifdef CONFIG_PPC64
 250 static __always_inline unsigned long
 251 __xchg_u64(volatile void *p, unsigned long val)
 252 {
 253         unsigned long prev;
 254
 255         __asm__ __volatile__(
 256         LWSYNC_ON_SMP
 257 "1:     ldarx   %0,0,%2 \n"
 258         PPC405_ERR77(0,%2)
 259 "       stdcx.  %3,0,%2 \n\
 260         bne-    1b"
 261         ISYNC_ON_SMP
 262         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 263         : "r" (p), "r" (val)
 264         : "cc", "memory");
 265
 266         return prev;
 267 }
 268
 269 static __always_inline unsigned long
 270 __xchg_u64_local(volatile void *p, unsigned long val)
 271 {
 272         unsigned long prev;
 273
 274         __asm__ __volatile__(
 275 "1:     ldarx   %0,0,%2 \n"
 276         PPC405_ERR77(0,%2)
 277 "       stdcx.  %3,0,%2 \n\
 278         bne-    1b"
 279         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 280         : "r" (p), "r" (val)
 281         : "cc", "memory");
 282
 283         return prev;
 284 }
 285 #endif
 286
 287 /*
 288  * This function doesn't exist, so you'll get a linker error
 289  * if something tries to do an invalid xchg().
 290  */
 291 extern void __xchg_called_with_bad_pointer(void);
 292
 293 static __always_inline unsigned long
 294 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 295 {
 296         switch (size) {
 297         case 4:
 298                 return __xchg_u32(ptr, x);
 299 #ifdef CONFIG_PPC64
 300         case 8:
 301                 return __xchg_u64(ptr, x);
 302 #endif
 303         }
 304         __xchg_called_with_bad_pointer();
 305         return x;
 306 }
 307
 308 static __always_inline unsigned long
 309 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
 310 {
 311         switch (size) {
 312         case 4:
 313                 return __xchg_u32_local(ptr, x);
 314 #ifdef CONFIG_PPC64
 315         case 8:
 316                 return __xchg_u64_local(ptr, x);
 317 #endif
 318         }
 319         __xchg_called_with_bad_pointer();
 320         return x;
 321 }
 322 #define xchg(ptr,x)                                                          \
 323   ({                                                                         \
 324      __typeof__(*(ptr)) _x_ = (x);                                           \
 325      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 326   })
 327
 328 #define xchg_local(ptr,x)                                                    \
 329   ({                                                                         \
 330      __typeof__(*(ptr)) _x_ = (x);                                           \
 331      (__typeof__(*(ptr))) __xchg_local((ptr),                                \
 332                 (unsigned long)_x_, sizeof(*(ptr)));                         \
 333   })
 334
 335 /*
 336  * Compare and exchange - if *p == old, set it to new,
 337  * and return the old value of *p.
 338  */
 339 #define __HAVE_ARCH_CMPXCHG     1
 340
 341 static __always_inline unsigned long
 342 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 343 {
 344         unsigned int prev;
 345
 346         __asm__ __volatile__ (
 347         LWSYNC_ON_SMP
 348 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 349         cmpw    0,%0,%3\n\
 350         bne-    2f\n"
 351         PPC405_ERR77(0,%2)
 352 "       stwcx.  %4,0,%2\n\
 353         bne-    1b"
 354         ISYNC_ON_SMP
 355         "\n\
 356 2:"
 357         : "=&r" (prev), "+m" (*p)
 358         : "r" (p), "r" (old), "r" (new)
 359         : "cc", "memory");
 360
 361         return prev;
 362 }
 363
 364 static __always_inline unsigned long
 365 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 366                         unsigned long new)
 367 {
 368         unsigned int prev;
 369
 370         __asm__ __volatile__ (
 371 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 372         cmpw    0,%0,%3\n\
 373         bne-    2f\n"
 374         PPC405_ERR77(0,%2)
 375 "       stwcx.  %4,0,%2\n\
 376         bne-    1b"
 377         "\n\
 378 2:"
 379         : "=&r" (prev), "+m" (*p)
 380         : "r" (p), "r" (old), "r" (new)
 381         : "cc", "memory");
 382
 383         return prev;
 384 }
 385
 386 #ifdef CONFIG_PPC64
 387 static __always_inline unsigned long
 388 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 389 {
 390         unsigned long prev;
 391
 392         __asm__ __volatile__ (
 393         LWSYNC_ON_SMP
 394 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 395         cmpd    0,%0,%3\n\
 396         bne-    2f\n\
 397         stdcx.  %4,0,%2\n\
 398         bne-    1b"
 399         ISYNC_ON_SMP
 400         "\n\
 401 2:"
 402         : "=&r" (prev), "+m" (*p)
 403         : "r" (p), "r" (old), "r" (new)
 404         : "cc", "memory");
 405
 406         return prev;
 407 }
 408
 409 static __always_inline unsigned long
 410 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
 411                         unsigned long new)
 412 {
 413         unsigned long prev;
 414
 415         __asm__ __volatile__ (
 416 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 417         cmpd    0,%0,%3\n\
 418         bne-    2f\n\
 419         stdcx.  %4,0,%2\n\
 420         bne-    1b"
 421         "\n\
 422 2:"
 423         : "=&r" (prev), "+m" (*p)
 424         : "r" (p), "r" (old), "r" (new)
 425         : "cc", "memory");
 426
 427         return prev;
 428 }
 429 #endif
 430
 431 /* This function doesn't exist, so you'll get a linker error
 432    if something tries to do an invalid cmpxchg().  */
 433 extern void __cmpxchg_called_with_bad_pointer(void);
 434
 435 static __always_inline unsigned long
 436 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 437           unsigned int size)
 438 {
 439         switch (size) {
 440         case 4:
 441                 return __cmpxchg_u32(ptr, old, new);
 442 #ifdef CONFIG_PPC64
 443         case 8:
 444                 return __cmpxchg_u64(ptr, old, new);
 445 #endif
 446         }
 447         __cmpxchg_called_with_bad_pointer();
 448         return old;
 449 }
 450
 451 static __always_inline unsigned long
 452 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
 453           unsigned int size)
 454 {
 455         switch (size) {
 456         case 4:
 457                 return __cmpxchg_u32_local(ptr, old, new);
 458 #ifdef CONFIG_PPC64
 459         case 8:
 460                 return __cmpxchg_u64_local(ptr, old, new);
 461 #endif
 462         }
 463         __cmpxchg_called_with_bad_pointer();
 464         return old;
 465 }
 466
 467 #define cmpxchg(ptr, o, n)                                               \
 468   ({                                                                     \
 469      __typeof__(*(ptr)) _o_ = (o);                                       \
 470      __typeof__(*(ptr)) _n_ = (n);                                       \
 471      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 472                                     (unsigned long)_n_, sizeof(*(ptr))); \
 473   })
 474
 475
 476 #define cmpxchg_local(ptr, o, n)                                         \
 477   ({                                                                     \
 478      __typeof__(*(ptr)) _o_ = (o);                                       \
 479      __typeof__(*(ptr)) _n_ = (n);                                       \
 480      (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
 481                                     (unsigned long)_n_, sizeof(*(ptr))); \
 482   })
 483
 484 #ifdef CONFIG_PPC64
 485 /*
 486  * We handle most unaligned accesses in hardware. On the other hand
 487  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 488  * powers of 2 writes until it reaches sufficient alignment).
 489  *
 490  * Based on this we disable the IP header alignment in network drivers.
 491  * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 492  * cacheline alignment of buffers.
 493  */
 494 #define NET_IP_ALIGN    0
 495 #define NET_SKB_PAD     L1_CACHE_BYTES
 496
 497 #define cmpxchg64(ptr, o, n)                                            \
 498   ({                                                                    \
 499         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 500         cmpxchg((ptr), (o), (n));                                       \
 501   })
 502 #define cmpxchg64_local(ptr, o, n)                                      \
 503   ({                                                                    \
 504         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 505         cmpxchg_local((ptr), (o), (n));                                 \
 506   })
 507 #else
 508 #include <asm-generic/cmpxchg-local.h>
 509 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 510 #endif
 511
 512 #define arch_align_stack(x) (x)
 513
 514 /* Used in very early kernel initialization. */
 515 extern unsigned long reloc_offset(void);
 516 extern unsigned long add_reloc_offset(unsigned long);
 517 extern void reloc_got2(unsigned long);
 518
 519 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 520
 521 static inline void create_instruction(unsigned long addr, unsigned int instr)
 522 {
 523         unsigned int *p;
 524         p  = (unsigned int *)addr;
 525         *p = instr;
 526         asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
 527 }
 528
 529 /* Flags for create_branch:
 530  * "b"   == create_branch(addr, target, 0);
 531  * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
 532  * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
 533  * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
 534  */
 535 #define BRANCH_SET_LINK 0x1
 536 #define BRANCH_ABSOLUTE 0x2
 537
 538 static inline void create_branch(unsigned long addr,
 539                 unsigned long target, int flags)
 540 {
 541         unsigned int instruction;
 542
 543         if (! (flags & BRANCH_ABSOLUTE))
 544                 target = target - addr;
 545
 546         /* Mask out the flags and target, so they don't step on each other. */
 547         instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
 548
 549         create_instruction(addr, instruction);
 550 }
 551
 552 static inline void create_function_call(unsigned long addr, void * func)
 553 {
 554         unsigned long func_addr;
 555
 556 #ifdef CONFIG_PPC64
 557         /*
 558          * On PPC64 the function pointer actually points to the function's
 559          * descriptor. The first entry in the descriptor is the address
 560          * of the function text.
 561          */
 562         func_addr = *(unsigned long *)func;
 563 #else
 564         func_addr = (unsigned long)func;
 565 #endif
 566         create_branch(addr, func_addr, BRANCH_SET_LINK);
 567 }
 568
 569 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 570 extern void account_system_vtime(struct task_struct *);
 571 #endif
 572
 573 extern struct dentry *powerpc_debugfs_root;
 574
 575 #endif /* __KERNEL__ */
 576 #endif /* _ASM_POWERPC_SYSTEM_H */