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sh: Enable use of the clk fwk on SH-5.
[linux-2.6/verdex.git] / drivers / serial / sh-sci.c
blob0a051bca01c74f168a3662a6bc9875c60fd081be
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49
50 #ifdef CONFIG_SUPERH
51 #include <asm/clock.h>
52 #include <asm/sh_bios.h>
53 #include <asm/kgdb.h>
54 #endif
55
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 #ifdef CONFIG_SUPERH
82 /* Port clock */
83 struct clk *clk;
84 #endif
85 };
86
87 #ifdef CONFIG_SH_KGDB
88 static struct sci_port *kgdb_sci_port;
89 #endif
90
91 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
92 static struct sci_port *serial_console_port;
93 #endif
94
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port *port);
97
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
99
100 static struct sci_port sci_ports[SCI_NPORTS];
101 static struct uart_driver sci_uart_driver;
102
103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
104 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
105 static inline void handle_error(struct uart_port *port)
106 {
107 /* Clear error flags */
108 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
109 }
110
111 static int get_char(struct uart_port *port)
112 {
113 unsigned long flags;
114 unsigned short status;
115 int c;
116
117 spin_lock_irqsave(&port->lock, flags);
118 do {
119 status = sci_in(port, SCxSR);
120 if (status & SCxSR_ERRORS(port)) {
121 handle_error(port);
122 continue;
123 }
124 } while (!(status & SCxSR_RDxF(port)));
125 c = sci_in(port, SCxRDR);
126 sci_in(port, SCxSR); /* Dummy read */
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128 spin_unlock_irqrestore(&port->lock, flags);
129
130 return c;
131 }
132 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
133
134 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
135 static void put_char(struct uart_port *port, char c)
136 {
137 unsigned long flags;
138 unsigned short status;
139
140 spin_lock_irqsave(&port->lock, flags);
141
142 do {
143 status = sci_in(port, SCxSR);
144 } while (!(status & SCxSR_TDxE(port)));
145
146 sci_out(port, SCxTDR, c);
147 sci_in(port, SCxSR); /* Dummy read */
148 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
149
150 spin_unlock_irqrestore(&port->lock, flags);
151 }
152 #endif
153
154 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
155 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
156 {
157 struct uart_port *port = &sci_port->port;
158 const unsigned char *p = buffer;
159 int i;
160
161 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
162 int checksum;
163 int usegdb=0;
164
165 #ifdef CONFIG_SH_STANDARD_BIOS
166 /* This call only does a trap the first time it is
167 * called, and so is safe to do here unconditionally
168 */
169 usegdb |= sh_bios_in_gdb_mode();
170 #endif
171 #ifdef CONFIG_SH_KGDB
172 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
173 #endif
174
175 if (usegdb) {
176 /* $<packet info>#<checksum>. */
177 do {
178 unsigned char c;
179 put_char(port, '$');
180 put_char(port, 'O'); /* 'O'utput to console */
181 checksum = 'O';
182
183 for (i=0; i<count; i++) { /* Don't use run length encoding */
184 int h, l;
185
186 c = *p++;
187 h = highhex(c);
188 l = lowhex(c);
189 put_char(port, h);
190 put_char(port, l);
191 checksum += h + l;
192 }
193 put_char(port, '#');
194 put_char(port, highhex(checksum));
195 put_char(port, lowhex(checksum));
196 } while (get_char(port) != '+');
197 } else
198 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
199 for (i=0; i<count; i++) {
200 if (*p == 10)
201 put_char(port, '\r');
202 put_char(port, *p++);
203 }
204 }
205 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
206
207 #ifdef CONFIG_SH_KGDB
208 static int kgdb_sci_getchar(void)
209 {
210 int c;
211
212 /* Keep trying to read a character, this could be neater */
213 while ((c = get_char(&kgdb_sci_port->port)) < 0)
214 cpu_relax();
215
216 return c;
217 }
218
219 static inline void kgdb_sci_putchar(int c)
220 {
221 put_char(&kgdb_sci_port->port, c);
222 }
223 #endif /* CONFIG_SH_KGDB */
224
225 #if defined(__H8300S__)
226 enum { sci_disable, sci_enable };
227
228 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
229 {
230 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
231 int ch = (port->mapbase - SMR0) >> 3;
232 unsigned char mask = 1 << (ch+1);
233
234 if (ctrl == sci_disable) {
235 *mstpcrl |= mask;
236 } else {
237 *mstpcrl &= ~mask;
238 }
239 }
240
241 static inline void h8300_sci_enable(struct uart_port *port)
242 {
243 h8300_sci_config(port, sci_enable);
244 }
245
246 static inline void h8300_sci_disable(struct uart_port *port)
247 {
248 h8300_sci_config(port, sci_disable);
249 }
250 #endif
251
252 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
253 defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
255 {
256 int ch = (port->mapbase - SMR0) >> 3;
257
258 /* set DDR regs */
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].rx,
261 H8300_GPIO_INPUT);
262 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
263 h8300_sci_pins[ch].tx,
264 H8300_GPIO_OUTPUT);
265
266 /* tx mark output*/
267 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
268 }
269 #else
270 #define sci_init_pins_sci NULL
271 #endif
272
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
275 {
276 unsigned int fcr_val = 0;
277
278 if (cflag & CRTSCTS)
279 fcr_val |= SCFCR_MCE;
280
281 sci_out(port, SCFCR, fcr_val);
282 }
283 #else
284 #define sci_init_pins_irda NULL
285 #endif
286
287 #ifdef SCI_ONLY
288 #define sci_init_pins_scif NULL
289 #endif
290
291 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
293 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
294 {
295 unsigned int fcr_val = 0;
296
297 set_sh771x_scif_pfc(port);
298 if (cflag & CRTSCTS) {
299 fcr_val |= SCFCR_MCE;
300 }
301 sci_out(port, SCFCR, fcr_val);
302 }
303 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
304 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
305 {
306 unsigned int fcr_val = 0;
307 unsigned short data;
308
309 if (cflag & CRTSCTS) {
310 /* enable RTS/CTS */
311 if (port->mapbase == 0xa4430000) { /* SCIF0 */
312 /* Clear PTCR bit 9-2; enable all scif pins but sck */
313 data = ctrl_inw(PORT_PTCR);
314 ctrl_outw((data & 0xfc03), PORT_PTCR);
315 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
316 /* Clear PVCR bit 9-2 */
317 data = ctrl_inw(PORT_PVCR);
318 ctrl_outw((data & 0xfc03), PORT_PVCR);
319 }
320 fcr_val |= SCFCR_MCE;
321 } else {
322 if (port->mapbase == 0xa4430000) { /* SCIF0 */
323 /* Clear PTCR bit 5-2; enable only tx and rx */
324 data = ctrl_inw(PORT_PTCR);
325 ctrl_outw((data & 0xffc3), PORT_PTCR);
326 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
327 /* Clear PVCR bit 5-2 */
328 data = ctrl_inw(PORT_PVCR);
329 ctrl_outw((data & 0xffc3), PORT_PVCR);
330 }
331 }
332 sci_out(port, SCFCR, fcr_val);
333 }
334 #elif defined(CONFIG_CPU_SH3)
335 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
337 {
338 unsigned int fcr_val = 0;
339 unsigned short data;
340
341 /* We need to set SCPCR to enable RTS/CTS */
342 data = ctrl_inw(SCPCR);
343 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
344 ctrl_outw(data & 0x0fcf, SCPCR);
345
346 if (cflag & CRTSCTS)
347 fcr_val |= SCFCR_MCE;
348 else {
349 /* We need to set SCPCR to enable RTS/CTS */
350 data = ctrl_inw(SCPCR);
351 /* Clear out SCP7MD1,0, SCP4MD1,0,
352 Set SCP6MD1,0 = {01} (output) */
353 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
354
355 data = ctrl_inb(SCPDR);
356 /* Set /RTS2 (bit6) = 0 */
357 ctrl_outb(data & 0xbf, SCPDR);
358 }
359
360 sci_out(port, SCFCR, fcr_val);
361 }
362 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
363 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
364 {
365 unsigned int fcr_val = 0;
366
367 if (cflag & CRTSCTS) {
368 fcr_val |= SCFCR_MCE;
369
370 ctrl_outw(0x0000, PORT_PSCR);
371 } else {
372 unsigned short data;
373
374 data = ctrl_inw(PORT_PSCR);
375 data &= 0x033f;
376 data |= 0x0400;
377 ctrl_outw(data, PORT_PSCR);
378
379 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
380 }
381
382 sci_out(port, SCFCR, fcr_val);
383 }
384 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
385 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
386 {
387 /* Nothing to do here.. */
388 sci_out(port, SCFCR, 0);
389 }
390 #else
391 /* For SH7750 */
392 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
393 {
394 unsigned int fcr_val = 0;
395
396 if (cflag & CRTSCTS) {
397 fcr_val |= SCFCR_MCE;
398 } else {
399 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
400 /* Nothing */
401 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
402 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
403 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
404 defined(CONFIG_CPU_SUBTYPE_SHX3)
405 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
406 #else
407 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
408 #endif
409 }
410 sci_out(port, SCFCR, fcr_val);
411 }
412 #endif
413
414 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
416 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
417 defined(CONFIG_CPU_SUBTYPE_SH7785)
418 static inline int scif_txroom(struct uart_port *port)
419 {
420 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
421 }
422
423 static inline int scif_rxroom(struct uart_port *port)
424 {
425 return sci_in(port, SCRFDR) & 0xff;
426 }
427 #else
428 static inline int scif_txroom(struct uart_port *port)
429 {
430 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
431 }
432
433 static inline int scif_rxroom(struct uart_port *port)
434 {
435 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
436 }
437 #endif
438 #endif /* SCIF_ONLY || SCI_AND_SCIF */
439
440 static inline int sci_txroom(struct uart_port *port)
441 {
442 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
443 }
444
445 static inline int sci_rxroom(struct uart_port *port)
446 {
447 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
448 }
449
450 /* ********************************************************************** *
451 * the interrupt related routines *
452 * ********************************************************************** */
453
454 static void sci_transmit_chars(struct uart_port *port)
455 {
456 struct circ_buf *xmit = &port->info->xmit;
457 unsigned int stopped = uart_tx_stopped(port);
458 unsigned short status;
459 unsigned short ctrl;
460 int count;
461
462 status = sci_in(port, SCxSR);
463 if (!(status & SCxSR_TDxE(port))) {
464 ctrl = sci_in(port, SCSCR);
465 if (uart_circ_empty(xmit)) {
466 ctrl &= ~SCI_CTRL_FLAGS_TIE;
467 } else {
468 ctrl |= SCI_CTRL_FLAGS_TIE;
469 }
470 sci_out(port, SCSCR, ctrl);
471 return;
472 }
473
474 #ifndef SCI_ONLY
475 if (port->type == PORT_SCIF)
476 count = scif_txroom(port);
477 else
478 #endif
479 count = sci_txroom(port);
480
481 do {
482 unsigned char c;
483
484 if (port->x_char) {
485 c = port->x_char;
486 port->x_char = 0;
487 } else if (!uart_circ_empty(xmit) && !stopped) {
488 c = xmit->buf[xmit->tail];
489 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
490 } else {
491 break;
492 }
493
494 sci_out(port, SCxTDR, c);
495
496 port->icount.tx++;
497 } while (--count > 0);
498
499 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
500
501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
502 uart_write_wakeup(port);
503 if (uart_circ_empty(xmit)) {
504 sci_stop_tx(port);
505 } else {
506 ctrl = sci_in(port, SCSCR);
507
508 #if !defined(SCI_ONLY)
509 if (port->type == PORT_SCIF) {
510 sci_in(port, SCxSR); /* Dummy read */
511 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
512 }
513 #endif
514
515 ctrl |= SCI_CTRL_FLAGS_TIE;
516 sci_out(port, SCSCR, ctrl);
517 }
518 }
519
520 /* On SH3, SCIF may read end-of-break as a space->mark char */
521 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
522
523 static inline void sci_receive_chars(struct uart_port *port)
524 {
525 struct sci_port *sci_port = (struct sci_port *)port;
526 struct tty_struct *tty = port->info->tty;
527 int i, count, copied = 0;
528 unsigned short status;
529 unsigned char flag;
530
531 status = sci_in(port, SCxSR);
532 if (!(status & SCxSR_RDxF(port)))
533 return;
534
535 while (1) {
536 #if !defined(SCI_ONLY)
537 if (port->type == PORT_SCIF)
538 count = scif_rxroom(port);
539 else
540 #endif
541 count = sci_rxroom(port);
542
543 /* Don't copy more bytes than there is room for in the buffer */
544 count = tty_buffer_request_room(tty, count);
545
546 /* If for any reason we can't copy more data, we're done! */
547 if (count == 0)
548 break;
549
550 if (port->type == PORT_SCI) {
551 char c = sci_in(port, SCxRDR);
552 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
553 count = 0;
554 else {
555 tty_insert_flip_char(tty, c, TTY_NORMAL);
556 }
557 } else {
558 for (i=0; i<count; i++) {
559 char c = sci_in(port, SCxRDR);
560 status = sci_in(port, SCxSR);
561 #if defined(CONFIG_CPU_SH3)
562 /* Skip "chars" during break */
563 if (sci_port->break_flag) {
564 if ((c == 0) &&
565 (status & SCxSR_FER(port))) {
566 count--; i--;
567 continue;
568 }
569
570 /* Nonzero => end-of-break */
571 pr_debug("scif: debounce<%02x>\n", c);
572 sci_port->break_flag = 0;
573
574 if (STEPFN(c)) {
575 count--; i--;
576 continue;
577 }
578 }
579 #endif /* CONFIG_CPU_SH3 */
580 if (uart_handle_sysrq_char(port, c)) {
581 count--; i--;
582 continue;
583 }
584
585 /* Store data and status */
586 if (status&SCxSR_FER(port)) {
587 flag = TTY_FRAME;
588 pr_debug("sci: frame error\n");
589 } else if (status&SCxSR_PER(port)) {
590 flag = TTY_PARITY;
591 pr_debug("sci: parity error\n");
592 } else
593 flag = TTY_NORMAL;
594 tty_insert_flip_char(tty, c, flag);
595 }
596 }
597
598 sci_in(port, SCxSR); /* dummy read */
599 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
600
601 copied += count;
602 port->icount.rx += count;
603 }
604
605 if (copied) {
606 /* Tell the rest of the system the news. New characters! */
607 tty_flip_buffer_push(tty);
608 } else {
609 sci_in(port, SCxSR); /* dummy read */
610 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
611 }
612 }
613
614 #define SCI_BREAK_JIFFIES (HZ/20)
615 /* The sci generates interrupts during the break,
616 * 1 per millisecond or so during the break period, for 9600 baud.
617 * So dont bother disabling interrupts.
618 * But dont want more than 1 break event.
619 * Use a kernel timer to periodically poll the rx line until
620 * the break is finished.
621 */
622 static void sci_schedule_break_timer(struct sci_port *port)
623 {
624 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
625 add_timer(&port->break_timer);
626 }
627 /* Ensure that two consecutive samples find the break over. */
628 static void sci_break_timer(unsigned long data)
629 {
630 struct sci_port *port = (struct sci_port *)data;
631
632 if (sci_rxd_in(&port->port) == 0) {
633 port->break_flag = 1;
634 sci_schedule_break_timer(port);
635 } else if (port->break_flag == 1) {
636 /* break is over. */
637 port->break_flag = 2;
638 sci_schedule_break_timer(port);
639 } else
640 port->break_flag = 0;
641 }
642
643 static inline int sci_handle_errors(struct uart_port *port)
644 {
645 int copied = 0;
646 unsigned short status = sci_in(port, SCxSR);
647 struct tty_struct *tty = port->info->tty;
648
649 if (status & SCxSR_ORER(port)) {
650 /* overrun error */
651 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
652 copied++;
653 pr_debug("sci: overrun error\n");
654 }
655
656 if (status & SCxSR_FER(port)) {
657 if (sci_rxd_in(port) == 0) {
658 /* Notify of BREAK */
659 struct sci_port *sci_port = (struct sci_port *)port;
660
661 if (!sci_port->break_flag) {
662 sci_port->break_flag = 1;
663 sci_schedule_break_timer(sci_port);
664
665 /* Do sysrq handling. */
666 if (uart_handle_break(port))
667 return 0;
668 pr_debug("sci: BREAK detected\n");
669 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
670 copied++;
671 }
672 } else {
673 /* frame error */
674 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
675 copied++;
676 pr_debug("sci: frame error\n");
677 }
678 }
679
680 if (status & SCxSR_PER(port)) {
681 /* parity error */
682 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
683 copied++;
684 pr_debug("sci: parity error\n");
685 }
686
687 if (copied)
688 tty_flip_buffer_push(tty);
689
690 return copied;
691 }
692
693 static inline int sci_handle_breaks(struct uart_port *port)
694 {
695 int copied = 0;
696 unsigned short status = sci_in(port, SCxSR);
697 struct tty_struct *tty = port->info->tty;
698 struct sci_port *s = &sci_ports[port->line];
699
700 if (uart_handle_break(port))
701 return 0;
702
703 if (!s->break_flag && status & SCxSR_BRK(port)) {
704 #if defined(CONFIG_CPU_SH3)
705 /* Debounce break */
706 s->break_flag = 1;
707 #endif
708 /* Notify of BREAK */
709 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
710 copied++;
711 pr_debug("sci: BREAK detected\n");
712 }
713
714 #if defined(SCIF_ORER)
715 /* XXX: Handle SCIF overrun error */
716 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
717 sci_out(port, SCLSR, 0);
718 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
719 copied++;
720 pr_debug("sci: overrun error\n");
721 }
722 }
723 #endif
724
725 if (copied)
726 tty_flip_buffer_push(tty);
727
728 return copied;
729 }
730
731 static irqreturn_t sci_rx_interrupt(int irq, void *port)
732 {
733 /* I think sci_receive_chars has to be called irrespective
734 * of whether the I_IXOFF is set, otherwise, how is the interrupt
735 * to be disabled?
736 */
737 sci_receive_chars(port);
738
739 return IRQ_HANDLED;
740 }
741
742 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
743 {
744 struct uart_port *port = ptr;
745
746 spin_lock_irq(&port->lock);
747 sci_transmit_chars(port);
748 spin_unlock_irq(&port->lock);
749
750 return IRQ_HANDLED;
751 }
752
753 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
754 {
755 struct uart_port *port = ptr;
756
757 /* Handle errors */
758 if (port->type == PORT_SCI) {
759 if (sci_handle_errors(port)) {
760 /* discard character in rx buffer */
761 sci_in(port, SCxSR);
762 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
763 }
764 } else {
765 #if defined(SCIF_ORER)
766 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
767 struct tty_struct *tty = port->info->tty;
768
769 sci_out(port, SCLSR, 0);
770 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
771 tty_flip_buffer_push(tty);
772 pr_debug("scif: overrun error\n");
773 }
774 #endif
775 sci_rx_interrupt(irq, ptr);
776 }
777
778 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
779
780 /* Kick the transmission */
781 sci_tx_interrupt(irq, ptr);
782
783 return IRQ_HANDLED;
784 }
785
786 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
787 {
788 struct uart_port *port = ptr;
789
790 /* Handle BREAKs */
791 sci_handle_breaks(port);
792 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
793
794 return IRQ_HANDLED;
795 }
796
797 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
798 {
799 unsigned short ssr_status, scr_status;
800 struct uart_port *port = ptr;
801
802 ssr_status = sci_in(port,SCxSR);
803 scr_status = sci_in(port,SCSCR);
804
805 /* Tx Interrupt */
806 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
807 sci_tx_interrupt(irq, ptr);
808 /* Rx Interrupt */
809 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
810 sci_rx_interrupt(irq, ptr);
811 /* Error Interrupt */
812 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
813 sci_er_interrupt(irq, ptr);
814 /* Break Interrupt */
815 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
816 sci_br_interrupt(irq, ptr);
817
818 return IRQ_HANDLED;
819 }
820
821 #ifdef CONFIG_CPU_FREQ
822 /*
823 * Here we define a transistion notifier so that we can update all of our
824 * ports' baud rate when the peripheral clock changes.
825 */
826 static int sci_notifier(struct notifier_block *self,
827 unsigned long phase, void *p)
828 {
829 struct cpufreq_freqs *freqs = p;
830 int i;
831
832 if ((phase == CPUFREQ_POSTCHANGE) ||
833 (phase == CPUFREQ_RESUMECHANGE)){
834 for (i = 0; i < SCI_NPORTS; i++) {
835 struct uart_port *port = &sci_ports[i].port;
836 struct clk *clk;
837
838 /*
839 * Update the uartclk per-port if frequency has
840 * changed, since it will no longer necessarily be
841 * consistent with the old frequency.
842 *
843 * Really we want to be able to do something like
844 * uart_change_speed() or something along those lines
845 * here to implicitly reset the per-port baud rate..
846 *
847 * Clean this up later..
848 */
849 clk = clk_get(NULL, "module_clk");
850 port->uartclk = clk_get_rate(clk) * 16;
851 clk_put(clk);
852 }
853
854 printk(KERN_INFO "%s: got a postchange notification "
855 "for cpu %d (old %d, new %d)\n",
856 __func__, freqs->cpu, freqs->old, freqs->new);
857 }
858
859 return NOTIFY_OK;
860 }
861
862 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
863 #endif /* CONFIG_CPU_FREQ */
864
865 static int sci_request_irq(struct sci_port *port)
866 {
867 int i;
868 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
869 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
870 sci_br_interrupt,
871 };
872 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
873 "SCI Transmit Data Empty", "SCI Break" };
874
875 if (port->irqs[0] == port->irqs[1]) {
876 if (!port->irqs[0]) {
877 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
878 return -ENODEV;
879 }
880
881 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
882 IRQF_DISABLED, "sci", port)) {
883 printk(KERN_ERR "sci: Cannot allocate irq.\n");
884 return -ENODEV;
885 }
886 } else {
887 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
888 if (!port->irqs[i])
889 continue;
890 if (request_irq(port->irqs[i], handlers[i],
891 IRQF_DISABLED, desc[i], port)) {
892 printk(KERN_ERR "sci: Cannot allocate irq.\n");
893 return -ENODEV;
894 }
895 }
896 }
897
898 return 0;
899 }
900
901 static void sci_free_irq(struct sci_port *port)
902 {
903 int i;
904
905 if (port->irqs[0] == port->irqs[1]) {
906 if (!port->irqs[0])
907 printk("sci: sci_free_irq error\n");
908 else
909 free_irq(port->irqs[0], port);
910 } else {
911 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
912 if (!port->irqs[i])
913 continue;
914
915 free_irq(port->irqs[i], port);
916 }
917 }
918 }
919
920 static unsigned int sci_tx_empty(struct uart_port *port)
921 {
922 /* Can't detect */
923 return TIOCSER_TEMT;
924 }
925
926 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
927 {
928 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
929 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
930 /* If you have signals for DTR and DCD, please implement here. */
931 }
932
933 static unsigned int sci_get_mctrl(struct uart_port *port)
934 {
935 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
936 and CTS/RTS */
937
938 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
939 }
940
941 static void sci_start_tx(struct uart_port *port)
942 {
943 unsigned short ctrl;
944
945 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
946 ctrl = sci_in(port, SCSCR);
947 ctrl |= SCI_CTRL_FLAGS_TIE;
948 sci_out(port, SCSCR, ctrl);
949 }
950
951 static void sci_stop_tx(struct uart_port *port)
952 {
953 unsigned short ctrl;
954
955 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
956 ctrl = sci_in(port, SCSCR);
957 ctrl &= ~SCI_CTRL_FLAGS_TIE;
958 sci_out(port, SCSCR, ctrl);
959 }
960
961 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
962 {
963 unsigned short ctrl;
964
965 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
966 ctrl = sci_in(port, SCSCR);
967 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
968 sci_out(port, SCSCR, ctrl);
969 }
970
971 static void sci_stop_rx(struct uart_port *port)
972 {
973 unsigned short ctrl;
974
975 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
976 ctrl = sci_in(port, SCSCR);
977 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
978 sci_out(port, SCSCR, ctrl);
979 }
980
981 static void sci_enable_ms(struct uart_port *port)
982 {
983 /* Nothing here yet .. */
984 }
985
986 static void sci_break_ctl(struct uart_port *port, int break_state)
987 {
988 /* Nothing here yet .. */
989 }
990
991 static int sci_startup(struct uart_port *port)
992 {
993 struct sci_port *s = &sci_ports[port->line];
994
995 if (s->enable)
996 s->enable(port);
997
998 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
999 s->clk = clk_get(NULL, "module_clk");
1000 #endif
1001
1002 sci_request_irq(s);
1003 sci_start_tx(port);
1004 sci_start_rx(port, 1);
1005
1006 return 0;
1007 }
1008
1009 static void sci_shutdown(struct uart_port *port)
1010 {
1011 struct sci_port *s = &sci_ports[port->line];
1012
1013 sci_stop_rx(port);
1014 sci_stop_tx(port);
1015 sci_free_irq(s);
1016
1017 if (s->disable)
1018 s->disable(port);
1019
1020 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1021 clk_put(s->clk);
1022 s->clk = NULL;
1023 #endif
1024 }
1025
1026 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1027 struct ktermios *old)
1028 {
1029 struct sci_port *s = &sci_ports[port->line];
1030 unsigned int status, baud, smr_val;
1031 int t;
1032
1033 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1034
1035 switch (baud) {
1036 case 0:
1037 t = -1;
1038 break;
1039 default:
1040 {
1041 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1042 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1043 #else
1044 t = SCBRR_VALUE(baud);
1045 #endif
1046 break;
1047 }
1048 }
1049
1050 do {
1051 status = sci_in(port, SCxSR);
1052 } while (!(status & SCxSR_TEND(port)));
1053
1054 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1055
1056 #if !defined(SCI_ONLY)
1057 if (port->type == PORT_SCIF)
1058 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1059 #endif
1060
1061 smr_val = sci_in(port, SCSMR) & 3;
1062 if ((termios->c_cflag & CSIZE) == CS7)
1063 smr_val |= 0x40;
1064 if (termios->c_cflag & PARENB)
1065 smr_val |= 0x20;
1066 if (termios->c_cflag & PARODD)
1067 smr_val |= 0x30;
1068 if (termios->c_cflag & CSTOPB)
1069 smr_val |= 0x08;
1070
1071 uart_update_timeout(port, termios->c_cflag, baud);
1072
1073 sci_out(port, SCSMR, smr_val);
1074
1075 if (t > 0) {
1076 if(t >= 256) {
1077 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1078 t >>= 2;
1079 } else {
1080 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1081 }
1082 sci_out(port, SCBRR, t);
1083 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1084 }
1085
1086 if (likely(s->init_pins))
1087 s->init_pins(port, termios->c_cflag);
1088
1089 sci_out(port, SCSCR, SCSCR_INIT(port));
1090
1091 if ((termios->c_cflag & CREAD) != 0)
1092 sci_start_rx(port,0);
1093 }
1094
1095 static const char *sci_type(struct uart_port *port)
1096 {
1097 switch (port->type) {
1098 case PORT_SCI: return "sci";
1099 case PORT_SCIF: return "scif";
1100 case PORT_IRDA: return "irda";
1101 }
1102
1103 return 0;
1104 }
1105
1106 static void sci_release_port(struct uart_port *port)
1107 {
1108 /* Nothing here yet .. */
1109 }
1110
1111 static int sci_request_port(struct uart_port *port)
1112 {
1113 /* Nothing here yet .. */
1114 return 0;
1115 }
1116
1117 static void sci_config_port(struct uart_port *port, int flags)
1118 {
1119 struct sci_port *s = &sci_ports[port->line];
1120
1121 port->type = s->type;
1122
1123 switch (port->type) {
1124 case PORT_SCI:
1125 s->init_pins = sci_init_pins_sci;
1126 break;
1127 case PORT_SCIF:
1128 s->init_pins = sci_init_pins_scif;
1129 break;
1130 case PORT_IRDA:
1131 s->init_pins = sci_init_pins_irda;
1132 break;
1133 }
1134
1135 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1136 if (port->mapbase == 0)
1137 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1138
1139 port->membase = (void __iomem *)port->mapbase;
1140 #endif
1141 }
1142
1143 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1144 {
1145 struct sci_port *s = &sci_ports[port->line];
1146
1147 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1148 return -EINVAL;
1149 if (ser->baud_base < 2400)
1150 /* No paper tape reader for Mitch.. */
1151 return -EINVAL;
1152
1153 return 0;
1154 }
1155
1156 static struct uart_ops sci_uart_ops = {
1157 .tx_empty = sci_tx_empty,
1158 .set_mctrl = sci_set_mctrl,
1159 .get_mctrl = sci_get_mctrl,
1160 .start_tx = sci_start_tx,
1161 .stop_tx = sci_stop_tx,
1162 .stop_rx = sci_stop_rx,
1163 .enable_ms = sci_enable_ms,
1164 .break_ctl = sci_break_ctl,
1165 .startup = sci_startup,
1166 .shutdown = sci_shutdown,
1167 .set_termios = sci_set_termios,
1168 .type = sci_type,
1169 .release_port = sci_release_port,
1170 .request_port = sci_request_port,
1171 .config_port = sci_config_port,
1172 .verify_port = sci_verify_port,
1173 };
1174
1175 static void __init sci_init_ports(void)
1176 {
1177 static int first = 1;
1178 int i;
1179
1180 if (!first)
1181 return;
1182
1183 first = 0;
1184
1185 for (i = 0; i < SCI_NPORTS; i++) {
1186 sci_ports[i].port.ops = &sci_uart_ops;
1187 sci_ports[i].port.iotype = UPIO_MEM;
1188 sci_ports[i].port.line = i;
1189 sci_ports[i].port.fifosize = 1;
1190
1191 #if defined(__H8300H__) || defined(__H8300S__)
1192 #ifdef __H8300S__
1193 sci_ports[i].enable = h8300_sci_enable;
1194 sci_ports[i].disable = h8300_sci_disable;
1195 #endif
1196 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1197 #elif defined(CONFIG_SUPERH64)
1198 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1199 #else
1200 /*
1201 * XXX: We should use a proper SCI/SCIF clock
1202 */
1203 {
1204 struct clk *clk = clk_get(NULL, "module_clk");
1205 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1206 clk_put(clk);
1207 }
1208 #endif
1209
1210 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1211 sci_ports[i].break_timer.function = sci_break_timer;
1212
1213 init_timer(&sci_ports[i].break_timer);
1214 }
1215 }
1216
1217 int __init early_sci_setup(struct uart_port *port)
1218 {
1219 if (unlikely(port->line > SCI_NPORTS))
1220 return -ENODEV;
1221
1222 sci_init_ports();
1223
1224 sci_ports[port->line].port.membase = port->membase;
1225 sci_ports[port->line].port.mapbase = port->mapbase;
1226 sci_ports[port->line].port.type = port->type;
1227
1228 return 0;
1229 }
1230
1231 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1232 /*
1233 * Print a string to the serial port trying not to disturb
1234 * any possible real use of the port...
1235 */
1236 static void serial_console_write(struct console *co, const char *s,
1237 unsigned count)
1238 {
1239 put_string(serial_console_port, s, count);
1240 }
1241
1242 static int __init serial_console_setup(struct console *co, char *options)
1243 {
1244 struct uart_port *port;
1245 int baud = 115200;
1246 int bits = 8;
1247 int parity = 'n';
1248 int flow = 'n';
1249 int ret;
1250
1251 /*
1252 * Check whether an invalid uart number has been specified, and
1253 * if so, search for the first available port that does have
1254 * console support.
1255 */
1256 if (co->index >= SCI_NPORTS)
1257 co->index = 0;
1258
1259 serial_console_port = &sci_ports[co->index];
1260 port = &serial_console_port->port;
1261
1262 /*
1263 * Also need to check port->type, we don't actually have any
1264 * UPIO_PORT ports, but uart_report_port() handily misreports
1265 * it anyways if we don't have a port available by the time this is
1266 * called.
1267 */
1268 if (!port->type)
1269 return -ENODEV;
1270 if (!port->membase || !port->mapbase)
1271 return -ENODEV;
1272
1273 port->type = serial_console_port->type;
1274
1275 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1276 if (!serial_console_port->clk)
1277 serial_console_port->clk = clk_get(NULL, "module_clk");
1278 #endif
1279
1280 if (port->flags & UPF_IOREMAP)
1281 sci_config_port(port, 0);
1282
1283 if (serial_console_port->enable)
1284 serial_console_port->enable(port);
1285
1286 if (options)
1287 uart_parse_options(options, &baud, &parity, &bits, &flow);
1288
1289 ret = uart_set_options(port, co, baud, parity, bits, flow);
1290 #if defined(__H8300H__) || defined(__H8300S__)
1291 /* disable rx interrupt */
1292 if (ret == 0)
1293 sci_stop_rx(port);
1294 #endif
1295 return ret;
1296 }
1297
1298 static struct console serial_console = {
1299 .name = "ttySC",
1300 .device = uart_console_device,
1301 .write = serial_console_write,
1302 .setup = serial_console_setup,
1303 .flags = CON_PRINTBUFFER,
1304 .index = -1,
1305 .data = &sci_uart_driver,
1306 };
1307
1308 static int __init sci_console_init(void)
1309 {
1310 sci_init_ports();
1311 register_console(&serial_console);
1312 return 0;
1313 }
1314 console_initcall(sci_console_init);
1315 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1316
1317 #ifdef CONFIG_SH_KGDB_CONSOLE
1318 /*
1319 * FIXME: Most of this can go away.. at the moment, we rely on
1320 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1321 * most of that can easily be done here instead.
1322 *
1323 * For the time being, just accept the values that were parsed earlier..
1324 */
1325 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1326 int *parity, int *bits)
1327 {
1328 *baud = kgdb_baud;
1329 *parity = tolower(kgdb_parity);
1330 *bits = kgdb_bits - '0';
1331 }
1332
1333 /*
1334 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1335 * care of the early-on initialization for kgdb, regardless of whether we
1336 * actually use kgdb as a console or not.
1337 *
1338 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1339 */
1340 int __init kgdb_console_setup(struct console *co, char *options)
1341 {
1342 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1343 int baud = 38400;
1344 int bits = 8;
1345 int parity = 'n';
1346 int flow = 'n';
1347
1348 if (co->index != kgdb_portnum)
1349 co->index = kgdb_portnum;
1350
1351 kgdb_sci_port = &sci_ports[co->index];
1352 port = &kgdb_sci_port->port;
1353
1354 /*
1355 * Also need to check port->type, we don't actually have any
1356 * UPIO_PORT ports, but uart_report_port() handily misreports
1357 * it anyways if we don't have a port available by the time this is
1358 * called.
1359 */
1360 if (!port->type)
1361 return -ENODEV;
1362 if (!port->membase || !port->mapbase)
1363 return -ENODEV;
1364
1365 if (options)
1366 uart_parse_options(options, &baud, &parity, &bits, &flow);
1367 else
1368 kgdb_console_get_options(port, &baud, &parity, &bits);
1369
1370 kgdb_getchar = kgdb_sci_getchar;
1371 kgdb_putchar = kgdb_sci_putchar;
1372
1373 return uart_set_options(port, co, baud, parity, bits, flow);
1374 }
1375
1376 static struct console kgdb_console = {
1377 .name = "ttySC",
1378 .device = uart_console_device,
1379 .write = kgdb_console_write,
1380 .setup = kgdb_console_setup,
1381 .flags = CON_PRINTBUFFER,
1382 .index = -1,
1383 .data = &sci_uart_driver,
1384 };
1385
1386 /* Register the KGDB console so we get messages (d'oh!) */
1387 static int __init kgdb_console_init(void)
1388 {
1389 sci_init_ports();
1390 register_console(&kgdb_console);
1391 return 0;
1392 }
1393 console_initcall(kgdb_console_init);
1394 #endif /* CONFIG_SH_KGDB_CONSOLE */
1395
1396 #if defined(CONFIG_SH_KGDB_CONSOLE)
1397 #define SCI_CONSOLE &kgdb_console
1398 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1399 #define SCI_CONSOLE &serial_console
1400 #else
1401 #define SCI_CONSOLE 0
1402 #endif
1403
1404 static char banner[] __initdata =
1405 KERN_INFO "SuperH SCI(F) driver initialized\n";
1406
1407 static struct uart_driver sci_uart_driver = {
1408 .owner = THIS_MODULE,
1409 .driver_name = "sci",
1410 .dev_name = "ttySC",
1411 .major = SCI_MAJOR,
1412 .minor = SCI_MINOR_START,
1413 .nr = SCI_NPORTS,
1414 .cons = SCI_CONSOLE,
1415 };
1416
1417 /*
1418 * Register a set of serial devices attached to a platform device. The
1419 * list is terminated with a zero flags entry, which means we expect
1420 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1421 * remapping (such as sh64) should also set UPF_IOREMAP.
1422 */
1423 static int __devinit sci_probe(struct platform_device *dev)
1424 {
1425 struct plat_sci_port *p = dev->dev.platform_data;
1426 int i;
1427
1428 for (i = 0; p && p->flags != 0; p++, i++) {
1429 struct sci_port *sciport = &sci_ports[i];
1430
1431 /* Sanity check */
1432 if (unlikely(i == SCI_NPORTS)) {
1433 dev_notice(&dev->dev, "Attempting to register port "
1434 "%d when only %d are available.\n",
1435 i+1, SCI_NPORTS);
1436 dev_notice(&dev->dev, "Consider bumping "
1437 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1438 break;
1439 }
1440
1441 sciport->port.mapbase = p->mapbase;
1442
1443 /*
1444 * For the simple (and majority of) cases where we don't need
1445 * to do any remapping, just cast the cookie directly.
1446 */
1447 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1448 p->membase = (void __iomem *)p->mapbase;
1449
1450 sciport->port.membase = p->membase;
1451
1452 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1453 sciport->port.flags = p->flags;
1454 sciport->port.dev = &dev->dev;
1455
1456 sciport->type = sciport->port.type = p->type;
1457
1458 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1459
1460 uart_add_one_port(&sci_uart_driver, &sciport->port);
1461 }
1462
1463 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1464 kgdb_sci_port = &sci_ports[kgdb_portnum];
1465 kgdb_getchar = kgdb_sci_getchar;
1466 kgdb_putchar = kgdb_sci_putchar;
1467 #endif
1468
1469 #ifdef CONFIG_CPU_FREQ
1470 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1471 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1472 #endif
1473
1474 #ifdef CONFIG_SH_STANDARD_BIOS
1475 sh_bios_gdb_detach();
1476 #endif
1477
1478 return 0;
1479 }
1480
1481 static int __devexit sci_remove(struct platform_device *dev)
1482 {
1483 int i;
1484
1485 for (i = 0; i < SCI_NPORTS; i++)
1486 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1487
1488 return 0;
1489 }
1490
1491 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1492 {
1493 int i;
1494
1495 for (i = 0; i < SCI_NPORTS; i++) {
1496 struct sci_port *p = &sci_ports[i];
1497
1498 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1499 uart_suspend_port(&sci_uart_driver, &p->port);
1500 }
1501
1502 return 0;
1503 }
1504
1505 static int sci_resume(struct platform_device *dev)
1506 {
1507 int i;
1508
1509 for (i = 0; i < SCI_NPORTS; i++) {
1510 struct sci_port *p = &sci_ports[i];
1511
1512 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1513 uart_resume_port(&sci_uart_driver, &p->port);
1514 }
1515
1516 return 0;
1517 }
1518
1519 static struct platform_driver sci_driver = {
1520 .probe = sci_probe,
1521 .remove = __devexit_p(sci_remove),
1522 .suspend = sci_suspend,
1523 .resume = sci_resume,
1524 .driver = {
1525 .name = "sh-sci",
1526 .owner = THIS_MODULE,
1527 },
1528 };
1529
1530 static int __init sci_init(void)
1531 {
1532 int ret;
1533
1534 printk(banner);
1535
1536 sci_init_ports();
1537
1538 ret = uart_register_driver(&sci_uart_driver);
1539 if (likely(ret == 0)) {
1540 ret = platform_driver_register(&sci_driver);
1541 if (unlikely(ret))
1542 uart_unregister_driver(&sci_uart_driver);
1543 }
1544
1545 return ret;
1546 }
1547
1548 static void __exit sci_exit(void)
1549 {
1550 platform_driver_unregister(&sci_driver);
1551 uart_unregister_driver(&sci_uart_driver);
1552 }
1553
1554 module_init(sci_init);
1555 module_exit(sci_exit);
1556
1557 MODULE_LICENSE("GPL");
1558 MODULE_ALIAS("platform:sh-sci");
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