cgroups: implement namespace tracking subsystem
[linux-2.6/verdex.git] / include / asm-m68knommu / bitops.h
blobb8b2770d6870965de40edcf112b405aadd2f881e
1 #ifndef _M68KNOMMU_BITOPS_H
2 #define _M68KNOMMU_BITOPS_H
4 /*
5 * Copyright 1992, Linus Torvalds.
6 */
8 #include <linux/compiler.h>
9 #include <asm/byteorder.h> /* swab32 */
11 #ifdef __KERNEL__
13 #include <asm-generic/bitops/ffs.h>
14 #include <asm-generic/bitops/__ffs.h>
15 #include <asm-generic/bitops/sched.h>
16 #include <asm-generic/bitops/ffz.h>
18 static __inline__ void set_bit(int nr, volatile unsigned long * addr)
20 #ifdef CONFIG_COLDFIRE
21 __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)"
22 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
23 : "d" (nr)
24 : "%a0", "cc");
25 #else
26 __asm__ __volatile__ ("bset %1,%0"
27 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
28 : "di" (nr)
29 : "cc");
30 #endif
33 #define __set_bit(nr, addr) set_bit(nr, addr)
36 * clear_bit() doesn't provide any barrier for the compiler.
38 #define smp_mb__before_clear_bit() barrier()
39 #define smp_mb__after_clear_bit() barrier()
41 static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
43 #ifdef CONFIG_COLDFIRE
44 __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)"
45 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
46 : "d" (nr)
47 : "%a0", "cc");
48 #else
49 __asm__ __volatile__ ("bclr %1,%0"
50 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
51 : "di" (nr)
52 : "cc");
53 #endif
56 #define __clear_bit(nr, addr) clear_bit(nr, addr)
58 static __inline__ void change_bit(int nr, volatile unsigned long * addr)
60 #ifdef CONFIG_COLDFIRE
61 __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)"
62 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
63 : "d" (nr)
64 : "%a0", "cc");
65 #else
66 __asm__ __volatile__ ("bchg %1,%0"
67 : "+m" (((volatile char *)addr)[(nr^31) >> 3])
68 : "di" (nr)
69 : "cc");
70 #endif
73 #define __change_bit(nr, addr) change_bit(nr, addr)
75 static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
77 char retval;
79 #ifdef CONFIG_COLDFIRE
80 __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
81 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
82 : "d" (nr)
83 : "%a0");
84 #else
85 __asm__ __volatile__ ("bset %2,%1; sne %0"
86 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
87 : "di" (nr)
88 /* No clobber */);
89 #endif
91 return retval;
94 #define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
96 static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
98 char retval;
100 #ifdef CONFIG_COLDFIRE
101 __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
102 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
103 : "d" (nr)
104 : "%a0");
105 #else
106 __asm__ __volatile__ ("bclr %2,%1; sne %0"
107 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
108 : "di" (nr)
109 /* No clobber */);
110 #endif
112 return retval;
115 #define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
117 static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
119 char retval;
121 #ifdef CONFIG_COLDFIRE
122 __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0"
123 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
124 : "d" (nr)
125 : "%a0");
126 #else
127 __asm__ __volatile__ ("bchg %2,%1; sne %0"
128 : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
129 : "di" (nr)
130 /* No clobber */);
131 #endif
133 return retval;
136 #define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr)
139 * This routine doesn't need to be atomic.
141 static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr)
143 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
146 static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
148 int * a = (int *) addr;
149 int mask;
151 a += nr >> 5;
152 mask = 1 << (nr & 0x1f);
153 return ((mask & *a) != 0);
156 #define test_bit(nr,addr) \
157 (__builtin_constant_p(nr) ? \
158 __constant_test_bit((nr),(addr)) : \
159 __test_bit((nr),(addr)))
161 #include <asm-generic/bitops/find.h>
162 #include <asm-generic/bitops/hweight.h>
163 #include <asm-generic/bitops/lock.h>
165 static __inline__ int ext2_set_bit(int nr, volatile void * addr)
167 char retval;
169 #ifdef CONFIG_COLDFIRE
170 __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
171 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
172 : "d" (nr)
173 : "%a0");
174 #else
175 __asm__ __volatile__ ("bset %2,%1; sne %0"
176 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
177 : "di" (nr)
178 /* No clobber */);
179 #endif
181 return retval;
184 static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
186 char retval;
188 #ifdef CONFIG_COLDFIRE
189 __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
190 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
191 : "d" (nr)
192 : "%a0");
193 #else
194 __asm__ __volatile__ ("bclr %2,%1; sne %0"
195 : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
196 : "di" (nr)
197 /* No clobber */);
198 #endif
200 return retval;
203 #define ext2_set_bit_atomic(lock, nr, addr) \
204 ({ \
205 int ret; \
206 spin_lock(lock); \
207 ret = ext2_set_bit((nr), (addr)); \
208 spin_unlock(lock); \
209 ret; \
212 #define ext2_clear_bit_atomic(lock, nr, addr) \
213 ({ \
214 int ret; \
215 spin_lock(lock); \
216 ret = ext2_clear_bit((nr), (addr)); \
217 spin_unlock(lock); \
218 ret; \
221 static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
223 char retval;
225 #ifdef CONFIG_COLDFIRE
226 __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0"
227 : "=d" (retval)
228 : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr)
229 : "%a0");
230 #else
231 __asm__ __volatile__ ("btst %2,%1; sne %0"
232 : "=d" (retval)
233 : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr)
234 /* No clobber */);
235 #endif
237 return retval;
240 #define ext2_find_first_zero_bit(addr, size) \
241 ext2_find_next_zero_bit((addr), (size), 0)
243 static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
245 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
246 unsigned long result = offset & ~31UL;
247 unsigned long tmp;
249 if (offset >= size)
250 return size;
251 size -= result;
252 offset &= 31UL;
253 if(offset) {
254 /* We hold the little endian value in tmp, but then the
255 * shift is illegal. So we could keep a big endian value
256 * in tmp, like this:
258 * tmp = __swab32(*(p++));
259 * tmp |= ~0UL >> (32-offset);
261 * but this would decrease preformance, so we change the
262 * shift:
264 tmp = *(p++);
265 tmp |= __swab32(~0UL >> (32-offset));
266 if(size < 32)
267 goto found_first;
268 if(~tmp)
269 goto found_middle;
270 size -= 32;
271 result += 32;
273 while(size & ~31UL) {
274 if(~(tmp = *(p++)))
275 goto found_middle;
276 result += 32;
277 size -= 32;
279 if(!size)
280 return result;
281 tmp = *p;
283 found_first:
284 /* tmp is little endian, so we would have to swab the shift,
285 * see above. But then we have to swab tmp below for ffz, so
286 * we might as well do this here.
288 return result + ffz(__swab32(tmp) | (~0UL << size));
289 found_middle:
290 return result + ffz(__swab32(tmp));
293 #include <asm-generic/bitops/minix.h>
295 #endif /* __KERNEL__ */
297 #include <asm-generic/bitops/fls.h>
298 #include <asm-generic/bitops/fls64.h>
300 #endif /* _M68KNOMMU_BITOPS_H */