?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sparc: unify ipcbuf.h
[linux-2.6/verdex.git] / drivers / net / bnx2x.h
blobfd705d1295a7b0ea78c27d79a905b5d21ba165cf
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 /* error/debug prints */
24
25 #define DRV_MODULE_NAME "bnx2x"
26 #define PFX DRV_MODULE_NAME ": "
27
28 /* for messages that are currently off */
29 #define BNX2X_MSG_OFF 0
30 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
31 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
32 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
33 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
34 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
35 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
36
37 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
38
39 /* regular debug print */
40 #define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \
42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
43 bp->dev ? (bp->dev->name) : "?", ##__args); \
44 } while (0)
45
46 /* errors debug print */
47 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev ? (bp->dev->name) : "?", ##__args); \
51 } while (0)
52
53 /* for errors (never masked) */
54 #define BNX2X_ERR(__fmt, __args...) do { \
55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
56 bp->dev ? (bp->dev->name) : "?", ##__args); \
57 } while (0)
58
59 /* before we have a dev->name use dev_info() */
60 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
61 if (bp->msglevel & NETIF_MSG_PROBE) \
62 dev_info(&bp->pdev->dev, __fmt, ##__args); \
63 } while (0)
64
65
66 #ifdef BNX2X_STOP_ON_ERROR
67 #define bnx2x_panic() do { \
68 bp->panic = 1; \
69 BNX2X_ERR("driver assert\n"); \
70 bnx2x_int_disable(bp); \
71 bnx2x_panic_dump(bp); \
72 } while (0)
73 #else
74 #define bnx2x_panic() do { \
75 BNX2X_ERR("driver assert\n"); \
76 bnx2x_panic_dump(bp); \
77 } while (0)
78 #endif
79
80
81 #ifdef NETIF_F_HW_VLAN_TX
82 #define BCM_VLAN 1
83 #endif
84
85
86 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
88 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
89
90
91 #define REG_ADDR(bp, offset) (bp->regview + offset)
92
93 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95 #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
98 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
99 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
100 #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
101
102 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
104
105 #define REG_RD_DMAE(bp, offset, valp, len32) \
106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
110
111 #define REG_WR_DMAE(bp, offset, valp, len32) \
112 do { \
113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
115 offset, len32); \
116 } while (0)
117
118 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
119 offsetof(struct shmem_region, field))
120 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122
123 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125
126
127 /* fast path */
128
129 struct sw_rx_bd {
130 struct sk_buff *skb;
131 DECLARE_PCI_UNMAP_ADDR(mapping)
132 };
133
134 struct sw_tx_bd {
135 struct sk_buff *skb;
136 u16 first_bd;
137 };
138
139 struct sw_rx_page {
140 struct page *page;
141 DECLARE_PCI_UNMAP_ADDR(mapping)
142 };
143
144
145 /* MC hsi */
146 #define BCM_PAGE_SHIFT 12
147 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
148 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
149 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
150
151 #define PAGES_PER_SGE_SHIFT 0
152 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
153
154 #define BCM_RX_ETH_PAYLOAD_ALIGN 64
155
156 /* SGE ring related macros */
157 #define NUM_RX_SGE_PAGES 2
158 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
159 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
160 /* RX_SGE_CNT is promised to be a power of 2 */
161 #define RX_SGE_MASK (RX_SGE_CNT - 1)
162 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
163 #define MAX_RX_SGE (NUM_RX_SGE - 1)
164 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
165 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
166 #define RX_SGE(x) ((x) & MAX_RX_SGE)
167
168 /* SGE producer mask related macros */
169 /* Number of bits in one sge_mask array element */
170 #define RX_SGE_MASK_ELEM_SZ 64
171 #define RX_SGE_MASK_ELEM_SHIFT 6
172 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
173
174 /* Creates a bitmask of all ones in less significant bits.
175 idx - index of the most significant bit in the created mask */
176 #define RX_SGE_ONES_MASK(idx) \
177 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
178 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
179
180 /* Number of u64 elements in SGE mask array */
181 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
182 RX_SGE_MASK_ELEM_SZ)
183 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
184 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
185
186
187 struct bnx2x_fastpath {
188
189 struct napi_struct napi;
190
191 struct host_status_block *status_blk;
192 dma_addr_t status_blk_mapping;
193
194 struct eth_tx_db_data *hw_tx_prods;
195 dma_addr_t tx_prods_mapping;
196
197 struct sw_tx_bd *tx_buf_ring;
198
199 struct eth_tx_bd *tx_desc_ring;
200 dma_addr_t tx_desc_mapping;
201
202 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
203 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
204
205 struct eth_rx_bd *rx_desc_ring;
206 dma_addr_t rx_desc_mapping;
207
208 union eth_rx_cqe *rx_comp_ring;
209 dma_addr_t rx_comp_mapping;
210
211 /* SGE ring */
212 struct eth_rx_sge *rx_sge_ring;
213 dma_addr_t rx_sge_mapping;
214
215 u64 sge_mask[RX_SGE_MASK_LEN];
216
217 int state;
218 #define BNX2X_FP_STATE_CLOSED 0
219 #define BNX2X_FP_STATE_IRQ 0x80000
220 #define BNX2X_FP_STATE_OPENING 0x90000
221 #define BNX2X_FP_STATE_OPEN 0xa0000
222 #define BNX2X_FP_STATE_HALTING 0xb0000
223 #define BNX2X_FP_STATE_HALTED 0xc0000
224
225 u8 index; /* number in fp array */
226 u8 cl_id; /* eth client id */
227 u8 sb_id; /* status block number in HW */
228 #define FP_IDX(fp) (fp->index)
229 #define FP_CL_ID(fp) (fp->cl_id)
230 #define BP_CL_ID(bp) (bp->fp[0].cl_id)
231 #define FP_SB_ID(fp) (fp->sb_id)
232 #define CNIC_SB_ID 0
233
234 u16 tx_pkt_prod;
235 u16 tx_pkt_cons;
236 u16 tx_bd_prod;
237 u16 tx_bd_cons;
238 u16 *tx_cons_sb;
239
240 u16 fp_c_idx;
241 u16 fp_u_idx;
242
243 u16 rx_bd_prod;
244 u16 rx_bd_cons;
245 u16 rx_comp_prod;
246 u16 rx_comp_cons;
247 u16 rx_sge_prod;
248 /* The last maximal completed SGE */
249 u16 last_max_sge;
250 u16 *rx_cons_sb;
251 u16 *rx_bd_cons_sb;
252
253 unsigned long tx_pkt,
254 rx_pkt,
255 rx_calls;
256 /* TPA related */
257 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
258 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
259 #define BNX2X_TPA_START 1
260 #define BNX2X_TPA_STOP 2
261 u8 disable_tpa;
262 #ifdef BNX2X_STOP_ON_ERROR
263 u64 tpa_queue_used;
264 #endif
265
266 struct bnx2x *bp; /* parent */
267 };
268
269 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
270
271 #define BNX2X_HAS_TX_WORK(fp) \
272 ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
273 (fp->tx_pkt_prod != fp->tx_pkt_cons))
274
275 #define BNX2X_HAS_RX_WORK(fp) \
276 (fp->rx_comp_cons != rx_cons_sb)
277
278 #define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
279
280
281 /* MC hsi */
282 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
283 #define RX_COPY_THRESH 92
284
285 #define NUM_TX_RINGS 16
286 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
287 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
288 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
289 #define MAX_TX_BD (NUM_TX_BD - 1)
290 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
291 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
292 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
293 #define TX_BD(x) ((x) & MAX_TX_BD)
294 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
295
296 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
297 #define NUM_RX_RINGS 8
298 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
299 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
300 #define RX_DESC_MASK (RX_DESC_CNT - 1)
301 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
302 #define MAX_RX_BD (NUM_RX_BD - 1)
303 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
304 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
305 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
306 #define RX_BD(x) ((x) & MAX_RX_BD)
307
308 /* As long as CQE is 4 times bigger than BD entry we have to allocate
309 4 times more pages for CQ ring in order to keep it balanced with
310 BD ring */
311 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
312 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
313 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
314 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
315 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
316 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
317 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
318 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
319 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
320
321
322 /* This is needed for determining of last_max */
323 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
324
325 #define __SGE_MASK_SET_BIT(el, bit) \
326 do { \
327 el = ((el) | ((u64)0x1 << (bit))); \
328 } while (0)
329
330 #define __SGE_MASK_CLEAR_BIT(el, bit) \
331 do { \
332 el = ((el) & (~((u64)0x1 << (bit)))); \
333 } while (0)
334
335 #define SGE_MASK_SET_BIT(fp, idx) \
336 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
337 ((idx) & RX_SGE_MASK_ELEM_MASK))
338
339 #define SGE_MASK_CLEAR_BIT(fp, idx) \
340 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
341 ((idx) & RX_SGE_MASK_ELEM_MASK))
342
343
344 /* used on a CID received from the HW */
345 #define SW_CID(x) (le32_to_cpu(x) & \
346 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
347 #define CQE_CMD(x) (le32_to_cpu(x) >> \
348 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
349
350 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
351 le32_to_cpu((bd)->addr_lo))
352 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
353
354
355 #define DPM_TRIGER_TYPE 0x40
356 #define DOORBELL(bp, cid, val) \
357 do { \
358 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
359 DPM_TRIGER_TYPE); \
360 } while (0)
361
362
363 /* TX CSUM helpers */
364 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
365 skb->csum_offset)
366 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
367 skb->csum_offset))
368
369 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
370
371 #define XMIT_PLAIN 0
372 #define XMIT_CSUM_V4 0x1
373 #define XMIT_CSUM_V6 0x2
374 #define XMIT_CSUM_TCP 0x4
375 #define XMIT_GSO_V4 0x8
376 #define XMIT_GSO_V6 0x10
377
378 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
379 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
380
381
382 /* stuff added to make the code fit 80Col */
383
384 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
385
386 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
387 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
388 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
389 (TPA_TYPE_START | TPA_TYPE_END))
390
391 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
392
393 #define BNX2X_IP_CSUM_ERR(cqe) \
394 (!((cqe)->fast_path_cqe.status_flags & \
395 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
396 ((cqe)->fast_path_cqe.type_error_flags & \
397 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
398
399 #define BNX2X_L4_CSUM_ERR(cqe) \
400 (!((cqe)->fast_path_cqe.status_flags & \
401 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
402 ((cqe)->fast_path_cqe.type_error_flags & \
403 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
404
405 #define BNX2X_RX_CSUM_OK(cqe) \
406 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
407
408 #define BNX2X_RX_SUM_FIX(cqe) \
409 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
410 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
411 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
412
413
414 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
415 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
416
417 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
418 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
419 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
420
421 #define BNX2X_RX_SB_INDEX \
422 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
423
424 #define BNX2X_RX_SB_BD_INDEX \
425 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
426
427 #define BNX2X_RX_SB_INDEX_NUM \
428 (((U_SB_ETH_RX_CQ_INDEX << \
429 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
430 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
431 ((U_SB_ETH_RX_BD_INDEX << \
432 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
433 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
434
435 #define BNX2X_TX_SB_INDEX \
436 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
437
438
439 /* end of fast path */
440
441 /* common */
442
443 struct bnx2x_common {
444
445 u32 chip_id;
446 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
447 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
448
449 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
450 #define CHIP_NUM_57710 0x164e
451 #define CHIP_NUM_57711 0x164f
452 #define CHIP_NUM_57711E 0x1650
453 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
454 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
455 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
456 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
457 CHIP_IS_57711E(bp))
458 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
459
460 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
461 #define CHIP_REV_Ax 0x00000000
462 /* assume maximum 5 revisions */
463 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
464 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
465 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
466 !(CHIP_REV(bp) & 0x00001000))
467 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
468 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
469 (CHIP_REV(bp) & 0x00001000))
470
471 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
472 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
473
474 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
475 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
476
477 int flash_size;
478 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
479 #define NVRAM_TIMEOUT_COUNT 30000
480 #define NVRAM_PAGE_SIZE 256
481
482 u32 shmem_base;
483
484 u32 hw_config;
485 u32 board;
486
487 u32 bc_ver;
488
489 char *name;
490 };
491
492
493 /* end of common */
494
495 /* port */
496
497 struct nig_stats {
498 u32 brb_discard;
499 u32 brb_packet;
500 u32 brb_truncate;
501 u32 flow_ctrl_discard;
502 u32 flow_ctrl_octets;
503 u32 flow_ctrl_packet;
504 u32 mng_discard;
505 u32 mng_octet_inp;
506 u32 mng_octet_out;
507 u32 mng_packet_inp;
508 u32 mng_packet_out;
509 u32 pbf_octets;
510 u32 pbf_packet;
511 u32 safc_inp;
512 u32 egress_mac_pkt0_lo;
513 u32 egress_mac_pkt0_hi;
514 u32 egress_mac_pkt1_lo;
515 u32 egress_mac_pkt1_hi;
516 };
517
518 struct bnx2x_port {
519 u32 pmf;
520
521 u32 link_config;
522
523 u32 supported;
524 /* link settings - missing defines */
525 #define SUPPORTED_2500baseX_Full (1 << 15)
526
527 u32 advertising;
528 /* link settings - missing defines */
529 #define ADVERTISED_2500baseX_Full (1 << 15)
530
531 u32 phy_addr;
532
533 /* used to synchronize phy accesses */
534 struct mutex phy_mutex;
535
536 u32 port_stx;
537
538 struct nig_stats old_nig_stats;
539 };
540
541 /* end of port */
542
543
544 enum bnx2x_stats_event {
545 STATS_EVENT_PMF = 0,
546 STATS_EVENT_LINK_UP,
547 STATS_EVENT_UPDATE,
548 STATS_EVENT_STOP,
549 STATS_EVENT_MAX
550 };
551
552 enum bnx2x_stats_state {
553 STATS_STATE_DISABLED = 0,
554 STATS_STATE_ENABLED,
555 STATS_STATE_MAX
556 };
557
558 struct bnx2x_eth_stats {
559 u32 total_bytes_received_hi;
560 u32 total_bytes_received_lo;
561 u32 total_bytes_transmitted_hi;
562 u32 total_bytes_transmitted_lo;
563 u32 total_unicast_packets_received_hi;
564 u32 total_unicast_packets_received_lo;
565 u32 total_multicast_packets_received_hi;
566 u32 total_multicast_packets_received_lo;
567 u32 total_broadcast_packets_received_hi;
568 u32 total_broadcast_packets_received_lo;
569 u32 total_unicast_packets_transmitted_hi;
570 u32 total_unicast_packets_transmitted_lo;
571 u32 total_multicast_packets_transmitted_hi;
572 u32 total_multicast_packets_transmitted_lo;
573 u32 total_broadcast_packets_transmitted_hi;
574 u32 total_broadcast_packets_transmitted_lo;
575 u32 valid_bytes_received_hi;
576 u32 valid_bytes_received_lo;
577
578 u32 error_bytes_received_hi;
579 u32 error_bytes_received_lo;
580
581 u32 rx_stat_ifhcinbadoctets_hi;
582 u32 rx_stat_ifhcinbadoctets_lo;
583 u32 tx_stat_ifhcoutbadoctets_hi;
584 u32 tx_stat_ifhcoutbadoctets_lo;
585 u32 rx_stat_dot3statsfcserrors_hi;
586 u32 rx_stat_dot3statsfcserrors_lo;
587 u32 rx_stat_dot3statsalignmenterrors_hi;
588 u32 rx_stat_dot3statsalignmenterrors_lo;
589 u32 rx_stat_dot3statscarriersenseerrors_hi;
590 u32 rx_stat_dot3statscarriersenseerrors_lo;
591 u32 rx_stat_falsecarriererrors_hi;
592 u32 rx_stat_falsecarriererrors_lo;
593 u32 rx_stat_etherstatsundersizepkts_hi;
594 u32 rx_stat_etherstatsundersizepkts_lo;
595 u32 rx_stat_dot3statsframestoolong_hi;
596 u32 rx_stat_dot3statsframestoolong_lo;
597 u32 rx_stat_etherstatsfragments_hi;
598 u32 rx_stat_etherstatsfragments_lo;
599 u32 rx_stat_etherstatsjabbers_hi;
600 u32 rx_stat_etherstatsjabbers_lo;
601 u32 rx_stat_maccontrolframesreceived_hi;
602 u32 rx_stat_maccontrolframesreceived_lo;
603 u32 rx_stat_bmac_xpf_hi;
604 u32 rx_stat_bmac_xpf_lo;
605 u32 rx_stat_bmac_xcf_hi;
606 u32 rx_stat_bmac_xcf_lo;
607 u32 rx_stat_xoffstateentered_hi;
608 u32 rx_stat_xoffstateentered_lo;
609 u32 rx_stat_xonpauseframesreceived_hi;
610 u32 rx_stat_xonpauseframesreceived_lo;
611 u32 rx_stat_xoffpauseframesreceived_hi;
612 u32 rx_stat_xoffpauseframesreceived_lo;
613 u32 tx_stat_outxonsent_hi;
614 u32 tx_stat_outxonsent_lo;
615 u32 tx_stat_outxoffsent_hi;
616 u32 tx_stat_outxoffsent_lo;
617 u32 tx_stat_flowcontroldone_hi;
618 u32 tx_stat_flowcontroldone_lo;
619 u32 tx_stat_etherstatscollisions_hi;
620 u32 tx_stat_etherstatscollisions_lo;
621 u32 tx_stat_dot3statssinglecollisionframes_hi;
622 u32 tx_stat_dot3statssinglecollisionframes_lo;
623 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
624 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
625 u32 tx_stat_dot3statsdeferredtransmissions_hi;
626 u32 tx_stat_dot3statsdeferredtransmissions_lo;
627 u32 tx_stat_dot3statsexcessivecollisions_hi;
628 u32 tx_stat_dot3statsexcessivecollisions_lo;
629 u32 tx_stat_dot3statslatecollisions_hi;
630 u32 tx_stat_dot3statslatecollisions_lo;
631 u32 tx_stat_etherstatspkts64octets_hi;
632 u32 tx_stat_etherstatspkts64octets_lo;
633 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
634 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
635 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
636 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
637 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
638 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
639 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
640 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
641 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
642 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
643 u32 tx_stat_etherstatspktsover1522octets_hi;
644 u32 tx_stat_etherstatspktsover1522octets_lo;
645 u32 tx_stat_bmac_2047_hi;
646 u32 tx_stat_bmac_2047_lo;
647 u32 tx_stat_bmac_4095_hi;
648 u32 tx_stat_bmac_4095_lo;
649 u32 tx_stat_bmac_9216_hi;
650 u32 tx_stat_bmac_9216_lo;
651 u32 tx_stat_bmac_16383_hi;
652 u32 tx_stat_bmac_16383_lo;
653 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
654 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
655 u32 tx_stat_bmac_ufl_hi;
656 u32 tx_stat_bmac_ufl_lo;
657
658 u32 brb_drop_hi;
659 u32 brb_drop_lo;
660 u32 brb_truncate_hi;
661 u32 brb_truncate_lo;
662
663 u32 jabber_packets_received;
664
665 u32 etherstatspkts1024octetsto1522octets_hi;
666 u32 etherstatspkts1024octetsto1522octets_lo;
667 u32 etherstatspktsover1522octets_hi;
668 u32 etherstatspktsover1522octets_lo;
669
670 u32 no_buff_discard;
671
672 u32 mac_filter_discard;
673 u32 xxoverflow_discard;
674 u32 brb_truncate_discard;
675 u32 mac_discard;
676
677 u32 driver_xoff;
678 u32 rx_err_discard_pkt;
679 u32 rx_skb_alloc_failed;
680 u32 hw_csum_err;
681 };
682
683 #define STATS_OFFSET32(stat_name) \
684 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
685
686
687 #ifdef BNX2X_MULTI
688 #define MAX_CONTEXT 16
689 #else
690 #define MAX_CONTEXT 1
691 #endif
692
693 union cdu_context {
694 struct eth_context eth;
695 char pad[1024];
696 };
697
698 #define MAX_DMAE_C 8
699
700 /* DMA memory not used in fastpath */
701 struct bnx2x_slowpath {
702 union cdu_context context[MAX_CONTEXT];
703 struct eth_stats_query fw_stats;
704 struct mac_configuration_cmd mac_config;
705 struct mac_configuration_cmd mcast_config;
706
707 /* used by dmae command executer */
708 struct dmae_command dmae[MAX_DMAE_C];
709
710 u32 stats_comp;
711 union mac_stats mac_stats;
712 struct nig_stats nig_stats;
713 struct host_port_stats port_stats;
714 struct host_func_stats func_stats;
715
716 u32 wb_comp;
717 u32 wb_data[4];
718 };
719
720 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
721 #define bnx2x_sp_mapping(bp, var) \
722 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
723
724
725 /* attn group wiring */
726 #define MAX_DYNAMIC_ATTN_GRPS 8
727
728 struct attn_route {
729 u32 sig[4];
730 };
731
732 struct bnx2x {
733 /* Fields used in the tx and intr/napi performance paths
734 * are grouped together in the beginning of the structure
735 */
736 struct bnx2x_fastpath fp[MAX_CONTEXT];
737 void __iomem *regview;
738 void __iomem *doorbells;
739 #define BNX2X_DB_SIZE (16*2048)
740
741 struct net_device *dev;
742 struct pci_dev *pdev;
743
744 atomic_t intr_sem;
745 struct msix_entry msix_table[MAX_CONTEXT+1];
746
747 int tx_ring_size;
748
749 #ifdef BCM_VLAN
750 struct vlan_group *vlgrp;
751 #endif
752
753 u32 rx_csum;
754 u32 rx_offset;
755 u32 rx_buf_size;
756 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
757 #define ETH_MIN_PACKET_SIZE 60
758 #define ETH_MAX_PACKET_SIZE 1500
759 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
760
761 struct host_def_status_block *def_status_blk;
762 #define DEF_SB_ID 16
763 u16 def_c_idx;
764 u16 def_u_idx;
765 u16 def_x_idx;
766 u16 def_t_idx;
767 u16 def_att_idx;
768 u32 attn_state;
769 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
770 u32 nig_mask;
771
772 /* slow path ring */
773 struct eth_spe *spq;
774 dma_addr_t spq_mapping;
775 u16 spq_prod_idx;
776 struct eth_spe *spq_prod_bd;
777 struct eth_spe *spq_last_bd;
778 u16 *dsb_sp_prod;
779 u16 spq_left; /* serialize spq */
780 /* used to synchronize spq accesses */
781 spinlock_t spq_lock;
782
783 /* Flags for marking that there is a STAT_QUERY or
784 SET_MAC ramrod pending */
785 u8 stats_pending;
786 u8 set_mac_pending;
787
788 /* End of fields used in the performance code paths */
789
790 int panic;
791 int msglevel;
792
793 u32 flags;
794 #define PCIX_FLAG 1
795 #define PCI_32BIT_FLAG 2
796 #define ONE_TDMA_FLAG 4 /* no longer used */
797 #define NO_WOL_FLAG 8
798 #define USING_DAC_FLAG 0x10
799 #define USING_MSIX_FLAG 0x20
800 #define ASF_ENABLE_FLAG 0x40
801 #define TPA_ENABLE_FLAG 0x80
802 #define NO_MCP_FLAG 0x100
803 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
804
805 int func;
806 #define BP_PORT(bp) (bp->func % PORT_MAX)
807 #define BP_FUNC(bp) (bp->func)
808 #define BP_E1HVN(bp) (bp->func >> 1)
809 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
810
811 int pm_cap;
812 int pcie_cap;
813
814 struct work_struct sp_task;
815 struct work_struct reset_task;
816
817 struct timer_list timer;
818 int timer_interval;
819 int current_interval;
820
821 u16 fw_seq;
822 u16 fw_drv_pulse_wr_seq;
823 u32 func_stx;
824
825 struct link_params link_params;
826 struct link_vars link_vars;
827
828 struct bnx2x_common common;
829 struct bnx2x_port port;
830
831 u32 mf_config;
832 u16 e1hov;
833 u8 e1hmf;
834 #define IS_E1HMF(bp) (bp->e1hmf != 0)
835
836 u8 wol;
837
838 int rx_ring_size;
839
840 u16 tx_quick_cons_trip_int;
841 u16 tx_quick_cons_trip;
842 u16 tx_ticks_int;
843 u16 tx_ticks;
844
845 u16 rx_quick_cons_trip_int;
846 u16 rx_quick_cons_trip;
847 u16 rx_ticks_int;
848 u16 rx_ticks;
849
850 u32 lin_cnt;
851
852 int state;
853 #define BNX2X_STATE_CLOSED 0x0
854 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
855 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
856 #define BNX2X_STATE_OPEN 0x3000
857 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
858 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
859 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
860 #define BNX2X_STATE_DISABLED 0xd000
861 #define BNX2X_STATE_DIAG 0xe000
862 #define BNX2X_STATE_ERROR 0xf000
863
864 int num_queues;
865 #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
866
867 u32 rx_mode;
868 #define BNX2X_RX_MODE_NONE 0
869 #define BNX2X_RX_MODE_NORMAL 1
870 #define BNX2X_RX_MODE_ALLMULTI 2
871 #define BNX2X_RX_MODE_PROMISC 3
872 #define BNX2X_MAX_MULTICAST 64
873 #define BNX2X_MAX_EMUL_MULTI 16
874
875 dma_addr_t def_status_blk_mapping;
876
877 struct bnx2x_slowpath *slowpath;
878 dma_addr_t slowpath_mapping;
879
880 #ifdef BCM_ISCSI
881 void *t1;
882 dma_addr_t t1_mapping;
883 void *t2;
884 dma_addr_t t2_mapping;
885 void *timers;
886 dma_addr_t timers_mapping;
887 void *qm;
888 dma_addr_t qm_mapping;
889 #endif
890
891 int dmae_ready;
892 /* used to synchronize dmae accesses */
893 struct mutex dmae_mutex;
894 struct dmae_command init_dmae;
895
896 /* used to synchronize stats collecting */
897 int stats_state;
898 /* used by dmae command loader */
899 struct dmae_command stats_dmae;
900 int executer_idx;
901
902 u16 stats_counter;
903 struct tstorm_per_client_stats old_tclient;
904 struct xstorm_per_client_stats old_xclient;
905 struct bnx2x_eth_stats eth_stats;
906
907 struct z_stream_s *strm;
908 void *gunzip_buf;
909 dma_addr_t gunzip_mapping;
910 int gunzip_outlen;
911 #define FW_BUF_SIZE 0x8000
912
913 };
914
915
916 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
917
918 #define for_each_nondefault_queue(bp, var) \
919 for (var = 1; var < bp->num_queues; var++)
920 #define is_multi(bp) (bp->num_queues > 1)
921
922
923 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
924 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
925 u32 len32);
926 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
927
928 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
929 int wait)
930 {
931 u32 val;
932
933 do {
934 val = REG_RD(bp, reg);
935 if (val == expected)
936 break;
937 ms -= wait;
938 msleep(wait);
939
940 } while (ms > 0);
941
942 return val;
943 }
944
945
946 /* load/unload mode */
947 #define LOAD_NORMAL 0
948 #define LOAD_OPEN 1
949 #define LOAD_DIAG 2
950 #define UNLOAD_NORMAL 0
951 #define UNLOAD_CLOSE 1
952
953
954 /* DMAE command defines */
955 #define DMAE_CMD_SRC_PCI 0
956 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
957
958 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
959 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
960
961 #define DMAE_CMD_C_DST_PCI 0
962 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
963
964 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
965
966 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
967 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
968 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
969 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
970
971 #define DMAE_CMD_PORT_0 0
972 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
973
974 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
975 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
976 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
977
978 #define DMAE_LEN32_RD_MAX 0x80
979 #define DMAE_LEN32_WR_MAX 0x400
980
981 #define DMAE_COMP_VAL 0xe0d0d0ae
982
983 #define MAX_DMAE_C_PER_PORT 8
984 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
985 BP_E1HVN(bp))
986 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
987 E1HVN_MAX)
988
989
990 /* PCIE link and speed */
991 #define PCICFG_LINK_WIDTH 0x1f00000
992 #define PCICFG_LINK_WIDTH_SHIFT 20
993 #define PCICFG_LINK_SPEED 0xf0000
994 #define PCICFG_LINK_SPEED_SHIFT 16
995
996
997 #define BNX2X_NUM_STATS 42
998 #define BNX2X_NUM_TESTS 8
999
1000 #define BNX2X_MAC_LOOPBACK 0
1001 #define BNX2X_PHY_LOOPBACK 1
1002 #define BNX2X_MAC_LOOPBACK_FAILED 1
1003 #define BNX2X_PHY_LOOPBACK_FAILED 2
1004 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1005 BNX2X_PHY_LOOPBACK_FAILED)
1006
1007
1008 #define STROM_ASSERT_ARRAY_SIZE 50
1009
1010
1011 /* must be used on a CID before placing it on a HW ring */
1012 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1013
1014 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1015 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1016
1017
1018 #define BNX2X_BTR 3
1019 #define MAX_SPQ_PENDING 8
1020
1021
1022 /* CMNG constants
1023 derived from lab experiments, and not from system spec calculations !!! */
1024 #define DEF_MIN_RATE 100
1025 /* resolution of the rate shaping timer - 100 usec */
1026 #define RS_PERIODIC_TIMEOUT_USEC 100
1027 /* resolution of fairness algorithm in usecs -
1028 coefficient for calculating the actual t fair */
1029 #define T_FAIR_COEF 10000000
1030 /* number of bytes in single QM arbitration cycle -
1031 coefficient for calculating the fairness timer */
1032 #define QM_ARB_BYTES 40000
1033 #define FAIR_MEM 2
1034
1035
1036 #define ATTN_NIG_FOR_FUNC (1L << 8)
1037 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1038 #define GPIO_2_FUNC (1L << 10)
1039 #define GPIO_3_FUNC (1L << 11)
1040 #define GPIO_4_FUNC (1L << 12)
1041 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1042 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1043 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1044 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1045 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1046 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1047
1048 #define ATTN_HARD_WIRED_MASK 0xff00
1049 #define ATTENTION_ID 4
1050
1051
1052 /* stuff added to make the code fit 80Col */
1053
1054 #define BNX2X_PMF_LINK_ASSERT \
1055 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1056
1057 #define BNX2X_MC_ASSERT_BITS \
1058 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1059 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1060 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1061 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1062
1063 #define BNX2X_MCP_ASSERT \
1064 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1065
1066 #define BNX2X_DOORQ_ASSERT \
1067 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1068
1069 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1070 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1071 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1072 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1073 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1074 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1075 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1076
1077 #define HW_INTERRUT_ASSERT_SET_0 \
1078 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1079 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1080 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1081 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1082 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1083 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1084 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1085 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1086 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1087 #define HW_INTERRUT_ASSERT_SET_1 \
1088 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1089 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1090 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1091 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1092 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1093 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1094 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1095 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1096 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1097 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1098 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1099 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1100 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1101 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1102 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1103 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1104 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1105 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1106 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1107 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1108 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1109 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1110 #define HW_INTERRUT_ASSERT_SET_2 \
1111 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1112 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1113 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1114 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1115 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1116 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1117 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1118 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1119 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1120 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1121 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1122 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1123
1124
1125 #define MULTI_FLAGS \
1126 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1127 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1128 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1129 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1130 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1131
1132 #define MULTI_MASK 0x7f
1133
1134
1135 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1136 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1137 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1138 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1139
1140 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1141
1142 #define BNX2X_SP_DSB_INDEX \
1143 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1144
1145
1146 #define CAM_IS_INVALID(x) \
1147 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1148
1149 #define CAM_INVALIDATE(x) \
1150 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1151
1152
1153 /* Number of u32 elements in MC hash array */
1154 #define MC_HASH_SIZE 8
1155 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1156 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1157
1158
1159 #ifndef PXP2_REG_PXP2_INT_STS
1160 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1161 #endif
1162
1163 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1164
1165 #endif /* bnx2x.h */
Verdex Pro support