2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.8"
47 #define PFX DRV_NAME " "
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
61 #define LINK_HZ (HZ/2)
63 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65 MODULE_LICENSE("GPL");
66 MODULE_VERSION(DRV_VERSION
);
68 static const u32 default_msg
69 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
72 static int debug
= -1; /* defaults above */
73 module_param(debug
, int, 0);
74 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
76 static const struct pci_device_id skge_id_table
[] = {
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940
) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940B
) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_GE
) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_YU
) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, PCI_DEVICE_ID_DLINK_DGE510T
), },
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) }, /* DGE-530T */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, PCI_DEVICE_ID_CNET_GIGACARD
) },
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, PCI_DEVICE_ID_LINKSYS_EG1064
) },
87 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015, },
90 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
92 static int skge_up(struct net_device
*dev
);
93 static int skge_down(struct net_device
*dev
);
94 static void skge_phy_reset(struct skge_port
*skge
);
95 static void skge_tx_clean(struct net_device
*dev
);
96 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
97 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
98 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
99 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
100 static void yukon_init(struct skge_hw
*hw
, int port
);
101 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
102 static void genesis_link_up(struct skge_port
*skge
);
104 /* Avoid conditionals by using array */
105 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
106 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
107 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
108 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
109 static const u32 irqmask
[] = { IS_R1_F
|IS_XA1_F
, IS_R2_F
|IS_XA2_F
};
111 static int skge_get_regs_len(struct net_device
*dev
)
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
121 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
124 const struct skge_port
*skge
= netdev_priv(dev
);
125 const void __iomem
*io
= skge
->hw
->regs
;
128 memset(p
, 0, regs
->len
);
129 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
131 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
132 regs
->len
- B3_RI_WTO_R1
);
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static int wol_supported(const struct skge_hw
*hw
)
138 return !((hw
->chip_id
== CHIP_ID_GENESIS
||
139 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)));
142 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
144 struct skge_port
*skge
= netdev_priv(dev
);
146 wol
->supported
= wol_supported(skge
->hw
) ? WAKE_MAGIC
: 0;
147 wol
->wolopts
= skge
->wol
? WAKE_MAGIC
: 0;
150 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
152 struct skge_port
*skge
= netdev_priv(dev
);
153 struct skge_hw
*hw
= skge
->hw
;
155 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
158 if (wol
->wolopts
== WAKE_MAGIC
&& !wol_supported(hw
))
161 skge
->wol
= wol
->wolopts
== WAKE_MAGIC
;
164 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
166 skge_write16(hw
, WOL_CTRL_STAT
,
167 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
168 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
170 skge_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
175 /* Determine supported/advertised modes based on hardware.
176 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
178 static u32
skge_supported_modes(const struct skge_hw
*hw
)
183 supported
= SUPPORTED_10baseT_Half
184 | SUPPORTED_10baseT_Full
185 | SUPPORTED_100baseT_Half
186 | SUPPORTED_100baseT_Full
187 | SUPPORTED_1000baseT_Half
188 | SUPPORTED_1000baseT_Full
189 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
191 if (hw
->chip_id
== CHIP_ID_GENESIS
)
192 supported
&= ~(SUPPORTED_10baseT_Half
193 | SUPPORTED_10baseT_Full
194 | SUPPORTED_100baseT_Half
195 | SUPPORTED_100baseT_Full
);
197 else if (hw
->chip_id
== CHIP_ID_YUKON
)
198 supported
&= ~SUPPORTED_1000baseT_Half
;
200 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
206 static int skge_get_settings(struct net_device
*dev
,
207 struct ethtool_cmd
*ecmd
)
209 struct skge_port
*skge
= netdev_priv(dev
);
210 struct skge_hw
*hw
= skge
->hw
;
212 ecmd
->transceiver
= XCVR_INTERNAL
;
213 ecmd
->supported
= skge_supported_modes(hw
);
216 ecmd
->port
= PORT_TP
;
217 ecmd
->phy_address
= hw
->phy_addr
;
219 ecmd
->port
= PORT_FIBRE
;
221 ecmd
->advertising
= skge
->advertising
;
222 ecmd
->autoneg
= skge
->autoneg
;
223 ecmd
->speed
= skge
->speed
;
224 ecmd
->duplex
= skge
->duplex
;
228 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
230 struct skge_port
*skge
= netdev_priv(dev
);
231 const struct skge_hw
*hw
= skge
->hw
;
232 u32 supported
= skge_supported_modes(hw
);
234 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
235 ecmd
->advertising
= supported
;
241 switch (ecmd
->speed
) {
243 if (ecmd
->duplex
== DUPLEX_FULL
)
244 setting
= SUPPORTED_1000baseT_Full
;
245 else if (ecmd
->duplex
== DUPLEX_HALF
)
246 setting
= SUPPORTED_1000baseT_Half
;
251 if (ecmd
->duplex
== DUPLEX_FULL
)
252 setting
= SUPPORTED_100baseT_Full
;
253 else if (ecmd
->duplex
== DUPLEX_HALF
)
254 setting
= SUPPORTED_100baseT_Half
;
260 if (ecmd
->duplex
== DUPLEX_FULL
)
261 setting
= SUPPORTED_10baseT_Full
;
262 else if (ecmd
->duplex
== DUPLEX_HALF
)
263 setting
= SUPPORTED_10baseT_Half
;
271 if ((setting
& supported
) == 0)
274 skge
->speed
= ecmd
->speed
;
275 skge
->duplex
= ecmd
->duplex
;
278 skge
->autoneg
= ecmd
->autoneg
;
279 skge
->advertising
= ecmd
->advertising
;
281 if (netif_running(dev
))
282 skge_phy_reset(skge
);
287 static void skge_get_drvinfo(struct net_device
*dev
,
288 struct ethtool_drvinfo
*info
)
290 struct skge_port
*skge
= netdev_priv(dev
);
292 strcpy(info
->driver
, DRV_NAME
);
293 strcpy(info
->version
, DRV_VERSION
);
294 strcpy(info
->fw_version
, "N/A");
295 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
298 static const struct skge_stat
{
299 char name
[ETH_GSTRING_LEN
];
303 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
304 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
306 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
307 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
308 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
309 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
310 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
311 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
312 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
313 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
315 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
316 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
317 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
318 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
319 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
320 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
322 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
323 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
324 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
325 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
326 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
329 static int skge_get_stats_count(struct net_device
*dev
)
331 return ARRAY_SIZE(skge_stats
);
334 static void skge_get_ethtool_stats(struct net_device
*dev
,
335 struct ethtool_stats
*stats
, u64
*data
)
337 struct skge_port
*skge
= netdev_priv(dev
);
339 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
340 genesis_get_stats(skge
, data
);
342 yukon_get_stats(skge
, data
);
345 /* Use hardware MIB variables for critical path statistics and
346 * transmit feedback not reported at interrupt.
347 * Other errors are accounted for in interrupt handler.
349 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
351 struct skge_port
*skge
= netdev_priv(dev
);
352 u64 data
[ARRAY_SIZE(skge_stats
)];
354 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
355 genesis_get_stats(skge
, data
);
357 yukon_get_stats(skge
, data
);
359 skge
->net_stats
.tx_bytes
= data
[0];
360 skge
->net_stats
.rx_bytes
= data
[1];
361 skge
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
362 skge
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
363 skge
->net_stats
.multicast
= data
[3] + data
[5];
364 skge
->net_stats
.collisions
= data
[10];
365 skge
->net_stats
.tx_aborted_errors
= data
[12];
367 return &skge
->net_stats
;
370 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
376 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
377 memcpy(data
+ i
* ETH_GSTRING_LEN
,
378 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
383 static void skge_get_ring_param(struct net_device
*dev
,
384 struct ethtool_ringparam
*p
)
386 struct skge_port
*skge
= netdev_priv(dev
);
388 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
389 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
390 p
->rx_mini_max_pending
= 0;
391 p
->rx_jumbo_max_pending
= 0;
393 p
->rx_pending
= skge
->rx_ring
.count
;
394 p
->tx_pending
= skge
->tx_ring
.count
;
395 p
->rx_mini_pending
= 0;
396 p
->rx_jumbo_pending
= 0;
399 static int skge_set_ring_param(struct net_device
*dev
,
400 struct ethtool_ringparam
*p
)
402 struct skge_port
*skge
= netdev_priv(dev
);
405 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
406 p
->tx_pending
< TX_LOW_WATER
|| p
->tx_pending
> MAX_TX_RING_SIZE
)
409 skge
->rx_ring
.count
= p
->rx_pending
;
410 skge
->tx_ring
.count
= p
->tx_pending
;
412 if (netif_running(dev
)) {
422 static u32
skge_get_msglevel(struct net_device
*netdev
)
424 struct skge_port
*skge
= netdev_priv(netdev
);
425 return skge
->msg_enable
;
428 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
430 struct skge_port
*skge
= netdev_priv(netdev
);
431 skge
->msg_enable
= value
;
434 static int skge_nway_reset(struct net_device
*dev
)
436 struct skge_port
*skge
= netdev_priv(dev
);
438 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
441 skge_phy_reset(skge
);
445 static int skge_set_sg(struct net_device
*dev
, u32 data
)
447 struct skge_port
*skge
= netdev_priv(dev
);
448 struct skge_hw
*hw
= skge
->hw
;
450 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
452 return ethtool_op_set_sg(dev
, data
);
455 static int skge_set_tx_csum(struct net_device
*dev
, u32 data
)
457 struct skge_port
*skge
= netdev_priv(dev
);
458 struct skge_hw
*hw
= skge
->hw
;
460 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
463 return ethtool_op_set_tx_csum(dev
, data
);
466 static u32
skge_get_rx_csum(struct net_device
*dev
)
468 struct skge_port
*skge
= netdev_priv(dev
);
470 return skge
->rx_csum
;
473 /* Only Yukon supports checksum offload. */
474 static int skge_set_rx_csum(struct net_device
*dev
, u32 data
)
476 struct skge_port
*skge
= netdev_priv(dev
);
478 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
481 skge
->rx_csum
= data
;
485 static void skge_get_pauseparam(struct net_device
*dev
,
486 struct ethtool_pauseparam
*ecmd
)
488 struct skge_port
*skge
= netdev_priv(dev
);
490 ecmd
->tx_pause
= (skge
->flow_control
== FLOW_MODE_LOC_SEND
)
491 || (skge
->flow_control
== FLOW_MODE_SYMMETRIC
);
492 ecmd
->rx_pause
= (skge
->flow_control
== FLOW_MODE_REM_SEND
)
493 || (skge
->flow_control
== FLOW_MODE_SYMMETRIC
);
495 ecmd
->autoneg
= skge
->autoneg
;
498 static int skge_set_pauseparam(struct net_device
*dev
,
499 struct ethtool_pauseparam
*ecmd
)
501 struct skge_port
*skge
= netdev_priv(dev
);
503 skge
->autoneg
= ecmd
->autoneg
;
504 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
505 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
506 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
507 skge
->flow_control
= FLOW_MODE_REM_SEND
;
508 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
509 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
511 skge
->flow_control
= FLOW_MODE_NONE
;
513 if (netif_running(dev
))
514 skge_phy_reset(skge
);
518 /* Chip internal frequency for clock calculations */
519 static inline u32
hwkhz(const struct skge_hw
*hw
)
521 return (hw
->chip_id
== CHIP_ID_GENESIS
) ? 53125 : 78125;
524 /* Chip HZ to microseconds */
525 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
527 return (ticks
* 1000) / hwkhz(hw
);
530 /* Microseconds to chip HZ */
531 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
533 return hwkhz(hw
) * usec
/ 1000;
536 static int skge_get_coalesce(struct net_device
*dev
,
537 struct ethtool_coalesce
*ecmd
)
539 struct skge_port
*skge
= netdev_priv(dev
);
540 struct skge_hw
*hw
= skge
->hw
;
541 int port
= skge
->port
;
543 ecmd
->rx_coalesce_usecs
= 0;
544 ecmd
->tx_coalesce_usecs
= 0;
546 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
547 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
548 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
550 if (msk
& rxirqmask
[port
])
551 ecmd
->rx_coalesce_usecs
= delay
;
552 if (msk
& txirqmask
[port
])
553 ecmd
->tx_coalesce_usecs
= delay
;
559 /* Note: interrupt timer is per board, but can turn on/off per port */
560 static int skge_set_coalesce(struct net_device
*dev
,
561 struct ethtool_coalesce
*ecmd
)
563 struct skge_port
*skge
= netdev_priv(dev
);
564 struct skge_hw
*hw
= skge
->hw
;
565 int port
= skge
->port
;
566 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
569 if (ecmd
->rx_coalesce_usecs
== 0)
570 msk
&= ~rxirqmask
[port
];
571 else if (ecmd
->rx_coalesce_usecs
< 25 ||
572 ecmd
->rx_coalesce_usecs
> 33333)
575 msk
|= rxirqmask
[port
];
576 delay
= ecmd
->rx_coalesce_usecs
;
579 if (ecmd
->tx_coalesce_usecs
== 0)
580 msk
&= ~txirqmask
[port
];
581 else if (ecmd
->tx_coalesce_usecs
< 25 ||
582 ecmd
->tx_coalesce_usecs
> 33333)
585 msk
|= txirqmask
[port
];
586 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
589 skge_write32(hw
, B2_IRQM_MSK
, msk
);
591 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
593 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
594 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
599 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
600 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
602 struct skge_hw
*hw
= skge
->hw
;
603 int port
= skge
->port
;
605 mutex_lock(&hw
->phy_mutex
);
606 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
609 if (hw
->phy_type
== SK_PHY_BCOM
)
610 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
612 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 0);
613 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_T_OFF
);
615 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
616 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
617 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
621 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
622 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
624 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
625 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
630 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
631 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
632 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
634 if (hw
->phy_type
== SK_PHY_BCOM
)
635 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
637 skge_write8(hw
, SK_REG(port
, TX_LED_TST
), LED_T_ON
);
638 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 100);
639 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
646 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
647 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
648 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
649 PHY_M_LED_MO_10(MO_LED_OFF
) |
650 PHY_M_LED_MO_100(MO_LED_OFF
) |
651 PHY_M_LED_MO_1000(MO_LED_OFF
) |
652 PHY_M_LED_MO_RX(MO_LED_OFF
));
655 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
656 PHY_M_LED_PULS_DUR(PULS_170MS
) |
657 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
661 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
662 PHY_M_LED_MO_RX(MO_LED_OFF
) |
663 (skge
->speed
== SPEED_100
?
664 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
667 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
668 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
669 PHY_M_LED_MO_DUP(MO_LED_ON
) |
670 PHY_M_LED_MO_10(MO_LED_ON
) |
671 PHY_M_LED_MO_100(MO_LED_ON
) |
672 PHY_M_LED_MO_1000(MO_LED_ON
) |
673 PHY_M_LED_MO_RX(MO_LED_ON
));
676 mutex_unlock(&hw
->phy_mutex
);
679 /* blink LED's for finding board */
680 static int skge_phys_id(struct net_device
*dev
, u32 data
)
682 struct skge_port
*skge
= netdev_priv(dev
);
684 enum led_mode mode
= LED_MODE_TST
;
686 if (!data
|| data
> (u32
)(MAX_SCHEDULE_TIMEOUT
/ HZ
))
687 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
/ HZ
) * 1000;
692 skge_led(skge
, mode
);
693 mode
^= LED_MODE_TST
;
695 if (msleep_interruptible(BLINK_MS
))
700 /* back to regular LED state */
701 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
706 static const struct ethtool_ops skge_ethtool_ops
= {
707 .get_settings
= skge_get_settings
,
708 .set_settings
= skge_set_settings
,
709 .get_drvinfo
= skge_get_drvinfo
,
710 .get_regs_len
= skge_get_regs_len
,
711 .get_regs
= skge_get_regs
,
712 .get_wol
= skge_get_wol
,
713 .set_wol
= skge_set_wol
,
714 .get_msglevel
= skge_get_msglevel
,
715 .set_msglevel
= skge_set_msglevel
,
716 .nway_reset
= skge_nway_reset
,
717 .get_link
= ethtool_op_get_link
,
718 .get_ringparam
= skge_get_ring_param
,
719 .set_ringparam
= skge_set_ring_param
,
720 .get_pauseparam
= skge_get_pauseparam
,
721 .set_pauseparam
= skge_set_pauseparam
,
722 .get_coalesce
= skge_get_coalesce
,
723 .set_coalesce
= skge_set_coalesce
,
724 .get_sg
= ethtool_op_get_sg
,
725 .set_sg
= skge_set_sg
,
726 .get_tx_csum
= ethtool_op_get_tx_csum
,
727 .set_tx_csum
= skge_set_tx_csum
,
728 .get_rx_csum
= skge_get_rx_csum
,
729 .set_rx_csum
= skge_set_rx_csum
,
730 .get_strings
= skge_get_strings
,
731 .phys_id
= skge_phys_id
,
732 .get_stats_count
= skge_get_stats_count
,
733 .get_ethtool_stats
= skge_get_ethtool_stats
,
734 .get_perm_addr
= ethtool_op_get_perm_addr
,
738 * Allocate ring elements and chain them together
739 * One-to-one association of board descriptors with ring elements
741 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u32 base
)
743 struct skge_tx_desc
*d
;
744 struct skge_element
*e
;
747 ring
->start
= kcalloc(sizeof(*e
), ring
->count
, GFP_KERNEL
);
751 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
753 if (i
== ring
->count
- 1) {
754 e
->next
= ring
->start
;
755 d
->next_offset
= base
;
758 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
761 ring
->to_use
= ring
->to_clean
= ring
->start
;
766 /* Allocate and setup a new buffer for receiving */
767 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
768 struct sk_buff
*skb
, unsigned int bufsize
)
770 struct skge_rx_desc
*rd
= e
->desc
;
773 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
777 rd
->dma_hi
= map
>> 32;
779 rd
->csum1_start
= ETH_HLEN
;
780 rd
->csum2_start
= ETH_HLEN
;
786 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
787 pci_unmap_addr_set(e
, mapaddr
, map
);
788 pci_unmap_len_set(e
, maplen
, bufsize
);
791 /* Resume receiving using existing skb,
792 * Note: DMA address is not changed by chip.
793 * MTU not changed while receiver active.
795 static inline void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
797 struct skge_rx_desc
*rd
= e
->desc
;
800 rd
->csum2_start
= ETH_HLEN
;
804 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
808 /* Free all buffers in receive ring, assumes receiver stopped */
809 static void skge_rx_clean(struct skge_port
*skge
)
811 struct skge_hw
*hw
= skge
->hw
;
812 struct skge_ring
*ring
= &skge
->rx_ring
;
813 struct skge_element
*e
;
817 struct skge_rx_desc
*rd
= e
->desc
;
820 pci_unmap_single(hw
->pdev
,
821 pci_unmap_addr(e
, mapaddr
),
822 pci_unmap_len(e
, maplen
),
824 dev_kfree_skb(e
->skb
);
827 } while ((e
= e
->next
) != ring
->start
);
831 /* Allocate buffers for receive ring
832 * For receive: to_clean is next received frame.
834 static int skge_rx_fill(struct net_device
*dev
)
836 struct skge_port
*skge
= netdev_priv(dev
);
837 struct skge_ring
*ring
= &skge
->rx_ring
;
838 struct skge_element
*e
;
844 skb
= __netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
,
849 skb_reserve(skb
, NET_IP_ALIGN
);
850 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
851 } while ( (e
= e
->next
) != ring
->start
);
853 ring
->to_clean
= ring
->start
;
857 static void skge_link_up(struct skge_port
*skge
)
859 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
860 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
862 netif_carrier_on(skge
->netdev
);
863 netif_wake_queue(skge
->netdev
);
865 if (netif_msg_link(skge
))
867 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
868 skge
->netdev
->name
, skge
->speed
,
869 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
870 (skge
->flow_control
== FLOW_MODE_NONE
) ? "none" :
871 (skge
->flow_control
== FLOW_MODE_LOC_SEND
) ? "tx only" :
872 (skge
->flow_control
== FLOW_MODE_REM_SEND
) ? "rx only" :
873 (skge
->flow_control
== FLOW_MODE_SYMMETRIC
) ? "tx and rx" :
877 static void skge_link_down(struct skge_port
*skge
)
879 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
880 netif_carrier_off(skge
->netdev
);
881 netif_stop_queue(skge
->netdev
);
883 if (netif_msg_link(skge
))
884 printk(KERN_INFO PFX
"%s: Link is down.\n", skge
->netdev
->name
);
887 static int __xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
891 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
892 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
894 if (hw
->phy_type
== SK_PHY_XMAC
)
897 for (i
= 0; i
< PHY_RETRIES
; i
++) {
898 if (xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_RDY
)
905 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
910 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
913 if (__xm_phy_read(hw
, port
, reg
, &v
))
914 printk(KERN_WARNING PFX
"%s: phy read timed out\n",
915 hw
->dev
[port
]->name
);
919 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
923 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
924 for (i
= 0; i
< PHY_RETRIES
; i
++) {
925 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
932 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
933 for (i
= 0; i
< PHY_RETRIES
; i
++) {
934 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
941 static void genesis_init(struct skge_hw
*hw
)
943 /* set blink source counter */
944 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
945 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
947 /* configure mac arbiter */
948 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
950 /* configure mac arbiter timeout values */
951 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
952 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
953 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
954 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
956 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
957 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
958 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
959 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
961 /* configure packet arbiter timeout */
962 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
963 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
964 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
965 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
966 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
969 static void genesis_reset(struct skge_hw
*hw
, int port
)
971 const u8 zero
[8] = { 0 };
973 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
975 /* reset the statistics module */
976 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
977 xm_write16(hw
, port
, XM_IMSK
, 0xffff); /* disable XMAC IRQs */
978 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
979 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
980 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
982 /* disable Broadcom PHY IRQ */
983 if (hw
->phy_type
== SK_PHY_BCOM
)
984 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
986 xm_outhash(hw
, port
, XM_HSM
, zero
);
990 /* Convert mode to MII values */
991 static const u16 phy_pause_map
[] = {
992 [FLOW_MODE_NONE
] = 0,
993 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
994 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
995 [FLOW_MODE_REM_SEND
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
999 /* Check status of Broadcom phy link */
1000 static void bcom_check_link(struct skge_hw
*hw
, int port
)
1002 struct net_device
*dev
= hw
->dev
[port
];
1003 struct skge_port
*skge
= netdev_priv(dev
);
1006 /* read twice because of latch */
1007 (void) xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1008 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1010 if ((status
& PHY_ST_LSYNC
) == 0) {
1011 u16 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1012 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1013 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1014 /* dummy read to ensure writing */
1015 (void) xm_read16(hw
, port
, XM_MMU_CMD
);
1017 if (netif_carrier_ok(dev
))
1018 skge_link_down(skge
);
1022 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1025 if (!(status
& PHY_ST_AN_OVER
))
1028 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1029 if (lpa
& PHY_B_AN_RF
) {
1030 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1035 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1037 /* Check Duplex mismatch */
1038 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1039 case PHY_B_RES_1000FD
:
1040 skge
->duplex
= DUPLEX_FULL
;
1042 case PHY_B_RES_1000HD
:
1043 skge
->duplex
= DUPLEX_HALF
;
1046 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1052 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1053 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1054 case PHY_B_AS_PAUSE_MSK
:
1055 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
1058 skge
->flow_control
= FLOW_MODE_REM_SEND
;
1061 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
1064 skge
->flow_control
= FLOW_MODE_NONE
;
1066 skge
->speed
= SPEED_1000
;
1069 if (!netif_carrier_ok(dev
))
1070 genesis_link_up(skge
);
1073 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1074 * Phy on for 100 or 10Mbit operation
1076 static void bcom_phy_init(struct skge_port
*skge
)
1078 struct skge_hw
*hw
= skge
->hw
;
1079 int port
= skge
->port
;
1081 u16 id1
, r
, ext
, ctl
;
1083 /* magic workaround patterns for Broadcom */
1084 static const struct {
1088 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1089 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1090 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1091 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1093 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1094 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1097 /* read Id from external PHY (all have the same address) */
1098 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1100 /* Optimize MDIO transfer by suppressing preamble. */
1101 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1103 xm_write16(hw
, port
, XM_MMU_CMD
,r
);
1106 case PHY_BCOM_ID1_C0
:
1108 * Workaround BCOM Errata for the C0 type.
1109 * Write magic patterns to reserved registers.
1111 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1112 xm_phy_write(hw
, port
,
1113 C0hack
[i
].reg
, C0hack
[i
].val
);
1116 case PHY_BCOM_ID1_A1
:
1118 * Workaround BCOM Errata for the A1 type.
1119 * Write magic patterns to reserved registers.
1121 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1122 xm_phy_write(hw
, port
,
1123 A1hack
[i
].reg
, A1hack
[i
].val
);
1128 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1129 * Disable Power Management after reset.
1131 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1132 r
|= PHY_B_AC_DIS_PM
;
1133 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1136 xm_read16(hw
, port
, XM_ISRC
);
1138 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1139 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1141 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1143 * Workaround BCOM Errata #1 for the C5 type.
1144 * 1000Base-T Link Acquisition Failure in Slave Mode
1145 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1147 u16 adv
= PHY_B_1000C_RD
;
1148 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1149 adv
|= PHY_B_1000C_AHD
;
1150 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1151 adv
|= PHY_B_1000C_AFD
;
1152 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1154 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1156 if (skge
->duplex
== DUPLEX_FULL
)
1157 ctl
|= PHY_CT_DUP_MD
;
1158 /* Force to slave */
1159 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1162 /* Set autonegotiation pause parameters */
1163 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1164 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1166 /* Handle Jumbo frames */
1167 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
1168 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1169 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1171 ext
|= PHY_B_PEC_HIGH_LA
;
1175 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1176 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1178 /* Use link status change interrupt */
1179 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1182 static void xm_phy_init(struct skge_port
*skge
)
1184 struct skge_hw
*hw
= skge
->hw
;
1185 int port
= skge
->port
;
1188 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1189 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1190 ctrl
|= PHY_X_AN_HD
;
1191 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1192 ctrl
|= PHY_X_AN_FD
;
1194 switch(skge
->flow_control
) {
1195 case FLOW_MODE_NONE
:
1196 ctrl
|= PHY_X_P_NO_PAUSE
;
1198 case FLOW_MODE_LOC_SEND
:
1199 ctrl
|= PHY_X_P_ASYM_MD
;
1201 case FLOW_MODE_SYMMETRIC
:
1202 ctrl
|= PHY_X_P_BOTH_MD
;
1206 xm_phy_write(hw
, port
, PHY_XMAC_AUNE_ADV
, ctrl
);
1208 /* Restart Auto-negotiation */
1209 ctrl
= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1211 /* Set DuplexMode in Config register */
1212 if (skge
->duplex
== DUPLEX_FULL
)
1213 ctrl
|= PHY_CT_DUP_MD
;
1215 * Do NOT enable Auto-negotiation here. This would hold
1216 * the link down because no IDLEs are transmitted
1220 xm_phy_write(hw
, port
, PHY_XMAC_CTRL
, ctrl
);
1222 /* Poll PHY for status changes */
1223 schedule_delayed_work(&skge
->link_thread
, LINK_HZ
);
1226 static void xm_check_link(struct net_device
*dev
)
1228 struct skge_port
*skge
= netdev_priv(dev
);
1229 struct skge_hw
*hw
= skge
->hw
;
1230 int port
= skge
->port
;
1233 /* read twice because of latch */
1234 (void) xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1235 status
= xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1237 if ((status
& PHY_ST_LSYNC
) == 0) {
1238 u16 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1239 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1240 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1241 /* dummy read to ensure writing */
1242 (void) xm_read16(hw
, port
, XM_MMU_CMD
);
1244 if (netif_carrier_ok(dev
))
1245 skge_link_down(skge
);
1249 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1252 if (!(status
& PHY_ST_AN_OVER
))
1255 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1256 if (lpa
& PHY_B_AN_RF
) {
1257 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1262 res
= xm_phy_read(hw
, port
, PHY_XMAC_RES_ABI
);
1264 /* Check Duplex mismatch */
1265 switch (res
& (PHY_X_RS_HD
| PHY_X_RS_FD
)) {
1267 skge
->duplex
= DUPLEX_FULL
;
1270 skge
->duplex
= DUPLEX_HALF
;
1273 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1278 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1279 if (lpa
& PHY_X_P_SYM_MD
)
1280 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
1281 else if ((lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_ASYM_MD
)
1282 skge
->flow_control
= FLOW_MODE_REM_SEND
;
1283 else if ((lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_BOTH_MD
)
1284 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
1286 skge
->flow_control
= FLOW_MODE_NONE
;
1289 skge
->speed
= SPEED_1000
;
1292 if (!netif_carrier_ok(dev
))
1293 genesis_link_up(skge
);
1296 /* Poll to check for link coming up.
1297 * Since internal PHY is wired to a level triggered pin, can't
1298 * get an interrupt when carrier is detected.
1300 static void xm_link_timer(void *arg
)
1302 struct net_device
*dev
= arg
;
1303 struct skge_port
*skge
= netdev_priv(arg
);
1304 struct skge_hw
*hw
= skge
->hw
;
1305 int port
= skge
->port
;
1307 if (!netif_running(dev
))
1310 if (netif_carrier_ok(dev
)) {
1311 xm_read16(hw
, port
, XM_ISRC
);
1312 if (!(xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
))
1315 if (xm_read32(hw
, port
, XM_GP_PORT
) & XM_GP_INP_ASS
)
1317 xm_read16(hw
, port
, XM_ISRC
);
1318 if (xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
)
1322 mutex_lock(&hw
->phy_mutex
);
1324 mutex_unlock(&hw
->phy_mutex
);
1327 schedule_delayed_work(&skge
->link_thread
, LINK_HZ
);
1330 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1332 struct net_device
*dev
= hw
->dev
[port
];
1333 struct skge_port
*skge
= netdev_priv(dev
);
1334 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1337 const u8 zero
[6] = { 0 };
1339 for (i
= 0; i
< 10; i
++) {
1340 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
1342 if (skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
)
1347 printk(KERN_WARNING PFX
"%s: genesis reset failed\n", dev
->name
);
1350 /* Unreset the XMAC. */
1351 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1354 * Perform additional initialization for external PHYs,
1355 * namely for the 1000baseTX cards that use the XMAC's
1358 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1359 /* Take external Phy out of reset */
1360 r
= skge_read32(hw
, B2_GP_IO
);
1362 r
|= GP_DIR_0
|GP_IO_0
;
1364 r
|= GP_DIR_2
|GP_IO_2
;
1366 skge_write32(hw
, B2_GP_IO
, r
);
1368 /* Enable GMII interface */
1369 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1373 switch(hw
->phy_type
) {
1378 bcom_phy_init(skge
);
1379 bcom_check_link(hw
, port
);
1382 /* Set Station Address */
1383 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1385 /* We don't use match addresses so clear */
1386 for (i
= 1; i
< 16; i
++)
1387 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1389 /* Clear MIB counters */
1390 xm_write16(hw
, port
, XM_STAT_CMD
,
1391 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1392 /* Clear two times according to Errata #3 */
1393 xm_write16(hw
, port
, XM_STAT_CMD
,
1394 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1396 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1397 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1399 /* We don't need the FCS appended to the packet. */
1400 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1402 r
|= XM_RX_BIG_PK_OK
;
1404 if (skge
->duplex
== DUPLEX_HALF
) {
1406 * If in manual half duplex mode the other side might be in
1407 * full duplex mode, so ignore if a carrier extension is not seen
1408 * on frames received
1410 r
|= XM_RX_DIS_CEXT
;
1412 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1415 /* We want short frames padded to 60 bytes. */
1416 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1419 * Bump up the transmit threshold. This helps hold off transmit
1420 * underruns when we're blasting traffic from both ports at once.
1422 xm_write16(hw
, port
, XM_TX_THR
, 512);
1425 * Enable the reception of all error frames. This is is
1426 * a necessary evil due to the design of the XMAC. The
1427 * XMAC's receive FIFO is only 8K in size, however jumbo
1428 * frames can be up to 9000 bytes in length. When bad
1429 * frame filtering is enabled, the XMAC's RX FIFO operates
1430 * in 'store and forward' mode. For this to work, the
1431 * entire frame has to fit into the FIFO, but that means
1432 * that jumbo frames larger than 8192 bytes will be
1433 * truncated. Disabling all bad frame filtering causes
1434 * the RX FIFO to operate in streaming mode, in which
1435 * case the XMAC will start transferring frames out of the
1436 * RX FIFO as soon as the FIFO threshold is reached.
1438 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1442 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1443 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1444 * and 'Octets Rx OK Hi Cnt Ov'.
1446 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1449 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1450 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1451 * and 'Octets Tx OK Hi Cnt Ov'.
1453 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1455 /* Configure MAC arbiter */
1456 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1458 /* configure timeout values */
1459 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1460 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1461 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1462 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1464 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1465 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1466 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1467 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1469 /* Configure Rx MAC FIFO */
1470 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1471 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1472 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1474 /* Configure Tx MAC FIFO */
1475 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1476 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1477 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1480 /* Enable frame flushing if jumbo frames used */
1481 skge_write16(hw
, SK_REG(port
,RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1483 /* enable timeout timers if normal frames */
1484 skge_write16(hw
, B3_PA_CTRL
,
1485 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1489 static void genesis_stop(struct skge_port
*skge
)
1491 struct skge_hw
*hw
= skge
->hw
;
1492 int port
= skge
->port
;
1495 genesis_reset(hw
, port
);
1497 /* Clear Tx packet arbiter timeout IRQ */
1498 skge_write16(hw
, B3_PA_CTRL
,
1499 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1502 * If the transfer sticks at the MAC the STOP command will not
1503 * terminate if we don't flush the XMAC's transmit FIFO !
1505 xm_write32(hw
, port
, XM_MODE
,
1506 xm_read32(hw
, port
, XM_MODE
)|XM_MD_FTF
);
1510 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1512 /* For external PHYs there must be special handling */
1513 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1514 reg
= skge_read32(hw
, B2_GP_IO
);
1522 skge_write32(hw
, B2_GP_IO
, reg
);
1523 skge_read32(hw
, B2_GP_IO
);
1526 xm_write16(hw
, port
, XM_MMU_CMD
,
1527 xm_read16(hw
, port
, XM_MMU_CMD
)
1528 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1530 xm_read16(hw
, port
, XM_MMU_CMD
);
1534 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1536 struct skge_hw
*hw
= skge
->hw
;
1537 int port
= skge
->port
;
1539 unsigned long timeout
= jiffies
+ HZ
;
1541 xm_write16(hw
, port
,
1542 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1544 /* wait for update to complete */
1545 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1546 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1547 if (time_after(jiffies
, timeout
))
1552 /* special case for 64 bit octet counter */
1553 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1554 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1555 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1556 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1558 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1559 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1562 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1564 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1565 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1567 if (netif_msg_intr(skge
))
1568 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1569 skge
->netdev
->name
, status
);
1571 if (status
& XM_IS_TXF_UR
) {
1572 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1573 ++skge
->net_stats
.tx_fifo_errors
;
1575 if (status
& XM_IS_RXF_OV
) {
1576 xm_write32(hw
, port
, XM_MODE
, XM_MD_FRF
);
1577 ++skge
->net_stats
.rx_fifo_errors
;
1581 static void genesis_link_up(struct skge_port
*skge
)
1583 struct skge_hw
*hw
= skge
->hw
;
1584 int port
= skge
->port
;
1588 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1591 * enabling pause frame reception is required for 1000BT
1592 * because the XMAC is not reset if the link is going down
1594 if (skge
->flow_control
== FLOW_MODE_NONE
||
1595 skge
->flow_control
== FLOW_MODE_LOC_SEND
)
1596 /* Disable Pause Frame Reception */
1597 cmd
|= XM_MMU_IGN_PF
;
1599 /* Enable Pause Frame Reception */
1600 cmd
&= ~XM_MMU_IGN_PF
;
1602 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1604 mode
= xm_read32(hw
, port
, XM_MODE
);
1605 if (skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1606 skge
->flow_control
== FLOW_MODE_LOC_SEND
) {
1608 * Configure Pause Frame Generation
1609 * Use internal and external Pause Frame Generation.
1610 * Sending pause frames is edge triggered.
1611 * Send a Pause frame with the maximum pause time if
1612 * internal oder external FIFO full condition occurs.
1613 * Send a zero pause time frame to re-start transmission.
1615 /* XM_PAUSE_DA = '010000C28001' (default) */
1616 /* XM_MAC_PTIME = 0xffff (maximum) */
1617 /* remember this value is defined in big endian (!) */
1618 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1620 mode
|= XM_PAUSE_MODE
;
1621 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1624 * disable pause frame generation is required for 1000BT
1625 * because the XMAC is not reset if the link is going down
1627 /* Disable Pause Mode in Mode Register */
1628 mode
&= ~XM_PAUSE_MODE
;
1630 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1633 xm_write32(hw
, port
, XM_MODE
, mode
);
1634 xm_write16(hw
, port
, XM_IMSK
, XM_DEF_MSK
);
1635 xm_read16(hw
, port
, XM_ISRC
);
1637 /* get MMU Command Reg. */
1638 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1639 if (hw
->phy_type
!= SK_PHY_XMAC
&& skge
->duplex
== DUPLEX_FULL
)
1640 cmd
|= XM_MMU_GMII_FD
;
1643 * Workaround BCOM Errata (#10523) for all BCom Phys
1644 * Enable Power Management after link up
1646 if (hw
->phy_type
== SK_PHY_BCOM
) {
1647 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1648 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1649 & ~PHY_B_AC_DIS_PM
);
1650 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1654 xm_write16(hw
, port
, XM_MMU_CMD
,
1655 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1660 static inline void bcom_phy_intr(struct skge_port
*skge
)
1662 struct skge_hw
*hw
= skge
->hw
;
1663 int port
= skge
->port
;
1666 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1667 if (netif_msg_intr(skge
))
1668 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x\n",
1669 skge
->netdev
->name
, isrc
);
1671 if (isrc
& PHY_B_IS_PSE
)
1672 printk(KERN_ERR PFX
"%s: uncorrectable pair swap error\n",
1673 hw
->dev
[port
]->name
);
1675 /* Workaround BCom Errata:
1676 * enable and disable loopback mode if "NO HCD" occurs.
1678 if (isrc
& PHY_B_IS_NO_HDCL
) {
1679 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1680 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1681 ctrl
| PHY_CT_LOOP
);
1682 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1683 ctrl
& ~PHY_CT_LOOP
);
1686 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1687 bcom_check_link(hw
, port
);
1691 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1695 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1696 gma_write16(hw
, port
, GM_SMI_CTRL
,
1697 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1698 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1701 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1705 printk(KERN_WARNING PFX
"%s: phy write timeout\n",
1706 hw
->dev
[port
]->name
);
1710 static int __gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1714 gma_write16(hw
, port
, GM_SMI_CTRL
,
1715 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1716 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1718 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1720 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1726 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
1730 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1733 if (__gm_phy_read(hw
, port
, reg
, &v
))
1734 printk(KERN_WARNING PFX
"%s: phy read timeout\n",
1735 hw
->dev
[port
]->name
);
1739 /* Marvell Phy Initialization */
1740 static void yukon_init(struct skge_hw
*hw
, int port
)
1742 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1743 u16 ctrl
, ct1000
, adv
;
1745 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1746 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1748 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1749 PHY_M_EC_MAC_S_MSK
);
1750 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1752 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1754 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1757 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1758 if (skge
->autoneg
== AUTONEG_DISABLE
)
1759 ctrl
&= ~PHY_CT_ANE
;
1761 ctrl
|= PHY_CT_RESET
;
1762 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1768 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1770 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1771 ct1000
|= PHY_M_1000C_AFD
;
1772 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1773 ct1000
|= PHY_M_1000C_AHD
;
1774 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1775 adv
|= PHY_M_AN_100_FD
;
1776 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1777 adv
|= PHY_M_AN_100_HD
;
1778 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1779 adv
|= PHY_M_AN_10_FD
;
1780 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1781 adv
|= PHY_M_AN_10_HD
;
1782 } else /* special defines for FIBER (88E1011S only) */
1783 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
1785 /* Set Flow-control capabilities */
1786 adv
|= phy_pause_map
[skge
->flow_control
];
1788 /* Restart Auto-negotiation */
1789 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1791 /* forced speed/duplex settings */
1792 ct1000
= PHY_M_1000C_MSE
;
1794 if (skge
->duplex
== DUPLEX_FULL
)
1795 ctrl
|= PHY_CT_DUP_MD
;
1797 switch (skge
->speed
) {
1799 ctrl
|= PHY_CT_SP1000
;
1802 ctrl
|= PHY_CT_SP100
;
1806 ctrl
|= PHY_CT_RESET
;
1809 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
1811 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
1812 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1814 /* Enable phy interrupt on autonegotiation complete (or link up) */
1815 if (skge
->autoneg
== AUTONEG_ENABLE
)
1816 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
1818 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1821 static void yukon_reset(struct skge_hw
*hw
, int port
)
1823 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
1824 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
1825 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
1826 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
1827 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
1829 gma_write16(hw
, port
, GM_RX_CTRL
,
1830 gma_read16(hw
, port
, GM_RX_CTRL
)
1831 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
1834 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1835 static int is_yukon_lite_a0(struct skge_hw
*hw
)
1840 if (hw
->chip_id
!= CHIP_ID_YUKON
)
1843 reg
= skge_read32(hw
, B2_FAR
);
1844 skge_write8(hw
, B2_FAR
+ 3, 0xff);
1845 ret
= (skge_read8(hw
, B2_FAR
+ 3) != 0);
1846 skge_write32(hw
, B2_FAR
, reg
);
1850 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
1852 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1855 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
1857 /* WA code for COMA mode -- set PHY reset */
1858 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1859 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1860 reg
= skge_read32(hw
, B2_GP_IO
);
1861 reg
|= GP_DIR_9
| GP_IO_9
;
1862 skge_write32(hw
, B2_GP_IO
, reg
);
1866 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1867 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1869 /* WA code for COMA mode -- clear PHY reset */
1870 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1871 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1872 reg
= skge_read32(hw
, B2_GP_IO
);
1875 skge_write32(hw
, B2_GP_IO
, reg
);
1878 /* Set hardware config mode */
1879 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
1880 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
1881 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
1883 /* Clear GMC reset */
1884 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
1885 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
1886 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
1888 if (skge
->autoneg
== AUTONEG_DISABLE
) {
1889 reg
= GM_GPCR_AU_ALL_DIS
;
1890 gma_write16(hw
, port
, GM_GP_CTRL
,
1891 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
1893 switch (skge
->speed
) {
1895 reg
&= ~GM_GPCR_SPEED_100
;
1896 reg
|= GM_GPCR_SPEED_1000
;
1899 reg
&= ~GM_GPCR_SPEED_1000
;
1900 reg
|= GM_GPCR_SPEED_100
;
1903 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1907 if (skge
->duplex
== DUPLEX_FULL
)
1908 reg
|= GM_GPCR_DUP_FULL
;
1910 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
1912 switch (skge
->flow_control
) {
1913 case FLOW_MODE_NONE
:
1914 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1915 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1917 case FLOW_MODE_LOC_SEND
:
1918 /* disable Rx flow-control */
1919 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1922 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1923 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
1925 yukon_init(hw
, port
);
1928 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
1929 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
1931 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
1932 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
1933 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
1935 /* transmit control */
1936 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
1938 /* receive control reg: unicast + multicast + no FCS */
1939 gma_write16(hw
, port
, GM_RX_CTRL
,
1940 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
1942 /* transmit flow control */
1943 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
1945 /* transmit parameter */
1946 gma_write16(hw
, port
, GM_TX_PARAM
,
1947 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
1948 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
1949 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
1951 /* serial mode register */
1952 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1953 if (hw
->dev
[port
]->mtu
> 1500)
1954 reg
|= GM_SMOD_JUMBO_ENA
;
1956 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
1958 /* physical address: used for pause frames */
1959 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
1960 /* virtual address for data */
1961 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
1963 /* enable interrupt mask for counter overflows */
1964 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
1965 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
1966 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
1968 /* Initialize Mac Fifo */
1970 /* Configure Rx MAC FIFO */
1971 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
1972 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
1974 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1975 if (is_yukon_lite_a0(hw
))
1976 reg
&= ~GMF_RX_F_FL_ON
;
1978 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
1979 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
1981 * because Pause Packet Truncation in GMAC is not working
1982 * we have to increase the Flush Threshold to 64 bytes
1983 * in order to flush pause packets in Rx FIFO on Yukon-1
1985 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
1987 /* Configure Tx MAC FIFO */
1988 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
1989 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
1992 /* Go into power down mode */
1993 static void yukon_suspend(struct skge_hw
*hw
, int port
)
1997 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
1998 ctrl
|= PHY_M_PC_POL_R_DIS
;
1999 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
2001 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2002 ctrl
|= PHY_CT_RESET
;
2003 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2005 /* switch IEEE compatible power down mode on */
2006 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2007 ctrl
|= PHY_CT_PDOWN
;
2008 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2011 static void yukon_stop(struct skge_port
*skge
)
2013 struct skge_hw
*hw
= skge
->hw
;
2014 int port
= skge
->port
;
2016 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
2017 yukon_reset(hw
, port
);
2019 gma_write16(hw
, port
, GM_GP_CTRL
,
2020 gma_read16(hw
, port
, GM_GP_CTRL
)
2021 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
2022 gma_read16(hw
, port
, GM_GP_CTRL
);
2024 yukon_suspend(hw
, port
);
2026 /* set GPHY Control reset */
2027 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2028 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2031 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
2033 struct skge_hw
*hw
= skge
->hw
;
2034 int port
= skge
->port
;
2037 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2038 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
2039 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2040 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
2042 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
2043 data
[i
] = gma_read32(hw
, port
,
2044 skge_stats
[i
].gma_offset
);
2047 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
2049 struct net_device
*dev
= hw
->dev
[port
];
2050 struct skge_port
*skge
= netdev_priv(dev
);
2051 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2053 if (netif_msg_intr(skge
))
2054 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
2057 if (status
& GM_IS_RX_FF_OR
) {
2058 ++skge
->net_stats
.rx_fifo_errors
;
2059 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2062 if (status
& GM_IS_TX_FF_UR
) {
2063 ++skge
->net_stats
.tx_fifo_errors
;
2064 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2069 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
2071 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2072 case PHY_M_PS_SPEED_1000
:
2074 case PHY_M_PS_SPEED_100
:
2081 static void yukon_link_up(struct skge_port
*skge
)
2083 struct skge_hw
*hw
= skge
->hw
;
2084 int port
= skge
->port
;
2087 /* Enable Transmit FIFO Underrun */
2088 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
2090 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2091 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
2092 reg
|= GM_GPCR_DUP_FULL
;
2095 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2096 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2098 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2102 static void yukon_link_down(struct skge_port
*skge
)
2104 struct skge_hw
*hw
= skge
->hw
;
2105 int port
= skge
->port
;
2108 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2110 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2111 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2112 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2114 if (skge
->flow_control
== FLOW_MODE_REM_SEND
) {
2115 /* restore Asymmetric Pause bit */
2116 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
2117 gm_phy_read(hw
, port
,
2123 yukon_reset(hw
, port
);
2124 skge_link_down(skge
);
2126 yukon_init(hw
, port
);
2129 static void yukon_phy_intr(struct skge_port
*skge
)
2131 struct skge_hw
*hw
= skge
->hw
;
2132 int port
= skge
->port
;
2133 const char *reason
= NULL
;
2134 u16 istatus
, phystat
;
2136 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2137 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2139 if (netif_msg_intr(skge
))
2140 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2141 skge
->netdev
->name
, istatus
, phystat
);
2143 if (istatus
& PHY_M_IS_AN_COMPL
) {
2144 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
2146 reason
= "remote fault";
2150 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
2151 reason
= "master/slave fault";
2155 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
2156 reason
= "speed/duplex";
2160 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
2161 ? DUPLEX_FULL
: DUPLEX_HALF
;
2162 skge
->speed
= yukon_speed(hw
, phystat
);
2164 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2165 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
2166 case PHY_M_PS_PAUSE_MSK
:
2167 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
2169 case PHY_M_PS_RX_P_EN
:
2170 skge
->flow_control
= FLOW_MODE_REM_SEND
;
2172 case PHY_M_PS_TX_P_EN
:
2173 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
2176 skge
->flow_control
= FLOW_MODE_NONE
;
2179 if (skge
->flow_control
== FLOW_MODE_NONE
||
2180 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
2181 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2183 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2184 yukon_link_up(skge
);
2188 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2189 skge
->speed
= yukon_speed(hw
, phystat
);
2191 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2192 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2193 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2194 if (phystat
& PHY_M_PS_LINK_UP
)
2195 yukon_link_up(skge
);
2197 yukon_link_down(skge
);
2201 printk(KERN_ERR PFX
"%s: autonegotiation failed (%s)\n",
2202 skge
->netdev
->name
, reason
);
2204 /* XXX restart autonegotiation? */
2207 static void skge_phy_reset(struct skge_port
*skge
)
2209 struct skge_hw
*hw
= skge
->hw
;
2210 int port
= skge
->port
;
2212 netif_stop_queue(skge
->netdev
);
2213 netif_carrier_off(skge
->netdev
);
2215 mutex_lock(&hw
->phy_mutex
);
2216 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2217 genesis_reset(hw
, port
);
2218 genesis_mac_init(hw
, port
);
2220 yukon_reset(hw
, port
);
2221 yukon_init(hw
, port
);
2223 mutex_unlock(&hw
->phy_mutex
);
2226 /* Basic MII support */
2227 static int skge_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2229 struct mii_ioctl_data
*data
= if_mii(ifr
);
2230 struct skge_port
*skge
= netdev_priv(dev
);
2231 struct skge_hw
*hw
= skge
->hw
;
2232 int err
= -EOPNOTSUPP
;
2234 if (!netif_running(dev
))
2235 return -ENODEV
; /* Phy still in reset */
2239 data
->phy_id
= hw
->phy_addr
;
2244 mutex_lock(&hw
->phy_mutex
);
2245 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2246 err
= __xm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2248 err
= __gm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2249 mutex_unlock(&hw
->phy_mutex
);
2250 data
->val_out
= val
;
2255 if (!capable(CAP_NET_ADMIN
))
2258 mutex_lock(&hw
->phy_mutex
);
2259 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2260 err
= xm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2263 err
= gm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2265 mutex_unlock(&hw
->phy_mutex
);
2271 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, size_t len
)
2277 end
= start
+ len
- 1;
2279 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
2280 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
2281 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
2282 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
2283 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
2285 if (q
== Q_R1
|| q
== Q_R2
) {
2286 /* Set thresholds on receive queue's */
2287 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
),
2289 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
),
2292 /* Enable store & forward on Tx queue's because
2293 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2295 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2298 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2301 /* Setup Bus Memory Interface */
2302 static void skge_qset(struct skge_port
*skge
, u16 q
,
2303 const struct skge_element
*e
)
2305 struct skge_hw
*hw
= skge
->hw
;
2306 u32 watermark
= 0x600;
2307 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2309 /* optimization to reduce window on 32bit/33mhz */
2310 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2313 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2314 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2315 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2316 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2319 static int skge_up(struct net_device
*dev
)
2321 struct skge_port
*skge
= netdev_priv(dev
);
2322 struct skge_hw
*hw
= skge
->hw
;
2323 int port
= skge
->port
;
2324 u32 chunk
, ram_addr
;
2325 size_t rx_size
, tx_size
;
2328 if (netif_msg_ifup(skge
))
2329 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
2331 if (dev
->mtu
> RX_BUF_SIZE
)
2332 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
;
2334 skge
->rx_buf_size
= RX_BUF_SIZE
;
2337 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2338 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2339 skge
->mem_size
= tx_size
+ rx_size
;
2340 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2344 BUG_ON(skge
->dma
& 7);
2346 if ((u64
)skge
->dma
>> 32 != ((u64
) skge
->dma
+ skge
->mem_size
) >> 32) {
2347 printk(KERN_ERR PFX
"pci_alloc_consistent region crosses 4G boundary\n");
2352 memset(skge
->mem
, 0, skge
->mem_size
);
2354 err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
);
2358 err
= skge_rx_fill(dev
);
2362 err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2363 skge
->dma
+ rx_size
);
2367 /* Initialize MAC */
2368 mutex_lock(&hw
->phy_mutex
);
2369 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2370 genesis_mac_init(hw
, port
);
2372 yukon_mac_init(hw
, port
);
2373 mutex_unlock(&hw
->phy_mutex
);
2375 /* Configure RAMbuffers */
2376 chunk
= hw
->ram_size
/ ((hw
->ports
+ 1)*2);
2377 ram_addr
= hw
->ram_offset
+ 2 * chunk
* port
;
2379 skge_ramset(hw
, rxqaddr
[port
], ram_addr
, chunk
);
2380 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2382 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2383 skge_ramset(hw
, txqaddr
[port
], ram_addr
+chunk
, chunk
);
2384 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2386 /* Start receiver BMU */
2388 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2389 skge_led(skge
, LED_MODE_ON
);
2391 netif_poll_enable(dev
);
2395 skge_rx_clean(skge
);
2396 kfree(skge
->rx_ring
.start
);
2398 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2404 static int skge_down(struct net_device
*dev
)
2406 struct skge_port
*skge
= netdev_priv(dev
);
2407 struct skge_hw
*hw
= skge
->hw
;
2408 int port
= skge
->port
;
2410 if (skge
->mem
== NULL
)
2413 if (netif_msg_ifdown(skge
))
2414 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
2416 netif_stop_queue(dev
);
2417 if (hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
)
2418 cancel_rearming_delayed_work(&skge
->link_thread
);
2420 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2421 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2426 /* Stop transmitter */
2427 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2428 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2429 RB_RST_SET
|RB_DIS_OP_MD
);
2432 /* Disable Force Sync bit and Enable Alloc bit */
2433 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2434 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2436 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2437 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2438 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2440 /* Reset PCI FIFO */
2441 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2442 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2444 /* Reset the RAM Buffer async Tx queue */
2445 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2447 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2448 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2449 RB_RST_SET
|RB_DIS_OP_MD
);
2450 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2452 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2453 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2454 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2456 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2457 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2460 skge_led(skge
, LED_MODE_OFF
);
2462 netif_poll_disable(dev
);
2464 skge_rx_clean(skge
);
2466 kfree(skge
->rx_ring
.start
);
2467 kfree(skge
->tx_ring
.start
);
2468 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2473 static inline int skge_avail(const struct skge_ring
*ring
)
2475 return ((ring
->to_clean
> ring
->to_use
) ? 0 : ring
->count
)
2476 + (ring
->to_clean
- ring
->to_use
) - 1;
2479 static int skge_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
2481 struct skge_port
*skge
= netdev_priv(dev
);
2482 struct skge_hw
*hw
= skge
->hw
;
2483 struct skge_element
*e
;
2484 struct skge_tx_desc
*td
;
2489 if (skb_padto(skb
, ETH_ZLEN
))
2490 return NETDEV_TX_OK
;
2492 if (unlikely(skge_avail(&skge
->tx_ring
) < skb_shinfo(skb
)->nr_frags
+ 1))
2493 return NETDEV_TX_BUSY
;
2495 e
= skge
->tx_ring
.to_use
;
2497 BUG_ON(td
->control
& BMU_OWN
);
2499 len
= skb_headlen(skb
);
2500 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2501 pci_unmap_addr_set(e
, mapaddr
, map
);
2502 pci_unmap_len_set(e
, maplen
, len
);
2505 td
->dma_hi
= map
>> 32;
2507 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2508 int offset
= skb
->h
.raw
- skb
->data
;
2510 /* This seems backwards, but it is what the sk98lin
2511 * does. Looks like hardware is wrong?
2513 if (skb
->h
.ipiph
->protocol
== IPPROTO_UDP
2514 && hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2515 control
= BMU_TCP_CHECK
;
2517 control
= BMU_UDP_CHECK
;
2520 td
->csum_start
= offset
;
2521 td
->csum_write
= offset
+ skb
->csum
;
2523 control
= BMU_CHECK
;
2525 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2526 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2528 struct skge_tx_desc
*tf
= td
;
2530 control
|= BMU_STFWD
;
2531 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2532 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2534 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2535 frag
->size
, PCI_DMA_TODEVICE
);
2540 BUG_ON(tf
->control
& BMU_OWN
);
2543 tf
->dma_hi
= (u64
) map
>> 32;
2544 pci_unmap_addr_set(e
, mapaddr
, map
);
2545 pci_unmap_len_set(e
, maplen
, frag
->size
);
2547 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2549 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2551 /* Make sure all the descriptors written */
2553 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2556 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2558 if (unlikely(netif_msg_tx_queued(skge
)))
2559 printk(KERN_DEBUG
"%s: tx queued, slot %td, len %d\n",
2560 dev
->name
, e
- skge
->tx_ring
.start
, skb
->len
);
2562 skge
->tx_ring
.to_use
= e
->next
;
2563 if (skge_avail(&skge
->tx_ring
) <= TX_LOW_WATER
) {
2564 pr_debug("%s: transmit queue full\n", dev
->name
);
2565 netif_stop_queue(dev
);
2568 dev
->trans_start
= jiffies
;
2570 return NETDEV_TX_OK
;
2574 /* Free resources associated with this reing element */
2575 static void skge_tx_free(struct skge_port
*skge
, struct skge_element
*e
,
2578 struct pci_dev
*pdev
= skge
->hw
->pdev
;
2582 /* skb header vs. fragment */
2583 if (control
& BMU_STF
)
2584 pci_unmap_single(pdev
, pci_unmap_addr(e
, mapaddr
),
2585 pci_unmap_len(e
, maplen
),
2588 pci_unmap_page(pdev
, pci_unmap_addr(e
, mapaddr
),
2589 pci_unmap_len(e
, maplen
),
2592 if (control
& BMU_EOF
) {
2593 if (unlikely(netif_msg_tx_done(skge
)))
2594 printk(KERN_DEBUG PFX
"%s: tx done slot %td\n",
2595 skge
->netdev
->name
, e
- skge
->tx_ring
.start
);
2597 dev_kfree_skb(e
->skb
);
2602 /* Free all buffers in transmit ring */
2603 static void skge_tx_clean(struct net_device
*dev
)
2605 struct skge_port
*skge
= netdev_priv(dev
);
2606 struct skge_element
*e
;
2608 netif_tx_lock_bh(dev
);
2609 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
2610 struct skge_tx_desc
*td
= e
->desc
;
2611 skge_tx_free(skge
, e
, td
->control
);
2615 skge
->tx_ring
.to_clean
= e
;
2616 netif_wake_queue(dev
);
2617 netif_tx_unlock_bh(dev
);
2620 static void skge_tx_timeout(struct net_device
*dev
)
2622 struct skge_port
*skge
= netdev_priv(dev
);
2624 if (netif_msg_timer(skge
))
2625 printk(KERN_DEBUG PFX
"%s: tx timeout\n", dev
->name
);
2627 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2631 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2635 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2638 if (!netif_running(dev
)) {
2654 static void genesis_set_multicast(struct net_device
*dev
)
2656 struct skge_port
*skge
= netdev_priv(dev
);
2657 struct skge_hw
*hw
= skge
->hw
;
2658 int port
= skge
->port
;
2659 int i
, count
= dev
->mc_count
;
2660 struct dev_mc_list
*list
= dev
->mc_list
;
2664 mode
= xm_read32(hw
, port
, XM_MODE
);
2665 mode
|= XM_MD_ENA_HASH
;
2666 if (dev
->flags
& IFF_PROMISC
)
2667 mode
|= XM_MD_ENA_PROM
;
2669 mode
&= ~XM_MD_ENA_PROM
;
2671 if (dev
->flags
& IFF_ALLMULTI
)
2672 memset(filter
, 0xff, sizeof(filter
));
2674 memset(filter
, 0, sizeof(filter
));
2675 for (i
= 0; list
&& i
< count
; i
++, list
= list
->next
) {
2677 crc
= ether_crc_le(ETH_ALEN
, list
->dmi_addr
);
2679 filter
[bit
/8] |= 1 << (bit
%8);
2683 xm_write32(hw
, port
, XM_MODE
, mode
);
2684 xm_outhash(hw
, port
, XM_HSM
, filter
);
2687 static void yukon_set_multicast(struct net_device
*dev
)
2689 struct skge_port
*skge
= netdev_priv(dev
);
2690 struct skge_hw
*hw
= skge
->hw
;
2691 int port
= skge
->port
;
2692 struct dev_mc_list
*list
= dev
->mc_list
;
2696 memset(filter
, 0, sizeof(filter
));
2698 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2699 reg
|= GM_RXCR_UCF_ENA
;
2701 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2702 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2703 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2704 memset(filter
, 0xff, sizeof(filter
));
2705 else if (dev
->mc_count
== 0) /* no multicast */
2706 reg
&= ~GM_RXCR_MCF_ENA
;
2709 reg
|= GM_RXCR_MCF_ENA
;
2711 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2712 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2713 filter
[bit
/8] |= 1 << (bit
%8);
2718 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2719 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2720 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2721 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2722 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2723 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2724 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2725 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2727 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2730 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2732 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2733 return status
>> XMR_FS_LEN_SHIFT
;
2735 return status
>> GMR_FS_LEN_SHIFT
;
2738 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2740 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2741 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2743 return (status
& GMR_FS_ANY_ERR
) ||
2744 (status
& GMR_FS_RX_OK
) == 0;
2748 /* Get receive buffer from descriptor.
2749 * Handles copy of small buffers and reallocation failures
2751 static struct sk_buff
*skge_rx_get(struct net_device
*dev
,
2752 struct skge_element
*e
,
2753 u32 control
, u32 status
, u16 csum
)
2755 struct skge_port
*skge
= netdev_priv(dev
);
2756 struct sk_buff
*skb
;
2757 u16 len
= control
& BMU_BBC
;
2759 if (unlikely(netif_msg_rx_status(skge
)))
2760 printk(KERN_DEBUG PFX
"%s: rx slot %td status 0x%x len %d\n",
2761 dev
->name
, e
- skge
->rx_ring
.start
,
2764 if (len
> skge
->rx_buf_size
)
2767 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
2770 if (bad_phy_status(skge
->hw
, status
))
2773 if (phy_length(skge
->hw
, status
) != len
)
2776 if (len
< RX_COPY_THRESHOLD
) {
2777 skb
= netdev_alloc_skb(dev
, len
+ 2);
2781 skb_reserve(skb
, 2);
2782 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
2783 pci_unmap_addr(e
, mapaddr
),
2784 len
, PCI_DMA_FROMDEVICE
);
2785 memcpy(skb
->data
, e
->skb
->data
, len
);
2786 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
2787 pci_unmap_addr(e
, mapaddr
),
2788 len
, PCI_DMA_FROMDEVICE
);
2789 skge_rx_reuse(e
, skge
->rx_buf_size
);
2791 struct sk_buff
*nskb
;
2792 nskb
= netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
);
2796 skb_reserve(nskb
, NET_IP_ALIGN
);
2797 pci_unmap_single(skge
->hw
->pdev
,
2798 pci_unmap_addr(e
, mapaddr
),
2799 pci_unmap_len(e
, maplen
),
2800 PCI_DMA_FROMDEVICE
);
2802 prefetch(skb
->data
);
2803 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
2807 if (skge
->rx_csum
) {
2809 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2812 skb
->protocol
= eth_type_trans(skb
, dev
);
2817 if (netif_msg_rx_err(skge
))
2818 printk(KERN_DEBUG PFX
"%s: rx err, slot %td control 0x%x status 0x%x\n",
2819 dev
->name
, e
- skge
->rx_ring
.start
,
2822 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
) {
2823 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
2824 skge
->net_stats
.rx_length_errors
++;
2825 if (status
& XMR_FS_FRA_ERR
)
2826 skge
->net_stats
.rx_frame_errors
++;
2827 if (status
& XMR_FS_FCS_ERR
)
2828 skge
->net_stats
.rx_crc_errors
++;
2830 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
2831 skge
->net_stats
.rx_length_errors
++;
2832 if (status
& GMR_FS_FRAGMENT
)
2833 skge
->net_stats
.rx_frame_errors
++;
2834 if (status
& GMR_FS_CRC_ERR
)
2835 skge
->net_stats
.rx_crc_errors
++;
2839 skge_rx_reuse(e
, skge
->rx_buf_size
);
2843 /* Free all buffers in Tx ring which are no longer owned by device */
2844 static void skge_tx_done(struct net_device
*dev
)
2846 struct skge_port
*skge
= netdev_priv(dev
);
2847 struct skge_ring
*ring
= &skge
->tx_ring
;
2848 struct skge_element
*e
;
2850 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
2853 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
2854 struct skge_tx_desc
*td
= e
->desc
;
2856 if (td
->control
& BMU_OWN
)
2859 skge_tx_free(skge
, e
, td
->control
);
2861 skge
->tx_ring
.to_clean
= e
;
2863 if (skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)
2864 netif_wake_queue(dev
);
2866 netif_tx_unlock(dev
);
2869 static int skge_poll(struct net_device
*dev
, int *budget
)
2871 struct skge_port
*skge
= netdev_priv(dev
);
2872 struct skge_hw
*hw
= skge
->hw
;
2873 struct skge_ring
*ring
= &skge
->rx_ring
;
2874 struct skge_element
*e
;
2875 int to_do
= min(dev
->quota
, *budget
);
2880 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
2882 for (e
= ring
->to_clean
; prefetch(e
->next
), work_done
< to_do
; e
= e
->next
) {
2883 struct skge_rx_desc
*rd
= e
->desc
;
2884 struct sk_buff
*skb
;
2888 control
= rd
->control
;
2889 if (control
& BMU_OWN
)
2892 skb
= skge_rx_get(dev
, e
, control
, rd
->status
, rd
->csum2
);
2894 dev
->last_rx
= jiffies
;
2895 netif_receive_skb(skb
);
2902 /* restart receiver */
2904 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2906 *budget
-= work_done
;
2907 dev
->quota
-= work_done
;
2909 if (work_done
>= to_do
)
2910 return 1; /* not done */
2912 spin_lock_irq(&hw
->hw_lock
);
2913 __netif_rx_complete(dev
);
2914 hw
->intr_mask
|= irqmask
[skge
->port
];
2915 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2916 skge_read32(hw
, B0_IMSK
);
2917 spin_unlock_irq(&hw
->hw_lock
);
2922 /* Parity errors seem to happen when Genesis is connected to a switch
2923 * with no other ports present. Heartbeat error??
2925 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
2927 struct net_device
*dev
= hw
->dev
[port
];
2930 struct skge_port
*skge
= netdev_priv(dev
);
2931 ++skge
->net_stats
.tx_heartbeat_errors
;
2934 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2935 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
2938 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2939 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
2940 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
2941 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
2944 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
2946 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2947 genesis_mac_intr(hw
, port
);
2949 yukon_mac_intr(hw
, port
);
2952 /* Handle device specific framing and timeout interrupts */
2953 static void skge_error_irq(struct skge_hw
*hw
)
2955 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
2957 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2958 /* clear xmac errors */
2959 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
2960 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
2961 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
2962 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
2964 /* Timestamp (unused) overflow */
2965 if (hwstatus
& IS_IRQ_TIST_OV
)
2966 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2969 if (hwstatus
& IS_RAM_RD_PAR
) {
2970 printk(KERN_ERR PFX
"Ram read data parity error\n");
2971 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
2974 if (hwstatus
& IS_RAM_WR_PAR
) {
2975 printk(KERN_ERR PFX
"Ram write data parity error\n");
2976 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
2979 if (hwstatus
& IS_M1_PAR_ERR
)
2980 skge_mac_parity(hw
, 0);
2982 if (hwstatus
& IS_M2_PAR_ERR
)
2983 skge_mac_parity(hw
, 1);
2985 if (hwstatus
& IS_R1_PAR_ERR
) {
2986 printk(KERN_ERR PFX
"%s: receive queue parity error\n",
2988 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
2991 if (hwstatus
& IS_R2_PAR_ERR
) {
2992 printk(KERN_ERR PFX
"%s: receive queue parity error\n",
2994 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
2997 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
2998 u16 pci_status
, pci_cmd
;
3000 pci_read_config_word(hw
->pdev
, PCI_COMMAND
, &pci_cmd
);
3001 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3003 printk(KERN_ERR PFX
"%s: PCI error cmd=%#x status=%#x\n",
3004 pci_name(hw
->pdev
), pci_cmd
, pci_status
);
3006 /* Write the error bits back to clear them. */
3007 pci_status
&= PCI_STATUS_ERROR_BITS
;
3008 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3009 pci_write_config_word(hw
->pdev
, PCI_COMMAND
,
3010 pci_cmd
| PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
3011 pci_write_config_word(hw
->pdev
, PCI_STATUS
, pci_status
);
3012 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3014 /* if error still set then just ignore it */
3015 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3016 if (hwstatus
& IS_IRQ_STAT
) {
3017 printk(KERN_INFO PFX
"unable to clear error (so ignoring them)\n");
3018 hw
->intr_mask
&= ~IS_HW_ERR
;
3024 * Interrupt from PHY are handled in work queue
3025 * because accessing phy registers requires spin wait which might
3026 * cause excess interrupt latency.
3028 static void skge_extirq(void *arg
)
3030 struct skge_hw
*hw
= arg
;
3033 mutex_lock(&hw
->phy_mutex
);
3034 for (port
= 0; port
< hw
->ports
; port
++) {
3035 struct net_device
*dev
= hw
->dev
[port
];
3036 struct skge_port
*skge
= netdev_priv(dev
);
3038 if (netif_running(dev
)) {
3039 if (hw
->chip_id
!= CHIP_ID_GENESIS
)
3040 yukon_phy_intr(skge
);
3041 else if (hw
->phy_type
== SK_PHY_BCOM
)
3042 bcom_phy_intr(skge
);
3045 mutex_unlock(&hw
->phy_mutex
);
3047 spin_lock_irq(&hw
->hw_lock
);
3048 hw
->intr_mask
|= IS_EXT_REG
;
3049 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3050 skge_read32(hw
, B0_IMSK
);
3051 spin_unlock_irq(&hw
->hw_lock
);
3054 static irqreturn_t
skge_intr(int irq
, void *dev_id
)
3056 struct skge_hw
*hw
= dev_id
;
3060 spin_lock(&hw
->hw_lock
);
3061 /* Reading this register masks IRQ */
3062 status
= skge_read32(hw
, B0_SP_ISRC
);
3063 if (status
== 0 || status
== ~0)
3067 status
&= hw
->intr_mask
;
3068 if (status
& IS_EXT_REG
) {
3069 hw
->intr_mask
&= ~IS_EXT_REG
;
3070 schedule_work(&hw
->phy_work
);
3073 if (status
& (IS_XA1_F
|IS_R1_F
)) {
3074 hw
->intr_mask
&= ~(IS_XA1_F
|IS_R1_F
);
3075 netif_rx_schedule(hw
->dev
[0]);
3078 if (status
& IS_PA_TO_TX1
)
3079 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
3081 if (status
& IS_PA_TO_RX1
) {
3082 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3084 ++skge
->net_stats
.rx_over_errors
;
3085 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
3089 if (status
& IS_MAC1
)
3090 skge_mac_intr(hw
, 0);
3093 if (status
& (IS_XA2_F
|IS_R2_F
)) {
3094 hw
->intr_mask
&= ~(IS_XA2_F
|IS_R2_F
);
3095 netif_rx_schedule(hw
->dev
[1]);
3098 if (status
& IS_PA_TO_RX2
) {
3099 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
3100 ++skge
->net_stats
.rx_over_errors
;
3101 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
3104 if (status
& IS_PA_TO_TX2
)
3105 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
3107 if (status
& IS_MAC2
)
3108 skge_mac_intr(hw
, 1);
3111 if (status
& IS_HW_ERR
)
3114 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3115 skge_read32(hw
, B0_IMSK
);
3117 spin_unlock(&hw
->hw_lock
);
3119 return IRQ_RETVAL(handled
);
3122 #ifdef CONFIG_NET_POLL_CONTROLLER
3123 static void skge_netpoll(struct net_device
*dev
)
3125 struct skge_port
*skge
= netdev_priv(dev
);
3127 disable_irq(dev
->irq
);
3128 skge_intr(dev
->irq
, skge
->hw
);
3129 enable_irq(dev
->irq
);
3133 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
3135 struct skge_port
*skge
= netdev_priv(dev
);
3136 struct skge_hw
*hw
= skge
->hw
;
3137 unsigned port
= skge
->port
;
3138 const struct sockaddr
*addr
= p
;
3140 if (!is_valid_ether_addr(addr
->sa_data
))
3141 return -EADDRNOTAVAIL
;
3143 mutex_lock(&hw
->phy_mutex
);
3144 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3145 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8,
3146 dev
->dev_addr
, ETH_ALEN
);
3147 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8,
3148 dev
->dev_addr
, ETH_ALEN
);
3150 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3151 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
3153 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3154 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3156 mutex_unlock(&hw
->phy_mutex
);
3161 static const struct {
3165 { CHIP_ID_GENESIS
, "Genesis" },
3166 { CHIP_ID_YUKON
, "Yukon" },
3167 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
3168 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
3171 static const char *skge_board_name(const struct skge_hw
*hw
)
3174 static char buf
[16];
3176 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
3177 if (skge_chips
[i
].id
== hw
->chip_id
)
3178 return skge_chips
[i
].name
;
3180 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
3186 * Setup the board data structure, but don't bring up
3189 static int skge_reset(struct skge_hw
*hw
)
3192 u16 ctst
, pci_status
;
3193 u8 t8
, mac_cfg
, pmd_type
;
3196 ctst
= skge_read16(hw
, B0_CTST
);
3199 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3200 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
3202 /* clear PCI errors, if any */
3203 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3204 skge_write8(hw
, B2_TST_CTRL2
, 0);
3206 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3207 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
3208 pci_status
| PCI_STATUS_ERROR_BITS
);
3209 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3210 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3212 /* restore CLK_RUN bits (for Yukon-Lite) */
3213 skge_write16(hw
, B0_CTST
,
3214 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
3216 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
3217 hw
->phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
3218 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
3219 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
3221 switch (hw
->chip_id
) {
3222 case CHIP_ID_GENESIS
:
3223 switch (hw
->phy_type
) {
3225 hw
->phy_addr
= PHY_ADDR_XMAC
;
3228 hw
->phy_addr
= PHY_ADDR_BCOM
;
3231 printk(KERN_ERR PFX
"%s: unsupported phy type 0x%x\n",
3232 pci_name(hw
->pdev
), hw
->phy_type
);
3238 case CHIP_ID_YUKON_LITE
:
3239 case CHIP_ID_YUKON_LP
:
3240 if (hw
->phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
3243 hw
->phy_addr
= PHY_ADDR_MARV
;
3247 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
3248 pci_name(hw
->pdev
), hw
->chip_id
);
3252 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
3253 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
3254 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
3256 /* read the adapters RAM size */
3257 t8
= skge_read8(hw
, B2_E_0
);
3258 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3260 /* special case: 4 x 64k x 36, offset = 0x80000 */
3261 hw
->ram_size
= 0x100000;
3262 hw
->ram_offset
= 0x80000;
3264 hw
->ram_size
= t8
* 512;
3267 hw
->ram_size
= 0x20000;
3269 hw
->ram_size
= t8
* 4096;
3271 hw
->intr_mask
= IS_HW_ERR
| IS_PORT_1
;
3273 hw
->intr_mask
|= IS_PORT_2
;
3275 if (!(hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
))
3276 hw
->intr_mask
|= IS_EXT_REG
;
3278 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3281 /* switch power to VCC (WA for VAUX problem) */
3282 skge_write8(hw
, B0_POWER_CTRL
,
3283 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
3285 /* avoid boards with stuck Hardware error bits */
3286 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
3287 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
3288 printk(KERN_WARNING PFX
"stuck hardware sensor bit\n");
3289 hw
->intr_mask
&= ~IS_HW_ERR
;
3292 /* Clear PHY COMA */
3293 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3294 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®
);
3295 reg
&= ~PCI_PHY_COMA
;
3296 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg
);
3297 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3300 for (i
= 0; i
< hw
->ports
; i
++) {
3301 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3302 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3306 /* turn off hardware timer (unused) */
3307 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3308 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3309 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
3311 /* enable the Tx Arbiters */
3312 for (i
= 0; i
< hw
->ports
; i
++)
3313 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3315 /* Initialize ram interface */
3316 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
3318 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
3319 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
3320 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
3321 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
3322 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
3323 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
3324 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
3325 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
3326 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
3327 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
3328 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
3329 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
3331 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
3333 /* Set interrupt moderation for Transmit only
3334 * Receive interrupts avoided by NAPI
3336 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
3337 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
3338 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
3340 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3342 mutex_lock(&hw
->phy_mutex
);
3343 for (i
= 0; i
< hw
->ports
; i
++) {
3344 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3345 genesis_reset(hw
, i
);
3349 mutex_unlock(&hw
->phy_mutex
);
3354 /* Initialize network device */
3355 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3358 struct skge_port
*skge
;
3359 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3362 printk(KERN_ERR
"skge etherdev alloc failed");
3366 SET_MODULE_OWNER(dev
);
3367 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3368 dev
->open
= skge_up
;
3369 dev
->stop
= skge_down
;
3370 dev
->do_ioctl
= skge_ioctl
;
3371 dev
->hard_start_xmit
= skge_xmit_frame
;
3372 dev
->get_stats
= skge_get_stats
;
3373 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3374 dev
->set_multicast_list
= genesis_set_multicast
;
3376 dev
->set_multicast_list
= yukon_set_multicast
;
3378 dev
->set_mac_address
= skge_set_mac_address
;
3379 dev
->change_mtu
= skge_change_mtu
;
3380 SET_ETHTOOL_OPS(dev
, &skge_ethtool_ops
);
3381 dev
->tx_timeout
= skge_tx_timeout
;
3382 dev
->watchdog_timeo
= TX_WATCHDOG
;
3383 dev
->poll
= skge_poll
;
3384 dev
->weight
= NAPI_WEIGHT
;
3385 #ifdef CONFIG_NET_POLL_CONTROLLER
3386 dev
->poll_controller
= skge_netpoll
;
3388 dev
->irq
= hw
->pdev
->irq
;
3391 dev
->features
|= NETIF_F_HIGHDMA
;
3393 skge
= netdev_priv(dev
);
3396 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3397 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3398 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3400 /* Auto speed and flow control */
3401 skge
->autoneg
= AUTONEG_ENABLE
;
3402 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
3405 skge
->advertising
= skge_supported_modes(hw
);
3407 hw
->dev
[port
] = dev
;
3411 /* Only used for Genesis XMAC */
3412 INIT_WORK(&skge
->link_thread
, xm_link_timer
, dev
);
3414 if (hw
->chip_id
!= CHIP_ID_GENESIS
) {
3415 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3419 /* read the mac address */
3420 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3421 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3423 /* device is off until link detection */
3424 netif_carrier_off(dev
);
3425 netif_stop_queue(dev
);
3430 static void __devinit
skge_show_addr(struct net_device
*dev
)
3432 const struct skge_port
*skge
= netdev_priv(dev
);
3434 if (netif_msg_probe(skge
))
3435 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3437 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3438 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3441 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3442 const struct pci_device_id
*ent
)
3444 struct net_device
*dev
, *dev1
;
3446 int err
, using_dac
= 0;
3448 err
= pci_enable_device(pdev
);
3450 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3455 err
= pci_request_regions(pdev
, DRV_NAME
);
3457 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3459 goto err_out_disable_pdev
;
3462 pci_set_master(pdev
);
3464 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3466 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3467 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3469 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3473 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3475 goto err_out_free_regions
;
3479 /* byte swap descriptors in hardware */
3483 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3484 reg
|= PCI_REV_DESC
;
3485 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3490 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3492 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3494 goto err_out_free_regions
;
3498 mutex_init(&hw
->phy_mutex
);
3499 INIT_WORK(&hw
->phy_work
, skge_extirq
, hw
);
3500 spin_lock_init(&hw
->hw_lock
);
3502 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3504 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3506 goto err_out_free_hw
;
3509 err
= skge_reset(hw
);
3511 goto err_out_iounmap
;
3513 printk(KERN_INFO PFX DRV_VERSION
" addr 0x%llx irq %d chip %s rev %d\n",
3514 (unsigned long long)pci_resource_start(pdev
, 0), pdev
->irq
,
3515 skge_board_name(hw
), hw
->chip_rev
);
3517 dev
= skge_devinit(hw
, 0, using_dac
);
3519 goto err_out_led_off
;
3521 if (!is_valid_ether_addr(dev
->dev_addr
)) {
3522 printk(KERN_ERR PFX
"%s: bad (zero?) ethernet address in rom\n",
3525 goto err_out_free_netdev
;
3528 err
= register_netdev(dev
);
3530 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3532 goto err_out_free_netdev
;
3535 err
= request_irq(pdev
->irq
, skge_intr
, IRQF_SHARED
, dev
->name
, hw
);
3537 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3538 dev
->name
, pdev
->irq
);
3539 goto err_out_unregister
;
3541 skge_show_addr(dev
);
3543 if (hw
->ports
> 1 && (dev1
= skge_devinit(hw
, 1, using_dac
))) {
3544 if (register_netdev(dev1
) == 0)
3545 skge_show_addr(dev1
);
3547 /* Failure to register second port need not be fatal */
3548 printk(KERN_WARNING PFX
"register of second port failed\n");
3553 pci_set_drvdata(pdev
, hw
);
3558 unregister_netdev(dev
);
3559 err_out_free_netdev
:
3562 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3567 err_out_free_regions
:
3568 pci_release_regions(pdev
);
3569 err_out_disable_pdev
:
3570 pci_disable_device(pdev
);
3571 pci_set_drvdata(pdev
, NULL
);
3576 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3578 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3579 struct net_device
*dev0
, *dev1
;
3584 if ((dev1
= hw
->dev
[1]))
3585 unregister_netdev(dev1
);
3587 unregister_netdev(dev0
);
3589 spin_lock_irq(&hw
->hw_lock
);
3591 skge_write32(hw
, B0_IMSK
, 0);
3592 skge_read32(hw
, B0_IMSK
);
3593 spin_unlock_irq(&hw
->hw_lock
);
3595 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3596 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3598 flush_scheduled_work();
3600 free_irq(pdev
->irq
, hw
);
3601 pci_release_regions(pdev
);
3602 pci_disable_device(pdev
);
3609 pci_set_drvdata(pdev
, NULL
);
3613 static int skge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3615 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3618 pci_save_state(pdev
);
3619 for (i
= 0; i
< hw
->ports
; i
++) {
3620 struct net_device
*dev
= hw
->dev
[i
];
3622 if (netif_running(dev
)) {
3623 struct skge_port
*skge
= netdev_priv(dev
);
3625 netif_carrier_off(dev
);
3627 netif_stop_queue(dev
);
3632 netif_device_detach(dev
);
3635 skge_write32(hw
, B0_IMSK
, 0);
3636 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3637 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3642 static int skge_resume(struct pci_dev
*pdev
)
3644 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3647 pci_set_power_state(pdev
, PCI_D0
);
3648 pci_restore_state(pdev
);
3649 pci_enable_wake(pdev
, PCI_D0
, 0);
3651 err
= skge_reset(hw
);
3655 for (i
= 0; i
< hw
->ports
; i
++) {
3656 struct net_device
*dev
= hw
->dev
[i
];
3658 netif_device_attach(dev
);
3659 if (netif_running(dev
)) {
3663 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3675 static struct pci_driver skge_driver
= {
3677 .id_table
= skge_id_table
,
3678 .probe
= skge_probe
,
3679 .remove
= __devexit_p(skge_remove
),
3681 .suspend
= skge_suspend
,
3682 .resume
= skge_resume
,
3686 static int __init
skge_init_module(void)
3688 return pci_register_driver(&skge_driver
);
3691 static void __exit
skge_cleanup_module(void)
3693 pci_unregister_driver(&skge_driver
);
3696 module_init(skge_init_module
);
3697 module_exit(skge_cleanup_module
);