1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
9 * Copyright 2004 The Unichrome project.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sub license,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the
20 * next paragraph) shall be included in all copies or substantial portions
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29 * USE OR OTHER DEALINGS IN THE SOFTWARE.
41 #include "via_3d_reg.h"
43 #define CMDBUF_ALIGNMENT_SIZE (0x100)
44 #define CMDBUF_ALIGNMENT_MASK (0x0ff)
46 /* defines for VIA 3D registers */
47 #define VIA_REG_STATUS 0x400
48 #define VIA_REG_TRANSET 0x43C
49 #define VIA_REG_TRANSPACE 0x440
51 /* VIA_REG_STATUS(0x400): Engine Status */
52 #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
53 #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
54 #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
55 #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
57 #define SetReg2DAGP(nReg, nData) { \
58 *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
59 *((uint32_t *)(vb) + 1) = (nData); \
60 vb = ((uint32_t *)vb) + 2; \
61 dev_priv->dma_low +=8; \
64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
66 #define VIA_OUT_RING_QW(w1,w2) \
69 dev_priv->dma_low += 8;
71 static void via_cmdbuf_start(drm_via_private_t
* dev_priv
);
72 static void via_cmdbuf_pause(drm_via_private_t
* dev_priv
);
73 static void via_cmdbuf_reset(drm_via_private_t
* dev_priv
);
74 static void via_cmdbuf_rewind(drm_via_private_t
* dev_priv
);
75 static int via_wait_idle(drm_via_private_t
* dev_priv
);
76 static void via_pad_cache(drm_via_private_t
* dev_priv
, int qwords
);
79 * Free space in command buffer.
82 static uint32_t via_cmdbuf_space(drm_via_private_t
* dev_priv
)
84 uint32_t agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
85 uint32_t hw_addr
= *(dev_priv
->hw_addr_ptr
) - agp_base
;
87 return ((hw_addr
<= dev_priv
->dma_low
) ?
88 (dev_priv
->dma_high
+ hw_addr
- dev_priv
->dma_low
) :
89 (hw_addr
- dev_priv
->dma_low
));
93 * How much does the command regulator lag behind?
96 static uint32_t via_cmdbuf_lag(drm_via_private_t
* dev_priv
)
98 uint32_t agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
99 uint32_t hw_addr
= *(dev_priv
->hw_addr_ptr
) - agp_base
;
101 return ((hw_addr
<= dev_priv
->dma_low
) ?
102 (dev_priv
->dma_low
- hw_addr
) :
103 (dev_priv
->dma_wrap
+ dev_priv
->dma_low
- hw_addr
));
107 * Check that the given size fits in the buffer, otherwise wait.
111 via_cmdbuf_wait(drm_via_private_t
* dev_priv
, unsigned int size
)
113 uint32_t agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
114 uint32_t cur_addr
, hw_addr
, next_addr
;
115 volatile uint32_t *hw_addr_ptr
;
117 hw_addr_ptr
= dev_priv
->hw_addr_ptr
;
118 cur_addr
= dev_priv
->dma_low
;
119 next_addr
= cur_addr
+ size
+ 512 * 1024;
122 hw_addr
= *hw_addr_ptr
- agp_base
;
125 ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126 hw_addr
, cur_addr
, next_addr
);
129 } while ((cur_addr
< hw_addr
) && (next_addr
>= hw_addr
));
134 * Checks whether buffer head has reach the end. Rewind the ring buffer
137 * Returns virtual pointer to ring buffer.
140 static inline uint32_t *via_check_dma(drm_via_private_t
* dev_priv
,
143 if ((dev_priv
->dma_low
+ size
+ 4 * CMDBUF_ALIGNMENT_SIZE
) >
144 dev_priv
->dma_high
) {
145 via_cmdbuf_rewind(dev_priv
);
147 if (via_cmdbuf_wait(dev_priv
, size
) != 0) {
151 return (uint32_t *) (dev_priv
->dma_ptr
+ dev_priv
->dma_low
);
154 int via_dma_cleanup(drm_device_t
* dev
)
156 if (dev
->dev_private
) {
157 drm_via_private_t
*dev_priv
=
158 (drm_via_private_t
*) dev
->dev_private
;
160 if (dev_priv
->ring
.virtual_start
) {
161 via_cmdbuf_reset(dev_priv
);
163 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
164 dev_priv
->ring
.virtual_start
= NULL
;
172 static int via_initialize(drm_device_t
* dev
,
173 drm_via_private_t
* dev_priv
,
174 drm_via_dma_init_t
* init
)
176 if (!dev_priv
|| !dev_priv
->mmio
) {
177 DRM_ERROR("via_dma_init called before via_map_init\n");
178 return DRM_ERR(EFAULT
);
181 if (dev_priv
->ring
.virtual_start
!= NULL
) {
182 DRM_ERROR("%s called again without calling cleanup\n",
184 return DRM_ERR(EFAULT
);
187 if (!dev
->agp
|| !dev
->agp
->base
) {
188 DRM_ERROR("%s called with no agp memory available\n",
190 return DRM_ERR(EFAULT
);
193 dev_priv
->ring
.map
.offset
= dev
->agp
->base
+ init
->offset
;
194 dev_priv
->ring
.map
.size
= init
->size
;
195 dev_priv
->ring
.map
.type
= 0;
196 dev_priv
->ring
.map
.flags
= 0;
197 dev_priv
->ring
.map
.mtrr
= 0;
199 drm_core_ioremap(&dev_priv
->ring
.map
, dev
);
201 if (dev_priv
->ring
.map
.handle
== NULL
) {
202 via_dma_cleanup(dev
);
203 DRM_ERROR("can not ioremap virtual address for"
205 return DRM_ERR(ENOMEM
);
208 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
210 dev_priv
->dma_ptr
= dev_priv
->ring
.virtual_start
;
211 dev_priv
->dma_low
= 0;
212 dev_priv
->dma_high
= init
->size
;
213 dev_priv
->dma_wrap
= init
->size
;
214 dev_priv
->dma_offset
= init
->offset
;
215 dev_priv
->last_pause_ptr
= NULL
;
216 dev_priv
->hw_addr_ptr
= dev_priv
->mmio
->handle
+ init
->reg_pause_addr
;
218 via_cmdbuf_start(dev_priv
);
223 int via_dma_init(DRM_IOCTL_ARGS
)
226 drm_via_private_t
*dev_priv
= (drm_via_private_t
*) dev
->dev_private
;
227 drm_via_dma_init_t init
;
230 DRM_COPY_FROM_USER_IOCTL(init
, (drm_via_dma_init_t __user
*) data
,
235 if (!capable(CAP_SYS_ADMIN
))
236 retcode
= DRM_ERR(EPERM
);
238 retcode
= via_initialize(dev
, dev_priv
, &init
);
240 case VIA_CLEANUP_DMA
:
241 if (!capable(CAP_SYS_ADMIN
))
242 retcode
= DRM_ERR(EPERM
);
244 retcode
= via_dma_cleanup(dev
);
246 case VIA_DMA_INITIALIZED
:
247 retcode
= (dev_priv
->ring
.virtual_start
!= NULL
) ?
251 retcode
= DRM_ERR(EINVAL
);
258 static int via_dispatch_cmdbuffer(drm_device_t
* dev
, drm_via_cmdbuffer_t
* cmd
)
260 drm_via_private_t
*dev_priv
;
264 dev_priv
= (drm_via_private_t
*) dev
->dev_private
;
266 if (dev_priv
->ring
.virtual_start
== NULL
) {
267 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
269 return DRM_ERR(EFAULT
);
272 if (cmd
->size
> VIA_PCI_BUF_SIZE
) {
273 return DRM_ERR(ENOMEM
);
276 if (DRM_COPY_FROM_USER(dev_priv
->pci_buf
, cmd
->buf
, cmd
->size
))
277 return DRM_ERR(EFAULT
);
280 * Running this function on AGP memory is dead slow. Therefore
281 * we run it on a temporary cacheable system memory buffer and
282 * copy it to AGP memory when ready.
286 via_verify_command_stream((uint32_t *) dev_priv
->pci_buf
,
287 cmd
->size
, dev
, 1))) {
291 vb
= via_check_dma(dev_priv
, (cmd
->size
< 0x100) ? 0x102 : cmd
->size
);
293 return DRM_ERR(EAGAIN
);
296 memcpy(vb
, dev_priv
->pci_buf
, cmd
->size
);
298 dev_priv
->dma_low
+= cmd
->size
;
301 * Small submissions somehow stalls the CPU. (AGP cache effects?)
302 * pad to greater size.
305 if (cmd
->size
< 0x100)
306 via_pad_cache(dev_priv
, (0x100 - cmd
->size
) >> 3);
307 via_cmdbuf_pause(dev_priv
);
312 int via_driver_dma_quiescent(drm_device_t
* dev
)
314 drm_via_private_t
*dev_priv
= dev
->dev_private
;
316 if (!via_wait_idle(dev_priv
)) {
317 return DRM_ERR(EBUSY
);
322 int via_flush_ioctl(DRM_IOCTL_ARGS
)
326 LOCK_TEST_WITH_RETURN(dev
, filp
);
328 return via_driver_dma_quiescent(dev
);
331 int via_cmdbuffer(DRM_IOCTL_ARGS
)
334 drm_via_cmdbuffer_t cmdbuf
;
337 LOCK_TEST_WITH_RETURN(dev
, filp
);
339 DRM_COPY_FROM_USER_IOCTL(cmdbuf
, (drm_via_cmdbuffer_t __user
*) data
,
342 DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf
.buf
, cmdbuf
.size
);
344 ret
= via_dispatch_cmdbuffer(dev
, &cmdbuf
);
353 via_parse_command_stream(drm_device_t
* dev
, const uint32_t * buf
,
355 static int via_dispatch_pci_cmdbuffer(drm_device_t
* dev
,
356 drm_via_cmdbuffer_t
* cmd
)
358 drm_via_private_t
*dev_priv
= dev
->dev_private
;
361 if (cmd
->size
> VIA_PCI_BUF_SIZE
) {
362 return DRM_ERR(ENOMEM
);
364 if (DRM_COPY_FROM_USER(dev_priv
->pci_buf
, cmd
->buf
, cmd
->size
))
365 return DRM_ERR(EFAULT
);
368 via_verify_command_stream((uint32_t *) dev_priv
->pci_buf
,
369 cmd
->size
, dev
, 0))) {
374 via_parse_command_stream(dev
, (const uint32_t *)dev_priv
->pci_buf
,
379 int via_pci_cmdbuffer(DRM_IOCTL_ARGS
)
382 drm_via_cmdbuffer_t cmdbuf
;
385 LOCK_TEST_WITH_RETURN(dev
, filp
);
387 DRM_COPY_FROM_USER_IOCTL(cmdbuf
, (drm_via_cmdbuffer_t __user
*) data
,
390 DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf
.buf
,
393 ret
= via_dispatch_pci_cmdbuffer(dev
, &cmdbuf
);
401 static inline uint32_t *via_align_buffer(drm_via_private_t
* dev_priv
,
402 uint32_t * vb
, int qw_count
)
404 for (; qw_count
> 0; --qw_count
) {
405 VIA_OUT_RING_QW(HC_DUMMY
, HC_DUMMY
);
411 * This function is used internally by ring buffer mangement code.
413 * Returns virtual pointer to ring buffer.
415 static inline uint32_t *via_get_dma(drm_via_private_t
* dev_priv
)
417 return (uint32_t *) (dev_priv
->dma_ptr
+ dev_priv
->dma_low
);
421 * Hooks a segment of data into the tail of the ring-buffer by
422 * modifying the pause address stored in the buffer itself. If
423 * the regulator has already paused, restart it.
425 static int via_hook_segment(drm_via_private_t
* dev_priv
,
426 uint32_t pause_addr_hi
, uint32_t pause_addr_lo
,
430 volatile uint32_t *paused_at
= dev_priv
->last_pause_ptr
;
432 via_flush_write_combine();
433 while (!*(via_get_dma(dev_priv
) - 1)) ;
434 *dev_priv
->last_pause_ptr
= pause_addr_lo
;
435 via_flush_write_combine();
438 * The below statement is inserted to really force the flush.
439 * Not sure it is needed.
442 while (!*dev_priv
->last_pause_ptr
) ;
443 dev_priv
->last_pause_ptr
= via_get_dma(dev_priv
) - 1;
444 while (!*dev_priv
->last_pause_ptr
) ;
449 while (!(paused
= (VIA_READ(0x41c) & 0x80000000)) && count
--) ;
450 if ((count
<= 8) && (count
>= 0)) {
452 rgtr
= *(dev_priv
->hw_addr_ptr
);
453 ptr
= ((char *)dev_priv
->last_pause_ptr
- dev_priv
->dma_ptr
) +
454 dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
+ 4 -
455 CMDBUF_ALIGNMENT_SIZE
;
458 ("Command regulator\npaused at count %d, address %x, "
459 "while current pause address is %x.\n"
460 "Please mail this message to "
461 "<unichrome-devel@lists.sourceforge.net>\n", count
,
466 if (paused
&& !no_pci_fire
) {
471 while ((VIA_READ(VIA_REG_STATUS
) & VIA_CMD_RGTR_BUSY
)
474 rgtr
= *(dev_priv
->hw_addr_ptr
);
475 ptr
= ((char *)paused_at
- dev_priv
->dma_ptr
) +
476 dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
+ 4;
478 ptr_low
= (ptr
> 3 * CMDBUF_ALIGNMENT_SIZE
) ?
479 ptr
- 3 * CMDBUF_ALIGNMENT_SIZE
: 0;
480 if (rgtr
<= ptr
&& rgtr
>= ptr_low
) {
481 VIA_WRITE(VIA_REG_TRANSET
, (HC_ParaType_PreCR
<< 16));
482 VIA_WRITE(VIA_REG_TRANSPACE
, pause_addr_hi
);
483 VIA_WRITE(VIA_REG_TRANSPACE
, pause_addr_lo
);
489 static int via_wait_idle(drm_via_private_t
* dev_priv
)
491 int count
= 10000000;
492 while (count
-- && (VIA_READ(VIA_REG_STATUS
) &
493 (VIA_CMD_RGTR_BUSY
| VIA_2D_ENG_BUSY
|
498 static uint32_t *via_align_cmd(drm_via_private_t
* dev_priv
, uint32_t cmd_type
,
499 uint32_t addr
, uint32_t * cmd_addr_hi
,
500 uint32_t * cmd_addr_lo
, int skip_wait
)
503 uint32_t cmd_addr
, addr_lo
, addr_hi
;
505 uint32_t qw_pad_count
;
508 via_cmdbuf_wait(dev_priv
, 2 * CMDBUF_ALIGNMENT_SIZE
);
510 vb
= via_get_dma(dev_priv
);
511 VIA_OUT_RING_QW(HC_HEADER2
| ((VIA_REG_TRANSET
>> 2) << 12) |
512 (VIA_REG_TRANSPACE
>> 2), HC_ParaType_PreCR
<< 16);
513 agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
514 qw_pad_count
= (CMDBUF_ALIGNMENT_SIZE
>> 3) -
515 ((dev_priv
->dma_low
& CMDBUF_ALIGNMENT_MASK
) >> 3);
517 cmd_addr
= (addr
) ? addr
:
518 agp_base
+ dev_priv
->dma_low
- 8 + (qw_pad_count
<< 3);
519 addr_lo
= ((HC_SubA_HAGPBpL
<< 24) | (cmd_type
& HC_HAGPBpID_MASK
) |
520 (cmd_addr
& HC_HAGPBpL_MASK
));
521 addr_hi
= ((HC_SubA_HAGPBpH
<< 24) | (cmd_addr
>> 24));
523 vb
= via_align_buffer(dev_priv
, vb
, qw_pad_count
- 1);
524 VIA_OUT_RING_QW(*cmd_addr_hi
= addr_hi
, *cmd_addr_lo
= addr_lo
);
528 static void via_cmdbuf_start(drm_via_private_t
* dev_priv
)
530 uint32_t pause_addr_lo
, pause_addr_hi
;
531 uint32_t start_addr
, start_addr_lo
;
532 uint32_t end_addr
, end_addr_lo
;
536 dev_priv
->dma_low
= 0;
538 agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
539 start_addr
= agp_base
;
540 end_addr
= agp_base
+ dev_priv
->dma_high
;
542 start_addr_lo
= ((HC_SubA_HAGPBstL
<< 24) | (start_addr
& 0xFFFFFF));
543 end_addr_lo
= ((HC_SubA_HAGPBendL
<< 24) | (end_addr
& 0xFFFFFF));
544 command
= ((HC_SubA_HAGPCMNT
<< 24) | (start_addr
>> 24) |
545 ((end_addr
& 0xff000000) >> 16));
547 dev_priv
->last_pause_ptr
=
548 via_align_cmd(dev_priv
, HC_HAGPBpID_PAUSE
, 0,
549 &pause_addr_hi
, &pause_addr_lo
, 1) - 1;
551 via_flush_write_combine();
552 while (!*dev_priv
->last_pause_ptr
) ;
554 VIA_WRITE(VIA_REG_TRANSET
, (HC_ParaType_PreCR
<< 16));
555 VIA_WRITE(VIA_REG_TRANSPACE
, command
);
556 VIA_WRITE(VIA_REG_TRANSPACE
, start_addr_lo
);
557 VIA_WRITE(VIA_REG_TRANSPACE
, end_addr_lo
);
559 VIA_WRITE(VIA_REG_TRANSPACE
, pause_addr_hi
);
560 VIA_WRITE(VIA_REG_TRANSPACE
, pause_addr_lo
);
562 VIA_WRITE(VIA_REG_TRANSPACE
, command
| HC_HAGPCMNT_MASK
);
565 static void via_pad_cache(drm_via_private_t
* dev_priv
, int qwords
)
569 via_cmdbuf_wait(dev_priv
, qwords
+ 2);
570 vb
= via_get_dma(dev_priv
);
571 VIA_OUT_RING_QW(HC_HEADER2
, HC_ParaType_NotTex
<< 16);
572 via_align_buffer(dev_priv
, vb
, qwords
);
575 static inline void via_dummy_bitblt(drm_via_private_t
* dev_priv
)
577 uint32_t *vb
= via_get_dma(dev_priv
);
578 SetReg2DAGP(0x0C, (0 | (0 << 16)));
579 SetReg2DAGP(0x10, 0 | (0 << 16));
580 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
583 static void via_cmdbuf_jump(drm_via_private_t
* dev_priv
)
586 uint32_t pause_addr_lo
, pause_addr_hi
;
587 uint32_t jump_addr_lo
, jump_addr_hi
;
588 volatile uint32_t *last_pause_ptr
;
589 uint32_t dma_low_save1
, dma_low_save2
;
591 agp_base
= dev_priv
->dma_offset
+ (uint32_t) dev_priv
->agpAddr
;
592 via_align_cmd(dev_priv
, HC_HAGPBpID_JUMP
, 0, &jump_addr_hi
,
595 dev_priv
->dma_wrap
= dev_priv
->dma_low
;
598 * Wrap command buffer to the beginning.
601 dev_priv
->dma_low
= 0;
602 if (via_cmdbuf_wait(dev_priv
, CMDBUF_ALIGNMENT_SIZE
) != 0) {
603 DRM_ERROR("via_cmdbuf_jump failed\n");
606 via_dummy_bitblt(dev_priv
);
607 via_dummy_bitblt(dev_priv
);
610 via_align_cmd(dev_priv
, HC_HAGPBpID_PAUSE
, 0, &pause_addr_hi
,
611 &pause_addr_lo
, 0) - 1;
612 via_align_cmd(dev_priv
, HC_HAGPBpID_PAUSE
, 0, &pause_addr_hi
,
615 *last_pause_ptr
= pause_addr_lo
;
616 dma_low_save1
= dev_priv
->dma_low
;
619 * Now, set a trap that will pause the regulator if it tries to rerun the old
620 * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
621 * and reissues the jump command over PCI, while the regulator has already taken the jump
622 * and actually paused at the current buffer end).
623 * There appears to be no other way to detect this condition, since the hw_addr_pointer
624 * does not seem to get updated immediately when a jump occurs.
628 via_align_cmd(dev_priv
, HC_HAGPBpID_PAUSE
, 0, &pause_addr_hi
,
629 &pause_addr_lo
, 0) - 1;
630 via_align_cmd(dev_priv
, HC_HAGPBpID_PAUSE
, 0, &pause_addr_hi
,
632 *last_pause_ptr
= pause_addr_lo
;
634 dma_low_save2
= dev_priv
->dma_low
;
635 dev_priv
->dma_low
= dma_low_save1
;
636 via_hook_segment(dev_priv
, jump_addr_hi
, jump_addr_lo
, 0);
637 dev_priv
->dma_low
= dma_low_save2
;
638 via_hook_segment(dev_priv
, pause_addr_hi
, pause_addr_lo
, 0);
641 static void via_cmdbuf_rewind(drm_via_private_t
* dev_priv
)
643 via_cmdbuf_jump(dev_priv
);
646 static void via_cmdbuf_flush(drm_via_private_t
* dev_priv
, uint32_t cmd_type
)
648 uint32_t pause_addr_lo
, pause_addr_hi
;
650 via_align_cmd(dev_priv
, cmd_type
, 0, &pause_addr_hi
, &pause_addr_lo
, 0);
651 via_hook_segment(dev_priv
, pause_addr_hi
, pause_addr_lo
, 0);
654 static void via_cmdbuf_pause(drm_via_private_t
* dev_priv
)
656 via_cmdbuf_flush(dev_priv
, HC_HAGPBpID_PAUSE
);
659 static void via_cmdbuf_reset(drm_via_private_t
* dev_priv
)
661 via_cmdbuf_flush(dev_priv
, HC_HAGPBpID_STOP
);
662 via_wait_idle(dev_priv
);
666 * User interface to the space and lag functions.
669 int via_cmdbuf_size(DRM_IOCTL_ARGS
)
672 drm_via_cmdbuf_size_t d_siz
;
674 uint32_t tmp_size
, count
;
675 drm_via_private_t
*dev_priv
;
677 DRM_DEBUG("via cmdbuf_size\n");
678 LOCK_TEST_WITH_RETURN(dev
, filp
);
680 dev_priv
= (drm_via_private_t
*) dev
->dev_private
;
682 if (dev_priv
->ring
.virtual_start
== NULL
) {
683 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
685 return DRM_ERR(EFAULT
);
688 DRM_COPY_FROM_USER_IOCTL(d_siz
, (drm_via_cmdbuf_size_t __user
*) data
,
692 tmp_size
= d_siz
.size
;
693 switch (d_siz
.func
) {
694 case VIA_CMDBUF_SPACE
:
695 while (((tmp_size
= via_cmdbuf_space(dev_priv
)) < d_siz
.size
)
702 DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
703 ret
= DRM_ERR(EAGAIN
);
707 while (((tmp_size
= via_cmdbuf_lag(dev_priv
)) > d_siz
.size
)
714 DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
715 ret
= DRM_ERR(EAGAIN
);
719 ret
= DRM_ERR(EFAULT
);
721 d_siz
.size
= tmp_size
;
723 DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user
*) data
, d_siz
,