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ext2: trivial indentation fix.
[linux-2.6/verdex.git] / drivers / char / drm / savage_bci.c
blob6d10515795cc91f1dc7564d0060a02a7afa78b9c
1 /* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #include "drmP.h"
26 #include "savage_drm.h"
27 #include "savage_drv.h"
28
29 /* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
31 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
33 #define SAVAGE_FREELIST_DEBUG 0
34
35 static int
36 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
37 {
38 uint32_t mask = dev_priv->status_used_mask;
39 uint32_t threshold = dev_priv->bci_threshold_hi;
40 uint32_t status;
41 int i;
42
43 #if SAVAGE_BCI_DEBUG
44 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
45 DRM_ERROR("Trying to emit %d words "
46 "(more than guaranteed space in COB)\n", n);
47 #endif
48
49 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
50 DRM_MEMORYBARRIER();
51 status = dev_priv->status_ptr[0];
52 if ((status & mask) < threshold)
53 return 0;
54 DRM_UDELAY(1);
55 }
56
57 #if SAVAGE_BCI_DEBUG
58 DRM_ERROR("failed!\n");
59 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
60 #endif
61 return DRM_ERR(EBUSY);
62 }
63
64 static int
65 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
66 {
67 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
68 uint32_t status;
69 int i;
70
71 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
72 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
73 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
74 return 0;
75 DRM_UDELAY(1);
76 }
77
78 #if SAVAGE_BCI_DEBUG
79 DRM_ERROR("failed!\n");
80 DRM_INFO(" status=0x%08x\n", status);
81 #endif
82 return DRM_ERR(EBUSY);
83 }
84
85 static int
86 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
87 {
88 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
89 uint32_t status;
90 int i;
91
92 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
93 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
94 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
95 return 0;
96 DRM_UDELAY(1);
97 }
98
99 #if SAVAGE_BCI_DEBUG
100 DRM_ERROR("failed!\n");
101 DRM_INFO(" status=0x%08x\n", status);
102 #endif
103 return DRM_ERR(EBUSY);
104 }
105
106 /*
107 * Waiting for events.
108 *
109 * The BIOSresets the event tag to 0 on mode changes. Therefore we
110 * never emit 0 to the event tag. If we find a 0 event tag we know the
111 * BIOS stomped on it and return success assuming that the BIOS waited
112 * for engine idle.
113 *
114 * Note: if the Xserver uses the event tag it has to follow the same
115 * rule. Otherwise there may be glitches every 2^16 events.
116 */
117 static int
118 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
119 {
120 uint32_t status;
121 int i;
122
123 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
124 DRM_MEMORYBARRIER();
125 status = dev_priv->status_ptr[1];
126 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
127 (status & 0xffff) == 0)
128 return 0;
129 DRM_UDELAY(1);
130 }
131
132 #if SAVAGE_BCI_DEBUG
133 DRM_ERROR("failed!\n");
134 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
135 #endif
136
137 return DRM_ERR(EBUSY);
138 }
139
140 static int
141 savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
142 {
143 uint32_t status;
144 int i;
145
146 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
147 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
148 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
149 (status & 0xffff) == 0)
150 return 0;
151 DRM_UDELAY(1);
152 }
153
154 #if SAVAGE_BCI_DEBUG
155 DRM_ERROR("failed!\n");
156 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
157 #endif
158
159 return DRM_ERR(EBUSY);
160 }
161
162 uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
163 unsigned int flags)
164 {
165 uint16_t count;
166 BCI_LOCALS;
167
168 if (dev_priv->status_ptr) {
169 /* coordinate with Xserver */
170 count = dev_priv->status_ptr[1023];
171 if (count < dev_priv->event_counter)
172 dev_priv->event_wrap++;
173 } else {
174 count = dev_priv->event_counter;
175 }
176 count = (count + 1) & 0xffff;
177 if (count == 0) {
178 count++; /* See the comment above savage_wait_event_*. */
179 dev_priv->event_wrap++;
180 }
181 dev_priv->event_counter = count;
182 if (dev_priv->status_ptr)
183 dev_priv->status_ptr[1023] = (uint32_t) count;
184
185 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
186 unsigned int wait_cmd = BCI_CMD_WAIT;
187 if ((flags & SAVAGE_WAIT_2D))
188 wait_cmd |= BCI_CMD_WAIT_2D;
189 if ((flags & SAVAGE_WAIT_3D))
190 wait_cmd |= BCI_CMD_WAIT_3D;
191 BEGIN_BCI(2);
192 BCI_WRITE(wait_cmd);
193 } else {
194 BEGIN_BCI(1);
195 }
196 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
197
198 return count;
199 }
200
201 /*
202 * Freelist management
203 */
204 static int savage_freelist_init(drm_device_t * dev)
205 {
206 drm_savage_private_t *dev_priv = dev->dev_private;
207 drm_device_dma_t *dma = dev->dma;
208 drm_buf_t *buf;
209 drm_savage_buf_priv_t *entry;
210 int i;
211 DRM_DEBUG("count=%d\n", dma->buf_count);
212
213 dev_priv->head.next = &dev_priv->tail;
214 dev_priv->head.prev = NULL;
215 dev_priv->head.buf = NULL;
216
217 dev_priv->tail.next = NULL;
218 dev_priv->tail.prev = &dev_priv->head;
219 dev_priv->tail.buf = NULL;
220
221 for (i = 0; i < dma->buf_count; i++) {
222 buf = dma->buflist[i];
223 entry = buf->dev_private;
224
225 SET_AGE(&entry->age, 0, 0);
226 entry->buf = buf;
227
228 entry->next = dev_priv->head.next;
229 entry->prev = &dev_priv->head;
230 dev_priv->head.next->prev = entry;
231 dev_priv->head.next = entry;
232 }
233
234 return 0;
235 }
236
237 static drm_buf_t *savage_freelist_get(drm_device_t * dev)
238 {
239 drm_savage_private_t *dev_priv = dev->dev_private;
240 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
241 uint16_t event;
242 unsigned int wrap;
243 DRM_DEBUG("\n");
244
245 UPDATE_EVENT_COUNTER();
246 if (dev_priv->status_ptr)
247 event = dev_priv->status_ptr[1] & 0xffff;
248 else
249 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
250 wrap = dev_priv->event_wrap;
251 if (event > dev_priv->event_counter)
252 wrap--; /* hardware hasn't passed the last wrap yet */
253
254 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
255 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
256
257 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
258 drm_savage_buf_priv_t *next = tail->next;
259 drm_savage_buf_priv_t *prev = tail->prev;
260 prev->next = next;
261 next->prev = prev;
262 tail->next = tail->prev = NULL;
263 return tail->buf;
264 }
265
266 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
267 return NULL;
268 }
269
270 void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf)
271 {
272 drm_savage_private_t *dev_priv = dev->dev_private;
273 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
274
275 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
276
277 if (entry->next != NULL || entry->prev != NULL) {
278 DRM_ERROR("entry already on freelist.\n");
279 return;
280 }
281
282 prev = &dev_priv->head;
283 next = prev->next;
284 prev->next = entry;
285 next->prev = entry;
286 entry->prev = prev;
287 entry->next = next;
288 }
289
290 /*
291 * Command DMA
292 */
293 static int savage_dma_init(drm_savage_private_t * dev_priv)
294 {
295 unsigned int i;
296
297 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
298 (SAVAGE_DMA_PAGE_SIZE * 4);
299 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
300 dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
301 if (dev_priv->dma_pages == NULL)
302 return DRM_ERR(ENOMEM);
303
304 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
305 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
306 dev_priv->dma_pages[i].used = 0;
307 dev_priv->dma_pages[i].flushed = 0;
308 }
309 SET_AGE(&dev_priv->last_dma_age, 0, 0);
310
311 dev_priv->first_dma_page = 0;
312 dev_priv->current_dma_page = 0;
313
314 return 0;
315 }
316
317 void savage_dma_reset(drm_savage_private_t * dev_priv)
318 {
319 uint16_t event;
320 unsigned int wrap, i;
321 event = savage_bci_emit_event(dev_priv, 0);
322 wrap = dev_priv->event_wrap;
323 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
324 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
325 dev_priv->dma_pages[i].used = 0;
326 dev_priv->dma_pages[i].flushed = 0;
327 }
328 SET_AGE(&dev_priv->last_dma_age, event, wrap);
329 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
330 }
331
332 void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
333 {
334 uint16_t event;
335 unsigned int wrap;
336
337 /* Faked DMA buffer pages don't age. */
338 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
339 return;
340
341 UPDATE_EVENT_COUNTER();
342 if (dev_priv->status_ptr)
343 event = dev_priv->status_ptr[1] & 0xffff;
344 else
345 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
346 wrap = dev_priv->event_wrap;
347 if (event > dev_priv->event_counter)
348 wrap--; /* hardware hasn't passed the last wrap yet */
349
350 if (dev_priv->dma_pages[page].age.wrap > wrap ||
351 (dev_priv->dma_pages[page].age.wrap == wrap &&
352 dev_priv->dma_pages[page].age.event > event)) {
353 if (dev_priv->wait_evnt(dev_priv,
354 dev_priv->dma_pages[page].age.event)
355 < 0)
356 DRM_ERROR("wait_evnt failed!\n");
357 }
358 }
359
360 uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
361 {
362 unsigned int cur = dev_priv->current_dma_page;
363 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
364 dev_priv->dma_pages[cur].used;
365 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
366 SAVAGE_DMA_PAGE_SIZE;
367 uint32_t *dma_ptr;
368 unsigned int i;
369
370 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
371 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
372
373 if (cur + nr_pages < dev_priv->nr_dma_pages) {
374 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
375 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
376 if (n < rest)
377 rest = n;
378 dev_priv->dma_pages[cur].used += rest;
379 n -= rest;
380 cur++;
381 } else {
382 dev_priv->dma_flush(dev_priv);
383 nr_pages =
384 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
385 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
386 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
387 dev_priv->dma_pages[i].used = 0;
388 dev_priv->dma_pages[i].flushed = 0;
389 }
390 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
391 dev_priv->first_dma_page = cur = 0;
392 }
393 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
394 #if SAVAGE_DMA_DEBUG
395 if (dev_priv->dma_pages[i].used) {
396 DRM_ERROR("unflushed page %u: used=%u\n",
397 i, dev_priv->dma_pages[i].used);
398 }
399 #endif
400 if (n > SAVAGE_DMA_PAGE_SIZE)
401 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
402 else
403 dev_priv->dma_pages[i].used = n;
404 n -= SAVAGE_DMA_PAGE_SIZE;
405 }
406 dev_priv->current_dma_page = --i;
407
408 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
409 i, dev_priv->dma_pages[i].used, n);
410
411 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
412
413 return dma_ptr;
414 }
415
416 static void savage_dma_flush(drm_savage_private_t * dev_priv)
417 {
418 unsigned int first = dev_priv->first_dma_page;
419 unsigned int cur = dev_priv->current_dma_page;
420 uint16_t event;
421 unsigned int wrap, pad, align, len, i;
422 unsigned long phys_addr;
423 BCI_LOCALS;
424
425 if (first == cur &&
426 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
427 return;
428
429 /* pad length to multiples of 2 entries
430 * align start of next DMA block to multiles of 8 entries */
431 pad = -dev_priv->dma_pages[cur].used & 1;
432 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
433
434 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
435 "pad=%u, align=%u\n",
436 first, cur, dev_priv->dma_pages[first].flushed,
437 dev_priv->dma_pages[cur].used, pad, align);
438
439 /* pad with noops */
440 if (pad) {
441 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
442 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
443 dev_priv->dma_pages[cur].used += pad;
444 while (pad != 0) {
445 *dma_ptr++ = BCI_CMD_WAIT;
446 pad--;
447 }
448 }
449
450 DRM_MEMORYBARRIER();
451
452 /* do flush ... */
453 phys_addr = dev_priv->cmd_dma->offset +
454 (first * SAVAGE_DMA_PAGE_SIZE +
455 dev_priv->dma_pages[first].flushed) * 4;
456 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
457 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
458
459 DRM_DEBUG("phys_addr=%lx, len=%u\n",
460 phys_addr | dev_priv->dma_type, len);
461
462 BEGIN_BCI(3);
463 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
464 BCI_WRITE(phys_addr | dev_priv->dma_type);
465 BCI_DMA(len);
466
467 /* fix alignment of the start of the next block */
468 dev_priv->dma_pages[cur].used += align;
469
470 /* age DMA pages */
471 event = savage_bci_emit_event(dev_priv, 0);
472 wrap = dev_priv->event_wrap;
473 for (i = first; i < cur; ++i) {
474 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
475 dev_priv->dma_pages[i].used = 0;
476 dev_priv->dma_pages[i].flushed = 0;
477 }
478 /* age the current page only when it's full */
479 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
480 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
481 dev_priv->dma_pages[cur].used = 0;
482 dev_priv->dma_pages[cur].flushed = 0;
483 /* advance to next page */
484 cur++;
485 if (cur == dev_priv->nr_dma_pages)
486 cur = 0;
487 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
488 } else {
489 dev_priv->first_dma_page = cur;
490 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
491 }
492 SET_AGE(&dev_priv->last_dma_age, event, wrap);
493
494 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
495 dev_priv->dma_pages[cur].used,
496 dev_priv->dma_pages[cur].flushed);
497 }
498
499 static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
500 {
501 unsigned int i, j;
502 BCI_LOCALS;
503
504 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
505 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
506 return;
507
508 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
509 dev_priv->first_dma_page, dev_priv->current_dma_page,
510 dev_priv->dma_pages[dev_priv->current_dma_page].used);
511
512 for (i = dev_priv->first_dma_page;
513 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
514 ++i) {
515 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
516 i * SAVAGE_DMA_PAGE_SIZE;
517 #if SAVAGE_DMA_DEBUG
518 /* Sanity check: all pages except the last one must be full. */
519 if (i < dev_priv->current_dma_page &&
520 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
521 DRM_ERROR("partial DMA page %u: used=%u",
522 i, dev_priv->dma_pages[i].used);
523 }
524 #endif
525 BEGIN_BCI(dev_priv->dma_pages[i].used);
526 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
527 BCI_WRITE(dma_ptr[j]);
528 }
529 dev_priv->dma_pages[i].used = 0;
530 }
531
532 /* reset to first page */
533 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
534 }
535
536 /*
537 * Initalize mappings. On Savage4 and SavageIX the alignment
538 * and size of the aperture is not suitable for automatic MTRR setup
539 * in drm_addmap. Therefore we do it manually before the maps are
540 * initialized. We also need to take care of deleting the MTRRs in
541 * postcleanup.
542 */
543 int savage_preinit(drm_device_t * dev, unsigned long chipset)
544 {
545 drm_savage_private_t *dev_priv;
546 unsigned long mmio_base, fb_base, fb_size, aperture_base;
547 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
548 * in case we decide we need information on the BAR for BSD in the
549 * future.
550 */
551 unsigned int fb_rsrc, aper_rsrc;
552 int ret = 0;
553
554 dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
555 if (dev_priv == NULL)
556 return DRM_ERR(ENOMEM);
557
558 memset(dev_priv, 0, sizeof(drm_savage_private_t));
559 dev->dev_private = (void *)dev_priv;
560 dev_priv->chipset = (enum savage_family)chipset;
561
562 dev_priv->mtrr[0].handle = -1;
563 dev_priv->mtrr[1].handle = -1;
564 dev_priv->mtrr[2].handle = -1;
565 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
566 fb_rsrc = 0;
567 fb_base = drm_get_resource_start(dev, 0);
568 fb_size = SAVAGE_FB_SIZE_S3;
569 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
570 aper_rsrc = 0;
571 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
572 /* this should always be true */
573 if (drm_get_resource_len(dev, 0) == 0x08000000) {
574 /* Don't make MMIO write-cobining! We need 3
575 * MTRRs. */
576 dev_priv->mtrr[0].base = fb_base;
577 dev_priv->mtrr[0].size = 0x01000000;
578 dev_priv->mtrr[0].handle =
579 mtrr_add(dev_priv->mtrr[0].base,
580 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
581 1);
582 dev_priv->mtrr[1].base = fb_base + 0x02000000;
583 dev_priv->mtrr[1].size = 0x02000000;
584 dev_priv->mtrr[1].handle =
585 mtrr_add(dev_priv->mtrr[1].base,
586 dev_priv->mtrr[1].size, MTRR_TYPE_WRCOMB,
587 1);
588 dev_priv->mtrr[2].base = fb_base + 0x04000000;
589 dev_priv->mtrr[2].size = 0x04000000;
590 dev_priv->mtrr[2].handle =
591 mtrr_add(dev_priv->mtrr[2].base,
592 dev_priv->mtrr[2].size, MTRR_TYPE_WRCOMB,
593 1);
594 } else {
595 DRM_ERROR("strange pci_resource_len %08lx\n",
596 drm_get_resource_len(dev, 0));
597 }
598 } else if (chipset != S3_SUPERSAVAGE && chipset != S3_SAVAGE2000) {
599 mmio_base = drm_get_resource_start(dev, 0);
600 fb_rsrc = 1;
601 fb_base = drm_get_resource_start(dev, 1);
602 fb_size = SAVAGE_FB_SIZE_S4;
603 aper_rsrc = 1;
604 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
605 /* this should always be true */
606 if (drm_get_resource_len(dev, 1) == 0x08000000) {
607 /* Can use one MTRR to cover both fb and
608 * aperture. */
609 dev_priv->mtrr[0].base = fb_base;
610 dev_priv->mtrr[0].size = 0x08000000;
611 dev_priv->mtrr[0].handle =
612 mtrr_add(dev_priv->mtrr[0].base,
613 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
614 1);
615 } else {
616 DRM_ERROR("strange pci_resource_len %08lx\n",
617 drm_get_resource_len(dev, 1));
618 }
619 } else {
620 mmio_base = drm_get_resource_start(dev, 0);
621 fb_rsrc = 1;
622 fb_base = drm_get_resource_start(dev, 1);
623 fb_size = drm_get_resource_len(dev, 1);
624 aper_rsrc = 2;
625 aperture_base = drm_get_resource_start(dev, 2);
626 /* Automatic MTRR setup will do the right thing. */
627 }
628
629 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
630 _DRM_READ_ONLY, &dev_priv->mmio);
631 if (ret)
632 return ret;
633
634 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
635 _DRM_WRITE_COMBINING, &dev_priv->fb);
636 if (ret)
637 return ret;
638
639 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
640 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
641 &dev_priv->aperture);
642 if (ret)
643 return ret;
644
645 return ret;
646 }
647
648 /*
649 * Delete MTRRs and free device-private data.
650 */
651 int savage_postcleanup(drm_device_t * dev)
652 {
653 drm_savage_private_t *dev_priv = dev->dev_private;
654 int i;
655
656 for (i = 0; i < 3; ++i)
657 if (dev_priv->mtrr[i].handle >= 0)
658 mtrr_del(dev_priv->mtrr[i].handle,
659 dev_priv->mtrr[i].base,
660 dev_priv->mtrr[i].size);
661
662 drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
663
664 return 0;
665 }
666
667 static int savage_do_init_bci(drm_device_t * dev, drm_savage_init_t * init)
668 {
669 drm_savage_private_t *dev_priv = dev->dev_private;
670
671 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
672 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
673 return DRM_ERR(EINVAL);
674 }
675 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
676 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
677 return DRM_ERR(EINVAL);
678 }
679 if (init->dma_type != SAVAGE_DMA_AGP &&
680 init->dma_type != SAVAGE_DMA_PCI) {
681 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
682 return DRM_ERR(EINVAL);
683 }
684
685 dev_priv->cob_size = init->cob_size;
686 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
687 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
688 dev_priv->dma_type = init->dma_type;
689
690 dev_priv->fb_bpp = init->fb_bpp;
691 dev_priv->front_offset = init->front_offset;
692 dev_priv->front_pitch = init->front_pitch;
693 dev_priv->back_offset = init->back_offset;
694 dev_priv->back_pitch = init->back_pitch;
695 dev_priv->depth_bpp = init->depth_bpp;
696 dev_priv->depth_offset = init->depth_offset;
697 dev_priv->depth_pitch = init->depth_pitch;
698
699 dev_priv->texture_offset = init->texture_offset;
700 dev_priv->texture_size = init->texture_size;
701
702 DRM_GETSAREA();
703 if (!dev_priv->sarea) {
704 DRM_ERROR("could not find sarea!\n");
705 savage_do_cleanup_bci(dev);
706 return DRM_ERR(EINVAL);
707 }
708 if (init->status_offset != 0) {
709 dev_priv->status = drm_core_findmap(dev, init->status_offset);
710 if (!dev_priv->status) {
711 DRM_ERROR("could not find shadow status region!\n");
712 savage_do_cleanup_bci(dev);
713 return DRM_ERR(EINVAL);
714 }
715 } else {
716 dev_priv->status = NULL;
717 }
718 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
719 dev->agp_buffer_map = drm_core_findmap(dev,
720 init->buffers_offset);
721 if (!dev->agp_buffer_map) {
722 DRM_ERROR("could not find DMA buffer region!\n");
723 savage_do_cleanup_bci(dev);
724 return DRM_ERR(EINVAL);
725 }
726 drm_core_ioremap(dev->agp_buffer_map, dev);
727 if (!dev->agp_buffer_map) {
728 DRM_ERROR("failed to ioremap DMA buffer region!\n");
729 savage_do_cleanup_bci(dev);
730 return DRM_ERR(ENOMEM);
731 }
732 }
733 if (init->agp_textures_offset) {
734 dev_priv->agp_textures =
735 drm_core_findmap(dev, init->agp_textures_offset);
736 if (!dev_priv->agp_textures) {
737 DRM_ERROR("could not find agp texture region!\n");
738 savage_do_cleanup_bci(dev);
739 return DRM_ERR(EINVAL);
740 }
741 } else {
742 dev_priv->agp_textures = NULL;
743 }
744
745 if (init->cmd_dma_offset) {
746 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
747 DRM_ERROR("command DMA not supported on "
748 "Savage3D/MX/IX.\n");
749 savage_do_cleanup_bci(dev);
750 return DRM_ERR(EINVAL);
751 }
752 if (dev->dma && dev->dma->buflist) {
753 DRM_ERROR("command and vertex DMA not supported "
754 "at the same time.\n");
755 savage_do_cleanup_bci(dev);
756 return DRM_ERR(EINVAL);
757 }
758 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
759 if (!dev_priv->cmd_dma) {
760 DRM_ERROR("could not find command DMA region!\n");
761 savage_do_cleanup_bci(dev);
762 return DRM_ERR(EINVAL);
763 }
764 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
765 if (dev_priv->cmd_dma->type != _DRM_AGP) {
766 DRM_ERROR("AGP command DMA region is not a "
767 "_DRM_AGP map!\n");
768 savage_do_cleanup_bci(dev);
769 return DRM_ERR(EINVAL);
770 }
771 drm_core_ioremap(dev_priv->cmd_dma, dev);
772 if (!dev_priv->cmd_dma->handle) {
773 DRM_ERROR("failed to ioremap command "
774 "DMA region!\n");
775 savage_do_cleanup_bci(dev);
776 return DRM_ERR(ENOMEM);
777 }
778 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
779 DRM_ERROR("PCI command DMA region is not a "
780 "_DRM_CONSISTENT map!\n");
781 savage_do_cleanup_bci(dev);
782 return DRM_ERR(EINVAL);
783 }
784 } else {
785 dev_priv->cmd_dma = NULL;
786 }
787
788 dev_priv->dma_flush = savage_dma_flush;
789 if (!dev_priv->cmd_dma) {
790 DRM_DEBUG("falling back to faked command DMA.\n");
791 dev_priv->fake_dma.offset = 0;
792 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
793 dev_priv->fake_dma.type = _DRM_SHM;
794 dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
795 DRM_MEM_DRIVER);
796 if (!dev_priv->fake_dma.handle) {
797 DRM_ERROR("could not allocate faked DMA buffer!\n");
798 savage_do_cleanup_bci(dev);
799 return DRM_ERR(ENOMEM);
800 }
801 dev_priv->cmd_dma = &dev_priv->fake_dma;
802 dev_priv->dma_flush = savage_fake_dma_flush;
803 }
804
805 dev_priv->sarea_priv =
806 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
807 init->sarea_priv_offset);
808
809 /* setup bitmap descriptors */
810 {
811 unsigned int color_tile_format;
812 unsigned int depth_tile_format;
813 unsigned int front_stride, back_stride, depth_stride;
814 if (dev_priv->chipset <= S3_SAVAGE4) {
815 color_tile_format = dev_priv->fb_bpp == 16 ?
816 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
817 depth_tile_format = dev_priv->depth_bpp == 16 ?
818 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
819 } else {
820 color_tile_format = SAVAGE_BD_TILE_DEST;
821 depth_tile_format = SAVAGE_BD_TILE_DEST;
822 }
823 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
824 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
825 depth_stride =
826 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
827
828 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
829 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
830 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
831
832 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
833 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
834 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
835
836 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
837 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
838 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
839 }
840
841 /* setup status and bci ptr */
842 dev_priv->event_counter = 0;
843 dev_priv->event_wrap = 0;
844 dev_priv->bci_ptr = (volatile uint32_t *)
845 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
846 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
847 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
848 } else {
849 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
850 }
851 if (dev_priv->status != NULL) {
852 dev_priv->status_ptr =
853 (volatile uint32_t *)dev_priv->status->handle;
854 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
855 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
856 dev_priv->status_ptr[1023] = dev_priv->event_counter;
857 } else {
858 dev_priv->status_ptr = NULL;
859 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
860 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
861 } else {
862 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
863 }
864 dev_priv->wait_evnt = savage_bci_wait_event_reg;
865 }
866
867 /* cliprect functions */
868 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
869 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
870 else
871 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
872
873 if (savage_freelist_init(dev) < 0) {
874 DRM_ERROR("could not initialize freelist\n");
875 savage_do_cleanup_bci(dev);
876 return DRM_ERR(ENOMEM);
877 }
878
879 if (savage_dma_init(dev_priv) < 0) {
880 DRM_ERROR("could not initialize command DMA\n");
881 savage_do_cleanup_bci(dev);
882 return DRM_ERR(ENOMEM);
883 }
884
885 return 0;
886 }
887
888 int savage_do_cleanup_bci(drm_device_t * dev)
889 {
890 drm_savage_private_t *dev_priv = dev->dev_private;
891
892 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
893 if (dev_priv->fake_dma.handle)
894 drm_free(dev_priv->fake_dma.handle,
895 SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
896 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
897 dev_priv->cmd_dma->type == _DRM_AGP &&
898 dev_priv->dma_type == SAVAGE_DMA_AGP)
899 drm_core_ioremapfree(dev_priv->cmd_dma, dev);
900
901 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
902 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
903 drm_core_ioremapfree(dev->agp_buffer_map, dev);
904 /* make sure the next instance (which may be running
905 * in PCI mode) doesn't try to use an old
906 * agp_buffer_map. */
907 dev->agp_buffer_map = NULL;
908 }
909
910 if (dev_priv->dma_pages)
911 drm_free(dev_priv->dma_pages,
912 sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages,
913 DRM_MEM_DRIVER);
914
915 return 0;
916 }
917
918 static int savage_bci_init(DRM_IOCTL_ARGS)
919 {
920 DRM_DEVICE;
921 drm_savage_init_t init;
922
923 LOCK_TEST_WITH_RETURN(dev, filp);
924
925 DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data,
926 sizeof(init));
927
928 switch (init.func) {
929 case SAVAGE_INIT_BCI:
930 return savage_do_init_bci(dev, &init);
931 case SAVAGE_CLEANUP_BCI:
932 return savage_do_cleanup_bci(dev);
933 }
934
935 return DRM_ERR(EINVAL);
936 }
937
938 static int savage_bci_event_emit(DRM_IOCTL_ARGS)
939 {
940 DRM_DEVICE;
941 drm_savage_private_t *dev_priv = dev->dev_private;
942 drm_savage_event_emit_t event;
943
944 DRM_DEBUG("\n");
945
946 LOCK_TEST_WITH_RETURN(dev, filp);
947
948 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data,
949 sizeof(event));
950
951 event.count = savage_bci_emit_event(dev_priv, event.flags);
952 event.count |= dev_priv->event_wrap << 16;
953 DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *) data)->
954 count, event.count, sizeof(event.count));
955 return 0;
956 }
957
958 static int savage_bci_event_wait(DRM_IOCTL_ARGS)
959 {
960 DRM_DEVICE;
961 drm_savage_private_t *dev_priv = dev->dev_private;
962 drm_savage_event_wait_t event;
963 unsigned int event_e, hw_e;
964 unsigned int event_w, hw_w;
965
966 DRM_DEBUG("\n");
967
968 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data,
969 sizeof(event));
970
971 UPDATE_EVENT_COUNTER();
972 if (dev_priv->status_ptr)
973 hw_e = dev_priv->status_ptr[1] & 0xffff;
974 else
975 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
976 hw_w = dev_priv->event_wrap;
977 if (hw_e > dev_priv->event_counter)
978 hw_w--; /* hardware hasn't passed the last wrap yet */
979
980 event_e = event.count & 0xffff;
981 event_w = event.count >> 16;
982
983 /* Don't need to wait if
984 * - event counter wrapped since the event was emitted or
985 * - the hardware has advanced up to or over the event to wait for.
986 */
987 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
988 return 0;
989 else
990 return dev_priv->wait_evnt(dev_priv, event_e);
991 }
992
993 /*
994 * DMA buffer management
995 */
996
997 static int savage_bci_get_buffers(DRMFILE filp, drm_device_t * dev,
998 drm_dma_t * d)
999 {
1000 drm_buf_t *buf;
1001 int i;
1002
1003 for (i = d->granted_count; i < d->request_count; i++) {
1004 buf = savage_freelist_get(dev);
1005 if (!buf)
1006 return DRM_ERR(EAGAIN);
1007
1008 buf->filp = filp;
1009
1010 if (DRM_COPY_TO_USER(&d->request_indices[i],
1011 &buf->idx, sizeof(buf->idx)))
1012 return DRM_ERR(EFAULT);
1013 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1014 &buf->total, sizeof(buf->total)))
1015 return DRM_ERR(EFAULT);
1016
1017 d->granted_count++;
1018 }
1019 return 0;
1020 }
1021
1022 int savage_bci_buffers(DRM_IOCTL_ARGS)
1023 {
1024 DRM_DEVICE;
1025 drm_device_dma_t *dma = dev->dma;
1026 drm_dma_t d;
1027 int ret = 0;
1028
1029 LOCK_TEST_WITH_RETURN(dev, filp);
1030
1031 DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *) data, sizeof(d));
1032
1033 /* Please don't send us buffers.
1034 */
1035 if (d.send_count != 0) {
1036 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1037 DRM_CURRENTPID, d.send_count);
1038 return DRM_ERR(EINVAL);
1039 }
1040
1041 /* We'll send you buffers.
1042 */
1043 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1044 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1045 DRM_CURRENTPID, d.request_count, dma->buf_count);
1046 return DRM_ERR(EINVAL);
1047 }
1048
1049 d.granted_count = 0;
1050
1051 if (d.request_count) {
1052 ret = savage_bci_get_buffers(filp, dev, &d);
1053 }
1054
1055 DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *) data, d, sizeof(d));
1056
1057 return ret;
1058 }
1059
1060 void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp)
1061 {
1062 drm_device_dma_t *dma = dev->dma;
1063 drm_savage_private_t *dev_priv = dev->dev_private;
1064 int i;
1065
1066 if (!dma)
1067 return;
1068 if (!dev_priv)
1069 return;
1070 if (!dma->buflist)
1071 return;
1072
1073 /*i830_flush_queue(dev); */
1074
1075 for (i = 0; i < dma->buf_count; i++) {
1076 drm_buf_t *buf = dma->buflist[i];
1077 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1078
1079 if (buf->filp == filp && buf_priv &&
1080 buf_priv->next == NULL && buf_priv->prev == NULL) {
1081 uint16_t event;
1082 DRM_DEBUG("reclaimed from client\n");
1083 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1084 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1085 savage_freelist_put(dev, buf);
1086 }
1087 }
1088
1089 drm_core_reclaim_buffers(dev, filp);
1090 }
1091
1092 drm_ioctl_desc_t savage_ioctls[] = {
1093 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1},
1094 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0},
1095 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0},
1096 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0},
1097 };
1098
1099 int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
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