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ext2: trivial indentation fix.
[linux-2.6/verdex.git] / drivers / char / drm / mga_dma.c
blob70dc7f64b7b9146c138a42bf97d3648854bb3c5c
1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 /**
29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400.
31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include "drmP.h"
39 #include "drm.h"
40 #include "drm_sarea.h"
41 #include "mga_drm.h"
42 #include "mga_drv.h"
43
44 #define MGA_DEFAULT_USEC_TIMEOUT 10000
45 #define MGA_FREELIST_DEBUG 0
46
47 static int mga_do_cleanup_dma(drm_device_t * dev);
48
49 /* ================================================================
50 * Engine control
51 */
52
53 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
54 {
55 u32 status = 0;
56 int i;
57 DRM_DEBUG("\n");
58
59 for (i = 0; i < dev_priv->usec_timeout; i++) {
60 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
61 if (status == MGA_ENDPRDMASTS) {
62 MGA_WRITE8(MGA_CRTC_INDEX, 0);
63 return 0;
64 }
65 DRM_UDELAY(1);
66 }
67
68 #if MGA_DMA_DEBUG
69 DRM_ERROR("failed!\n");
70 DRM_INFO(" status=0x%08x\n", status);
71 #endif
72 return DRM_ERR(EBUSY);
73 }
74
75 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
76 {
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
79
80 DRM_DEBUG("\n");
81
82 /* The primary DMA stream should look like new right about now.
83 */
84 primary->tail = 0;
85 primary->space = primary->size;
86 primary->last_flush = 0;
87
88 sarea_priv->last_wrap = 0;
89
90 /* FIXME: Reset counters, buffer ages etc...
91 */
92
93 /* FIXME: What else do we need to reinitialize? WARP stuff?
94 */
95
96 return 0;
97 }
98
99 /* ================================================================
100 * Primary DMA stream
101 */
102
103 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
104 {
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
106 u32 head, tail;
107 u32 status = 0;
108 int i;
109 DMA_LOCALS;
110 DRM_DEBUG("\n");
111
112 /* We need to wait so that we can do an safe flush */
113 for (i = 0; i < dev_priv->usec_timeout; i++) {
114 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
115 if (status == MGA_ENDPRDMASTS)
116 break;
117 DRM_UDELAY(1);
118 }
119
120 if (primary->tail == primary->last_flush) {
121 DRM_DEBUG(" bailing out...\n");
122 return;
123 }
124
125 tail = primary->tail + dev_priv->primary->offset;
126
127 /* We need to pad the stream between flushes, as the card
128 * actually (partially?) reads the first of these commands.
129 * See page 4-16 in the G400 manual, middle of the page or so.
130 */
131 BEGIN_DMA(1);
132
133 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
134 MGA_DMAPAD, 0x00000000,
135 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
136
137 ADVANCE_DMA();
138
139 primary->last_flush = primary->tail;
140
141 head = MGA_READ(MGA_PRIMADDRESS);
142
143 if (head <= tail) {
144 primary->space = primary->size - primary->tail;
145 } else {
146 primary->space = head - tail;
147 }
148
149 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
150 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
151 DRM_DEBUG(" space = 0x%06x\n", primary->space);
152
153 mga_flush_write_combine();
154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
155
156 DRM_DEBUG("done.\n");
157 }
158
159 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
160 {
161 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
162 u32 head, tail;
163 DMA_LOCALS;
164 DRM_DEBUG("\n");
165
166 BEGIN_DMA_WRAP();
167
168 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
169 MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
171
172 ADVANCE_DMA();
173
174 tail = primary->tail + dev_priv->primary->offset;
175
176 primary->tail = 0;
177 primary->last_flush = 0;
178 primary->last_wrap++;
179
180 head = MGA_READ(MGA_PRIMADDRESS);
181
182 if (head == dev_priv->primary->offset) {
183 primary->space = primary->size;
184 } else {
185 primary->space = head - dev_priv->primary->offset;
186 }
187
188 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
189 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
190 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
191 DRM_DEBUG(" space = 0x%06x\n", primary->space);
192
193 mga_flush_write_combine();
194 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
195
196 set_bit(0, &primary->wrapped);
197 DRM_DEBUG("done.\n");
198 }
199
200 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
201 {
202 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 u32 head = dev_priv->primary->offset;
205 DRM_DEBUG("\n");
206
207 sarea_priv->last_wrap++;
208 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
209
210 mga_flush_write_combine();
211 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
212
213 clear_bit(0, &primary->wrapped);
214 DRM_DEBUG("done.\n");
215 }
216
217 /* ================================================================
218 * Freelist management
219 */
220
221 #define MGA_BUFFER_USED ~0
222 #define MGA_BUFFER_FREE 0
223
224 #if MGA_FREELIST_DEBUG
225 static void mga_freelist_print(drm_device_t * dev)
226 {
227 drm_mga_private_t *dev_priv = dev->dev_private;
228 drm_mga_freelist_t *entry;
229
230 DRM_INFO("\n");
231 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
232 dev_priv->sarea_priv->last_dispatch,
233 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
234 dev_priv->primary->offset));
235 DRM_INFO("current freelist:\n");
236
237 for (entry = dev_priv->head->next; entry; entry = entry->next) {
238 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
239 entry, entry->buf->idx, entry->age.head,
240 entry->age.head - dev_priv->primary->offset);
241 }
242 DRM_INFO("\n");
243 }
244 #endif
245
246 static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
247 {
248 drm_device_dma_t *dma = dev->dma;
249 drm_buf_t *buf;
250 drm_mga_buf_priv_t *buf_priv;
251 drm_mga_freelist_t *entry;
252 int i;
253 DRM_DEBUG("count=%d\n", dma->buf_count);
254
255 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
256 if (dev_priv->head == NULL)
257 return DRM_ERR(ENOMEM);
258
259 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
260 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
261
262 for (i = 0; i < dma->buf_count; i++) {
263 buf = dma->buflist[i];
264 buf_priv = buf->dev_private;
265
266 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
267 if (entry == NULL)
268 return DRM_ERR(ENOMEM);
269
270 memset(entry, 0, sizeof(drm_mga_freelist_t));
271
272 entry->next = dev_priv->head->next;
273 entry->prev = dev_priv->head;
274 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
275 entry->buf = buf;
276
277 if (dev_priv->head->next != NULL)
278 dev_priv->head->next->prev = entry;
279 if (entry->next == NULL)
280 dev_priv->tail = entry;
281
282 buf_priv->list_entry = entry;
283 buf_priv->discard = 0;
284 buf_priv->dispatched = 0;
285
286 dev_priv->head->next = entry;
287 }
288
289 return 0;
290 }
291
292 static void mga_freelist_cleanup(drm_device_t * dev)
293 {
294 drm_mga_private_t *dev_priv = dev->dev_private;
295 drm_mga_freelist_t *entry;
296 drm_mga_freelist_t *next;
297 DRM_DEBUG("\n");
298
299 entry = dev_priv->head;
300 while (entry) {
301 next = entry->next;
302 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
303 entry = next;
304 }
305
306 dev_priv->head = dev_priv->tail = NULL;
307 }
308
309 #if 0
310 /* FIXME: Still needed?
311 */
312 static void mga_freelist_reset(drm_device_t * dev)
313 {
314 drm_device_dma_t *dma = dev->dma;
315 drm_buf_t *buf;
316 drm_mga_buf_priv_t *buf_priv;
317 int i;
318
319 for (i = 0; i < dma->buf_count; i++) {
320 buf = dma->buflist[i];
321 buf_priv = buf->dev_private;
322 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
323 }
324 }
325 #endif
326
327 static drm_buf_t *mga_freelist_get(drm_device_t * dev)
328 {
329 drm_mga_private_t *dev_priv = dev->dev_private;
330 drm_mga_freelist_t *next;
331 drm_mga_freelist_t *prev;
332 drm_mga_freelist_t *tail = dev_priv->tail;
333 u32 head, wrap;
334 DRM_DEBUG("\n");
335
336 head = MGA_READ(MGA_PRIMADDRESS);
337 wrap = dev_priv->sarea_priv->last_wrap;
338
339 DRM_DEBUG(" tail=0x%06lx %d\n",
340 tail->age.head ?
341 tail->age.head - dev_priv->primary->offset : 0,
342 tail->age.wrap);
343 DRM_DEBUG(" head=0x%06lx %d\n",
344 head - dev_priv->primary->offset, wrap);
345
346 if (TEST_AGE(&tail->age, head, wrap)) {
347 prev = dev_priv->tail->prev;
348 next = dev_priv->tail;
349 prev->next = NULL;
350 next->prev = next->next = NULL;
351 dev_priv->tail = prev;
352 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
353 return next->buf;
354 }
355
356 DRM_DEBUG("returning NULL!\n");
357 return NULL;
358 }
359
360 int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
361 {
362 drm_mga_private_t *dev_priv = dev->dev_private;
363 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
364 drm_mga_freelist_t *head, *entry, *prev;
365
366 DRM_DEBUG("age=0x%06lx wrap=%d\n",
367 buf_priv->list_entry->age.head -
368 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
369
370 entry = buf_priv->list_entry;
371 head = dev_priv->head;
372
373 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
374 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
375 prev = dev_priv->tail;
376 prev->next = entry;
377 entry->prev = prev;
378 entry->next = NULL;
379 } else {
380 prev = head->next;
381 head->next = entry;
382 prev->prev = entry;
383 entry->prev = head;
384 entry->next = prev;
385 }
386
387 return 0;
388 }
389
390 /* ================================================================
391 * DMA initialization, cleanup
392 */
393
394 int mga_driver_preinit(drm_device_t * dev, unsigned long flags)
395 {
396 drm_mga_private_t *dev_priv;
397
398 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
399 if (!dev_priv)
400 return DRM_ERR(ENOMEM);
401
402 dev->dev_private = (void *)dev_priv;
403 memset(dev_priv, 0, sizeof(drm_mga_private_t));
404
405 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
406 dev_priv->chipset = flags;
407
408 return 0;
409 }
410
411 #if __OS_HAS_AGP
412 /**
413 * Bootstrap the driver for AGP DMA.
414 *
415 * \todo
416 * Investigate whether there is any benifit to storing the WARP microcode in
417 * AGP memory. If not, the microcode may as well always be put in PCI
418 * memory.
419 *
420 * \todo
421 * This routine needs to set dma_bs->agp_mode to the mode actually configured
422 * in the hardware. Looking just at the Linux AGP driver code, I don't see
423 * an easy way to determine this.
424 *
425 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
426 */
427 static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
428 drm_mga_dma_bootstrap_t * dma_bs)
429 {
430 drm_mga_private_t *const dev_priv =
431 (drm_mga_private_t *) dev->dev_private;
432 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
433 int err;
434 unsigned offset;
435 const unsigned secondary_size = dma_bs->secondary_bin_count
436 * dma_bs->secondary_bin_size;
437 const unsigned agp_size = (dma_bs->agp_size << 20);
438 drm_buf_desc_t req;
439 drm_agp_mode_t mode;
440 drm_agp_info_t info;
441
442 /* Acquire AGP. */
443 err = drm_agp_acquire(dev);
444 if (err) {
445 DRM_ERROR("Unable to acquire AGP\n");
446 return err;
447 }
448
449 err = drm_agp_info(dev, &info);
450 if (err) {
451 DRM_ERROR("Unable to get AGP info\n");
452 return err;
453 }
454
455 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
456 err = drm_agp_enable(dev, mode);
457 if (err) {
458 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
459 return err;
460 }
461
462 /* In addition to the usual AGP mode configuration, the G200 AGP cards
463 * need to have the AGP mode "manually" set.
464 */
465
466 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
467 if (mode.mode & 0x02) {
468 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
469 } else {
470 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
471 }
472 }
473
474 /* Allocate and bind AGP memory. */
475 dev_priv->agp_pages = agp_size / PAGE_SIZE;
476 dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0);
477 if (dev_priv->agp_mem == NULL) {
478 dev_priv->agp_pages = 0;
479 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
480 dma_bs->agp_size);
481 return DRM_ERR(ENOMEM);
482 }
483
484 err = drm_bind_agp(dev_priv->agp_mem, 0);
485 if (err) {
486 DRM_ERROR("Unable to bind AGP memory\n");
487 return err;
488 }
489
490 /* Make drm_addbufs happy by not trying to create a mapping for less
491 * than a page.
492 */
493 if (warp_size < PAGE_SIZE)
494 warp_size = PAGE_SIZE;
495
496 offset = 0;
497 err = drm_addmap(dev, offset, warp_size,
498 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
499 if (err) {
500 DRM_ERROR("Unable to map WARP microcode\n");
501 return err;
502 }
503
504 offset += warp_size;
505 err = drm_addmap(dev, offset, dma_bs->primary_size,
506 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
507 if (err) {
508 DRM_ERROR("Unable to map primary DMA region\n");
509 return err;
510 }
511
512 offset += dma_bs->primary_size;
513 err = drm_addmap(dev, offset, secondary_size,
514 _DRM_AGP, 0, &dev->agp_buffer_map);
515 if (err) {
516 DRM_ERROR("Unable to map secondary DMA region\n");
517 return err;
518 }
519
520 (void)memset(&req, 0, sizeof(req));
521 req.count = dma_bs->secondary_bin_count;
522 req.size = dma_bs->secondary_bin_size;
523 req.flags = _DRM_AGP_BUFFER;
524 req.agp_start = offset;
525
526 err = drm_addbufs_agp(dev, &req);
527 if (err) {
528 DRM_ERROR("Unable to add secondary DMA buffers\n");
529 return err;
530 }
531
532 offset += secondary_size;
533 err = drm_addmap(dev, offset, agp_size - offset,
534 _DRM_AGP, 0, &dev_priv->agp_textures);
535 if (err) {
536 DRM_ERROR("Unable to map AGP texture region\n");
537 return err;
538 }
539
540 drm_core_ioremap(dev_priv->warp, dev);
541 drm_core_ioremap(dev_priv->primary, dev);
542 drm_core_ioremap(dev->agp_buffer_map, dev);
543
544 if (!dev_priv->warp->handle ||
545 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
546 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
547 dev_priv->warp->handle, dev_priv->primary->handle,
548 dev->agp_buffer_map->handle);
549 return DRM_ERR(ENOMEM);
550 }
551
552 dev_priv->dma_access = MGA_PAGPXFER;
553 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
554
555 DRM_INFO("Initialized card for AGP DMA.\n");
556 return 0;
557 }
558 #else
559 static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
560 drm_mga_dma_bootstrap_t * dma_bs)
561 {
562 return -EINVAL;
563 }
564 #endif
565
566 /**
567 * Bootstrap the driver for PCI DMA.
568 *
569 * \todo
570 * The algorithm for decreasing the size of the primary DMA buffer could be
571 * better. The size should be rounded up to the nearest page size, then
572 * decrease the request size by a single page each pass through the loop.
573 *
574 * \todo
575 * Determine whether the maximum address passed to drm_pci_alloc is correct.
576 * The same goes for drm_addbufs_pci.
577 *
578 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
579 */
580 static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
581 drm_mga_dma_bootstrap_t * dma_bs)
582 {
583 drm_mga_private_t *const dev_priv =
584 (drm_mga_private_t *) dev->dev_private;
585 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
586 unsigned int primary_size;
587 unsigned int bin_count;
588 int err;
589 drm_buf_desc_t req;
590
591 if (dev->dma == NULL) {
592 DRM_ERROR("dev->dma is NULL\n");
593 return DRM_ERR(EFAULT);
594 }
595
596 /* Make drm_addbufs happy by not trying to create a mapping for less
597 * than a page.
598 */
599 if (warp_size < PAGE_SIZE)
600 warp_size = PAGE_SIZE;
601
602 /* The proper alignment is 0x100 for this mapping */
603 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
604 _DRM_READ_ONLY, &dev_priv->warp);
605 if (err != 0) {
606 DRM_ERROR("Unable to create mapping for WARP microcode\n");
607 return err;
608 }
609
610 /* Other than the bottom two bits being used to encode other
611 * information, there don't appear to be any restrictions on the
612 * alignment of the primary or secondary DMA buffers.
613 */
614
615 for (primary_size = dma_bs->primary_size; primary_size != 0;
616 primary_size >>= 1) {
617 /* The proper alignment for this mapping is 0x04 */
618 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
619 _DRM_READ_ONLY, &dev_priv->primary);
620 if (!err)
621 break;
622 }
623
624 if (err != 0) {
625 DRM_ERROR("Unable to allocate primary DMA region\n");
626 return DRM_ERR(ENOMEM);
627 }
628
629 if (dev_priv->primary->size != dma_bs->primary_size) {
630 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
631 dma_bs->primary_size,
632 (unsigned)dev_priv->primary->size);
633 dma_bs->primary_size = dev_priv->primary->size;
634 }
635
636 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
637 bin_count--) {
638 (void)memset(&req, 0, sizeof(req));
639 req.count = bin_count;
640 req.size = dma_bs->secondary_bin_size;
641
642 err = drm_addbufs_pci(dev, &req);
643 if (!err) {
644 break;
645 }
646 }
647
648 if (bin_count == 0) {
649 DRM_ERROR("Unable to add secondary DMA buffers\n");
650 return err;
651 }
652
653 if (bin_count != dma_bs->secondary_bin_count) {
654 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
655 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
656
657 dma_bs->secondary_bin_count = bin_count;
658 }
659
660 dev_priv->dma_access = 0;
661 dev_priv->wagp_enable = 0;
662
663 dma_bs->agp_mode = 0;
664
665 DRM_INFO("Initialized card for PCI DMA.\n");
666 return 0;
667 }
668
669 static int mga_do_dma_bootstrap(drm_device_t * dev,
670 drm_mga_dma_bootstrap_t * dma_bs)
671 {
672 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
673 int err;
674 drm_mga_private_t *const dev_priv =
675 (drm_mga_private_t *) dev->dev_private;
676
677 dev_priv->used_new_dma_init = 1;
678
679 /* The first steps are the same for both PCI and AGP based DMA. Map
680 * the cards MMIO registers and map a status page.
681 */
682 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
683 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
684 if (err) {
685 DRM_ERROR("Unable to map MMIO region\n");
686 return err;
687 }
688
689 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
690 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
691 &dev_priv->status);
692 if (err) {
693 DRM_ERROR("Unable to map status region\n");
694 return err;
695 }
696
697 /* The DMA initialization procedure is slightly different for PCI and
698 * AGP cards. AGP cards just allocate a large block of AGP memory and
699 * carve off portions of it for internal uses. The remaining memory
700 * is returned to user-mode to be used for AGP textures.
701 */
702 if (is_agp) {
703 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
704 }
705
706 /* If we attempted to initialize the card for AGP DMA but failed,
707 * clean-up any mess that may have been created.
708 */
709
710 if (err) {
711 mga_do_cleanup_dma(dev);
712 }
713
714 /* Not only do we want to try and initialized PCI cards for PCI DMA,
715 * but we also try to initialized AGP cards that could not be
716 * initialized for AGP DMA. This covers the case where we have an AGP
717 * card in a system with an unsupported AGP chipset. In that case the
718 * card will be detected as AGP, but we won't be able to allocate any
719 * AGP memory, etc.
720 */
721
722 if (!is_agp || err) {
723 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
724 }
725
726 return err;
727 }
728
729 int mga_dma_bootstrap(DRM_IOCTL_ARGS)
730 {
731 DRM_DEVICE;
732 drm_mga_dma_bootstrap_t bootstrap;
733 int err;
734
735 DRM_COPY_FROM_USER_IOCTL(bootstrap,
736 (drm_mga_dma_bootstrap_t __user *) data,
737 sizeof(bootstrap));
738
739 err = mga_do_dma_bootstrap(dev, &bootstrap);
740 if (!err) {
741 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
742 const drm_mga_private_t *const dev_priv =
743 (drm_mga_private_t *) dev->dev_private;
744
745 if (dev_priv->agp_textures != NULL) {
746 bootstrap.texture_handle =
747 dev_priv->agp_textures->offset;
748 bootstrap.texture_size = dev_priv->agp_textures->size;
749 } else {
750 bootstrap.texture_handle = 0;
751 bootstrap.texture_size = 0;
752 }
753
754 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07];
755 if (DRM_COPY_TO_USER((void __user *)data, &bootstrap,
756 sizeof(bootstrap))) {
757 err = DRM_ERR(EFAULT);
758 }
759 } else {
760 mga_do_cleanup_dma(dev);
761 }
762
763 return err;
764 }
765
766 static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
767 {
768 drm_mga_private_t *dev_priv;
769 int ret;
770 DRM_DEBUG("\n");
771
772 dev_priv = dev->dev_private;
773
774 if (init->sgram) {
775 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
776 } else {
777 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
778 }
779 dev_priv->maccess = init->maccess;
780
781 dev_priv->fb_cpp = init->fb_cpp;
782 dev_priv->front_offset = init->front_offset;
783 dev_priv->front_pitch = init->front_pitch;
784 dev_priv->back_offset = init->back_offset;
785 dev_priv->back_pitch = init->back_pitch;
786
787 dev_priv->depth_cpp = init->depth_cpp;
788 dev_priv->depth_offset = init->depth_offset;
789 dev_priv->depth_pitch = init->depth_pitch;
790
791 /* FIXME: Need to support AGP textures...
792 */
793 dev_priv->texture_offset = init->texture_offset[0];
794 dev_priv->texture_size = init->texture_size[0];
795
796 DRM_GETSAREA();
797
798 if (!dev_priv->sarea) {
799 DRM_ERROR("failed to find sarea!\n");
800 return DRM_ERR(EINVAL);
801 }
802
803 if (!dev_priv->used_new_dma_init) {
804
805 dev_priv->dma_access = MGA_PAGPXFER;
806 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
807
808 dev_priv->status = drm_core_findmap(dev, init->status_offset);
809 if (!dev_priv->status) {
810 DRM_ERROR("failed to find status page!\n");
811 return DRM_ERR(EINVAL);
812 }
813 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
814 if (!dev_priv->mmio) {
815 DRM_ERROR("failed to find mmio region!\n");
816 return DRM_ERR(EINVAL);
817 }
818 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
819 if (!dev_priv->warp) {
820 DRM_ERROR("failed to find warp microcode region!\n");
821 return DRM_ERR(EINVAL);
822 }
823 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
824 if (!dev_priv->primary) {
825 DRM_ERROR("failed to find primary dma region!\n");
826 return DRM_ERR(EINVAL);
827 }
828 dev->agp_buffer_token = init->buffers_offset;
829 dev->agp_buffer_map =
830 drm_core_findmap(dev, init->buffers_offset);
831 if (!dev->agp_buffer_map) {
832 DRM_ERROR("failed to find dma buffer region!\n");
833 return DRM_ERR(EINVAL);
834 }
835
836 drm_core_ioremap(dev_priv->warp, dev);
837 drm_core_ioremap(dev_priv->primary, dev);
838 drm_core_ioremap(dev->agp_buffer_map, dev);
839 }
840
841 dev_priv->sarea_priv =
842 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
843 init->sarea_priv_offset);
844
845 if (!dev_priv->warp->handle ||
846 !dev_priv->primary->handle ||
847 ((dev_priv->dma_access != 0) &&
848 ((dev->agp_buffer_map == NULL) ||
849 (dev->agp_buffer_map->handle == NULL)))) {
850 DRM_ERROR("failed to ioremap agp regions!\n");
851 return DRM_ERR(ENOMEM);
852 }
853
854 ret = mga_warp_install_microcode(dev_priv);
855 if (ret < 0) {
856 DRM_ERROR("failed to install WARP ucode!\n");
857 return ret;
858 }
859
860 ret = mga_warp_init(dev_priv);
861 if (ret < 0) {
862 DRM_ERROR("failed to init WARP engine!\n");
863 return ret;
864 }
865
866 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
867
868 mga_do_wait_for_idle(dev_priv);
869
870 /* Init the primary DMA registers.
871 */
872 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
873 #if 0
874 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
875 MGA_PRIMPTREN1); /* DWGSYNC */
876 #endif
877
878 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
879 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
880 + dev_priv->primary->size);
881 dev_priv->prim.size = dev_priv->primary->size;
882
883 dev_priv->prim.tail = 0;
884 dev_priv->prim.space = dev_priv->prim.size;
885 dev_priv->prim.wrapped = 0;
886
887 dev_priv->prim.last_flush = 0;
888 dev_priv->prim.last_wrap = 0;
889
890 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
891
892 dev_priv->prim.status[0] = dev_priv->primary->offset;
893 dev_priv->prim.status[1] = 0;
894
895 dev_priv->sarea_priv->last_wrap = 0;
896 dev_priv->sarea_priv->last_frame.head = 0;
897 dev_priv->sarea_priv->last_frame.wrap = 0;
898
899 if (mga_freelist_init(dev, dev_priv) < 0) {
900 DRM_ERROR("could not initialize freelist\n");
901 return DRM_ERR(ENOMEM);
902 }
903
904 return 0;
905 }
906
907 static int mga_do_cleanup_dma(drm_device_t * dev)
908 {
909 int err = 0;
910 DRM_DEBUG("\n");
911
912 /* Make sure interrupts are disabled here because the uninstall ioctl
913 * may not have been called from userspace and after dev_private
914 * is freed, it's too late.
915 */
916 if (dev->irq_enabled)
917 drm_irq_uninstall(dev);
918
919 if (dev->dev_private) {
920 drm_mga_private_t *dev_priv = dev->dev_private;
921
922 if ((dev_priv->warp != NULL)
923 && (dev_priv->warp->type != _DRM_CONSISTENT))
924 drm_core_ioremapfree(dev_priv->warp, dev);
925
926 if ((dev_priv->primary != NULL)
927 && (dev_priv->primary->type != _DRM_CONSISTENT))
928 drm_core_ioremapfree(dev_priv->primary, dev);
929
930 if (dev->agp_buffer_map != NULL)
931 drm_core_ioremapfree(dev->agp_buffer_map, dev);
932
933 if (dev_priv->used_new_dma_init) {
934 #if __OS_HAS_AGP
935 if (dev_priv->agp_mem != NULL) {
936 dev_priv->agp_textures = NULL;
937 drm_unbind_agp(dev_priv->agp_mem);
938
939 drm_free_agp(dev_priv->agp_mem,
940 dev_priv->agp_pages);
941 dev_priv->agp_pages = 0;
942 dev_priv->agp_mem = NULL;
943 }
944
945 if ((dev->agp != NULL) && dev->agp->acquired) {
946 err = drm_agp_release(dev);
947 }
948 #endif
949 dev_priv->used_new_dma_init = 0;
950 }
951
952 dev_priv->warp = NULL;
953 dev_priv->primary = NULL;
954 dev_priv->mmio = NULL;
955 dev_priv->status = NULL;
956 dev_priv->sarea = NULL;
957 dev_priv->sarea_priv = NULL;
958 dev->agp_buffer_map = NULL;
959
960 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
961 dev_priv->warp_pipe = 0;
962 memset(dev_priv->warp_pipe_phys, 0,
963 sizeof(dev_priv->warp_pipe_phys));
964
965 if (dev_priv->head != NULL) {
966 mga_freelist_cleanup(dev);
967 }
968 }
969
970 return err;
971 }
972
973 int mga_dma_init(DRM_IOCTL_ARGS)
974 {
975 DRM_DEVICE;
976 drm_mga_init_t init;
977 int err;
978
979 LOCK_TEST_WITH_RETURN(dev, filp);
980
981 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
982 sizeof(init));
983
984 switch (init.func) {
985 case MGA_INIT_DMA:
986 err = mga_do_init_dma(dev, &init);
987 if (err) {
988 (void)mga_do_cleanup_dma(dev);
989 }
990 return err;
991 case MGA_CLEANUP_DMA:
992 return mga_do_cleanup_dma(dev);
993 }
994
995 return DRM_ERR(EINVAL);
996 }
997
998 /* ================================================================
999 * Primary DMA stream management
1000 */
1001
1002 int mga_dma_flush(DRM_IOCTL_ARGS)
1003 {
1004 DRM_DEVICE;
1005 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1006 drm_lock_t lock;
1007
1008 LOCK_TEST_WITH_RETURN(dev, filp);
1009
1010 DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
1011 sizeof(lock));
1012
1013 DRM_DEBUG("%s%s%s\n",
1014 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1015 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1016 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1017
1018 WRAP_WAIT_WITH_RETURN(dev_priv);
1019
1020 if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1021 mga_do_dma_flush(dev_priv);
1022 }
1023
1024 if (lock.flags & _DRM_LOCK_QUIESCENT) {
1025 #if MGA_DMA_DEBUG
1026 int ret = mga_do_wait_for_idle(dev_priv);
1027 if (ret < 0)
1028 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1029 return ret;
1030 #else
1031 return mga_do_wait_for_idle(dev_priv);
1032 #endif
1033 } else {
1034 return 0;
1035 }
1036 }
1037
1038 int mga_dma_reset(DRM_IOCTL_ARGS)
1039 {
1040 DRM_DEVICE;
1041 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1042
1043 LOCK_TEST_WITH_RETURN(dev, filp);
1044
1045 return mga_do_dma_reset(dev_priv);
1046 }
1047
1048 /* ================================================================
1049 * DMA buffer management
1050 */
1051
1052 static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
1053 {
1054 drm_buf_t *buf;
1055 int i;
1056
1057 for (i = d->granted_count; i < d->request_count; i++) {
1058 buf = mga_freelist_get(dev);
1059 if (!buf)
1060 return DRM_ERR(EAGAIN);
1061
1062 buf->filp = filp;
1063
1064 if (DRM_COPY_TO_USER(&d->request_indices[i],
1065 &buf->idx, sizeof(buf->idx)))
1066 return DRM_ERR(EFAULT);
1067 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1068 &buf->total, sizeof(buf->total)))
1069 return DRM_ERR(EFAULT);
1070
1071 d->granted_count++;
1072 }
1073 return 0;
1074 }
1075
1076 int mga_dma_buffers(DRM_IOCTL_ARGS)
1077 {
1078 DRM_DEVICE;
1079 drm_device_dma_t *dma = dev->dma;
1080 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1081 drm_dma_t __user *argp = (void __user *)data;
1082 drm_dma_t d;
1083 int ret = 0;
1084
1085 LOCK_TEST_WITH_RETURN(dev, filp);
1086
1087 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1088
1089 /* Please don't send us buffers.
1090 */
1091 if (d.send_count != 0) {
1092 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1093 DRM_CURRENTPID, d.send_count);
1094 return DRM_ERR(EINVAL);
1095 }
1096
1097 /* We'll send you buffers.
1098 */
1099 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1100 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1101 DRM_CURRENTPID, d.request_count, dma->buf_count);
1102 return DRM_ERR(EINVAL);
1103 }
1104
1105 WRAP_TEST_WITH_RETURN(dev_priv);
1106
1107 d.granted_count = 0;
1108
1109 if (d.request_count) {
1110 ret = mga_dma_get_buffers(filp, dev, &d);
1111 }
1112
1113 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1114
1115 return ret;
1116 }
1117
1118 /**
1119 * Called just before the module is unloaded.
1120 */
1121 int mga_driver_postcleanup(drm_device_t * dev)
1122 {
1123 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1124 dev->dev_private = NULL;
1125
1126 return 0;
1127 }
1128
1129 /**
1130 * Called when the last opener of the device is closed.
1131 */
1132 void mga_driver_pretakedown(drm_device_t * dev)
1133 {
1134 mga_do_cleanup_dma(dev);
1135 }
1136
1137 int mga_driver_dma_quiescent(drm_device_t * dev)
1138 {
1139 drm_mga_private_t *dev_priv = dev->dev_private;
1140 return mga_do_wait_for_idle(dev_priv);
1141 }
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