drivers/char/drm/drm.h

   1 /**
   2  * \file drm.h
   3  * Header for the Direct Rendering Manager
   4  *
   5  * \author Rickard E. (Rik) Faith <faith@valinux.com>
   6  *
   7  * \par Acknowledgments:
   8  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
   9  */
  10
  11 /*
  12  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  13  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  14  * All rights reserved.
  15  *
  16  * Permission is hereby granted, free of charge, to any person obtaining a
  17  * copy of this software and associated documentation files (the "Software"),
  18  * to deal in the Software without restriction, including without limitation
  19  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  20  * and/or sell copies of the Software, and to permit persons to whom the
  21  * Software is furnished to do so, subject to the following conditions:
  22  *
  23  * The above copyright notice and this permission notice (including the next
  24  * paragraph) shall be included in all copies or substantial portions of the
  25  * Software.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  28  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  29  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  30  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  31  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  32  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  33  * OTHER DEALINGS IN THE SOFTWARE.
  34  */
  35
  36 #ifndef _DRM_H_
  37 #define _DRM_H_
  38
  39 #if defined(__linux__)
  40 #if defined(__KERNEL__)
  41 #include <linux/config.h>
  42 #endif
  43 #include <asm/ioctl.h>          /* For _IO* macros */
  44 #define DRM_IOCTL_NR(n)         _IOC_NR(n)
  45 #define DRM_IOC_VOID            _IOC_NONE
  46 #define DRM_IOC_READ            _IOC_READ
  47 #define DRM_IOC_WRITE           _IOC_WRITE
  48 #define DRM_IOC_READWRITE       _IOC_READ|_IOC_WRITE
  49 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
  50 #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
  51 #if defined(__FreeBSD__) && defined(IN_MODULE)
  52 /* Prevent name collision when including sys/ioccom.h */
  53 #undef ioctl
  54 #include <sys/ioccom.h>
  55 #define ioctl(a,b,c)            xf86ioctl(a,b,c)
  56 #else
  57 #include <sys/ioccom.h>
  58 #endif                          /* __FreeBSD__ && xf86ioctl */
  59 #define DRM_IOCTL_NR(n)         ((n) & 0xff)
  60 #define DRM_IOC_VOID            IOC_VOID
  61 #define DRM_IOC_READ            IOC_OUT
  62 #define DRM_IOC_WRITE           IOC_IN
  63 #define DRM_IOC_READWRITE       IOC_INOUT
  64 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
  65 #endif
  66
  67 #define XFREE86_VERSION(major,minor,patch,snap) \
  68                 ((major << 16) | (minor << 8) | patch)
  69
  70 #ifndef CONFIG_XFREE86_VERSION
  71 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
  72 #endif
  73
  74 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
  75 #define DRM_PROC_DEVICES "/proc/devices"
  76 #define DRM_PROC_MISC    "/proc/misc"
  77 #define DRM_PROC_DRM     "/proc/drm"
  78 #define DRM_DEV_DRM      "/dev/drm"
  79 #define DRM_DEV_MODE     (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
  80 #define DRM_DEV_UID      0
  81 #define DRM_DEV_GID      0
  82 #endif
  83
  84 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
  85 #define DRM_MAJOR       226
  86 #define DRM_MAX_MINOR   15
  87 #endif
  88 #define DRM_NAME        "drm"     /**< Name in kernel, /dev, and /proc */
  89 #define DRM_MIN_ORDER   5         /**< At least 2^5 bytes = 32 bytes */
  90 #define DRM_MAX_ORDER   22        /**< Up to 2^22 bytes = 4MB */
  91 #define DRM_RAM_PERCENT 10        /**< How much system ram can we lock? */
  92
  93 #define _DRM_LOCK_HELD  0x80000000 /**< Hardware lock is held */
  94 #define _DRM_LOCK_CONT  0x40000000 /**< Hardware lock is contended */
  95 #define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
  96 #define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
  97 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
  98
  99 typedef unsigned int drm_handle_t;
 100 typedef unsigned int drm_context_t;
 101 typedef unsigned int drm_drawable_t;
 102 typedef unsigned int drm_magic_t;
 103
 104 /**
 105  * Cliprect.
 106  *
 107  * \warning: If you change this structure, make sure you change
 108  * XF86DRIClipRectRec in the server as well
 109  *
 110  * \note KW: Actually it's illegal to change either for
 111  * backwards-compatibility reasons.
 112  */
 113 typedef struct drm_clip_rect {
 114         unsigned short x1;
 115         unsigned short y1;
 116         unsigned short x2;
 117         unsigned short y2;
 118 } drm_clip_rect_t;
 119
 120 /**
 121  * Texture region,
 122  */
 123 typedef struct drm_tex_region {
 124         unsigned char next;
 125         unsigned char prev;
 126         unsigned char in_use;
 127         unsigned char padding;
 128         unsigned int age;
 129 } drm_tex_region_t;
 130
 131 /**
 132  * Hardware lock.
 133  *
 134  * The lock structure is a simple cache-line aligned integer.  To avoid
 135  * processor bus contention on a multiprocessor system, there should not be any
 136  * other data stored in the same cache line.
 137  */
 138 typedef struct drm_hw_lock {
 139         __volatile__ unsigned int lock;         /**< lock variable */
 140         char padding[60];                       /**< Pad to cache line */
 141 } drm_hw_lock_t;
 142
 143 /**
 144  * DRM_IOCTL_VERSION ioctl argument type.
 145  *
 146  * \sa drmGetVersion().
 147  */
 148 typedef struct drm_version {
 149         int version_major;        /**< Major version */
 150         int version_minor;        /**< Minor version */
 151         int version_patchlevel;   /**< Patch level */
 152         size_t name_len;          /**< Length of name buffer */
 153         char __user *name;        /**< Name of driver */
 154         size_t date_len;          /**< Length of date buffer */
 155         char __user *date;        /**< User-space buffer to hold date */
 156         size_t desc_len;          /**< Length of desc buffer */
 157         char __user *desc;        /**< User-space buffer to hold desc */
 158 } drm_version_t;
 159
 160 /**
 161  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
 162  *
 163  * \sa drmGetBusid() and drmSetBusId().
 164  */
 165 typedef struct drm_unique {
 166         size_t unique_len;        /**< Length of unique */
 167         char __user *unique;      /**< Unique name for driver instantiation */
 168 } drm_unique_t;
 169
 170 typedef struct drm_list {
 171         int count;                /**< Length of user-space structures */
 172         drm_version_t __user *version;
 173 } drm_list_t;
 174
 175 typedef struct drm_block {
 176         int unused;
 177 } drm_block_t;
 178
 179 /**
 180  * DRM_IOCTL_CONTROL ioctl argument type.
 181  *
 182  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
 183  */
 184 typedef struct drm_control {
 185         enum {
 186                 DRM_ADD_COMMAND,
 187                 DRM_RM_COMMAND,
 188                 DRM_INST_HANDLER,
 189                 DRM_UNINST_HANDLER
 190         } func;
 191         int irq;
 192 } drm_control_t;
 193
 194 /**
 195  * Type of memory to map.
 196  */
 197 typedef enum drm_map_type {
 198         _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
 199         _DRM_REGISTERS = 1,       /**< no caching, no core dump */
 200         _DRM_SHM = 2,             /**< shared, cached */
 201         _DRM_AGP = 3,             /**< AGP/GART */
 202         _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 203         _DRM_CONSISTENT = 5,      /**< Consistent memory for PCI DMA */
 204 } drm_map_type_t;
 205
 206 /**
 207  * Memory mapping flags.
 208  */
 209 typedef enum drm_map_flags {
 210         _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
 211         _DRM_READ_ONLY = 0x02,
 212         _DRM_LOCKED = 0x04,          /**< shared, cached, locked */
 213         _DRM_KERNEL = 0x08,          /**< kernel requires access */
 214         _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
 215         _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
 216         _DRM_REMOVABLE = 0x40        /**< Removable mapping */
 217 } drm_map_flags_t;
 218
 219 typedef struct drm_ctx_priv_map {
 220         unsigned int ctx_id;     /**< Context requesting private mapping */
 221         void *handle;            /**< Handle of map */
 222 } drm_ctx_priv_map_t;
 223
 224 /**
 225  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 226  * argument type.
 227  *
 228  * \sa drmAddMap().
 229  */
 230 typedef struct drm_map {
 231         unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
 232         unsigned long size;      /**< Requested physical size (bytes) */
 233         drm_map_type_t type;     /**< Type of memory to map */
 234         drm_map_flags_t flags;   /**< Flags */
 235         void *handle;            /**< User-space: "Handle" to pass to mmap() */
 236                                  /**< Kernel-space: kernel-virtual address */
 237         int mtrr;                /**< MTRR slot used */
 238         /*   Private data */
 239 } drm_map_t;
 240
 241 /**
 242  * DRM_IOCTL_GET_CLIENT ioctl argument type.
 243  */
 244 typedef struct drm_client {
 245         int idx;                /**< Which client desired? */
 246         int auth;               /**< Is client authenticated? */
 247         unsigned long pid;      /**< Process ID */
 248         unsigned long uid;      /**< User ID */
 249         unsigned long magic;    /**< Magic */
 250         unsigned long iocs;     /**< Ioctl count */
 251 } drm_client_t;
 252
 253 typedef enum {
 254         _DRM_STAT_LOCK,
 255         _DRM_STAT_OPENS,
 256         _DRM_STAT_CLOSES,
 257         _DRM_STAT_IOCTLS,
 258         _DRM_STAT_LOCKS,
 259         _DRM_STAT_UNLOCKS,
 260         _DRM_STAT_VALUE,        /**< Generic value */
 261         _DRM_STAT_BYTE,         /**< Generic byte counter (1024bytes/K) */
 262         _DRM_STAT_COUNT,        /**< Generic non-byte counter (1000/k) */
 263
 264         _DRM_STAT_IRQ,          /**< IRQ */
 265         _DRM_STAT_PRIMARY,      /**< Primary DMA bytes */
 266         _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
 267         _DRM_STAT_DMA,          /**< DMA */
 268         _DRM_STAT_SPECIAL,      /**< Special DMA (e.g., priority or polled) */
 269         _DRM_STAT_MISSED        /**< Missed DMA opportunity */
 270             /* Add to the *END* of the list */
 271 } drm_stat_type_t;
 272
 273 /**
 274  * DRM_IOCTL_GET_STATS ioctl argument type.
 275  */
 276 typedef struct drm_stats {
 277         unsigned long count;
 278         struct {
 279                 unsigned long value;
 280                 drm_stat_type_t type;
 281         } data[15];
 282 } drm_stats_t;
 283
 284 /**
 285  * Hardware locking flags.
 286  */
 287 typedef enum drm_lock_flags {
 288         _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
 289         _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
 290         _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
 291         _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
 292         /* These *HALT* flags aren't supported yet
 293            -- they will be used to support the
 294            full-screen DGA-like mode. */
 295         _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 296         _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 297 } drm_lock_flags_t;
 298
 299 /**
 300  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 301  *
 302  * \sa drmGetLock() and drmUnlock().
 303  */
 304 typedef struct drm_lock {
 305         int context;
 306         drm_lock_flags_t flags;
 307 } drm_lock_t;
 308
 309 /**
 310  * DMA flags
 311  *
 312  * \warning
 313  * These values \e must match xf86drm.h.
 314  *
 315  * \sa drm_dma.
 316  */
 317 typedef enum drm_dma_flags {
 318         /* Flags for DMA buffer dispatch */
 319         _DRM_DMA_BLOCK = 0x01,        /**<
 320                                        * Block until buffer dispatched.
 321                                        *
 322                                        * \note The buffer may not yet have
 323                                        * been processed by the hardware --
 324                                        * getting a hardware lock with the
 325                                        * hardware quiescent will ensure
 326                                        * that the buffer has been
 327                                        * processed.
 328                                        */
 329         _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
 330         _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 331
 332         /* Flags for DMA buffer request */
 333         _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
 334         _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
 335         _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 336 } drm_dma_flags_t;
 337
 338 /**
 339  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 340  *
 341  * \sa drmAddBufs().
 342  */
 343 typedef struct drm_buf_desc {
 344         int count;               /**< Number of buffers of this size */
 345         int size;                /**< Size in bytes */
 346         int low_mark;            /**< Low water mark */
 347         int high_mark;           /**< High water mark */
 348         enum {
 349                 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
 350                 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
 351                 _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
 352                 _DRM_FB_BUFFER = 0x08   /**< Buffer is in frame buffer */
 353         } flags;
 354         unsigned long agp_start; /**<
 355                                   * Start address of where the AGP buffers are
 356                                   * in the AGP aperture
 357                                   */
 358 } drm_buf_desc_t;
 359
 360 /**
 361  * DRM_IOCTL_INFO_BUFS ioctl argument type.
 362  */
 363 typedef struct drm_buf_info {
 364         int count;              /**< Entries in list */
 365         drm_buf_desc_t __user *list;
 366 } drm_buf_info_t;
 367
 368 /**
 369  * DRM_IOCTL_FREE_BUFS ioctl argument type.
 370  */
 371 typedef struct drm_buf_free {
 372         int count;
 373         int __user *list;
 374 } drm_buf_free_t;
 375
 376 /**
 377  * Buffer information
 378  *
 379  * \sa drm_buf_map.
 380  */
 381 typedef struct drm_buf_pub {
 382         int idx;                       /**< Index into the master buffer list */
 383         int total;                     /**< Buffer size */
 384         int used;                      /**< Amount of buffer in use (for DMA) */
 385         void __user *address;          /**< Address of buffer */
 386 } drm_buf_pub_t;
 387
 388 /**
 389  * DRM_IOCTL_MAP_BUFS ioctl argument type.
 390  */
 391 typedef struct drm_buf_map {
 392         int count;              /**< Length of the buffer list */
 393         void __user *virtual;           /**< Mmap'd area in user-virtual */
 394         drm_buf_pub_t __user *list;     /**< Buffer information */
 395 } drm_buf_map_t;
 396
 397 /**
 398  * DRM_IOCTL_DMA ioctl argument type.
 399  *
 400  * Indices here refer to the offset into the buffer list in drm_buf_get.
 401  *
 402  * \sa drmDMA().
 403  */
 404 typedef struct drm_dma {
 405         int context;                      /**< Context handle */
 406         int send_count;                   /**< Number of buffers to send */
 407         int __user *send_indices;         /**< List of handles to buffers */
 408         int __user *send_sizes;           /**< Lengths of data to send */
 409         drm_dma_flags_t flags;            /**< Flags */
 410         int request_count;                /**< Number of buffers requested */
 411         int request_size;                 /**< Desired size for buffers */
 412         int __user *request_indices;      /**< Buffer information */
 413         int __user *request_sizes;
 414         int granted_count;                /**< Number of buffers granted */
 415 } drm_dma_t;
 416
 417 typedef enum {
 418         _DRM_CONTEXT_PRESERVED = 0x01,
 419         _DRM_CONTEXT_2DONLY = 0x02
 420 } drm_ctx_flags_t;
 421
 422 /**
 423  * DRM_IOCTL_ADD_CTX ioctl argument type.
 424  *
 425  * \sa drmCreateContext() and drmDestroyContext().
 426  */
 427 typedef struct drm_ctx {
 428         drm_context_t handle;
 429         drm_ctx_flags_t flags;
 430 } drm_ctx_t;
 431
 432 /**
 433  * DRM_IOCTL_RES_CTX ioctl argument type.
 434  */
 435 typedef struct drm_ctx_res {
 436         int count;
 437         drm_ctx_t __user *contexts;
 438 } drm_ctx_res_t;
 439
 440 /**
 441  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 442  */
 443 typedef struct drm_draw {
 444         drm_drawable_t handle;
 445 } drm_draw_t;
 446
 447 /**
 448  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 449  */
 450 typedef struct drm_auth {
 451         drm_magic_t magic;
 452 } drm_auth_t;
 453
 454 /**
 455  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 456  *
 457  * \sa drmGetInterruptFromBusID().
 458  */
 459 typedef struct drm_irq_busid {
 460         int irq;        /**< IRQ number */
 461         int busnum;     /**< bus number */
 462         int devnum;     /**< device number */
 463         int funcnum;    /**< function number */
 464 } drm_irq_busid_t;
 465
 466 typedef enum {
 467         _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
 468         _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
 469         _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
 470 } drm_vblank_seq_type_t;
 471
 472 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
 473
 474 struct drm_wait_vblank_request {
 475         drm_vblank_seq_type_t type;
 476         unsigned int sequence;
 477         unsigned long signal;
 478 };
 479
 480 struct drm_wait_vblank_reply {
 481         drm_vblank_seq_type_t type;
 482         unsigned int sequence;
 483         long tval_sec;
 484         long tval_usec;
 485 };
 486
 487 /**
 488  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 489  *
 490  * \sa drmWaitVBlank().
 491  */
 492 typedef union drm_wait_vblank {
 493         struct drm_wait_vblank_request request;
 494         struct drm_wait_vblank_reply reply;
 495 } drm_wait_vblank_t;
 496
 497 /**
 498  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 499  *
 500  * \sa drmAgpEnable().
 501  */
 502 typedef struct drm_agp_mode {
 503         unsigned long mode;     /**< AGP mode */
 504 } drm_agp_mode_t;
 505
 506 /**
 507  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 508  *
 509  * \sa drmAgpAlloc() and drmAgpFree().
 510  */
 511 typedef struct drm_agp_buffer {
 512         unsigned long size;     /**< In bytes -- will round to page boundary */
 513         unsigned long handle;   /**< Used for binding / unbinding */
 514         unsigned long type;     /**< Type of memory to allocate */
 515         unsigned long physical; /**< Physical used by i810 */
 516 } drm_agp_buffer_t;
 517
 518 /**
 519  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 520  *
 521  * \sa drmAgpBind() and drmAgpUnbind().
 522  */
 523 typedef struct drm_agp_binding {
 524         unsigned long handle;   /**< From drm_agp_buffer */
 525         unsigned long offset;   /**< In bytes -- will round to page boundary */
 526 } drm_agp_binding_t;
 527
 528 /**
 529  * DRM_IOCTL_AGP_INFO ioctl argument type.
 530  *
 531  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 532  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 533  * drmAgpVendorId() and drmAgpDeviceId().
 534  */
 535 typedef struct drm_agp_info {
 536         int agp_version_major;
 537         int agp_version_minor;
 538         unsigned long mode;
 539         unsigned long aperture_base;    /* physical address */
 540         unsigned long aperture_size;    /* bytes */
 541         unsigned long memory_allowed;   /* bytes */
 542         unsigned long memory_used;
 543
 544         /* PCI information */
 545         unsigned short id_vendor;
 546         unsigned short id_device;
 547 } drm_agp_info_t;
 548
 549 /**
 550  * DRM_IOCTL_SG_ALLOC ioctl argument type.
 551  */
 552 typedef struct drm_scatter_gather {
 553         unsigned long size;     /**< In bytes -- will round to page boundary */
 554         unsigned long handle;   /**< Used for mapping / unmapping */
 555 } drm_scatter_gather_t;
 556
 557 /**
 558  * DRM_IOCTL_SET_VERSION ioctl argument type.
 559  */
 560 typedef struct drm_set_version {
 561         int drm_di_major;
 562         int drm_di_minor;
 563         int drm_dd_major;
 564         int drm_dd_minor;
 565 } drm_set_version_t;
 566
 567 #define DRM_IOCTL_BASE                  'd'
 568 #define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
 569 #define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
 570 #define DRM_IOW(nr,type)                _IOW(DRM_IOCTL_BASE,nr,type)
 571 #define DRM_IOWR(nr,type)               _IOWR(DRM_IOCTL_BASE,nr,type)
 572
 573 #define DRM_IOCTL_VERSION               DRM_IOWR(0x00, drm_version_t)
 574 #define DRM_IOCTL_GET_UNIQUE            DRM_IOWR(0x01, drm_unique_t)
 575 #define DRM_IOCTL_GET_MAGIC             DRM_IOR( 0x02, drm_auth_t)
 576 #define DRM_IOCTL_IRQ_BUSID             DRM_IOWR(0x03, drm_irq_busid_t)
 577 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, drm_map_t)
 578 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, drm_client_t)
 579 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, drm_stats_t)
 580 #define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, drm_set_version_t)
 581
 582 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, drm_unique_t)
 583 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, drm_auth_t)
 584 #define DRM_IOCTL_BLOCK                 DRM_IOWR(0x12, drm_block_t)
 585 #define DRM_IOCTL_UNBLOCK               DRM_IOWR(0x13, drm_block_t)
 586 #define DRM_IOCTL_CONTROL               DRM_IOW( 0x14, drm_control_t)
 587 #define DRM_IOCTL_ADD_MAP               DRM_IOWR(0x15, drm_map_t)
 588 #define DRM_IOCTL_ADD_BUFS              DRM_IOWR(0x16, drm_buf_desc_t)
 589 #define DRM_IOCTL_MARK_BUFS             DRM_IOW( 0x17, drm_buf_desc_t)
 590 #define DRM_IOCTL_INFO_BUFS             DRM_IOWR(0x18, drm_buf_info_t)
 591 #define DRM_IOCTL_MAP_BUFS              DRM_IOWR(0x19, drm_buf_map_t)
 592 #define DRM_IOCTL_FREE_BUFS             DRM_IOW( 0x1a, drm_buf_free_t)
 593
 594 #define DRM_IOCTL_RM_MAP                DRM_IOW( 0x1b, drm_map_t)
 595
 596 #define DRM_IOCTL_SET_SAREA_CTX         DRM_IOW( 0x1c, drm_ctx_priv_map_t)
 597 #define DRM_IOCTL_GET_SAREA_CTX         DRM_IOWR(0x1d, drm_ctx_priv_map_t)
 598
 599 #define DRM_IOCTL_ADD_CTX               DRM_IOWR(0x20, drm_ctx_t)
 600 #define DRM_IOCTL_RM_CTX                DRM_IOWR(0x21, drm_ctx_t)
 601 #define DRM_IOCTL_MOD_CTX               DRM_IOW( 0x22, drm_ctx_t)
 602 #define DRM_IOCTL_GET_CTX               DRM_IOWR(0x23, drm_ctx_t)
 603 #define DRM_IOCTL_SWITCH_CTX            DRM_IOW( 0x24, drm_ctx_t)
 604 #define DRM_IOCTL_NEW_CTX               DRM_IOW( 0x25, drm_ctx_t)
 605 #define DRM_IOCTL_RES_CTX               DRM_IOWR(0x26, drm_ctx_res_t)
 606 #define DRM_IOCTL_ADD_DRAW              DRM_IOWR(0x27, drm_draw_t)
 607 #define DRM_IOCTL_RM_DRAW               DRM_IOWR(0x28, drm_draw_t)
 608 #define DRM_IOCTL_DMA                   DRM_IOWR(0x29, drm_dma_t)
 609 #define DRM_IOCTL_LOCK                  DRM_IOW( 0x2a, drm_lock_t)
 610 #define DRM_IOCTL_UNLOCK                DRM_IOW( 0x2b, drm_lock_t)
 611 #define DRM_IOCTL_FINISH                DRM_IOW( 0x2c, drm_lock_t)
 612
 613 #define DRM_IOCTL_AGP_ACQUIRE           DRM_IO(  0x30)
 614 #define DRM_IOCTL_AGP_RELEASE           DRM_IO(  0x31)
 615 #define DRM_IOCTL_AGP_ENABLE            DRM_IOW( 0x32, drm_agp_mode_t)
 616 #define DRM_IOCTL_AGP_INFO              DRM_IOR( 0x33, drm_agp_info_t)
 617 #define DRM_IOCTL_AGP_ALLOC             DRM_IOWR(0x34, drm_agp_buffer_t)
 618 #define DRM_IOCTL_AGP_FREE              DRM_IOW( 0x35, drm_agp_buffer_t)
 619 #define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, drm_agp_binding_t)
 620 #define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, drm_agp_binding_t)
 621
 622 #define DRM_IOCTL_SG_ALLOC              DRM_IOW( 0x38, drm_scatter_gather_t)
 623 #define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, drm_scatter_gather_t)
 624
 625 #define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, drm_wait_vblank_t)
 626
 627 /**
 628  * Device specific ioctls should only be in their respective headers
 629  * The device specific ioctl range is from 0x40 to 0x79.
 630  *
 631  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 632  * drmCommandReadWrite().
 633  */
 634 #define DRM_COMMAND_BASE                0x40
 635
 636 #endif