?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (10871): stv0900: delete debug messages not related to stv0900 tuning algorythm
[linux-2.6/verdex.git] / drivers / media / dvb / frontends / stv0900_core.c
blob3cc6626fe633a837640977fb709f2c19e04ce6d2
1 /*
2 * stv0900_core.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
31
32 #include "stv0900.h"
33 #include "stv0900_reg.h"
34 #include "stv0900_priv.h"
35 #include "stv0900_init.h"
36
37 static int stvdebug = 1;
38 module_param_named(debug, stvdebug, int, 0644);
39
40 /* internal params node */
41 struct stv0900_inode {
42 /* pointer for internal params, one for each pair of demods */
43 struct stv0900_internal *internal;
44 struct stv0900_inode *next_inode;
45 };
46
47 /* first internal params */
48 static struct stv0900_inode *stv0900_first_inode;
49
50 /* find chip by i2c adapter and i2c address */
51 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
52 u8 i2c_addr)
53 {
54 struct stv0900_inode *temp_chip = stv0900_first_inode;
55
56 if (temp_chip != NULL) {
57 /*
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_chip != NULL) &&
61 ((temp_chip->internal->i2c_adap != i2c_adap) ||
62 (temp_chip->internal->i2c_addr != i2c_addr)))
63
64 temp_chip = temp_chip->next_inode;
65
66 }
67
68 return temp_chip;
69 }
70
71 /* deallocating chip */
72 static void remove_inode(struct stv0900_internal *internal)
73 {
74 struct stv0900_inode *prev_node = stv0900_first_inode;
75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
76 internal->i2c_addr);
77
78 if (del_node != NULL) {
79 if (del_node == stv0900_first_inode) {
80 stv0900_first_inode = del_node->next_inode;
81 } else {
82 while (prev_node->next_inode != del_node)
83 prev_node = prev_node->next_inode;
84
85 if (del_node->next_inode == NULL)
86 prev_node->next_inode = NULL;
87 else
88 prev_node->next_inode =
89 prev_node->next_inode->next_inode;
90 }
91
92 kfree(del_node);
93 }
94 }
95
96 /* allocating new chip */
97 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
98 {
99 struct stv0900_inode *new_node = stv0900_first_inode;
100
101 if (new_node == NULL) {
102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
103 stv0900_first_inode = new_node;
104 } else {
105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode;
107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
109 if (new_node->next_inode != NULL)
110 new_node = new_node->next_inode;
111 else
112 new_node = NULL;
113 }
114
115 if (new_node != NULL) {
116 new_node->internal = internal;
117 new_node->next_inode = NULL;
118 }
119
120 return new_node;
121 }
122
123 s32 ge2comp(s32 a, s32 width)
124 {
125 if (width == 32)
126 return a;
127 else
128 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
129 }
130
131 void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
132 u8 reg_data)
133 {
134 u8 data[3];
135 int ret;
136 struct i2c_msg i2cmsg = {
137 .addr = i_params->i2c_addr,
138 .flags = 0,
139 .len = 3,
140 .buf = data,
141 };
142
143 data[0] = MSB(reg_addr);
144 data[1] = LSB(reg_addr);
145 data[2] = reg_data;
146
147 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
148 if (ret != 1)
149 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
150 }
151
152 u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg_addr)
153 {
154 u8 data[2];
155 int ret;
156 struct i2c_msg i2cmsg = {
157 .addr = i_params->i2c_addr,
158 .flags = 0,
159 .len = 2,
160 .buf = data,
161 };
162
163 data[0] = MSB(reg_addr);
164 data[1] = LSB(reg_addr);
165
166 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
167 if (ret != 1)
168 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
169
170 i2cmsg.flags = I2C_M_RD;
171 i2cmsg.len = 1;
172 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
173 if (ret != 1)
174 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
175
176 return data[0];
177 }
178
179 void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
180 {
181 u8 position = 0, i = 0;
182
183 (*mask) = label & 0xff;
184
185 while ((position == 0) && (i < 8)) {
186 position = ((*mask) >> i) & 0x01;
187 i++;
188 }
189
190 (*pos) = (i - 1);
191 }
192
193 void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
194 {
195 u8 reg, mask, pos;
196
197 reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
198 extract_mask_pos(label, &mask, &pos);
199
200 val = mask & (val << pos);
201
202 reg = (reg & (~mask)) | val;
203 stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
204
205 }
206
207 u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
208 {
209 u8 val = 0xff;
210 u8 mask, pos;
211
212 extract_mask_pos(label, &mask, &pos);
213
214 val = stv0900_read_reg(i_params, label >> 16);
215 val = (val & mask) >> pos;
216
217 return val;
218 }
219
220 enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
221 {
222 s32 i;
223 enum fe_stv0900_error error;
224
225 if (i_params != NULL) {
226 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
227 if (i_params->errs == STV0900_NO_ERROR) {
228 /*Startup sequence*/
229 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
230 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
231 stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
232 stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
233 stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x24);
234 stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x24);
235 stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
236 msleep(3);
237 stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
238
239 switch (i_params->clkmode) {
240 case 0:
241 case 2:
242 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
243 | i_params->clkmode);
244 break;
245 default:
246 /* preserve SELOSCI bit */
247 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
248 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
249 break;
250 }
251
252 msleep(3);
253 for (i = 0; i < 180; i++)
254 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
255
256 if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
257 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
258 for (i = 0; i < 32; i++)
259 stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
260 }
261
262 stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
263 stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
264 stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
266 }
267 error = i_params->errs;
268 } else
269 error = STV0900_INVALID_HANDLE;
270
271 return error;
272
273 }
274
275 u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
276 {
277 u32 mclk = 90000000, div = 0, ad_div = 0;
278
279 div = stv0900_get_bits(i_params, F0900_M_DIV);
280 ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
281
282 mclk = (div + 1) * ext_clk / ad_div;
283
284 dprintk(KERN_INFO "%s: Calculated Mclk = %d\n", __func__, mclk);
285
286 return mclk;
287 }
288
289 enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
290 {
291 enum fe_stv0900_error error = STV0900_NO_ERROR;
292 u32 m_div, clk_sel;
293
294 dprintk(KERN_INFO "%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
295 i_params->quartz);
296
297 if (i_params == NULL)
298 error = STV0900_INVALID_HANDLE;
299 else {
300 if (i_params->errs)
301 error = STV0900_I2C_ERROR;
302 else {
303 clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
304 m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
305 stv0900_write_bits(i_params, F0900_M_DIV, m_div);
306 i_params->mclk = stv0900_get_mclk_freq(i_params,
307 i_params->quartz);
308
309 /*Set the DiseqC frequency to 22KHz */
310 /*
311 Formula:
312 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
313 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
314 */
315 m_div = i_params->mclk / 704000;
316 stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
317 stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
318
319 stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
320 stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
321
322 if ((i_params->errs))
323 error = STV0900_I2C_ERROR;
324 }
325 }
326
327 return error;
328 }
329
330 u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
331 enum fe_stv0900_demod_num demod)
332 {
333 u32 lsb, msb, hsb, err_val;
334 s32 err1field_hsb, err1field_msb, err1field_lsb;
335 s32 err2field_hsb, err2field_msb, err2field_lsb;
336
337 dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
338 dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
339 dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
340
341 dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
342 dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
343 dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
344
345 switch (cntr) {
346 case 0:
347 default:
348 hsb = stv0900_get_bits(i_params, err1field_hsb);
349 msb = stv0900_get_bits(i_params, err1field_msb);
350 lsb = stv0900_get_bits(i_params, err1field_lsb);
351 break;
352 case 1:
353 hsb = stv0900_get_bits(i_params, err2field_hsb);
354 msb = stv0900_get_bits(i_params, err2field_msb);
355 lsb = stv0900_get_bits(i_params, err2field_lsb);
356 break;
357 }
358
359 err_val = (hsb << 16) + (msb << 8) + (lsb);
360
361 return err_val;
362 }
363
364 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
365 {
366 struct stv0900_state *state = fe->demodulator_priv;
367 struct stv0900_internal *i_params = state->internal;
368 enum fe_stv0900_demod_num demod = state->demod;
369
370 u32 fi2c;
371
372 dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
373 if (enable)
374 stv0900_write_bits(i_params, fi2c, 1);
375
376 return 0;
377 }
378
379 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
380 enum fe_stv0900_clock_type path1_ts,
381 enum fe_stv0900_clock_type path2_ts)
382 {
383
384 dprintk(KERN_INFO "%s\n", __func__);
385
386 if (i_params->chip_id >= 0x20) {
387 switch (path1_ts) {
388 case STV0900_PARALLEL_PUNCT_CLOCK:
389 case STV0900_DVBCI_CLOCK:
390 switch (path2_ts) {
391 case STV0900_SERIAL_PUNCT_CLOCK:
392 case STV0900_SERIAL_CONT_CLOCK:
393 default:
394 stv0900_write_reg(i_params, R0900_TSGENERAL,
395 0x00);
396 break;
397 case STV0900_PARALLEL_PUNCT_CLOCK:
398 case STV0900_DVBCI_CLOCK:
399 stv0900_write_reg(i_params, R0900_TSGENERAL,
400 0x06);
401 stv0900_write_bits(i_params,
402 F0900_P1_TSFIFO_MANSPEED, 3);
403 stv0900_write_bits(i_params,
404 F0900_P2_TSFIFO_MANSPEED, 0);
405 stv0900_write_reg(i_params,
406 R0900_P1_TSSPEED, 0x14);
407 stv0900_write_reg(i_params,
408 R0900_P2_TSSPEED, 0x28);
409 break;
410 }
411 break;
412 case STV0900_SERIAL_PUNCT_CLOCK:
413 case STV0900_SERIAL_CONT_CLOCK:
414 default:
415 switch (path2_ts) {
416 case STV0900_SERIAL_PUNCT_CLOCK:
417 case STV0900_SERIAL_CONT_CLOCK:
418 default:
419 stv0900_write_reg(i_params,
420 R0900_TSGENERAL, 0x0C);
421 break;
422 case STV0900_PARALLEL_PUNCT_CLOCK:
423 case STV0900_DVBCI_CLOCK:
424 stv0900_write_reg(i_params,
425 R0900_TSGENERAL, 0x0A);
426 dprintk(KERN_INFO "%s: 0x0a\n", __func__);
427 break;
428 }
429 break;
430 }
431 } else {
432 switch (path1_ts) {
433 case STV0900_PARALLEL_PUNCT_CLOCK:
434 case STV0900_DVBCI_CLOCK:
435 switch (path2_ts) {
436 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK:
438 default:
439 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
440 0x10);
441 break;
442 case STV0900_PARALLEL_PUNCT_CLOCK:
443 case STV0900_DVBCI_CLOCK:
444 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
445 0x16);
446 stv0900_write_bits(i_params,
447 F0900_P1_TSFIFO_MANSPEED, 3);
448 stv0900_write_bits(i_params,
449 F0900_P2_TSFIFO_MANSPEED, 0);
450 stv0900_write_reg(i_params, R0900_P1_TSSPEED,
451 0x14);
452 stv0900_write_reg(i_params, R0900_P2_TSSPEED,
453 0x28);
454 break;
455 }
456
457 break;
458 case STV0900_SERIAL_PUNCT_CLOCK:
459 case STV0900_SERIAL_CONT_CLOCK:
460 default:
461 switch (path2_ts) {
462 case STV0900_SERIAL_PUNCT_CLOCK:
463 case STV0900_SERIAL_CONT_CLOCK:
464 default:
465 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
466 0x14);
467 break;
468 case STV0900_PARALLEL_PUNCT_CLOCK:
469 case STV0900_DVBCI_CLOCK:
470 stv0900_write_reg(i_params, R0900_TSGENERAL1X,
471 0x12);
472 dprintk(KERN_INFO "%s: 0x12\n", __func__);
473 break;
474 }
475
476 break;
477 }
478 }
479
480 switch (path1_ts) {
481 case STV0900_PARALLEL_PUNCT_CLOCK:
482 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
483 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
484 break;
485 case STV0900_DVBCI_CLOCK:
486 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
487 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
488 break;
489 case STV0900_SERIAL_PUNCT_CLOCK:
490 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
491 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
492 break;
493 case STV0900_SERIAL_CONT_CLOCK:
494 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
495 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
496 break;
497 default:
498 break;
499 }
500
501 switch (path2_ts) {
502 case STV0900_PARALLEL_PUNCT_CLOCK:
503 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
504 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
505 break;
506 case STV0900_DVBCI_CLOCK:
507 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
508 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
509 break;
510 case STV0900_SERIAL_PUNCT_CLOCK:
511 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
512 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
513 break;
514 case STV0900_SERIAL_CONT_CLOCK:
515 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
516 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
517 break;
518 default:
519 break;
520 }
521
522 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
523 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
524 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
525 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
526 }
527
528 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
529 u32 bandwidth)
530 {
531 struct dvb_frontend_ops *frontend_ops = NULL;
532 struct dvb_tuner_ops *tuner_ops = NULL;
533
534 if (&fe->ops)
535 frontend_ops = &fe->ops;
536
537 if (&frontend_ops->tuner_ops)
538 tuner_ops = &frontend_ops->tuner_ops;
539
540 if (tuner_ops->set_frequency) {
541 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
542 dprintk("%s: Invalid parameter\n", __func__);
543 else
544 dprintk("%s: Frequency=%d\n", __func__, frequency);
545
546 }
547
548 if (tuner_ops->set_bandwidth) {
549 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
550 dprintk("%s: Invalid parameter\n", __func__);
551 else
552 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
553
554 }
555 }
556
557 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
558 {
559 struct dvb_frontend_ops *frontend_ops = NULL;
560 struct dvb_tuner_ops *tuner_ops = NULL;
561
562 if (&fe->ops)
563 frontend_ops = &fe->ops;
564
565 if (&frontend_ops->tuner_ops)
566 tuner_ops = &frontend_ops->tuner_ops;
567
568 if (tuner_ops->set_bandwidth) {
569 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
570 dprintk("%s: Invalid parameter\n", __func__);
571 else
572 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
573
574 }
575 }
576
577 static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
578 const struct stv0900_table *lookup,
579 enum fe_stv0900_demod_num demod)
580 {
581 s32 agc_gain = 0,
582 imin,
583 imax,
584 i,
585 rf_lvl = 0;
586
587 dprintk(KERN_INFO "%s\n", __func__);
588
589 if ((lookup != NULL) && lookup->size) {
590 switch (demod) {
591 case STV0900_DEMOD_1:
592 default:
593 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
594 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
595 break;
596 case STV0900_DEMOD_2:
597 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
598 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
599 break;
600 }
601
602 imin = 0;
603 imax = lookup->size - 1;
604 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
605 while ((imax - imin) > 1) {
606 i = (imax + imin) >> 1;
607
608 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
609 imax = i;
610 else
611 imin = i;
612 }
613
614 rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
615 * (lookup->table[imax].realval - lookup->table[imin].realval)
616 / (lookup->table[imax].regval - lookup->table[imin].regval))
617 + lookup->table[imin].realval;
618 } else if (agc_gain > lookup->table[0].regval)
619 rf_lvl = 5;
620 else if (agc_gain < lookup->table[lookup->size-1].regval)
621 rf_lvl = -100;
622
623 }
624
625 dprintk(KERN_INFO "%s: RFLevel = %d\n", __func__, rf_lvl);
626
627 return rf_lvl;
628 }
629
630 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
631 {
632 struct stv0900_state *state = fe->demodulator_priv;
633 struct stv0900_internal *internal = state->internal;
634 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
635 state->demod);
636
637 *strength = (rflevel + 100) * (16383 / 105);
638
639 return 0;
640 }
641
642
643 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
644 const struct stv0900_table *lookup)
645 {
646 struct stv0900_state *state = fe->demodulator_priv;
647 struct stv0900_internal *i_params = state->internal;
648 enum fe_stv0900_demod_num demod = state->demod;
649
650 s32 c_n = -100,
651 regval, imin, imax,
652 i,
653 lock_flag_field,
654 noise_field1,
655 noise_field0;
656
657 dprintk(KERN_INFO "%s\n", __func__);
658
659 dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
660 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
661 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1, F0900_P2_NOSPLHT_NORMED1);
662 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0, F0900_P2_NOSPLHT_NORMED0);
663 } else {
664 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1, F0900_P2_NOSDATAT_NORMED1);
665 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0, F0900_P1_NOSDATAT_NORMED0);
666 }
667
668 if (stv0900_get_bits(i_params, lock_flag_field)) {
669 if ((lookup != NULL) && lookup->size) {
670 regval = 0;
671 msleep(5);
672 for (i = 0; i < 16; i++) {
673 regval += MAKEWORD(stv0900_get_bits(i_params, noise_field1),
674 stv0900_get_bits(i_params, noise_field0));
675 msleep(1);
676 }
677
678 regval /= 16;
679 imin = 0;
680 imax = lookup->size - 1;
681 if (INRANGE(lookup->table[imin].regval, regval, lookup->table[imax].regval)) {
682 while ((imax - imin) > 1) {
683 i = (imax + imin) >> 1;
684
685 if (INRANGE(lookup->table[imin].regval, regval, lookup->table[i].regval))
686 imax = i;
687 else
688 imin = i;
689 }
690
691 c_n = ((regval - lookup->table[imin].regval)
692 * (lookup->table[imax].realval - lookup->table[imin].realval)
693 / (lookup->table[imax].regval - lookup->table[imin].regval))
694 + lookup->table[imin].realval;
695 } else if (regval < lookup->table[imin].regval)
696 c_n = 1000;
697 }
698 }
699
700 return c_n;
701 }
702
703 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
704 {
705 *snr = (16383 / 1030) * (30 + stv0900_carr_get_quality(fe, (const struct stv0900_table *)&stv0900_s2_cn));
706
707 return 0;
708 }
709
710 static u32 stv0900_get_ber(struct stv0900_internal *i_params,
711 enum fe_stv0900_demod_num demod)
712 {
713 u32 ber = 10000000, i;
714 s32 dmd_state_reg;
715 s32 demod_state;
716 s32 vstatus_reg;
717 s32 prvit_field;
718 s32 pdel_status_reg;
719 s32 pdel_lock_field;
720
721 dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
722 dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
723 dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
724 dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
725 dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
726 F0900_P2_PKTDELIN_LOCK);
727
728 demod_state = stv0900_get_bits(i_params, dmd_state_reg);
729
730 switch (demod_state) {
731 case STV0900_SEARCH:
732 case STV0900_PLH_DETECTED:
733 default:
734 ber = 10000000;
735 break;
736 case STV0900_DVBS_FOUND:
737 ber = 0;
738 for (i = 0; i < 5; i++) {
739 msleep(5);
740 ber += stv0900_get_err_count(i_params, 0, demod);
741 }
742
743 ber /= 5;
744 if (stv0900_get_bits(i_params, prvit_field)) {
745 ber *= 9766;
746 ber = ber >> 13;
747 }
748
749 break;
750 case STV0900_DVBS2_FOUND:
751 ber = 0;
752 for (i = 0; i < 5; i++) {
753 msleep(5);
754 ber += stv0900_get_err_count(i_params, 0, demod);
755 }
756
757 ber /= 5;
758 if (stv0900_get_bits(i_params, pdel_lock_field)) {
759 ber *= 9766;
760 ber = ber >> 13;
761 }
762
763 break;
764 }
765
766 return ber;
767 }
768
769 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
770 {
771 struct stv0900_state *state = fe->demodulator_priv;
772 struct stv0900_internal *internal = state->internal;
773
774 *ber = stv0900_get_ber(internal, state->demod);
775
776 return 0;
777 }
778
779 int stv0900_get_demod_lock(struct stv0900_internal *i_params,
780 enum fe_stv0900_demod_num demod, s32 time_out)
781 {
782 s32 timer = 0,
783 lock = 0,
784 header_field,
785 lock_field;
786
787 enum fe_stv0900_search_state dmd_state;
788
789 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
790 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
791 while ((timer < time_out) && (lock == 0)) {
792 dmd_state = stv0900_get_bits(i_params, header_field);
793 dprintk("Demod State = %d\n", dmd_state);
794 switch (dmd_state) {
795 case STV0900_SEARCH:
796 case STV0900_PLH_DETECTED:
797 default:
798 lock = 0;
799 break;
800 case STV0900_DVBS2_FOUND:
801 case STV0900_DVBS_FOUND:
802 lock = stv0900_get_bits(i_params, lock_field);
803 break;
804 }
805
806 if (lock == 0)
807 msleep(10);
808
809 timer += 10;
810 }
811
812 if (lock)
813 dprintk("DEMOD LOCK OK\n");
814 else
815 dprintk("DEMOD LOCK FAIL\n");
816
817 return lock;
818 }
819
820 void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
821 enum fe_stv0900_demod_num demod)
822 {
823 s32 regflist,
824 i;
825
826 dprintk(KERN_INFO "%s\n", __func__);
827
828 dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
829
830 for (i = 0; i < 16; i++)
831 stv0900_write_reg(i_params, regflist + i, 0xff);
832 }
833
834 void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
835 enum fe_stv0900_demod_num demod)
836 {
837 u32 matype,
838 mod_code,
839 fmod,
840 reg_index,
841 field_index;
842
843 dprintk(KERN_INFO "%s\n", __func__);
844
845 if (i_params->chip_id <= 0x11) {
846 msleep(5);
847
848 switch (demod) {
849 case STV0900_DEMOD_1:
850 default:
851 mod_code = stv0900_read_reg(i_params,
852 R0900_P1_PLHMODCOD);
853 matype = mod_code & 0x3;
854 mod_code = (mod_code & 0x7f) >> 2;
855
856 reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
857 field_index = mod_code % 2;
858 break;
859 case STV0900_DEMOD_2:
860 mod_code = stv0900_read_reg(i_params,
861 R0900_P2_PLHMODCOD);
862 matype = mod_code & 0x3;
863 mod_code = (mod_code & 0x7f) >> 2;
864
865 reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
866 field_index = mod_code % 2;
867 break;
868 }
869
870
871 switch (matype) {
872 case 0:
873 default:
874 fmod = 14;
875 break;
876 case 1:
877 fmod = 13;
878 break;
879 case 2:
880 fmod = 11;
881 break;
882 case 3:
883 fmod = 7;
884 break;
885 }
886
887 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
888 && (matype <= 1)) {
889 if (field_index == 0)
890 stv0900_write_reg(i_params, reg_index,
891 0xf0 | fmod);
892 else
893 stv0900_write_reg(i_params, reg_index,
894 (fmod << 4) | 0xf);
895 }
896 } else if (i_params->chip_id >= 0x12) {
897 switch (demod) {
898 case STV0900_DEMOD_1:
899 default:
900 for (reg_index = 0; reg_index < 7; reg_index++)
901 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
902
903 stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
904 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
905 for (reg_index = 0; reg_index < 8; reg_index++)
906 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
907
908 break;
909 case STV0900_DEMOD_2:
910 for (reg_index = 0; reg_index < 7; reg_index++)
911 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
912
913 stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
914 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
915 for (reg_index = 0; reg_index < 8; reg_index++)
916 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
917
918 break;
919 }
920
921 }
922 }
923
924 void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
925 enum fe_stv0900_demod_num demod)
926 {
927 u32 reg_index;
928
929 dprintk(KERN_INFO "%s\n", __func__);
930
931 switch (demod) {
932 case STV0900_DEMOD_1:
933 default:
934 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
935 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
936 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
937 for (reg_index = 0; reg_index < 13; reg_index++)
938 stv0900_write_reg(i_params,
939 R0900_P1_MODCODLST2 + reg_index, 0);
940
941 break;
942 case STV0900_DEMOD_2:
943 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
944 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
945 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
946 for (reg_index = 0; reg_index < 13; reg_index++)
947 stv0900_write_reg(i_params,
948 R0900_P2_MODCODLST2 + reg_index, 0);
949
950 break;
951 }
952 }
953
954 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
955 {
956 return DVBFE_ALGO_CUSTOM;
957 }
958
959 static int stb0900_set_property(struct dvb_frontend *fe,
960 struct dtv_property *tvp)
961 {
962 dprintk(KERN_INFO "%s(..)\n", __func__);
963
964 return 0;
965 }
966
967 static int stb0900_get_property(struct dvb_frontend *fe,
968 struct dtv_property *tvp)
969 {
970 dprintk(KERN_INFO "%s(..)\n", __func__);
971
972 return 0;
973 }
974
975 void stv0900_start_search(struct stv0900_internal *i_params,
976 enum fe_stv0900_demod_num demod)
977 {
978
979 switch (demod) {
980 case STV0900_DEMOD_1:
981 default:
982 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
983
984 if (i_params->chip_id == 0x10)
985 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
986
987 if (i_params->chip_id < 0x20)
988 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
989
990 if (i_params->dmd1_symbol_rate <= 5000000) {
991 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
992 stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
993 stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
994 stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
995 stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
996 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
997 } else {
998 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
999 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
1000 }
1001
1002 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
1003 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
1004
1005 if (i_params->chip_id >= 0x20) {
1006 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
1007 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1008
1009 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1010 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1011 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1012 }
1013 }
1014
1015 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1016 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
1017 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
1018 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1019 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1020 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1021 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1022 if (i_params->chip_id >= 0x20) {
1023 if (i_params->dmd1_symbol_rate < 2000000) {
1024 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1025 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1026 }
1027
1028 if (i_params->dmd1_symbol_rate < 10000000) {
1029 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1030 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1031 } else {
1032 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1033 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1034 }
1035
1036 } else {
1037 if (i_params->dmd1_symbol_rate < 10000000)
1038 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
1039 else
1040 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1041 }
1042
1043 switch (i_params->dmd1_srch_algo) {
1044 case STV0900_WARM_START:
1045 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1046 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1047 break;
1048 case STV0900_COLD_START:
1049 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1050 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1051 break;
1052 default:
1053 break;
1054 }
1055
1056 break;
1057 case STV0900_DEMOD_2:
1058 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
1059 if (i_params->chip_id == 0x10)
1060 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1061
1062 if (i_params->chip_id < 0x20)
1063 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1064
1065 if (i_params->dmd2_symbol_rate <= 5000000) {
1066 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1067 stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1068 stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1069 stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1070 stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1071 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1072 } else {
1073 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1074 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1075 }
1076
1077 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
1078 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
1079
1080 if (i_params->chip_id >= 0x20) {
1081 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
1082 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1083 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1084 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1085 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1086 }
1087 }
1088
1089 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1090 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
1091 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
1092 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1093 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1094 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1095 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1096 if (i_params->chip_id >= 0x20) {
1097 if (i_params->dmd2_symbol_rate < 2000000) {
1098 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1099 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1100 }
1101
1102 if (i_params->dmd2_symbol_rate < 10000000) {
1103 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
1104 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1105 } else {
1106 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
1107 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
1108 }
1109
1110 } else {
1111 if (i_params->dmd2_symbol_rate < 10000000)
1112 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
1113 else
1114 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1115 }
1116
1117 switch (i_params->dmd2_srch_algo) {
1118 case STV0900_WARM_START:
1119 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1120 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1121 break;
1122 case STV0900_COLD_START:
1123 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1124 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1125 break;
1126 default:
1127 break;
1128 }
1129
1130 break;
1131 }
1132 }
1133
1134 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1135 s32 pilot, u8 chip_id)
1136 {
1137 u8 aclc_value = 0x29;
1138 s32 i;
1139 const struct stv0900_car_loop_optim *car_loop_s2;
1140
1141 dprintk(KERN_INFO "%s\n", __func__);
1142
1143 if (chip_id <= 0x12)
1144 car_loop_s2 = FE_STV0900_S2CarLoop;
1145 else if (chip_id == 0x20)
1146 car_loop_s2 = FE_STV0900_S2CarLoopCut20;
1147 else
1148 car_loop_s2 = FE_STV0900_S2CarLoop;
1149
1150 if (modcode < STV0900_QPSK_12) {
1151 i = 0;
1152 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
1153 i++;
1154
1155 if (i >= 3)
1156 i = 2;
1157 } else {
1158 i = 0;
1159 while ((i < 14) && (modcode != car_loop_s2[i].modcode))
1160 i++;
1161
1162 if (i >= 14) {
1163 i = 0;
1164 while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
1165 i++;
1166
1167 if (i >= 11)
1168 i = 10;
1169 }
1170 }
1171
1172 if (modcode <= STV0900_QPSK_25) {
1173 if (pilot) {
1174 if (srate <= 3000000)
1175 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
1176 else if (srate <= 7000000)
1177 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
1178 else if (srate <= 15000000)
1179 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
1180 else if (srate <= 25000000)
1181 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
1182 else
1183 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
1184 } else {
1185 if (srate <= 3000000)
1186 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
1187 else if (srate <= 7000000)
1188 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
1189 else if (srate <= 15000000)
1190 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
1191 else if (srate <= 25000000)
1192 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
1193 else
1194 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
1195 }
1196
1197 } else if (modcode <= STV0900_8PSK_910) {
1198 if (pilot) {
1199 if (srate <= 3000000)
1200 aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
1201 else if (srate <= 7000000)
1202 aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
1203 else if (srate <= 15000000)
1204 aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
1205 else if (srate <= 25000000)
1206 aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
1207 else
1208 aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
1209 } else {
1210 if (srate <= 3000000)
1211 aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
1212 else if (srate <= 7000000)
1213 aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
1214 else if (srate <= 15000000)
1215 aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
1216 else if (srate <= 25000000)
1217 aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
1218 else
1219 aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
1220 }
1221
1222 } else {
1223 if (srate <= 3000000)
1224 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
1225 else if (srate <= 7000000)
1226 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
1227 else if (srate <= 15000000)
1228 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
1229 else if (srate <= 25000000)
1230 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
1231 else
1232 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
1233 }
1234
1235 return aclc_value;
1236 }
1237
1238 u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
1239 {
1240 s32 mod_index = 0;
1241
1242 u8 aclc_value = 0x0b;
1243
1244 dprintk(KERN_INFO "%s\n", __func__);
1245
1246 switch (modulation) {
1247 case STV0900_QPSK:
1248 default:
1249 mod_index = 0;
1250 break;
1251 case STV0900_8PSK:
1252 mod_index = 1;
1253 break;
1254 case STV0900_16APSK:
1255 mod_index = 2;
1256 break;
1257 case STV0900_32APSK:
1258 mod_index = 3;
1259 break;
1260 }
1261
1262 switch (chip_id) {
1263 case 0x20:
1264 if (srate <= 3000000)
1265 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
1266 else if (srate <= 7000000)
1267 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
1268 else if (srate <= 15000000)
1269 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
1270 else if (srate <= 25000000)
1271 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
1272 else
1273 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
1274
1275 break;
1276 case 0x12:
1277 default:
1278 if (srate <= 3000000)
1279 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
1280 else if (srate <= 7000000)
1281 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
1282 else if (srate <= 15000000)
1283 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
1284 else if (srate <= 25000000)
1285 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
1286 else
1287 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
1288
1289 break;
1290 }
1291
1292 return aclc_value;
1293 }
1294
1295 static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
1296 enum fe_stv0900_demod_mode LDPC_Mode,
1297 enum fe_stv0900_demod_num demod)
1298 {
1299 enum fe_stv0900_error error = STV0900_NO_ERROR;
1300
1301 dprintk(KERN_INFO "%s\n", __func__);
1302
1303 switch (LDPC_Mode) {
1304 case STV0900_DUAL:
1305 default:
1306 if ((i_params->demod_mode != STV0900_DUAL)
1307 || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
1308 stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
1309
1310 i_params->demod_mode = STV0900_DUAL;
1311
1312 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1313 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1314 }
1315
1316 break;
1317 case STV0900_SINGLE:
1318 if (demod == STV0900_DEMOD_2)
1319 stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
1320 else
1321 stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
1322
1323 i_params->demod_mode = STV0900_SINGLE;
1324
1325 stv0900_write_bits(i_params, F0900_FRESFEC, 1);
1326 stv0900_write_bits(i_params, F0900_FRESFEC, 0);
1327 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
1328 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
1329 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
1330 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
1331 break;
1332 }
1333
1334 return error;
1335 }
1336
1337 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1338 struct stv0900_init_params *p_init)
1339 {
1340 struct stv0900_state *state = fe->demodulator_priv;
1341 enum fe_stv0900_error error = STV0900_NO_ERROR;
1342 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1343 int selosci;
1344
1345 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1346 state->config->demod_address);
1347
1348 dprintk(KERN_INFO "%s\n", __func__);
1349
1350 if (temp_int != NULL) {
1351 state->internal = temp_int->internal;
1352 (state->internal->dmds_used)++;
1353 dprintk(KERN_INFO "%s: Find Internal Structure!\n", __func__);
1354 return STV0900_NO_ERROR;
1355 } else {
1356 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
1357 temp_int = append_internal(state->internal);
1358 state->internal->dmds_used = 1;
1359 state->internal->i2c_adap = state->i2c_adap;
1360 state->internal->i2c_addr = state->config->demod_address;
1361 state->internal->clkmode = state->config->clkmode;
1362 state->internal->errs = STV0900_NO_ERROR;
1363 dprintk(KERN_INFO "%s: Create New Internal Structure!\n", __func__);
1364 }
1365
1366 if (state->internal != NULL) {
1367 demodError = stv0900_initialize(state->internal);
1368 if (demodError == STV0900_NO_ERROR) {
1369 error = STV0900_NO_ERROR;
1370 } else {
1371 if (demodError == STV0900_INVALID_HANDLE)
1372 error = STV0900_INVALID_HANDLE;
1373 else
1374 error = STV0900_I2C_ERROR;
1375 }
1376
1377 if (state->internal != NULL) {
1378 if (error == STV0900_NO_ERROR) {
1379 state->internal->demod_mode = p_init->demod_mode;
1380
1381 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
1382
1383 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
1384 state->internal->rolloff = p_init->rolloff;
1385 state->internal->quartz = p_init->dmd_ref_clk;
1386
1387 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1388 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1389
1390 stv0900_set_ts_parallel_serial(state->internal, p_init->path1_ts_clock, p_init->path2_ts_clock);
1391 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1392 switch (p_init->tuner1_adc) {
1393 case 1:
1394 stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1395 break;
1396 default:
1397 break;
1398 }
1399
1400 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1401 switch (p_init->tuner2_adc) {
1402 case 1:
1403 stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
1404 break;
1405 default:
1406 break;
1407 }
1408
1409 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
1410 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1411 stv0900_set_mclk(state->internal, 135000000);
1412 msleep(3);
1413
1414 switch (state->internal->clkmode) {
1415 case 0:
1416 case 2:
1417 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1418 break;
1419 default:
1420 selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1421 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1422 break;
1423 }
1424 msleep(3);
1425
1426 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
1427 if (state->internal->errs)
1428 error = STV0900_I2C_ERROR;
1429 }
1430 } else {
1431 error = STV0900_INVALID_HANDLE;
1432 }
1433 }
1434
1435 return error;
1436 }
1437
1438 static int stv0900_status(struct stv0900_internal *i_params,
1439 enum fe_stv0900_demod_num demod)
1440 {
1441 enum fe_stv0900_search_state demod_state;
1442 s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1443 int locked = FALSE;
1444
1445 dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1446 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1447 dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1448 dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1449 dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1450
1451 demod_state = stv0900_get_bits(i_params, mode_field);
1452 switch (demod_state) {
1453 case STV0900_SEARCH:
1454 case STV0900_PLH_DETECTED:
1455 default:
1456 locked = FALSE;
1457 break;
1458 case STV0900_DVBS2_FOUND:
1459 locked = stv0900_get_bits(i_params, lock_field) &&
1460 stv0900_get_bits(i_params, delin_field) &&
1461 stv0900_get_bits(i_params, fifo_field);
1462 break;
1463 case STV0900_DVBS_FOUND:
1464 locked = stv0900_get_bits(i_params, lock_field) &&
1465 stv0900_get_bits(i_params, lockedvit_field) &&
1466 stv0900_get_bits(i_params, fifo_field);
1467 break;
1468 }
1469
1470 return locked;
1471 }
1472
1473 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1474 struct dvb_frontend_parameters *params)
1475 {
1476 struct stv0900_state *state = fe->demodulator_priv;
1477 struct stv0900_internal *i_params = state->internal;
1478 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1479
1480 struct stv0900_search_params p_search;
1481 struct stv0900_signal_info p_result;
1482
1483 enum fe_stv0900_error error = STV0900_NO_ERROR;
1484
1485 dprintk(KERN_INFO "%s: ", __func__);
1486
1487 p_result.locked = FALSE;
1488 p_search.path = state->demod;
1489 p_search.frequency = c->frequency;
1490 p_search.symbol_rate = c->symbol_rate;
1491 p_search.search_range = 10000000;
1492 p_search.fec = STV0900_FEC_UNKNOWN;
1493 p_search.standard = STV0900_AUTO_SEARCH;
1494 p_search.iq_inversion = STV0900_IQ_AUTO;
1495 p_search.search_algo = STV0900_BLIND_SEARCH;
1496
1497 if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
1498 (INRANGE(100000, p_search.search_range, 50000000))) {
1499 switch (p_search.path) {
1500 case STV0900_DEMOD_1:
1501 default:
1502 i_params->dmd1_srch_standard = p_search.standard;
1503 i_params->dmd1_symbol_rate = p_search.symbol_rate;
1504 i_params->dmd1_srch_range = p_search.search_range;
1505 i_params->tuner1_freq = p_search.frequency;
1506 i_params->dmd1_srch_algo = p_search.search_algo;
1507 i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
1508 i_params->dmd1_fec = p_search.fec;
1509 break;
1510
1511 case STV0900_DEMOD_2:
1512 i_params->dmd2_srch_stndrd = p_search.standard;
1513 i_params->dmd2_symbol_rate = p_search.symbol_rate;
1514 i_params->dmd2_srch_range = p_search.search_range;
1515 i_params->tuner2_freq = p_search.frequency;
1516 i_params->dmd2_srch_algo = p_search.search_algo;
1517 i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1518 i_params->dmd2_fec = p_search.fec;
1519 break;
1520 }
1521
1522 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1523 (i_params->errs == STV0900_NO_ERROR)) {
1524 switch (p_search.path) {
1525 case STV0900_DEMOD_1:
1526 default:
1527 p_result.locked = i_params->dmd1_rslts.locked;
1528 p_result.standard = i_params->dmd1_rslts.standard;
1529 p_result.frequency = i_params->dmd1_rslts.frequency;
1530 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1531 p_result.fec = i_params->dmd1_rslts.fec;
1532 p_result.modcode = i_params->dmd1_rslts.modcode;
1533 p_result.pilot = i_params->dmd1_rslts.pilot;
1534 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1535 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1536 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1537 p_result.modulation = i_params->dmd1_rslts.modulation;
1538 break;
1539 case STV0900_DEMOD_2:
1540 p_result.locked = i_params->dmd2_rslts.locked;
1541 p_result.standard = i_params->dmd2_rslts.standard;
1542 p_result.frequency = i_params->dmd2_rslts.frequency;
1543 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1544 p_result.fec = i_params->dmd2_rslts.fec;
1545 p_result.modcode = i_params->dmd2_rslts.modcode;
1546 p_result.pilot = i_params->dmd2_rslts.pilot;
1547 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1548 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1549 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1550 p_result.modulation = i_params->dmd2_rslts.modulation;
1551 break;
1552 }
1553
1554 } else {
1555 p_result.locked = FALSE;
1556 switch (p_search.path) {
1557 case STV0900_DEMOD_1:
1558 switch (i_params->dmd1_err) {
1559 case STV0900_I2C_ERROR:
1560 error = STV0900_I2C_ERROR;
1561 break;
1562 case STV0900_NO_ERROR:
1563 default:
1564 error = STV0900_SEARCH_FAILED;
1565 break;
1566 }
1567 break;
1568 case STV0900_DEMOD_2:
1569 switch (i_params->dmd2_err) {
1570 case STV0900_I2C_ERROR:
1571 error = STV0900_I2C_ERROR;
1572 break;
1573 case STV0900_NO_ERROR:
1574 default:
1575 error = STV0900_SEARCH_FAILED;
1576 break;
1577 }
1578 break;
1579 }
1580 }
1581
1582 } else
1583 error = STV0900_BAD_PARAMETER;
1584
1585 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1586 dprintk(KERN_INFO "Search Success\n");
1587 return DVBFE_ALGO_SEARCH_SUCCESS;
1588 } else {
1589 dprintk(KERN_INFO "Search Fail\n");
1590 return DVBFE_ALGO_SEARCH_FAILED;
1591 }
1592
1593 return DVBFE_ALGO_SEARCH_ERROR;
1594 }
1595
1596 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1597 {
1598 struct stv0900_state *state = fe->demodulator_priv;
1599
1600 dprintk("%s: ", __func__);
1601
1602 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1603 dprintk("DEMOD LOCK OK\n");
1604 *status = FE_HAS_CARRIER
1605 | FE_HAS_VITERBI
1606 | FE_HAS_SYNC
1607 | FE_HAS_LOCK;
1608 } else
1609 dprintk("DEMOD LOCK FAIL\n");
1610
1611 return 0;
1612 }
1613
1614 static int stv0900_track(struct dvb_frontend *fe,
1615 struct dvb_frontend_parameters *p)
1616 {
1617 return 0;
1618 }
1619
1620 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1621 {
1622
1623 struct stv0900_state *state = fe->demodulator_priv;
1624 struct stv0900_internal *i_params = state->internal;
1625 enum fe_stv0900_demod_num demod = state->demod;
1626 s32 rst_field;
1627
1628 dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1629
1630 if (stop_ts == TRUE)
1631 stv0900_write_bits(i_params, rst_field, 1);
1632 else
1633 stv0900_write_bits(i_params, rst_field, 0);
1634
1635 return 0;
1636 }
1637
1638 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1639 {
1640 struct stv0900_state *state = fe->demodulator_priv;
1641 struct stv0900_internal *i_params = state->internal;
1642 enum fe_stv0900_demod_num demod = state->demod;
1643 s32 mode_field, reset_field;
1644
1645 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1646 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1647
1648 stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1649 stv0900_write_bits(i_params, reset_field, 1);
1650 stv0900_write_bits(i_params, reset_field, 0);
1651
1652 return 0;
1653 }
1654
1655 static int stv0900_init(struct dvb_frontend *fe)
1656 {
1657 dprintk(KERN_INFO "%s\n", __func__);
1658
1659 stv0900_stop_ts(fe, 1);
1660 stv0900_diseqc_init(fe);
1661
1662 return 0;
1663 }
1664
1665 static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
1666 u32 NbData, enum fe_stv0900_demod_num demod)
1667 {
1668 s32 i = 0;
1669
1670 switch (demod) {
1671 case STV0900_DEMOD_1:
1672 default:
1673 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
1674 while (i < NbData) {
1675 while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
1676 ;/* checkpatch complains */
1677 stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1678 i++;
1679 }
1680
1681 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1682 i = 0;
1683 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1684 msleep(10);
1685 i++;
1686 }
1687
1688 break;
1689 case STV0900_DEMOD_2:
1690 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1691
1692 while (i < NbData) {
1693 while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1694 ;/* checkpatch complains */
1695 stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1696 i++;
1697 }
1698
1699 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
1700 i = 0;
1701 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
1702 msleep(10);
1703 i++;
1704 }
1705
1706 break;
1707 }
1708
1709 return 0;
1710 }
1711
1712 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1713 struct dvb_diseqc_master_cmd *cmd)
1714 {
1715 struct stv0900_state *state = fe->demodulator_priv;
1716
1717 return stv0900_diseqc_send(state->internal,
1718 cmd->msg,
1719 cmd->msg_len,
1720 state->demod);
1721 }
1722
1723 static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1724 {
1725 struct stv0900_state *state = fe->demodulator_priv;
1726 struct stv0900_internal *i_params = state->internal;
1727 enum fe_stv0900_demod_num demod = state->demod;
1728 s32 mode_field;
1729 u32 diseqc_fifo;
1730
1731 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1732 dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
1733
1734 switch (burst) {
1735 case SEC_MINI_A:
1736 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
1737 stv0900_write_reg(i_params, diseqc_fifo, 0x00);
1738 break;
1739 case SEC_MINI_B:
1740 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
1741 stv0900_write_reg(i_params, diseqc_fifo, 0xff);
1742 break;
1743 }
1744
1745 return 0;
1746 }
1747
1748 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1749 struct dvb_diseqc_slave_reply *reply)
1750 {
1751 struct stv0900_state *state = fe->demodulator_priv;
1752 struct stv0900_internal *i_params = state->internal;
1753 s32 i = 0;
1754
1755 switch (state->demod) {
1756 case STV0900_DEMOD_1:
1757 default:
1758 reply->msg_len = 0;
1759
1760 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1761 msleep(10);
1762 i++;
1763 }
1764
1765 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1766 reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1767
1768 for (i = 0; i < reply->msg_len; i++)
1769 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
1770 }
1771 break;
1772 case STV0900_DEMOD_2:
1773 reply->msg_len = 0;
1774
1775 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
1776 msleep(10);
1777 i++;
1778 }
1779
1780 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
1781 reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
1782
1783 for (i = 0; i < reply->msg_len; i++)
1784 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
1785 }
1786 break;
1787 }
1788
1789 return 0;
1790 }
1791
1792 static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1793 {
1794 struct stv0900_state *state = fe->demodulator_priv;
1795 struct stv0900_internal *i_params = state->internal;
1796 enum fe_stv0900_demod_num demod = state->demod;
1797 s32 mode_field, reset_field;
1798
1799 dprintk(KERN_INFO "%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
1800
1801 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1802 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1803
1804 if (tone) {
1805 /*Set the DiseqC mode to 22Khz continues tone*/
1806 stv0900_write_bits(i_params, mode_field, 0);
1807 stv0900_write_bits(i_params, reset_field, 1);
1808 /*release DiseqC reset to enable the 22KHz tone*/
1809 stv0900_write_bits(i_params, reset_field, 0);
1810 } else {
1811 stv0900_write_bits(i_params, mode_field, 0);
1812 /*maintain the DiseqC reset to disable the 22KHz tone*/
1813 stv0900_write_bits(i_params, reset_field, 1);
1814 }
1815
1816 return 0;
1817 }
1818
1819 static void stv0900_release(struct dvb_frontend *fe)
1820 {
1821 struct stv0900_state *state = fe->demodulator_priv;
1822
1823 dprintk(KERN_INFO "%s\n", __func__);
1824
1825 if ((--(state->internal->dmds_used)) <= 0) {
1826
1827 dprintk(KERN_INFO "%s: Actually removing\n", __func__);
1828
1829 remove_inode(state->internal);
1830 kfree(state->internal);
1831 }
1832
1833 kfree(state);
1834 }
1835
1836 static struct dvb_frontend_ops stv0900_ops = {
1837
1838 .info = {
1839 .name = "STV0900 frontend",
1840 .type = FE_QPSK,
1841 .frequency_min = 950000,
1842 .frequency_max = 2150000,
1843 .frequency_stepsize = 125,
1844 .frequency_tolerance = 0,
1845 .symbol_rate_min = 1000000,
1846 .symbol_rate_max = 45000000,
1847 .symbol_rate_tolerance = 500,
1848 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1849 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1850 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1851 FE_CAN_2G_MODULATION |
1852 FE_CAN_FEC_AUTO
1853 },
1854 .release = stv0900_release,
1855 .init = stv0900_init,
1856 .get_frontend_algo = stv0900_frontend_algo,
1857 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1858 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1859 .diseqc_send_burst = stv0900_send_burst,
1860 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1861 .set_tone = stv0900_set_tone,
1862 .set_property = stb0900_set_property,
1863 .get_property = stb0900_get_property,
1864 .search = stv0900_search,
1865 .track = stv0900_track,
1866 .read_status = stv0900_read_status,
1867 .read_ber = stv0900_read_ber,
1868 .read_signal_strength = stv0900_read_signal_strength,
1869 .read_snr = stv0900_read_snr,
1870 };
1871
1872 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1873 struct i2c_adapter *i2c,
1874 int demod)
1875 {
1876 struct stv0900_state *state = NULL;
1877 struct stv0900_init_params init_params;
1878 enum fe_stv0900_error err_stv0900;
1879
1880 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1881 if (state == NULL)
1882 goto error;
1883
1884 state->demod = demod;
1885 state->config = config;
1886 state->i2c_adap = i2c;
1887
1888 memcpy(&state->frontend.ops, &stv0900_ops,
1889 sizeof(struct dvb_frontend_ops));
1890 state->frontend.demodulator_priv = state;
1891
1892 switch (demod) {
1893 case 0:
1894 case 1:
1895 init_params.dmd_ref_clk = config->xtal;
1896 init_params.demod_mode = STV0900_DUAL;
1897 init_params.rolloff = STV0900_35;
1898 init_params.path1_ts_clock = config->path1_mode;
1899 init_params.tun1_maddress = config->tun1_maddress;
1900 init_params.tun1_iq_inversion = STV0900_IQ_NORMAL;
1901 init_params.tuner1_adc = config->tun1_adc;
1902 init_params.path2_ts_clock = config->path2_mode;
1903 init_params.tun2_maddress = config->tun2_maddress;
1904 init_params.tuner2_adc = config->tun2_adc;
1905 init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED;
1906
1907 err_stv0900 = stv0900_init_internal(&state->frontend,
1908 &init_params);
1909
1910 if (err_stv0900)
1911 goto error;
1912
1913 break;
1914 default:
1915 goto error;
1916 break;
1917 }
1918
1919 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1920 return &state->frontend;
1921
1922 error:
1923 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1924 __func__, demod);
1925 kfree(state);
1926 return NULL;
1927 }
1928 EXPORT_SYMBOL(stv0900_attach);
1929
1930 MODULE_PARM_DESC(debug, "Set debug");
1931
1932 MODULE_AUTHOR("Igor M. Liplianin");
1933 MODULE_DESCRIPTION("ST STV0900 frontend");
1934 MODULE_LICENSE("GPL");
Verdex Pro support