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tifm_sd: replace command completion state machine with full checking
[linux-2.6/verdex.git] / drivers / net / meth.c
blob0343ea12b299638770b46d0af70658f7b17b3f0b
1 /*
2 * meth.c -- O2 Builtin 10/100 Ethernet driver
3 *
4 * Copyright (C) 2001-2003 Ilya Volynets
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #include <linux/module.h>
12 #include <linux/init.h>
13
14 #include <linux/kernel.h> /* printk() */
15 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/errno.h> /* error codes */
18 #include <linux/types.h> /* size_t */
19 #include <linux/interrupt.h> /* mark_bh */
20
21 #include <linux/in.h>
22 #include <linux/in6.h>
23 #include <linux/device.h> /* struct device, et al */
24 #include <linux/netdevice.h> /* struct device, and other headers */
25 #include <linux/etherdevice.h> /* eth_type_trans */
26 #include <linux/ip.h> /* struct iphdr */
27 #include <linux/tcp.h> /* struct tcphdr */
28 #include <linux/skbuff.h>
29 #include <linux/mii.h> /* MII definitions */
30
31 #include <asm/ip32/mace.h>
32 #include <asm/ip32/ip32_ints.h>
33
34 #include <asm/io.h>
35 #include <asm/scatterlist.h>
36 #include <linux/dma-mapping.h>
37
38 #include "meth.h"
39
40 #ifndef MFE_DEBUG
41 #define MFE_DEBUG 0
42 #endif
43
44 #if MFE_DEBUG>=1
45 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
46 #define MFE_RX_DEBUG 2
47 #else
48 #define DPRINTK(str,args...)
49 #define MFE_RX_DEBUG 0
50 #endif
51
52
53 static const char *meth_str="SGI O2 Fast Ethernet";
54 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
55 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
56
57 #define HAVE_TX_TIMEOUT
58 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
59 #define TX_TIMEOUT (400*HZ/1000)
60
61 #ifdef HAVE_TX_TIMEOUT
62 static int timeout = TX_TIMEOUT;
63 module_param(timeout, int, 0);
64 #endif
65
66 /*
67 * This structure is private to each device. It is used to pass
68 * packets in and out, so there is place for a packet
69 */
70 struct meth_private {
71 struct net_device_stats stats;
72 /* in-memory copy of MAC Control register */
73 unsigned long mac_ctrl;
74 /* in-memory copy of DMA Control register */
75 unsigned long dma_ctrl;
76 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
77 unsigned long phy_addr;
78 tx_packet *tx_ring;
79 dma_addr_t tx_ring_dma;
80 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
81 dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
82 unsigned long tx_read, tx_write, tx_count;
83
84 rx_packet *rx_ring[RX_RING_ENTRIES];
85 dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
86 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
87 unsigned long rx_write;
88
89 spinlock_t meth_lock;
90 };
91
92 static void meth_tx_timeout(struct net_device *dev);
93 static irqreturn_t meth_interrupt(int irq, void *dev_id);
94
95 /* global, initialized in ip32-setup.c */
96 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
97
98 static inline void load_eaddr(struct net_device *dev)
99 {
100 int i;
101 DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
102 (int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF,
103 (int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF);
104 for (i = 0; i < 6; i++)
105 dev->dev_addr[i] = o2meth_eaddr[i];
106 mace->eth.mac_addr = (*(unsigned long*)o2meth_eaddr) >> 16;
107 }
108
109 /*
110 * Waits for BUSY status of mdio bus to clear
111 */
112 #define WAIT_FOR_PHY(___rval) \
113 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
114 udelay(25); \
115 }
116 /*read phy register, return value read */
117 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
118 {
119 unsigned long rval;
120 WAIT_FOR_PHY(rval);
121 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
122 udelay(25);
123 mace->eth.phy_trans_go = 1;
124 udelay(25);
125 WAIT_FOR_PHY(rval);
126 return rval & MDIO_DATA_MASK;
127 }
128
129 static int mdio_probe(struct meth_private *priv)
130 {
131 int i;
132 unsigned long p2, p3;
133 /* check if phy is detected already */
134 if(priv->phy_addr>=0&&priv->phy_addr<32)
135 return 0;
136 spin_lock(&priv->meth_lock);
137 for (i=0;i<32;++i){
138 priv->phy_addr=i;
139 p2=mdio_read(priv,2);
140 p3=mdio_read(priv,3);
141 #if MFE_DEBUG>=2
142 switch ((p2<<12)|(p3>>4)){
143 case PHY_QS6612X:
144 DPRINTK("PHY is QS6612X\n");
145 break;
146 case PHY_ICS1889:
147 DPRINTK("PHY is ICS1889\n");
148 break;
149 case PHY_ICS1890:
150 DPRINTK("PHY is ICS1890\n");
151 break;
152 case PHY_DP83840:
153 DPRINTK("PHY is DP83840\n");
154 break;
155 }
156 #endif
157 if(p2!=0xffff&&p2!=0x0000){
158 DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
159 break;
160 }
161 }
162 spin_unlock(&priv->meth_lock);
163 if(priv->phy_addr<32) {
164 return 0;
165 }
166 DPRINTK("Oopsie! PHY is not known!\n");
167 priv->phy_addr=-1;
168 return -ENODEV;
169 }
170
171 static void meth_check_link(struct net_device *dev)
172 {
173 struct meth_private *priv = netdev_priv(dev);
174 unsigned long mii_advertising = mdio_read(priv, 4);
175 unsigned long mii_partner = mdio_read(priv, 5);
176 unsigned long negotiated = mii_advertising & mii_partner;
177 unsigned long duplex, speed;
178
179 if (mii_partner == 0xffff)
180 return;
181
182 speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
183 duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
184 METH_PHY_FDX : 0;
185
186 if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
187 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
188 if (duplex)
189 priv->mac_ctrl |= METH_PHY_FDX;
190 else
191 priv->mac_ctrl &= ~METH_PHY_FDX;
192 mace->eth.mac_ctrl = priv->mac_ctrl;
193 }
194
195 if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
196 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
197 if (duplex)
198 priv->mac_ctrl |= METH_100MBIT;
199 else
200 priv->mac_ctrl &= ~METH_100MBIT;
201 mace->eth.mac_ctrl = priv->mac_ctrl;
202 }
203 }
204
205
206 static int meth_init_tx_ring(struct meth_private *priv)
207 {
208 /* Init TX ring */
209 priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
210 &priv->tx_ring_dma, GFP_ATOMIC);
211 if (!priv->tx_ring)
212 return -ENOMEM;
213 memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE);
214 priv->tx_count = priv->tx_read = priv->tx_write = 0;
215 mace->eth.tx_ring_base = priv->tx_ring_dma;
216 /* Now init skb save area */
217 memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
218 memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
219 return 0;
220 }
221
222 static int meth_init_rx_ring(struct meth_private *priv)
223 {
224 int i;
225
226 for (i = 0; i < RX_RING_ENTRIES; i++) {
227 priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
228 /* 8byte status vector + 3quad padding + 2byte padding,
229 * to put data on 64bit aligned boundary */
230 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
231 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
232 /* I'll need to re-sync it after each RX */
233 priv->rx_ring_dmas[i] =
234 dma_map_single(NULL, priv->rx_ring[i],
235 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
236 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
237 }
238 priv->rx_write = 0;
239 return 0;
240 }
241 static void meth_free_tx_ring(struct meth_private *priv)
242 {
243 int i;
244
245 /* Remove any pending skb */
246 for (i = 0; i < TX_RING_ENTRIES; i++) {
247 if (priv->tx_skbs[i])
248 dev_kfree_skb(priv->tx_skbs[i]);
249 priv->tx_skbs[i] = NULL;
250 }
251 dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
252 priv->tx_ring_dma);
253 }
254
255 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
256 static void meth_free_rx_ring(struct meth_private *priv)
257 {
258 int i;
259
260 for (i = 0; i < RX_RING_ENTRIES; i++) {
261 dma_unmap_single(NULL, priv->rx_ring_dmas[i],
262 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
263 priv->rx_ring[i] = 0;
264 priv->rx_ring_dmas[i] = 0;
265 kfree_skb(priv->rx_skbs[i]);
266 }
267 }
268
269 int meth_reset(struct net_device *dev)
270 {
271 struct meth_private *priv = netdev_priv(dev);
272
273 /* Reset card */
274 mace->eth.mac_ctrl = SGI_MAC_RESET;
275 udelay(1);
276 mace->eth.mac_ctrl = 0;
277 udelay(25);
278
279 /* Load ethernet address */
280 load_eaddr(dev);
281 /* Should load some "errata", but later */
282
283 /* Check for device */
284 if (mdio_probe(priv) < 0) {
285 DPRINTK("Unable to find PHY\n");
286 return -ENODEV;
287 }
288
289 /* Initial mode: 10 | Half-duplex | Accept normal packets */
290 priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
291 if (dev->flags | IFF_PROMISC)
292 priv->mac_ctrl |= METH_PROMISC;
293 mace->eth.mac_ctrl = priv->mac_ctrl;
294
295 /* Autonegotiate speed and duplex mode */
296 meth_check_link(dev);
297
298 /* Now set dma control, but don't enable DMA, yet */
299 priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
300 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
301 mace->eth.dma_ctrl = priv->dma_ctrl;
302
303 return 0;
304 }
305
306 /*============End Helper Routines=====================*/
307
308 /*
309 * Open and close
310 */
311 static int meth_open(struct net_device *dev)
312 {
313 struct meth_private *priv = netdev_priv(dev);
314 int ret;
315
316 priv->phy_addr = -1; /* No PHY is known yet... */
317
318 /* Initialize the hardware */
319 ret = meth_reset(dev);
320 if (ret < 0)
321 return ret;
322
323 /* Allocate the ring buffers */
324 ret = meth_init_tx_ring(priv);
325 if (ret < 0)
326 return ret;
327 ret = meth_init_rx_ring(priv);
328 if (ret < 0)
329 goto out_free_tx_ring;
330
331 ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
332 if (ret) {
333 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
334 goto out_free_rx_ring;
335 }
336
337 /* Start DMA */
338 priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
339 METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
340 mace->eth.dma_ctrl = priv->dma_ctrl;
341
342 DPRINTK("About to start queue\n");
343 netif_start_queue(dev);
344
345 return 0;
346
347 out_free_rx_ring:
348 meth_free_rx_ring(priv);
349 out_free_tx_ring:
350 meth_free_tx_ring(priv);
351
352 return ret;
353 }
354
355 static int meth_release(struct net_device *dev)
356 {
357 struct meth_private *priv = netdev_priv(dev);
358
359 DPRINTK("Stopping queue\n");
360 netif_stop_queue(dev); /* can't transmit any more */
361 /* shut down DMA */
362 priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
363 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
364 mace->eth.dma_ctrl = priv->dma_ctrl;
365 free_irq(dev->irq, dev);
366 meth_free_tx_ring(priv);
367 meth_free_rx_ring(priv);
368
369 return 0;
370 }
371
372 /*
373 * Receive a packet: retrieve, encapsulate and pass over to upper levels
374 */
375 static void meth_rx(struct net_device* dev, unsigned long int_status)
376 {
377 struct sk_buff *skb;
378 unsigned long status;
379 struct meth_private *priv = netdev_priv(dev);
380 unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
381
382 spin_lock(&priv->meth_lock);
383 priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
384 mace->eth.dma_ctrl = priv->dma_ctrl;
385 spin_unlock(&priv->meth_lock);
386
387 if (int_status & METH_INT_RX_UNDERFLOW) {
388 fifo_rptr = (fifo_rptr - 1) & 0x0f;
389 }
390 while (priv->rx_write != fifo_rptr) {
391 dma_unmap_single(NULL, priv->rx_ring_dmas[priv->rx_write],
392 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
393 status = priv->rx_ring[priv->rx_write]->status.raw;
394 #if MFE_DEBUG
395 if (!(status & METH_RX_ST_VALID)) {
396 DPRINTK("Not received? status=%016lx\n",status);
397 }
398 #endif
399 if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
400 int len = (status & 0xffff) - 4; /* omit CRC */
401 /* length sanity check */
402 if (len < 60 || len > 1518) {
403 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2lx.\n",
404 dev->name, priv->rx_write,
405 priv->rx_ring[priv->rx_write]->status.raw);
406 priv->stats.rx_errors++;
407 priv->stats.rx_length_errors++;
408 skb = priv->rx_skbs[priv->rx_write];
409 } else {
410 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC | GFP_DMA);
411 if (!skb) {
412 /* Ouch! No memory! Drop packet on the floor */
413 DPRINTK("No mem: dropping packet\n");
414 priv->stats.rx_dropped++;
415 skb = priv->rx_skbs[priv->rx_write];
416 } else {
417 struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
418 /* 8byte status vector + 3quad padding + 2byte padding,
419 * to put data on 64bit aligned boundary */
420 skb_reserve(skb, METH_RX_HEAD);
421 /* Write metadata, and then pass to the receive level */
422 skb_put(skb_c, len);
423 priv->rx_skbs[priv->rx_write] = skb;
424 skb_c->protocol = eth_type_trans(skb_c, dev);
425 dev->last_rx = jiffies;
426 priv->stats.rx_packets++;
427 priv->stats.rx_bytes += len;
428 netif_rx(skb_c);
429 }
430 }
431 } else {
432 priv->stats.rx_errors++;
433 skb=priv->rx_skbs[priv->rx_write];
434 #if MFE_DEBUG>0
435 printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
436 if(status&METH_RX_ST_RCV_CODE_VIOLATION)
437 printk(KERN_WARNING "Receive Code Violation\n");
438 if(status&METH_RX_ST_CRC_ERR)
439 printk(KERN_WARNING "CRC error\n");
440 if(status&METH_RX_ST_INV_PREAMBLE_CTX)
441 printk(KERN_WARNING "Invalid Preamble Context\n");
442 if(status&METH_RX_ST_LONG_EVT_SEEN)
443 printk(KERN_WARNING "Long Event Seen...\n");
444 if(status&METH_RX_ST_BAD_PACKET)
445 printk(KERN_WARNING "Bad Packet\n");
446 if(status&METH_RX_ST_CARRIER_EVT_SEEN)
447 printk(KERN_WARNING "Carrier Event Seen\n");
448 #endif
449 }
450 priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
451 priv->rx_ring[priv->rx_write]->status.raw = 0;
452 priv->rx_ring_dmas[priv->rx_write] =
453 dma_map_single(NULL, priv->rx_ring[priv->rx_write],
454 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
455 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
456 ADVANCE_RX_PTR(priv->rx_write);
457 }
458 spin_lock(&priv->meth_lock);
459 /* In case there was underflow, and Rx DMA was disabled */
460 priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
461 mace->eth.dma_ctrl = priv->dma_ctrl;
462 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
463 spin_unlock(&priv->meth_lock);
464 }
465
466 static int meth_tx_full(struct net_device *dev)
467 {
468 struct meth_private *priv = netdev_priv(dev);
469
470 return (priv->tx_count >= TX_RING_ENTRIES - 1);
471 }
472
473 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
474 {
475 struct meth_private *priv = netdev_priv(dev);
476 unsigned long status;
477 struct sk_buff *skb;
478 unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
479
480 spin_lock(&priv->meth_lock);
481
482 /* Stop DMA notification */
483 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
484 mace->eth.dma_ctrl = priv->dma_ctrl;
485
486 while (priv->tx_read != rptr) {
487 skb = priv->tx_skbs[priv->tx_read];
488 status = priv->tx_ring[priv->tx_read].header.raw;
489 #if MFE_DEBUG>=1
490 if (priv->tx_read == priv->tx_write)
491 DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
492 #endif
493 if (status & METH_TX_ST_DONE) {
494 if (status & METH_TX_ST_SUCCESS){
495 priv->stats.tx_packets++;
496 priv->stats.tx_bytes += skb->len;
497 } else {
498 priv->stats.tx_errors++;
499 #if MFE_DEBUG>=1
500 DPRINTK("TX error: status=%016lx <",status);
501 if(status & METH_TX_ST_SUCCESS)
502 printk(" SUCCESS");
503 if(status & METH_TX_ST_TOOLONG)
504 printk(" TOOLONG");
505 if(status & METH_TX_ST_UNDERRUN)
506 printk(" UNDERRUN");
507 if(status & METH_TX_ST_EXCCOLL)
508 printk(" EXCCOLL");
509 if(status & METH_TX_ST_DEFER)
510 printk(" DEFER");
511 if(status & METH_TX_ST_LATECOLL)
512 printk(" LATECOLL");
513 printk(" >\n");
514 #endif
515 }
516 } else {
517 DPRINTK("RPTR points us here, but packet not done?\n");
518 break;
519 }
520 dev_kfree_skb_irq(skb);
521 priv->tx_skbs[priv->tx_read] = NULL;
522 priv->tx_ring[priv->tx_read].header.raw = 0;
523 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
524 priv->tx_count--;
525 }
526
527 /* wake up queue if it was stopped */
528 if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
529 netif_wake_queue(dev);
530 }
531
532 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
533 spin_unlock(&priv->meth_lock);
534 }
535
536 static void meth_error(struct net_device* dev, unsigned status)
537 {
538 struct meth_private *priv = netdev_priv(dev);
539
540 printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
541 /* check for errors too... */
542 if (status & (METH_INT_TX_LINK_FAIL))
543 printk(KERN_WARNING "meth: link failure\n");
544 /* Should I do full reset in this case? */
545 if (status & (METH_INT_MEM_ERROR))
546 printk(KERN_WARNING "meth: memory error\n");
547 if (status & (METH_INT_TX_ABORT))
548 printk(KERN_WARNING "meth: aborted\n");
549 if (status & (METH_INT_RX_OVERFLOW))
550 printk(KERN_WARNING "meth: Rx overflow\n");
551 if (status & (METH_INT_RX_UNDERFLOW)) {
552 printk(KERN_WARNING "meth: Rx underflow\n");
553 spin_lock(&priv->meth_lock);
554 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
555 /* more underflow interrupts will be delivered,
556 * effectively throwing us into an infinite loop.
557 * Thus I stop processing Rx in this case. */
558 priv->dma_ctrl &= ~METH_DMA_RX_EN;
559 mace->eth.dma_ctrl = priv->dma_ctrl;
560 DPRINTK("Disabled meth Rx DMA temporarily\n");
561 spin_unlock(&priv->meth_lock);
562 }
563 mace->eth.int_stat = METH_INT_ERROR;
564 }
565
566 /*
567 * The typical interrupt entry point
568 */
569 static irqreturn_t meth_interrupt(int irq, void *dev_id)
570 {
571 struct net_device *dev = (struct net_device *)dev_id;
572 struct meth_private *priv = netdev_priv(dev);
573 unsigned long status;
574
575 status = mace->eth.int_stat;
576 while (status & 0xff) {
577 /* First handle errors - if we get Rx underflow,
578 * Rx DMA will be disabled, and Rx handler will reenable
579 * it. I don't think it's possible to get Rx underflow,
580 * without getting Rx interrupt */
581 if (status & METH_INT_ERROR) {
582 meth_error(dev, status);
583 }
584 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
585 /* a transmission is over: free the skb */
586 meth_tx_cleanup(dev, status);
587 }
588 if (status & METH_INT_RX_THRESHOLD) {
589 if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
590 break;
591 /* send it to meth_rx for handling */
592 meth_rx(dev, status);
593 }
594 status = mace->eth.int_stat;
595 }
596
597 return IRQ_HANDLED;
598 }
599
600 /*
601 * Transmits packets that fit into TX descriptor (are <=120B)
602 */
603 static void meth_tx_short_prepare(struct meth_private *priv,
604 struct sk_buff *skb)
605 {
606 tx_packet *desc = &priv->tx_ring[priv->tx_write];
607 int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
608
609 desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
610 /* maybe I should set whole thing to 0 first... */
611 skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
612 if (skb->len < len)
613 memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
614 }
615 #define TX_CATBUF1 BIT(25)
616 static void meth_tx_1page_prepare(struct meth_private *priv,
617 struct sk_buff *skb)
618 {
619 tx_packet *desc = &priv->tx_ring[priv->tx_write];
620 void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
621 int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
622 int buffer_len = skb->len - unaligned_len;
623 dma_addr_t catbuf;
624
625 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
626
627 /* unaligned part */
628 if (unaligned_len) {
629 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
630 unaligned_len);
631 desc->header.raw |= (128 - unaligned_len) << 16;
632 }
633
634 /* first page */
635 catbuf = dma_map_single(NULL, buffer_data, buffer_len,
636 DMA_TO_DEVICE);
637 desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
638 desc->data.cat_buf[0].form.len = buffer_len - 1;
639 }
640 #define TX_CATBUF2 BIT(26)
641 static void meth_tx_2page_prepare(struct meth_private *priv,
642 struct sk_buff *skb)
643 {
644 tx_packet *desc = &priv->tx_ring[priv->tx_write];
645 void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
646 void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
647 int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
648 int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
649 int buffer2_len = skb->len - buffer1_len - unaligned_len;
650 dma_addr_t catbuf1, catbuf2;
651
652 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
653 /* unaligned part */
654 if (unaligned_len){
655 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
656 unaligned_len);
657 desc->header.raw |= (128 - unaligned_len) << 16;
658 }
659
660 /* first page */
661 catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
662 DMA_TO_DEVICE);
663 desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
664 desc->data.cat_buf[0].form.len = buffer1_len - 1;
665 /* second page */
666 catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
667 DMA_TO_DEVICE);
668 desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
669 desc->data.cat_buf[1].form.len = buffer2_len - 1;
670 }
671
672 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
673 {
674 /* Remember the skb, so we can free it at interrupt time */
675 priv->tx_skbs[priv->tx_write] = skb;
676 if (skb->len <= 120) {
677 /* Whole packet fits into descriptor */
678 meth_tx_short_prepare(priv, skb);
679 } else if (PAGE_ALIGN((unsigned long)skb->data) !=
680 PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
681 /* Packet crosses page boundary */
682 meth_tx_2page_prepare(priv, skb);
683 } else {
684 /* Packet is in one page */
685 meth_tx_1page_prepare(priv, skb);
686 }
687 priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
688 mace->eth.tx_info = priv->tx_write;
689 priv->tx_count++;
690 }
691
692 /*
693 * Transmit a packet (called by the kernel)
694 */
695 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
696 {
697 struct meth_private *priv = netdev_priv(dev);
698 unsigned long flags;
699
700 spin_lock_irqsave(&priv->meth_lock, flags);
701 /* Stop DMA notification */
702 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
703 mace->eth.dma_ctrl = priv->dma_ctrl;
704
705 meth_add_to_tx_ring(priv, skb);
706 dev->trans_start = jiffies; /* save the timestamp */
707
708 /* If TX ring is full, tell the upper layer to stop sending packets */
709 if (meth_tx_full(dev)) {
710 printk(KERN_DEBUG "TX full: stopping\n");
711 netif_stop_queue(dev);
712 }
713
714 /* Restart DMA notification */
715 priv->dma_ctrl |= METH_DMA_TX_INT_EN;
716 mace->eth.dma_ctrl = priv->dma_ctrl;
717
718 spin_unlock_irqrestore(&priv->meth_lock, flags);
719
720 return 0;
721 }
722
723 /*
724 * Deal with a transmit timeout.
725 */
726 static void meth_tx_timeout(struct net_device *dev)
727 {
728 struct meth_private *priv = netdev_priv(dev);
729 unsigned long flags;
730
731 printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
732
733 /* Protect against concurrent rx interrupts */
734 spin_lock_irqsave(&priv->meth_lock,flags);
735
736 /* Try to reset the interface. */
737 meth_reset(dev);
738
739 priv->stats.tx_errors++;
740
741 /* Clear all rings */
742 meth_free_tx_ring(priv);
743 meth_free_rx_ring(priv);
744 meth_init_tx_ring(priv);
745 meth_init_rx_ring(priv);
746
747 /* Restart dma */
748 priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
749 mace->eth.dma_ctrl = priv->dma_ctrl;
750
751 /* Enable interrupt */
752 spin_unlock_irqrestore(&priv->meth_lock, flags);
753
754 dev->trans_start = jiffies;
755 netif_wake_queue(dev);
756
757 return;
758 }
759
760 /*
761 * Ioctl commands
762 */
763 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
764 {
765 /* XXX Not yet implemented */
766 switch(cmd) {
767 case SIOCGMIIPHY:
768 case SIOCGMIIREG:
769 case SIOCSMIIREG:
770 default:
771 return -EOPNOTSUPP;
772 }
773 }
774
775 /*
776 * Return statistics to the caller
777 */
778 static struct net_device_stats *meth_stats(struct net_device *dev)
779 {
780 struct meth_private *priv = netdev_priv(dev);
781 return &priv->stats;
782 }
783
784 /*
785 * The init function.
786 */
787 static struct net_device *meth_init(void)
788 {
789 struct net_device *dev;
790 struct meth_private *priv;
791 int ret;
792
793 dev = alloc_etherdev(sizeof(struct meth_private));
794 if (!dev)
795 return ERR_PTR(-ENOMEM);
796
797 dev->open = meth_open;
798 dev->stop = meth_release;
799 dev->hard_start_xmit = meth_tx;
800 dev->do_ioctl = meth_ioctl;
801 dev->get_stats = meth_stats;
802 #ifdef HAVE_TX_TIMEOUT
803 dev->tx_timeout = meth_tx_timeout;
804 dev->watchdog_timeo = timeout;
805 #endif
806 dev->irq = MACE_ETHERNET_IRQ;
807 dev->base_addr = (unsigned long)&mace->eth;
808
809 priv = netdev_priv(dev);
810 spin_lock_init(&priv->meth_lock);
811
812 ret = register_netdev(dev);
813 if (ret) {
814 free_netdev(dev);
815 return ERR_PTR(ret);
816 }
817
818 printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
819 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
820 return 0;
821 }
822
823 static struct net_device *meth_dev;
824
825 static int __init meth_init_module(void)
826 {
827 meth_dev = meth_init();
828 if (IS_ERR(meth_dev))
829 return PTR_ERR(meth_dev);
830 return 0;
831 }
832
833 static void __exit meth_exit_module(void)
834 {
835 unregister_netdev(meth_dev);
836 free_netdev(meth_dev);
837 }
838
839 module_init(meth_init_module);
840 module_exit(meth_exit_module);
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