arch/microblaze/kernel/timer.c

   1 /*
   2  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2007-2009 PetaLogix
   4  * Copyright (C) 2006 Atmark Techno, Inc.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/param.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/profile.h>
  16 #include <linux/irq.h>
  17 #include <linux/delay.h>
  18 #include <linux/sched.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/clockchips.h>
  24 #include <linux/io.h>
  25 #include <linux/bug.h>
  26 #include <asm/cpuinfo.h>
  27 #include <asm/setup.h>
  28 #include <asm/prom.h>
  29 #include <asm/irq.h>
  30 #include <asm/system.h>
  31
  32 #ifdef CONFIG_SELFMOD_TIMER
  33 #include <asm/selfmod.h>
  34 #define TIMER_BASE      BARRIER_BASE_ADDR
  35 #else
  36 static unsigned int timer_baseaddr;
  37 #define TIMER_BASE      timer_baseaddr
  38 #endif
  39
  40 #define TCSR0   (0x00)
  41 #define TLR0    (0x04)
  42 #define TCR0    (0x08)
  43 #define TCSR1   (0x10)
  44 #define TLR1    (0x14)
  45 #define TCR1    (0x18)
  46
  47 #define TCSR_MDT        (1<<0)
  48 #define TCSR_UDT        (1<<1)
  49 #define TCSR_GENT       (1<<2)
  50 #define TCSR_CAPT       (1<<3)
  51 #define TCSR_ARHT       (1<<4)
  52 #define TCSR_LOAD       (1<<5)
  53 #define TCSR_ENIT       (1<<6)
  54 #define TCSR_ENT        (1<<7)
  55 #define TCSR_TINT       (1<<8)
  56 #define TCSR_PWMA       (1<<9)
  57 #define TCSR_ENALL      (1<<10)
  58
  59 static inline void microblaze_timer0_stop(void)
  60 {
  61         out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
  62 }
  63
  64 static inline void microblaze_timer0_start_periodic(unsigned long load_val)
  65 {
  66         if (!load_val)
  67                 load_val = 1;
  68         out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
  69
  70         /* load the initial value */
  71         out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
  72
  73         /* see timer data sheet for detail
  74          * !ENALL - don't enable 'em all
  75          * !PWMA - disable pwm
  76          * TINT - clear interrupt status
  77          * ENT- enable timer itself
  78          * EINT - enable interrupt
  79          * !LOAD - clear the bit to let go
  80          * ARHT - auto reload
  81          * !CAPT - no external trigger
  82          * !GENT - no external signal
  83          * UDT - set the timer as down counter
  84          * !MDT0 - generate mode
  85          */
  86         out_be32(TIMER_BASE + TCSR0,
  87                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
  88 }
  89
  90 static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
  91 {
  92         if (!load_val)
  93                 load_val = 1;
  94         out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
  95
  96         /* load the initial value */
  97         out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
  98
  99         out_be32(TIMER_BASE + TCSR0,
 100                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
 101 }
 102
 103 static int microblaze_timer_set_next_event(unsigned long delta,
 104                                         struct clock_event_device *dev)
 105 {
 106         pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
 107         microblaze_timer0_start_oneshot(delta);
 108         return 0;
 109 }
 110
 111 static void microblaze_timer_set_mode(enum clock_event_mode mode,
 112                                 struct clock_event_device *evt)
 113 {
 114         switch (mode) {
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 printk(KERN_INFO "%s: periodic\n", __func__);
 117                 microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
 118                 break;
 119         case CLOCK_EVT_MODE_ONESHOT:
 120                 printk(KERN_INFO "%s: oneshot\n", __func__);
 121                 break;
 122         case CLOCK_EVT_MODE_UNUSED:
 123                 printk(KERN_INFO "%s: unused\n", __func__);
 124                 break;
 125         case CLOCK_EVT_MODE_SHUTDOWN:
 126                 printk(KERN_INFO "%s: shutdown\n", __func__);
 127                 microblaze_timer0_stop();
 128                 break;
 129         case CLOCK_EVT_MODE_RESUME:
 130                 printk(KERN_INFO "%s: resume\n", __func__);
 131                 break;
 132         }
 133 }
 134
 135 static struct clock_event_device clockevent_microblaze_timer = {
 136         .name           = "microblaze_clockevent",
 137         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 138         .shift          = 24,
 139         .rating         = 300,
 140         .set_next_event = microblaze_timer_set_next_event,
 141         .set_mode       = microblaze_timer_set_mode,
 142 };
 143
 144 static inline void timer_ack(void)
 145 {
 146         out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
 147 }
 148
 149 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 150 {
 151         struct clock_event_device *evt = &clockevent_microblaze_timer;
 152 #ifdef CONFIG_HEART_BEAT
 153         heartbeat();
 154 #endif
 155         timer_ack();
 156         evt->event_handler(evt);
 157         return IRQ_HANDLED;
 158 }
 159
 160 static struct irqaction timer_irqaction = {
 161         .handler = timer_interrupt,
 162         .flags = IRQF_DISABLED | IRQF_TIMER,
 163         .name = "timer",
 164         .dev_id = &clockevent_microblaze_timer,
 165 };
 166
 167 static __init void microblaze_clockevent_init(void)
 168 {
 169         clockevent_microblaze_timer.mult =
 170                 div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
 171                                 clockevent_microblaze_timer.shift);
 172         clockevent_microblaze_timer.max_delta_ns =
 173                 clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
 174         clockevent_microblaze_timer.min_delta_ns =
 175                 clockevent_delta2ns(1, &clockevent_microblaze_timer);
 176         clockevent_microblaze_timer.cpumask = cpumask_of(0);
 177         clockevents_register_device(&clockevent_microblaze_timer);
 178 }
 179
 180 static cycle_t microblaze_read(struct clocksource *cs)
 181 {
 182         /* reading actual value of timer 1 */
 183         return (cycle_t) (in_be32(TIMER_BASE + TCR1));
 184 }
 185
 186 static struct clocksource clocksource_microblaze = {
 187         .name           = "microblaze_clocksource",
 188         .rating         = 300,
 189         .read           = microblaze_read,
 190         .mask           = CLOCKSOURCE_MASK(32),
 191         .shift          = 24, /* I can shift it */
 192         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 193 };
 194
 195 static int __init microblaze_clocksource_init(void)
 196 {
 197         clocksource_microblaze.mult =
 198                         clocksource_hz2mult(cpuinfo.cpu_clock_freq,
 199                                                 clocksource_microblaze.shift);
 200         if (clocksource_register(&clocksource_microblaze))
 201                 panic("failed to register clocksource");
 202
 203         /* stop timer1 */
 204         out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
 205         /* start timer1 - up counting without interrupt */
 206         out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
 207         return 0;
 208 }
 209
 210 void __init time_init(void)
 211 {
 212         u32 irq, i = 0;
 213         u32 timer_num = 1;
 214         struct device_node *timer = NULL;
 215 #ifdef CONFIG_SELFMOD_TIMER
 216         unsigned int timer_baseaddr = 0;
 217         int arr_func[] = {
 218                                 (int)&microblaze_read,
 219                                 (int)&timer_interrupt,
 220                                 (int)&microblaze_clocksource_init,
 221                                 (int)&microblaze_timer_set_mode,
 222                                 (int)&microblaze_timer_set_next_event,
 223                                 0
 224                         };
 225 #endif
 226         char *timer_list[] = {
 227                                 "xlnx,xps-timer-1.00.a",
 228                                 "xlnx,opb-timer-1.00.b",
 229                                 "xlnx,opb-timer-1.00.a",
 230                                 NULL
 231                         };
 232
 233         for (i = 0; timer_list[i] != NULL; i++) {
 234                 timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
 235                 if (timer)
 236                         break;
 237         }
 238         BUG_ON(!timer);
 239
 240         timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
 241         timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
 242         irq = *(int *) of_get_property(timer, "interrupts", NULL);
 243         timer_num =
 244                 *(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);
 245         if (timer_num) {
 246                 printk(KERN_EMERG "Please enable two timers in HW\n");
 247                 BUG();
 248         }
 249
 250 #ifdef CONFIG_SELFMOD_TIMER
 251         selfmod_function((int *) arr_func, timer_baseaddr);
 252 #endif
 253         printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
 254                 timer_list[i], timer_baseaddr, irq);
 255
 256         cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
 257
 258         setup_irq(irq, &timer_irqaction);
 259 #ifdef CONFIG_HEART_BEAT
 260         setup_heartbeat();
 261 #endif
 262         microblaze_clocksource_init();
 263         microblaze_clockevent_init();
 264 }