2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn
)
70 return dma_pfn
>> (PAGE_SHIFT
- VTD_PAGE_SHIFT
);
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn
)
75 return mm_pfn
<< (PAGE_SHIFT
- VTD_PAGE_SHIFT
);
77 static inline unsigned long page_to_dma_pfn(struct page
*pg
)
79 return mm_to_dma_pfn(page_to_pfn(pg
));
81 static inline unsigned long virt_to_dma_pfn(void *p
)
83 return page_to_dma_pfn(virt_to_page(p
));
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu
**g_iommus
;
89 static int rwbf_quirk
;
94 * 12-63: Context Ptr (12 - (haw-1))
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry
*root
)
104 return (root
->val
& 1);
106 static inline void set_root_present(struct root_entry
*root
)
110 static inline void set_root_value(struct root_entry
*root
, unsigned long value
)
112 root
->val
|= value
& VTD_PAGE_MASK
;
115 static inline struct context_entry
*
116 get_context_addr_from_root(struct root_entry
*root
)
118 return (struct context_entry
*)
119 (root_present(root
)?phys_to_virt(
120 root
->val
& VTD_PAGE_MASK
) :
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
135 struct context_entry
{
140 static inline bool context_present(struct context_entry
*context
)
142 return (context
->lo
& 1);
144 static inline void context_set_present(struct context_entry
*context
)
149 static inline void context_set_fault_enable(struct context_entry
*context
)
151 context
->lo
&= (((u64
)-1) << 2) | 1;
154 static inline void context_set_translation_type(struct context_entry
*context
,
157 context
->lo
&= (((u64
)-1) << 4) | 3;
158 context
->lo
|= (value
& 3) << 2;
161 static inline void context_set_address_root(struct context_entry
*context
,
164 context
->lo
|= value
& VTD_PAGE_MASK
;
167 static inline void context_set_address_width(struct context_entry
*context
,
170 context
->hi
|= value
& 7;
173 static inline void context_set_domain_id(struct context_entry
*context
,
176 context
->hi
|= (value
& ((1 << 16) - 1)) << 8;
179 static inline void context_clear_entry(struct context_entry
*context
)
192 * 12-63: Host physcial address
198 static inline void dma_clear_pte(struct dma_pte
*pte
)
203 static inline void dma_set_pte_readable(struct dma_pte
*pte
)
205 pte
->val
|= DMA_PTE_READ
;
208 static inline void dma_set_pte_writable(struct dma_pte
*pte
)
210 pte
->val
|= DMA_PTE_WRITE
;
213 static inline void dma_set_pte_snp(struct dma_pte
*pte
)
215 pte
->val
|= DMA_PTE_SNP
;
218 static inline void dma_set_pte_prot(struct dma_pte
*pte
, unsigned long prot
)
220 pte
->val
= (pte
->val
& ~3) | (prot
& 3);
223 static inline u64
dma_pte_addr(struct dma_pte
*pte
)
225 return (pte
->val
& VTD_PAGE_MASK
);
228 static inline void dma_set_pte_pfn(struct dma_pte
*pte
, unsigned long pfn
)
230 pte
->val
|= (uint64_t)pfn
<< VTD_PAGE_SHIFT
;
233 static inline bool dma_pte_present(struct dma_pte
*pte
)
235 return (pte
->val
& 3) != 0;
239 * This domain is a statically identity mapping domain.
240 * 1. This domain creats a static 1:1 mapping to all usable memory.
241 * 2. It maps to each iommu if successful.
242 * 3. Each iommu mapps to this domain if successful.
244 struct dmar_domain
*si_domain
;
246 /* devices under the same p2p bridge are owned in one domain */
247 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
249 /* domain represents a virtual machine, more than one devices
250 * across iommus may be owned in one domain, e.g. kvm guest.
252 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
254 /* si_domain contains mulitple devices */
255 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
258 int id
; /* domain id */
259 unsigned long iommu_bmp
; /* bitmap of iommus this domain uses*/
261 struct list_head devices
; /* all devices' list */
262 struct iova_domain iovad
; /* iova's that belong to this domain */
264 struct dma_pte
*pgd
; /* virtual address */
265 spinlock_t mapping_lock
; /* page table lock */
266 int gaw
; /* max guest address width */
268 /* adjusted guest address width, 0 is level 2 30-bit */
271 int flags
; /* flags to find out type of domain */
273 int iommu_coherency
;/* indicate coherency of iommu access */
274 int iommu_snooping
; /* indicate snooping control feature*/
275 int iommu_count
; /* reference count of iommu */
276 spinlock_t iommu_lock
; /* protect iommu set in domain */
277 u64 max_addr
; /* maximum mapped address */
280 /* PCI domain-device relationship */
281 struct device_domain_info
{
282 struct list_head link
; /* link to domain siblings */
283 struct list_head global
; /* link to global list */
284 int segment
; /* PCI domain */
285 u8 bus
; /* PCI bus number */
286 u8 devfn
; /* PCI devfn number */
287 struct pci_dev
*dev
; /* it's NULL for PCIE-to-PCI bridge */
288 struct intel_iommu
*iommu
; /* IOMMU used by this device */
289 struct dmar_domain
*domain
; /* pointer to domain */
292 static void flush_unmaps_timeout(unsigned long data
);
294 DEFINE_TIMER(unmap_timer
, flush_unmaps_timeout
, 0, 0);
296 #define HIGH_WATER_MARK 250
297 struct deferred_flush_tables
{
299 struct iova
*iova
[HIGH_WATER_MARK
];
300 struct dmar_domain
*domain
[HIGH_WATER_MARK
];
303 static struct deferred_flush_tables
*deferred_flush
;
305 /* bitmap for indexing intel_iommus */
306 static int g_num_of_iommus
;
308 static DEFINE_SPINLOCK(async_umap_flush_lock
);
309 static LIST_HEAD(unmaps_to_do
);
312 static long list_size
;
314 static void domain_remove_dev_info(struct dmar_domain
*domain
);
316 #ifdef CONFIG_DMAR_DEFAULT_ON
317 int dmar_disabled
= 0;
319 int dmar_disabled
= 1;
320 #endif /*CONFIG_DMAR_DEFAULT_ON*/
322 static int __initdata dmar_map_gfx
= 1;
323 static int dmar_forcedac
;
324 static int intel_iommu_strict
;
326 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
327 static DEFINE_SPINLOCK(device_domain_lock
);
328 static LIST_HEAD(device_domain_list
);
330 static struct iommu_ops intel_iommu_ops
;
332 static int __init
intel_iommu_setup(char *str
)
337 if (!strncmp(str
, "on", 2)) {
339 printk(KERN_INFO
"Intel-IOMMU: enabled\n");
340 } else if (!strncmp(str
, "off", 3)) {
342 printk(KERN_INFO
"Intel-IOMMU: disabled\n");
343 } else if (!strncmp(str
, "igfx_off", 8)) {
346 "Intel-IOMMU: disable GFX device mapping\n");
347 } else if (!strncmp(str
, "forcedac", 8)) {
349 "Intel-IOMMU: Forcing DAC for PCI devices\n");
351 } else if (!strncmp(str
, "strict", 6)) {
353 "Intel-IOMMU: disable batched IOTLB flush\n");
354 intel_iommu_strict
= 1;
357 str
+= strcspn(str
, ",");
363 __setup("intel_iommu=", intel_iommu_setup
);
365 static struct kmem_cache
*iommu_domain_cache
;
366 static struct kmem_cache
*iommu_devinfo_cache
;
367 static struct kmem_cache
*iommu_iova_cache
;
369 static inline void *iommu_kmem_cache_alloc(struct kmem_cache
*cachep
)
374 /* trying to avoid low memory issues */
375 flags
= current
->flags
& PF_MEMALLOC
;
376 current
->flags
|= PF_MEMALLOC
;
377 vaddr
= kmem_cache_alloc(cachep
, GFP_ATOMIC
);
378 current
->flags
&= (~PF_MEMALLOC
| flags
);
383 static inline void *alloc_pgtable_page(void)
388 /* trying to avoid low memory issues */
389 flags
= current
->flags
& PF_MEMALLOC
;
390 current
->flags
|= PF_MEMALLOC
;
391 vaddr
= (void *)get_zeroed_page(GFP_ATOMIC
);
392 current
->flags
&= (~PF_MEMALLOC
| flags
);
396 static inline void free_pgtable_page(void *vaddr
)
398 free_page((unsigned long)vaddr
);
401 static inline void *alloc_domain_mem(void)
403 return iommu_kmem_cache_alloc(iommu_domain_cache
);
406 static void free_domain_mem(void *vaddr
)
408 kmem_cache_free(iommu_domain_cache
, vaddr
);
411 static inline void * alloc_devinfo_mem(void)
413 return iommu_kmem_cache_alloc(iommu_devinfo_cache
);
416 static inline void free_devinfo_mem(void *vaddr
)
418 kmem_cache_free(iommu_devinfo_cache
, vaddr
);
421 struct iova
*alloc_iova_mem(void)
423 return iommu_kmem_cache_alloc(iommu_iova_cache
);
426 void free_iova_mem(struct iova
*iova
)
428 kmem_cache_free(iommu_iova_cache
, iova
);
432 static inline int width_to_agaw(int width
);
434 static int __iommu_calculate_agaw(struct intel_iommu
*iommu
, int max_gaw
)
439 sagaw
= cap_sagaw(iommu
->cap
);
440 for (agaw
= width_to_agaw(max_gaw
);
442 if (test_bit(agaw
, &sagaw
))
450 * Calculate max SAGAW for each iommu.
452 int iommu_calculate_max_sagaw(struct intel_iommu
*iommu
)
454 return __iommu_calculate_agaw(iommu
, MAX_AGAW_WIDTH
);
458 * calculate agaw for each iommu.
459 * "SAGAW" may be different across iommus, use a default agaw, and
460 * get a supported less agaw for iommus that don't support the default agaw.
462 int iommu_calculate_agaw(struct intel_iommu
*iommu
)
464 return __iommu_calculate_agaw(iommu
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
467 /* This functionin only returns single iommu in a domain */
468 static struct intel_iommu
*domain_get_iommu(struct dmar_domain
*domain
)
472 /* si_domain and vm domain should not get here. */
473 BUG_ON(domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
);
474 BUG_ON(domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
);
476 iommu_id
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
477 if (iommu_id
< 0 || iommu_id
>= g_num_of_iommus
)
480 return g_iommus
[iommu_id
];
483 static void domain_update_iommu_coherency(struct dmar_domain
*domain
)
487 domain
->iommu_coherency
= 1;
489 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
490 for (; i
< g_num_of_iommus
; ) {
491 if (!ecap_coherent(g_iommus
[i
]->ecap
)) {
492 domain
->iommu_coherency
= 0;
495 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
499 static void domain_update_iommu_snooping(struct dmar_domain
*domain
)
503 domain
->iommu_snooping
= 1;
505 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
506 for (; i
< g_num_of_iommus
; ) {
507 if (!ecap_sc_support(g_iommus
[i
]->ecap
)) {
508 domain
->iommu_snooping
= 0;
511 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
515 /* Some capabilities may be different across iommus */
516 static void domain_update_iommu_cap(struct dmar_domain
*domain
)
518 domain_update_iommu_coherency(domain
);
519 domain_update_iommu_snooping(domain
);
522 static struct intel_iommu
*device_to_iommu(int segment
, u8 bus
, u8 devfn
)
524 struct dmar_drhd_unit
*drhd
= NULL
;
527 for_each_drhd_unit(drhd
) {
530 if (segment
!= drhd
->segment
)
533 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
534 if (drhd
->devices
[i
] &&
535 drhd
->devices
[i
]->bus
->number
== bus
&&
536 drhd
->devices
[i
]->devfn
== devfn
)
538 if (drhd
->devices
[i
] &&
539 drhd
->devices
[i
]->subordinate
&&
540 drhd
->devices
[i
]->subordinate
->number
<= bus
&&
541 drhd
->devices
[i
]->subordinate
->subordinate
>= bus
)
545 if (drhd
->include_all
)
552 static void domain_flush_cache(struct dmar_domain
*domain
,
553 void *addr
, int size
)
555 if (!domain
->iommu_coherency
)
556 clflush_cache_range(addr
, size
);
559 /* Gets context entry for a given bus and devfn */
560 static struct context_entry
* device_to_context_entry(struct intel_iommu
*iommu
,
563 struct root_entry
*root
;
564 struct context_entry
*context
;
565 unsigned long phy_addr
;
568 spin_lock_irqsave(&iommu
->lock
, flags
);
569 root
= &iommu
->root_entry
[bus
];
570 context
= get_context_addr_from_root(root
);
572 context
= (struct context_entry
*)alloc_pgtable_page();
574 spin_unlock_irqrestore(&iommu
->lock
, flags
);
577 __iommu_flush_cache(iommu
, (void *)context
, CONTEXT_SIZE
);
578 phy_addr
= virt_to_phys((void *)context
);
579 set_root_value(root
, phy_addr
);
580 set_root_present(root
);
581 __iommu_flush_cache(iommu
, root
, sizeof(*root
));
583 spin_unlock_irqrestore(&iommu
->lock
, flags
);
584 return &context
[devfn
];
587 static int device_context_mapped(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
589 struct root_entry
*root
;
590 struct context_entry
*context
;
594 spin_lock_irqsave(&iommu
->lock
, flags
);
595 root
= &iommu
->root_entry
[bus
];
596 context
= get_context_addr_from_root(root
);
601 ret
= context_present(&context
[devfn
]);
603 spin_unlock_irqrestore(&iommu
->lock
, flags
);
607 static void clear_context_table(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
609 struct root_entry
*root
;
610 struct context_entry
*context
;
613 spin_lock_irqsave(&iommu
->lock
, flags
);
614 root
= &iommu
->root_entry
[bus
];
615 context
= get_context_addr_from_root(root
);
617 context_clear_entry(&context
[devfn
]);
618 __iommu_flush_cache(iommu
, &context
[devfn
], \
621 spin_unlock_irqrestore(&iommu
->lock
, flags
);
624 static void free_context_table(struct intel_iommu
*iommu
)
626 struct root_entry
*root
;
629 struct context_entry
*context
;
631 spin_lock_irqsave(&iommu
->lock
, flags
);
632 if (!iommu
->root_entry
) {
635 for (i
= 0; i
< ROOT_ENTRY_NR
; i
++) {
636 root
= &iommu
->root_entry
[i
];
637 context
= get_context_addr_from_root(root
);
639 free_pgtable_page(context
);
641 free_pgtable_page(iommu
->root_entry
);
642 iommu
->root_entry
= NULL
;
644 spin_unlock_irqrestore(&iommu
->lock
, flags
);
647 /* page table handling */
648 #define LEVEL_STRIDE (9)
649 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
651 static inline int agaw_to_level(int agaw
)
656 static inline int agaw_to_width(int agaw
)
658 return 30 + agaw
* LEVEL_STRIDE
;
662 static inline int width_to_agaw(int width
)
664 return (width
- 30) / LEVEL_STRIDE
;
667 static inline unsigned int level_to_offset_bits(int level
)
669 return (level
- 1) * LEVEL_STRIDE
;
672 static inline int pfn_level_offset(unsigned long pfn
, int level
)
674 return (pfn
>> level_to_offset_bits(level
)) & LEVEL_MASK
;
677 static inline unsigned long level_mask(int level
)
679 return -1UL << level_to_offset_bits(level
);
682 static inline unsigned long level_size(int level
)
684 return 1UL << level_to_offset_bits(level
);
687 static inline unsigned long align_to_level(unsigned long pfn
, int level
)
689 return (pfn
+ level_size(level
) - 1) & level_mask(level
);
692 static struct dma_pte
*pfn_to_dma_pte(struct dmar_domain
*domain
,
695 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
696 struct dma_pte
*parent
, *pte
= NULL
;
697 int level
= agaw_to_level(domain
->agaw
);
701 BUG_ON(!domain
->pgd
);
702 BUG_ON(addr_width
< BITS_PER_LONG
&& pfn
>> addr_width
);
703 parent
= domain
->pgd
;
705 spin_lock_irqsave(&domain
->mapping_lock
, flags
);
709 offset
= pfn_level_offset(pfn
, level
);
710 pte
= &parent
[offset
];
714 if (!dma_pte_present(pte
)) {
715 tmp_page
= alloc_pgtable_page();
718 spin_unlock_irqrestore(&domain
->mapping_lock
,
722 domain_flush_cache(domain
, tmp_page
, PAGE_SIZE
);
723 dma_set_pte_pfn(pte
, virt_to_dma_pfn(tmp_page
));
725 * high level table always sets r/w, last level page
726 * table control read/write
728 dma_set_pte_readable(pte
);
729 dma_set_pte_writable(pte
);
730 domain_flush_cache(domain
, pte
, sizeof(*pte
));
732 parent
= phys_to_virt(dma_pte_addr(pte
));
736 spin_unlock_irqrestore(&domain
->mapping_lock
, flags
);
740 /* return address's pte at specific level */
741 static struct dma_pte
*dma_pfn_level_pte(struct dmar_domain
*domain
,
745 struct dma_pte
*parent
, *pte
= NULL
;
746 int total
= agaw_to_level(domain
->agaw
);
749 parent
= domain
->pgd
;
750 while (level
<= total
) {
751 offset
= pfn_level_offset(pfn
, total
);
752 pte
= &parent
[offset
];
756 if (!dma_pte_present(pte
))
758 parent
= phys_to_virt(dma_pte_addr(pte
));
764 /* clear last level pte, a tlb flush should be followed */
765 static void dma_pte_clear_range(struct dmar_domain
*domain
,
766 unsigned long start_pfn
,
767 unsigned long last_pfn
)
769 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
770 struct dma_pte
*first_pte
, *pte
;
772 BUG_ON(addr_width
< BITS_PER_LONG
&& start_pfn
>> addr_width
);
773 BUG_ON(addr_width
< BITS_PER_LONG
&& last_pfn
>> addr_width
);
775 /* we don't need lock here; nobody else touches the iova range */
776 while (start_pfn
<= last_pfn
) {
777 first_pte
= pte
= dma_pfn_level_pte(domain
, start_pfn
, 1);
779 start_pfn
= align_to_level(start_pfn
+ 1, 2);
782 while (start_pfn
<= last_pfn
&&
783 (unsigned long)pte
>> VTD_PAGE_SHIFT
==
784 (unsigned long)first_pte
>> VTD_PAGE_SHIFT
) {
789 domain_flush_cache(domain
, first_pte
,
790 (void *)pte
- (void *)first_pte
);
794 /* free page table pages. last level pte should already be cleared */
795 static void dma_pte_free_pagetable(struct dmar_domain
*domain
,
796 unsigned long start_pfn
,
797 unsigned long last_pfn
)
799 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
801 int total
= agaw_to_level(domain
->agaw
);
805 BUG_ON(addr_width
< BITS_PER_LONG
&& start_pfn
>> addr_width
);
806 BUG_ON(addr_width
< BITS_PER_LONG
&& last_pfn
>> addr_width
);
808 /* we don't need lock here, nobody else touches the iova range */
810 while (level
<= total
) {
811 tmp
= align_to_level(start_pfn
, level
);
813 /* Only clear this pte/pmd if we're asked to clear its
815 if (tmp
+ level_size(level
) - 1 > last_pfn
)
818 while (tmp
<= last_pfn
) {
819 pte
= dma_pfn_level_pte(domain
, tmp
, level
);
822 phys_to_virt(dma_pte_addr(pte
)));
824 domain_flush_cache(domain
, pte
, sizeof(*pte
));
826 tmp
+= level_size(level
);
831 if (start_pfn
== 0 && last_pfn
== DOMAIN_MAX_PFN(domain
->gaw
)) {
832 free_pgtable_page(domain
->pgd
);
838 static int iommu_alloc_root_entry(struct intel_iommu
*iommu
)
840 struct root_entry
*root
;
843 root
= (struct root_entry
*)alloc_pgtable_page();
847 __iommu_flush_cache(iommu
, root
, ROOT_SIZE
);
849 spin_lock_irqsave(&iommu
->lock
, flags
);
850 iommu
->root_entry
= root
;
851 spin_unlock_irqrestore(&iommu
->lock
, flags
);
856 static void iommu_set_root_entry(struct intel_iommu
*iommu
)
862 addr
= iommu
->root_entry
;
864 spin_lock_irqsave(&iommu
->register_lock
, flag
);
865 dmar_writeq(iommu
->reg
+ DMAR_RTADDR_REG
, virt_to_phys(addr
));
867 writel(iommu
->gcmd
| DMA_GCMD_SRTP
, iommu
->reg
+ DMAR_GCMD_REG
);
869 /* Make sure hardware complete it */
870 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
871 readl
, (sts
& DMA_GSTS_RTPS
), sts
);
873 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
876 static void iommu_flush_write_buffer(struct intel_iommu
*iommu
)
881 if (!rwbf_quirk
&& !cap_rwbf(iommu
->cap
))
884 spin_lock_irqsave(&iommu
->register_lock
, flag
);
885 writel(iommu
->gcmd
| DMA_GCMD_WBF
, iommu
->reg
+ DMAR_GCMD_REG
);
887 /* Make sure hardware complete it */
888 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
889 readl
, (!(val
& DMA_GSTS_WBFS
)), val
);
891 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
894 /* return value determine if we need a write buffer flush */
895 static void __iommu_flush_context(struct intel_iommu
*iommu
,
896 u16 did
, u16 source_id
, u8 function_mask
,
903 case DMA_CCMD_GLOBAL_INVL
:
904 val
= DMA_CCMD_GLOBAL_INVL
;
906 case DMA_CCMD_DOMAIN_INVL
:
907 val
= DMA_CCMD_DOMAIN_INVL
|DMA_CCMD_DID(did
);
909 case DMA_CCMD_DEVICE_INVL
:
910 val
= DMA_CCMD_DEVICE_INVL
|DMA_CCMD_DID(did
)
911 | DMA_CCMD_SID(source_id
) | DMA_CCMD_FM(function_mask
);
918 spin_lock_irqsave(&iommu
->register_lock
, flag
);
919 dmar_writeq(iommu
->reg
+ DMAR_CCMD_REG
, val
);
921 /* Make sure hardware complete it */
922 IOMMU_WAIT_OP(iommu
, DMAR_CCMD_REG
,
923 dmar_readq
, (!(val
& DMA_CCMD_ICC
)), val
);
925 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
928 /* return value determine if we need a write buffer flush */
929 static void __iommu_flush_iotlb(struct intel_iommu
*iommu
, u16 did
,
930 u64 addr
, unsigned int size_order
, u64 type
)
932 int tlb_offset
= ecap_iotlb_offset(iommu
->ecap
);
933 u64 val
= 0, val_iva
= 0;
937 case DMA_TLB_GLOBAL_FLUSH
:
938 /* global flush doesn't need set IVA_REG */
939 val
= DMA_TLB_GLOBAL_FLUSH
|DMA_TLB_IVT
;
941 case DMA_TLB_DSI_FLUSH
:
942 val
= DMA_TLB_DSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
944 case DMA_TLB_PSI_FLUSH
:
945 val
= DMA_TLB_PSI_FLUSH
|DMA_TLB_IVT
|DMA_TLB_DID(did
);
946 /* Note: always flush non-leaf currently */
947 val_iva
= size_order
| addr
;
952 /* Note: set drain read/write */
955 * This is probably to be super secure.. Looks like we can
956 * ignore it without any impact.
958 if (cap_read_drain(iommu
->cap
))
959 val
|= DMA_TLB_READ_DRAIN
;
961 if (cap_write_drain(iommu
->cap
))
962 val
|= DMA_TLB_WRITE_DRAIN
;
964 spin_lock_irqsave(&iommu
->register_lock
, flag
);
965 /* Note: Only uses first TLB reg currently */
967 dmar_writeq(iommu
->reg
+ tlb_offset
, val_iva
);
968 dmar_writeq(iommu
->reg
+ tlb_offset
+ 8, val
);
970 /* Make sure hardware complete it */
971 IOMMU_WAIT_OP(iommu
, tlb_offset
+ 8,
972 dmar_readq
, (!(val
& DMA_TLB_IVT
)), val
);
974 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
976 /* check IOTLB invalidation granularity */
977 if (DMA_TLB_IAIG(val
) == 0)
978 printk(KERN_ERR
"IOMMU: flush IOTLB failed\n");
979 if (DMA_TLB_IAIG(val
) != DMA_TLB_IIRG(type
))
980 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
981 (unsigned long long)DMA_TLB_IIRG(type
),
982 (unsigned long long)DMA_TLB_IAIG(val
));
985 static struct device_domain_info
*iommu_support_dev_iotlb(
986 struct dmar_domain
*domain
, int segment
, u8 bus
, u8 devfn
)
990 struct device_domain_info
*info
;
991 struct intel_iommu
*iommu
= device_to_iommu(segment
, bus
, devfn
);
993 if (!ecap_dev_iotlb_support(iommu
->ecap
))
999 spin_lock_irqsave(&device_domain_lock
, flags
);
1000 list_for_each_entry(info
, &domain
->devices
, link
)
1001 if (info
->bus
== bus
&& info
->devfn
== devfn
) {
1005 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1007 if (!found
|| !info
->dev
)
1010 if (!pci_find_ext_capability(info
->dev
, PCI_EXT_CAP_ID_ATS
))
1013 if (!dmar_find_matched_atsr_unit(info
->dev
))
1016 info
->iommu
= iommu
;
1021 static void iommu_enable_dev_iotlb(struct device_domain_info
*info
)
1026 pci_enable_ats(info
->dev
, VTD_PAGE_SHIFT
);
1029 static void iommu_disable_dev_iotlb(struct device_domain_info
*info
)
1031 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1034 pci_disable_ats(info
->dev
);
1037 static void iommu_flush_dev_iotlb(struct dmar_domain
*domain
,
1038 u64 addr
, unsigned mask
)
1041 unsigned long flags
;
1042 struct device_domain_info
*info
;
1044 spin_lock_irqsave(&device_domain_lock
, flags
);
1045 list_for_each_entry(info
, &domain
->devices
, link
) {
1046 if (!info
->dev
|| !pci_ats_enabled(info
->dev
))
1049 sid
= info
->bus
<< 8 | info
->devfn
;
1050 qdep
= pci_ats_queue_depth(info
->dev
);
1051 qi_flush_dev_iotlb(info
->iommu
, sid
, qdep
, addr
, mask
);
1053 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1056 static void iommu_flush_iotlb_psi(struct intel_iommu
*iommu
, u16 did
,
1057 unsigned long pfn
, unsigned int pages
)
1059 unsigned int mask
= ilog2(__roundup_pow_of_two(pages
));
1060 uint64_t addr
= (uint64_t)pfn
<< VTD_PAGE_SHIFT
;
1065 * Fallback to domain selective flush if no PSI support or the size is
1067 * PSI requires page size to be 2 ^ x, and the base address is naturally
1068 * aligned to the size
1070 if (!cap_pgsel_inv(iommu
->cap
) || mask
> cap_max_amask_val(iommu
->cap
))
1071 iommu
->flush
.flush_iotlb(iommu
, did
, 0, 0,
1074 iommu
->flush
.flush_iotlb(iommu
, did
, addr
, mask
,
1078 * In caching mode, domain ID 0 is reserved for non-present to present
1079 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1081 if (!cap_caching_mode(iommu
->cap
) || did
)
1082 iommu_flush_dev_iotlb(iommu
->domains
[did
], addr
, mask
);
1085 static void iommu_disable_protect_mem_regions(struct intel_iommu
*iommu
)
1088 unsigned long flags
;
1090 spin_lock_irqsave(&iommu
->register_lock
, flags
);
1091 pmen
= readl(iommu
->reg
+ DMAR_PMEN_REG
);
1092 pmen
&= ~DMA_PMEN_EPM
;
1093 writel(pmen
, iommu
->reg
+ DMAR_PMEN_REG
);
1095 /* wait for the protected region status bit to clear */
1096 IOMMU_WAIT_OP(iommu
, DMAR_PMEN_REG
,
1097 readl
, !(pmen
& DMA_PMEN_PRS
), pmen
);
1099 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1102 static int iommu_enable_translation(struct intel_iommu
*iommu
)
1105 unsigned long flags
;
1107 spin_lock_irqsave(&iommu
->register_lock
, flags
);
1108 iommu
->gcmd
|= DMA_GCMD_TE
;
1109 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1111 /* Make sure hardware complete it */
1112 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1113 readl
, (sts
& DMA_GSTS_TES
), sts
);
1115 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
1119 static int iommu_disable_translation(struct intel_iommu
*iommu
)
1124 spin_lock_irqsave(&iommu
->register_lock
, flag
);
1125 iommu
->gcmd
&= ~DMA_GCMD_TE
;
1126 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
1128 /* Make sure hardware complete it */
1129 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
1130 readl
, (!(sts
& DMA_GSTS_TES
)), sts
);
1132 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
1137 static int iommu_init_domains(struct intel_iommu
*iommu
)
1139 unsigned long ndomains
;
1140 unsigned long nlongs
;
1142 ndomains
= cap_ndoms(iommu
->cap
);
1143 pr_debug("Number of Domains supportd <%ld>\n", ndomains
);
1144 nlongs
= BITS_TO_LONGS(ndomains
);
1146 /* TBD: there might be 64K domains,
1147 * consider other allocation for future chip
1149 iommu
->domain_ids
= kcalloc(nlongs
, sizeof(unsigned long), GFP_KERNEL
);
1150 if (!iommu
->domain_ids
) {
1151 printk(KERN_ERR
"Allocating domain id array failed\n");
1154 iommu
->domains
= kcalloc(ndomains
, sizeof(struct dmar_domain
*),
1156 if (!iommu
->domains
) {
1157 printk(KERN_ERR
"Allocating domain array failed\n");
1158 kfree(iommu
->domain_ids
);
1162 spin_lock_init(&iommu
->lock
);
1165 * if Caching mode is set, then invalid translations are tagged
1166 * with domainid 0. Hence we need to pre-allocate it.
1168 if (cap_caching_mode(iommu
->cap
))
1169 set_bit(0, iommu
->domain_ids
);
1174 static void domain_exit(struct dmar_domain
*domain
);
1175 static void vm_domain_exit(struct dmar_domain
*domain
);
1177 void free_dmar_iommu(struct intel_iommu
*iommu
)
1179 struct dmar_domain
*domain
;
1181 unsigned long flags
;
1183 i
= find_first_bit(iommu
->domain_ids
, cap_ndoms(iommu
->cap
));
1184 for (; i
< cap_ndoms(iommu
->cap
); ) {
1185 domain
= iommu
->domains
[i
];
1186 clear_bit(i
, iommu
->domain_ids
);
1188 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1189 if (--domain
->iommu_count
== 0) {
1190 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
)
1191 vm_domain_exit(domain
);
1193 domain_exit(domain
);
1195 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1197 i
= find_next_bit(iommu
->domain_ids
,
1198 cap_ndoms(iommu
->cap
), i
+1);
1201 if (iommu
->gcmd
& DMA_GCMD_TE
)
1202 iommu_disable_translation(iommu
);
1205 set_irq_data(iommu
->irq
, NULL
);
1206 /* This will mask the irq */
1207 free_irq(iommu
->irq
, iommu
);
1208 destroy_irq(iommu
->irq
);
1211 kfree(iommu
->domains
);
1212 kfree(iommu
->domain_ids
);
1214 g_iommus
[iommu
->seq_id
] = NULL
;
1216 /* if all iommus are freed, free g_iommus */
1217 for (i
= 0; i
< g_num_of_iommus
; i
++) {
1222 if (i
== g_num_of_iommus
)
1225 /* free context mapping */
1226 free_context_table(iommu
);
1229 static struct dmar_domain
*alloc_domain(void)
1231 struct dmar_domain
*domain
;
1233 domain
= alloc_domain_mem();
1237 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
1243 static int iommu_attach_domain(struct dmar_domain
*domain
,
1244 struct intel_iommu
*iommu
)
1247 unsigned long ndomains
;
1248 unsigned long flags
;
1250 ndomains
= cap_ndoms(iommu
->cap
);
1252 spin_lock_irqsave(&iommu
->lock
, flags
);
1254 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1255 if (num
>= ndomains
) {
1256 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1257 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1262 set_bit(num
, iommu
->domain_ids
);
1263 set_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1264 iommu
->domains
[num
] = domain
;
1265 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1270 static void iommu_detach_domain(struct dmar_domain
*domain
,
1271 struct intel_iommu
*iommu
)
1273 unsigned long flags
;
1277 spin_lock_irqsave(&iommu
->lock
, flags
);
1278 ndomains
= cap_ndoms(iommu
->cap
);
1279 num
= find_first_bit(iommu
->domain_ids
, ndomains
);
1280 for (; num
< ndomains
; ) {
1281 if (iommu
->domains
[num
] == domain
) {
1285 num
= find_next_bit(iommu
->domain_ids
,
1286 cap_ndoms(iommu
->cap
), num
+1);
1290 clear_bit(num
, iommu
->domain_ids
);
1291 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1292 iommu
->domains
[num
] = NULL
;
1294 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1297 static struct iova_domain reserved_iova_list
;
1298 static struct lock_class_key reserved_alloc_key
;
1299 static struct lock_class_key reserved_rbtree_key
;
1301 static void dmar_init_reserved_ranges(void)
1303 struct pci_dev
*pdev
= NULL
;
1307 init_iova_domain(&reserved_iova_list
, DMA_32BIT_PFN
);
1309 lockdep_set_class(&reserved_iova_list
.iova_alloc_lock
,
1310 &reserved_alloc_key
);
1311 lockdep_set_class(&reserved_iova_list
.iova_rbtree_lock
,
1312 &reserved_rbtree_key
);
1314 /* IOAPIC ranges shouldn't be accessed by DMA */
1315 iova
= reserve_iova(&reserved_iova_list
, IOVA_PFN(IOAPIC_RANGE_START
),
1316 IOVA_PFN(IOAPIC_RANGE_END
));
1318 printk(KERN_ERR
"Reserve IOAPIC range failed\n");
1320 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1321 for_each_pci_dev(pdev
) {
1324 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1325 r
= &pdev
->resource
[i
];
1326 if (!r
->flags
|| !(r
->flags
& IORESOURCE_MEM
))
1328 iova
= reserve_iova(&reserved_iova_list
,
1332 printk(KERN_ERR
"Reserve iova failed\n");
1338 static void domain_reserve_special_ranges(struct dmar_domain
*domain
)
1340 copy_reserved_iova(&reserved_iova_list
, &domain
->iovad
);
1343 static inline int guestwidth_to_adjustwidth(int gaw
)
1346 int r
= (gaw
- 12) % 9;
1357 static int domain_init(struct dmar_domain
*domain
, int guest_width
)
1359 struct intel_iommu
*iommu
;
1360 int adjust_width
, agaw
;
1361 unsigned long sagaw
;
1363 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
1364 spin_lock_init(&domain
->mapping_lock
);
1365 spin_lock_init(&domain
->iommu_lock
);
1367 domain_reserve_special_ranges(domain
);
1369 /* calculate AGAW */
1370 iommu
= domain_get_iommu(domain
);
1371 if (guest_width
> cap_mgaw(iommu
->cap
))
1372 guest_width
= cap_mgaw(iommu
->cap
);
1373 domain
->gaw
= guest_width
;
1374 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
1375 agaw
= width_to_agaw(adjust_width
);
1376 sagaw
= cap_sagaw(iommu
->cap
);
1377 if (!test_bit(agaw
, &sagaw
)) {
1378 /* hardware doesn't support it, choose a bigger one */
1379 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw
);
1380 agaw
= find_next_bit(&sagaw
, 5, agaw
);
1384 domain
->agaw
= agaw
;
1385 INIT_LIST_HEAD(&domain
->devices
);
1387 if (ecap_coherent(iommu
->ecap
))
1388 domain
->iommu_coherency
= 1;
1390 domain
->iommu_coherency
= 0;
1392 if (ecap_sc_support(iommu
->ecap
))
1393 domain
->iommu_snooping
= 1;
1395 domain
->iommu_snooping
= 0;
1397 domain
->iommu_count
= 1;
1399 /* always allocate the top pgd */
1400 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page();
1403 __iommu_flush_cache(iommu
, domain
->pgd
, PAGE_SIZE
);
1407 static void domain_exit(struct dmar_domain
*domain
)
1409 struct dmar_drhd_unit
*drhd
;
1410 struct intel_iommu
*iommu
;
1412 /* Domain 0 is reserved, so dont process it */
1416 domain_remove_dev_info(domain
);
1418 put_iova_domain(&domain
->iovad
);
1421 dma_pte_clear_range(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
1423 /* free page tables */
1424 dma_pte_free_pagetable(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
1426 for_each_active_iommu(iommu
, drhd
)
1427 if (test_bit(iommu
->seq_id
, &domain
->iommu_bmp
))
1428 iommu_detach_domain(domain
, iommu
);
1430 free_domain_mem(domain
);
1433 static int domain_context_mapping_one(struct dmar_domain
*domain
, int segment
,
1434 u8 bus
, u8 devfn
, int translation
)
1436 struct context_entry
*context
;
1437 unsigned long flags
;
1438 struct intel_iommu
*iommu
;
1439 struct dma_pte
*pgd
;
1441 unsigned long ndomains
;
1444 struct device_domain_info
*info
= NULL
;
1446 pr_debug("Set context mapping for %02x:%02x.%d\n",
1447 bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
1449 BUG_ON(!domain
->pgd
);
1450 BUG_ON(translation
!= CONTEXT_TT_PASS_THROUGH
&&
1451 translation
!= CONTEXT_TT_MULTI_LEVEL
);
1453 iommu
= device_to_iommu(segment
, bus
, devfn
);
1457 context
= device_to_context_entry(iommu
, bus
, devfn
);
1460 spin_lock_irqsave(&iommu
->lock
, flags
);
1461 if (context_present(context
)) {
1462 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1469 if (domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
1470 domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
) {
1473 /* find an available domain id for this device in iommu */
1474 ndomains
= cap_ndoms(iommu
->cap
);
1475 num
= find_first_bit(iommu
->domain_ids
, ndomains
);
1476 for (; num
< ndomains
; ) {
1477 if (iommu
->domains
[num
] == domain
) {
1482 num
= find_next_bit(iommu
->domain_ids
,
1483 cap_ndoms(iommu
->cap
), num
+1);
1487 num
= find_first_zero_bit(iommu
->domain_ids
, ndomains
);
1488 if (num
>= ndomains
) {
1489 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1490 printk(KERN_ERR
"IOMMU: no free domain ids\n");
1494 set_bit(num
, iommu
->domain_ids
);
1495 set_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
1496 iommu
->domains
[num
] = domain
;
1500 /* Skip top levels of page tables for
1501 * iommu which has less agaw than default.
1503 for (agaw
= domain
->agaw
; agaw
!= iommu
->agaw
; agaw
--) {
1504 pgd
= phys_to_virt(dma_pte_addr(pgd
));
1505 if (!dma_pte_present(pgd
)) {
1506 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1512 context_set_domain_id(context
, id
);
1514 if (translation
!= CONTEXT_TT_PASS_THROUGH
) {
1515 info
= iommu_support_dev_iotlb(domain
, segment
, bus
, devfn
);
1516 translation
= info
? CONTEXT_TT_DEV_IOTLB
:
1517 CONTEXT_TT_MULTI_LEVEL
;
1520 * In pass through mode, AW must be programmed to indicate the largest
1521 * AGAW value supported by hardware. And ASR is ignored by hardware.
1523 if (unlikely(translation
== CONTEXT_TT_PASS_THROUGH
))
1524 context_set_address_width(context
, iommu
->msagaw
);
1526 context_set_address_root(context
, virt_to_phys(pgd
));
1527 context_set_address_width(context
, iommu
->agaw
);
1530 context_set_translation_type(context
, translation
);
1531 context_set_fault_enable(context
);
1532 context_set_present(context
);
1533 domain_flush_cache(domain
, context
, sizeof(*context
));
1536 * It's a non-present to present mapping. If hardware doesn't cache
1537 * non-present entry we only need to flush the write-buffer. If the
1538 * _does_ cache non-present entries, then it does so in the special
1539 * domain #0, which we have to flush:
1541 if (cap_caching_mode(iommu
->cap
)) {
1542 iommu
->flush
.flush_context(iommu
, 0,
1543 (((u16
)bus
) << 8) | devfn
,
1544 DMA_CCMD_MASK_NOBIT
,
1545 DMA_CCMD_DEVICE_INVL
);
1546 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_DSI_FLUSH
);
1548 iommu_flush_write_buffer(iommu
);
1550 iommu_enable_dev_iotlb(info
);
1551 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1553 spin_lock_irqsave(&domain
->iommu_lock
, flags
);
1554 if (!test_and_set_bit(iommu
->seq_id
, &domain
->iommu_bmp
)) {
1555 domain
->iommu_count
++;
1556 domain_update_iommu_cap(domain
);
1558 spin_unlock_irqrestore(&domain
->iommu_lock
, flags
);
1563 domain_context_mapping(struct dmar_domain
*domain
, struct pci_dev
*pdev
,
1567 struct pci_dev
*tmp
, *parent
;
1569 ret
= domain_context_mapping_one(domain
, pci_domain_nr(pdev
->bus
),
1570 pdev
->bus
->number
, pdev
->devfn
,
1575 /* dependent device mapping */
1576 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1579 /* Secondary interface's bus number and devfn 0 */
1580 parent
= pdev
->bus
->self
;
1581 while (parent
!= tmp
) {
1582 ret
= domain_context_mapping_one(domain
,
1583 pci_domain_nr(parent
->bus
),
1584 parent
->bus
->number
,
1585 parent
->devfn
, translation
);
1588 parent
= parent
->bus
->self
;
1590 if (tmp
->is_pcie
) /* this is a PCIE-to-PCI bridge */
1591 return domain_context_mapping_one(domain
,
1592 pci_domain_nr(tmp
->subordinate
),
1593 tmp
->subordinate
->number
, 0,
1595 else /* this is a legacy PCI bridge */
1596 return domain_context_mapping_one(domain
,
1597 pci_domain_nr(tmp
->bus
),
1603 static int domain_context_mapped(struct pci_dev
*pdev
)
1606 struct pci_dev
*tmp
, *parent
;
1607 struct intel_iommu
*iommu
;
1609 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
1614 ret
= device_context_mapped(iommu
, pdev
->bus
->number
, pdev
->devfn
);
1617 /* dependent device mapping */
1618 tmp
= pci_find_upstream_pcie_bridge(pdev
);
1621 /* Secondary interface's bus number and devfn 0 */
1622 parent
= pdev
->bus
->self
;
1623 while (parent
!= tmp
) {
1624 ret
= device_context_mapped(iommu
, parent
->bus
->number
,
1628 parent
= parent
->bus
->self
;
1631 return device_context_mapped(iommu
, tmp
->subordinate
->number
,
1634 return device_context_mapped(iommu
, tmp
->bus
->number
,
1638 static int domain_pfn_mapping(struct dmar_domain
*domain
, unsigned long iov_pfn
,
1639 unsigned long phys_pfn
, unsigned long nr_pages
,
1642 struct dma_pte
*first_pte
= NULL
, *pte
= NULL
;
1643 int addr_width
= agaw_to_width(domain
->agaw
) - VTD_PAGE_SHIFT
;
1645 BUG_ON(addr_width
< BITS_PER_LONG
&& (iov_pfn
+ nr_pages
- 1) >> addr_width
);
1647 if ((prot
& (DMA_PTE_READ
|DMA_PTE_WRITE
)) == 0)
1650 prot
&= DMA_PTE_READ
| DMA_PTE_WRITE
| DMA_PTE_SNP
;
1652 while (nr_pages
--) {
1654 first_pte
= pte
= pfn_to_dma_pte(domain
, iov_pfn
);
1658 /* We don't need lock here, nobody else
1659 * touches the iova range
1661 BUG_ON(dma_pte_addr(pte
));
1662 pte
->val
= (phys_pfn
<< VTD_PAGE_SHIFT
) | prot
;
1665 (unsigned long)pte
>> VTD_PAGE_SHIFT
!=
1666 (unsigned long)first_pte
>> VTD_PAGE_SHIFT
) {
1667 domain_flush_cache(domain
, first_pte
,
1668 (void *)pte
- (void *)first_pte
);
1677 static void iommu_detach_dev(struct intel_iommu
*iommu
, u8 bus
, u8 devfn
)
1682 clear_context_table(iommu
, bus
, devfn
);
1683 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
1684 DMA_CCMD_GLOBAL_INVL
);
1685 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
1688 static void domain_remove_dev_info(struct dmar_domain
*domain
)
1690 struct device_domain_info
*info
;
1691 unsigned long flags
;
1692 struct intel_iommu
*iommu
;
1694 spin_lock_irqsave(&device_domain_lock
, flags
);
1695 while (!list_empty(&domain
->devices
)) {
1696 info
= list_entry(domain
->devices
.next
,
1697 struct device_domain_info
, link
);
1698 list_del(&info
->link
);
1699 list_del(&info
->global
);
1701 info
->dev
->dev
.archdata
.iommu
= NULL
;
1702 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1704 iommu_disable_dev_iotlb(info
);
1705 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
1706 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
1707 free_devinfo_mem(info
);
1709 spin_lock_irqsave(&device_domain_lock
, flags
);
1711 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1716 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1718 static struct dmar_domain
*
1719 find_domain(struct pci_dev
*pdev
)
1721 struct device_domain_info
*info
;
1723 /* No lock here, assumes no domain exit in normal case */
1724 info
= pdev
->dev
.archdata
.iommu
;
1726 return info
->domain
;
1730 /* domain is initialized */
1731 static struct dmar_domain
*get_domain_for_dev(struct pci_dev
*pdev
, int gaw
)
1733 struct dmar_domain
*domain
, *found
= NULL
;
1734 struct intel_iommu
*iommu
;
1735 struct dmar_drhd_unit
*drhd
;
1736 struct device_domain_info
*info
, *tmp
;
1737 struct pci_dev
*dev_tmp
;
1738 unsigned long flags
;
1739 int bus
= 0, devfn
= 0;
1743 domain
= find_domain(pdev
);
1747 segment
= pci_domain_nr(pdev
->bus
);
1749 dev_tmp
= pci_find_upstream_pcie_bridge(pdev
);
1751 if (dev_tmp
->is_pcie
) {
1752 bus
= dev_tmp
->subordinate
->number
;
1755 bus
= dev_tmp
->bus
->number
;
1756 devfn
= dev_tmp
->devfn
;
1758 spin_lock_irqsave(&device_domain_lock
, flags
);
1759 list_for_each_entry(info
, &device_domain_list
, global
) {
1760 if (info
->segment
== segment
&&
1761 info
->bus
== bus
&& info
->devfn
== devfn
) {
1762 found
= info
->domain
;
1766 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1767 /* pcie-pci bridge already has a domain, uses it */
1774 domain
= alloc_domain();
1778 /* Allocate new domain for the device */
1779 drhd
= dmar_find_matched_drhd_unit(pdev
);
1781 printk(KERN_ERR
"IOMMU: can't find DMAR for device %s\n",
1785 iommu
= drhd
->iommu
;
1787 ret
= iommu_attach_domain(domain
, iommu
);
1789 domain_exit(domain
);
1793 if (domain_init(domain
, gaw
)) {
1794 domain_exit(domain
);
1798 /* register pcie-to-pci device */
1800 info
= alloc_devinfo_mem();
1802 domain_exit(domain
);
1805 info
->segment
= segment
;
1807 info
->devfn
= devfn
;
1809 info
->domain
= domain
;
1810 /* This domain is shared by devices under p2p bridge */
1811 domain
->flags
|= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES
;
1813 /* pcie-to-pci bridge already has a domain, uses it */
1815 spin_lock_irqsave(&device_domain_lock
, flags
);
1816 list_for_each_entry(tmp
, &device_domain_list
, global
) {
1817 if (tmp
->segment
== segment
&&
1818 tmp
->bus
== bus
&& tmp
->devfn
== devfn
) {
1819 found
= tmp
->domain
;
1824 free_devinfo_mem(info
);
1825 domain_exit(domain
);
1828 list_add(&info
->link
, &domain
->devices
);
1829 list_add(&info
->global
, &device_domain_list
);
1831 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1835 info
= alloc_devinfo_mem();
1838 info
->segment
= segment
;
1839 info
->bus
= pdev
->bus
->number
;
1840 info
->devfn
= pdev
->devfn
;
1842 info
->domain
= domain
;
1843 spin_lock_irqsave(&device_domain_lock
, flags
);
1844 /* somebody is fast */
1845 found
= find_domain(pdev
);
1846 if (found
!= NULL
) {
1847 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1848 if (found
!= domain
) {
1849 domain_exit(domain
);
1852 free_devinfo_mem(info
);
1855 list_add(&info
->link
, &domain
->devices
);
1856 list_add(&info
->global
, &device_domain_list
);
1857 pdev
->dev
.archdata
.iommu
= info
;
1858 spin_unlock_irqrestore(&device_domain_lock
, flags
);
1861 /* recheck it here, maybe others set it */
1862 return find_domain(pdev
);
1865 static int iommu_identity_mapping
;
1867 static int iommu_domain_identity_map(struct dmar_domain
*domain
,
1868 unsigned long long start
,
1869 unsigned long long end
)
1871 unsigned long first_vpfn
= start
>> VTD_PAGE_SHIFT
;
1872 unsigned long last_vpfn
= end
>> VTD_PAGE_SHIFT
;
1874 if (!reserve_iova(&domain
->iovad
, dma_to_mm_pfn(first_vpfn
),
1875 dma_to_mm_pfn(last_vpfn
))) {
1876 printk(KERN_ERR
"IOMMU: reserve iova failed\n");
1880 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1881 start
, end
, domain
->id
);
1883 * RMRR range might have overlap with physical memory range,
1886 dma_pte_clear_range(domain
, first_vpfn
, last_vpfn
);
1888 return domain_pfn_mapping(domain
, first_vpfn
, first_vpfn
,
1889 last_vpfn
- first_vpfn
+ 1,
1890 DMA_PTE_READ
|DMA_PTE_WRITE
);
1893 static int iommu_prepare_identity_map(struct pci_dev
*pdev
,
1894 unsigned long long start
,
1895 unsigned long long end
)
1897 struct dmar_domain
*domain
;
1901 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1902 pci_name(pdev
), start
, end
);
1904 domain
= get_domain_for_dev(pdev
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
1908 ret
= iommu_domain_identity_map(domain
, start
, end
);
1912 /* context entry init */
1913 ret
= domain_context_mapping(domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
1920 domain_exit(domain
);
1924 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit
*rmrr
,
1925 struct pci_dev
*pdev
)
1927 if (pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
)
1929 return iommu_prepare_identity_map(pdev
, rmrr
->base_address
,
1930 rmrr
->end_address
+ 1);
1933 #ifdef CONFIG_DMAR_FLOPPY_WA
1934 static inline void iommu_prepare_isa(void)
1936 struct pci_dev
*pdev
;
1939 pdev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
1943 printk(KERN_INFO
"IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1944 ret
= iommu_prepare_identity_map(pdev
, 0, 16*1024*1024);
1947 printk(KERN_ERR
"IOMMU: Failed to create 0-16MiB identity map; "
1948 "floppy might not work\n");
1952 static inline void iommu_prepare_isa(void)
1956 #endif /* !CONFIG_DMAR_FLPY_WA */
1958 /* Initialize each context entry as pass through.*/
1959 static int __init
init_context_pass_through(void)
1961 struct pci_dev
*pdev
= NULL
;
1962 struct dmar_domain
*domain
;
1965 for_each_pci_dev(pdev
) {
1966 domain
= get_domain_for_dev(pdev
, DEFAULT_DOMAIN_ADDRESS_WIDTH
);
1967 ret
= domain_context_mapping(domain
, pdev
,
1968 CONTEXT_TT_PASS_THROUGH
);
1975 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
);
1977 static int __init
si_domain_work_fn(unsigned long start_pfn
,
1978 unsigned long end_pfn
, void *datax
)
1982 *ret
= iommu_domain_identity_map(si_domain
,
1983 (uint64_t)start_pfn
<< PAGE_SHIFT
,
1984 (uint64_t)end_pfn
<< PAGE_SHIFT
);
1989 static int si_domain_init(void)
1991 struct dmar_drhd_unit
*drhd
;
1992 struct intel_iommu
*iommu
;
1995 si_domain
= alloc_domain();
1999 pr_debug("Identity mapping domain is domain %d\n", si_domain
->id
);
2001 for_each_active_iommu(iommu
, drhd
) {
2002 ret
= iommu_attach_domain(si_domain
, iommu
);
2004 domain_exit(si_domain
);
2009 if (md_domain_init(si_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
2010 domain_exit(si_domain
);
2014 si_domain
->flags
= DOMAIN_FLAG_STATIC_IDENTITY
;
2016 for_each_online_node(nid
) {
2017 work_with_active_regions(nid
, si_domain_work_fn
, &ret
);
2025 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
2026 struct pci_dev
*pdev
);
2027 static int identity_mapping(struct pci_dev
*pdev
)
2029 struct device_domain_info
*info
;
2031 if (likely(!iommu_identity_mapping
))
2035 list_for_each_entry(info
, &si_domain
->devices
, link
)
2036 if (info
->dev
== pdev
)
2041 static int domain_add_dev_info(struct dmar_domain
*domain
,
2042 struct pci_dev
*pdev
)
2044 struct device_domain_info
*info
;
2045 unsigned long flags
;
2047 info
= alloc_devinfo_mem();
2051 info
->segment
= pci_domain_nr(pdev
->bus
);
2052 info
->bus
= pdev
->bus
->number
;
2053 info
->devfn
= pdev
->devfn
;
2055 info
->domain
= domain
;
2057 spin_lock_irqsave(&device_domain_lock
, flags
);
2058 list_add(&info
->link
, &domain
->devices
);
2059 list_add(&info
->global
, &device_domain_list
);
2060 pdev
->dev
.archdata
.iommu
= info
;
2061 spin_unlock_irqrestore(&device_domain_lock
, flags
);
2066 static int iommu_prepare_static_identity_mapping(void)
2068 struct pci_dev
*pdev
= NULL
;
2071 ret
= si_domain_init();
2075 for_each_pci_dev(pdev
) {
2076 printk(KERN_INFO
"IOMMU: identity mapping for device %s\n",
2079 ret
= domain_context_mapping(si_domain
, pdev
,
2080 CONTEXT_TT_MULTI_LEVEL
);
2083 ret
= domain_add_dev_info(si_domain
, pdev
);
2091 int __init
init_dmars(void)
2093 struct dmar_drhd_unit
*drhd
;
2094 struct dmar_rmrr_unit
*rmrr
;
2095 struct pci_dev
*pdev
;
2096 struct intel_iommu
*iommu
;
2098 int pass_through
= 1;
2101 * In case pass through can not be enabled, iommu tries to use identity
2104 if (iommu_pass_through
)
2105 iommu_identity_mapping
= 1;
2110 * initialize and program root entry to not present
2113 for_each_drhd_unit(drhd
) {
2116 * lock not needed as this is only incremented in the single
2117 * threaded kernel __init code path all other access are read
2122 g_iommus
= kcalloc(g_num_of_iommus
, sizeof(struct intel_iommu
*),
2125 printk(KERN_ERR
"Allocating global iommu array failed\n");
2130 deferred_flush
= kzalloc(g_num_of_iommus
*
2131 sizeof(struct deferred_flush_tables
), GFP_KERNEL
);
2132 if (!deferred_flush
) {
2138 for_each_drhd_unit(drhd
) {
2142 iommu
= drhd
->iommu
;
2143 g_iommus
[iommu
->seq_id
] = iommu
;
2145 ret
= iommu_init_domains(iommu
);
2151 * we could share the same root & context tables
2152 * amoung all IOMMU's. Need to Split it later.
2154 ret
= iommu_alloc_root_entry(iommu
);
2156 printk(KERN_ERR
"IOMMU: allocate root entry failed\n");
2159 if (!ecap_pass_through(iommu
->ecap
))
2162 if (iommu_pass_through
)
2163 if (!pass_through
) {
2165 "Pass Through is not supported by hardware.\n");
2166 iommu_pass_through
= 0;
2170 * Start from the sane iommu hardware state.
2172 for_each_drhd_unit(drhd
) {
2176 iommu
= drhd
->iommu
;
2179 * If the queued invalidation is already initialized by us
2180 * (for example, while enabling interrupt-remapping) then
2181 * we got the things already rolling from a sane state.
2187 * Clear any previous faults.
2189 dmar_fault(-1, iommu
);
2191 * Disable queued invalidation if supported and already enabled
2192 * before OS handover.
2194 dmar_disable_qi(iommu
);
2197 for_each_drhd_unit(drhd
) {
2201 iommu
= drhd
->iommu
;
2203 if (dmar_enable_qi(iommu
)) {
2205 * Queued Invalidate not enabled, use Register Based
2208 iommu
->flush
.flush_context
= __iommu_flush_context
;
2209 iommu
->flush
.flush_iotlb
= __iommu_flush_iotlb
;
2210 printk(KERN_INFO
"IOMMU 0x%Lx: using Register based "
2212 (unsigned long long)drhd
->reg_base_addr
);
2214 iommu
->flush
.flush_context
= qi_flush_context
;
2215 iommu
->flush
.flush_iotlb
= qi_flush_iotlb
;
2216 printk(KERN_INFO
"IOMMU 0x%Lx: using Queued "
2218 (unsigned long long)drhd
->reg_base_addr
);
2223 * If pass through is set and enabled, context entries of all pci
2224 * devices are intialized by pass through translation type.
2226 if (iommu_pass_through
) {
2227 ret
= init_context_pass_through();
2229 printk(KERN_ERR
"IOMMU: Pass through init failed.\n");
2230 iommu_pass_through
= 0;
2235 * If pass through is not set or not enabled, setup context entries for
2236 * identity mappings for rmrr, gfx, and isa and may fall back to static
2237 * identity mapping if iommu_identity_mapping is set.
2239 if (!iommu_pass_through
) {
2240 if (iommu_identity_mapping
)
2241 iommu_prepare_static_identity_mapping();
2244 * for each dev attached to rmrr
2246 * locate drhd for dev, alloc domain for dev
2247 * allocate free domain
2248 * allocate page table entries for rmrr
2249 * if context not allocated for bus
2250 * allocate and init context
2251 * set present in root table for this bus
2252 * init context with domain, translation etc
2256 printk(KERN_INFO
"IOMMU: Setting RMRR:\n");
2257 for_each_rmrr_units(rmrr
) {
2258 for (i
= 0; i
< rmrr
->devices_cnt
; i
++) {
2259 pdev
= rmrr
->devices
[i
];
2261 * some BIOS lists non-exist devices in DMAR
2266 ret
= iommu_prepare_rmrr_dev(rmrr
, pdev
);
2269 "IOMMU: mapping reserved region failed\n");
2273 iommu_prepare_isa();
2279 * global invalidate context cache
2280 * global invalidate iotlb
2281 * enable translation
2283 for_each_drhd_unit(drhd
) {
2286 iommu
= drhd
->iommu
;
2288 iommu_flush_write_buffer(iommu
);
2290 ret
= dmar_set_interrupt(iommu
);
2294 iommu_set_root_entry(iommu
);
2296 iommu
->flush
.flush_context(iommu
, 0, 0, 0, DMA_CCMD_GLOBAL_INVL
);
2297 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH
);
2298 iommu_disable_protect_mem_regions(iommu
);
2300 ret
= iommu_enable_translation(iommu
);
2307 for_each_drhd_unit(drhd
) {
2310 iommu
= drhd
->iommu
;
2317 static inline unsigned long aligned_nrpages(unsigned long host_addr
,
2320 host_addr
&= ~PAGE_MASK
;
2321 host_addr
+= size
+ PAGE_SIZE
- 1;
2323 return host_addr
>> VTD_PAGE_SHIFT
;
2327 iommu_alloc_iova(struct dmar_domain
*domain
, size_t size
, u64 end
)
2331 /* Make sure it's in range */
2332 end
= min_t(u64
, DOMAIN_MAX_ADDR(domain
->gaw
), end
);
2333 if (!size
|| (IOVA_START_ADDR
+ size
> end
))
2336 piova
= alloc_iova(&domain
->iovad
,
2337 size
>> PAGE_SHIFT
, IOVA_PFN(end
), 1);
2341 static struct iova
*
2342 __intel_alloc_iova(struct device
*dev
, struct dmar_domain
*domain
,
2343 size_t size
, u64 dma_mask
)
2345 struct pci_dev
*pdev
= to_pci_dev(dev
);
2346 struct iova
*iova
= NULL
;
2348 if (dma_mask
<= DMA_BIT_MASK(32) || dmar_forcedac
)
2349 iova
= iommu_alloc_iova(domain
, size
, dma_mask
);
2352 * First try to allocate an io virtual address in
2353 * DMA_BIT_MASK(32) and if that fails then try allocating
2356 iova
= iommu_alloc_iova(domain
, size
, DMA_BIT_MASK(32));
2358 iova
= iommu_alloc_iova(domain
, size
, dma_mask
);
2362 printk(KERN_ERR
"Allocating iova for %s failed", pci_name(pdev
));
2369 static struct dmar_domain
*
2370 get_valid_domain_for_dev(struct pci_dev
*pdev
)
2372 struct dmar_domain
*domain
;
2375 domain
= get_domain_for_dev(pdev
,
2376 DEFAULT_DOMAIN_ADDRESS_WIDTH
);
2379 "Allocating domain for %s failed", pci_name(pdev
));
2383 /* make sure context mapping is ok */
2384 if (unlikely(!domain_context_mapped(pdev
))) {
2385 ret
= domain_context_mapping(domain
, pdev
,
2386 CONTEXT_TT_MULTI_LEVEL
);
2389 "Domain context map for %s failed",
2398 static int iommu_dummy(struct pci_dev
*pdev
)
2400 return pdev
->dev
.archdata
.iommu
== DUMMY_DEVICE_DOMAIN_INFO
;
2403 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2404 static int iommu_no_mapping(struct pci_dev
*pdev
)
2408 if (!iommu_identity_mapping
)
2409 return iommu_dummy(pdev
);
2411 found
= identity_mapping(pdev
);
2413 if (pdev
->dma_mask
> DMA_BIT_MASK(32))
2417 * 32 bit DMA is removed from si_domain and fall back
2418 * to non-identity mapping.
2420 domain_remove_one_dev_info(si_domain
, pdev
);
2421 printk(KERN_INFO
"32bit %s uses non-identity mapping\n",
2427 * In case of a detached 64 bit DMA device from vm, the device
2428 * is put into si_domain for identity mapping.
2430 if (pdev
->dma_mask
> DMA_BIT_MASK(32)) {
2432 ret
= domain_add_dev_info(si_domain
, pdev
);
2434 printk(KERN_INFO
"64bit %s uses identity mapping\n",
2441 return iommu_dummy(pdev
);
2444 static dma_addr_t
__intel_map_single(struct device
*hwdev
, phys_addr_t paddr
,
2445 size_t size
, int dir
, u64 dma_mask
)
2447 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2448 struct dmar_domain
*domain
;
2449 phys_addr_t start_paddr
;
2453 struct intel_iommu
*iommu
;
2455 BUG_ON(dir
== DMA_NONE
);
2457 if (iommu_no_mapping(pdev
))
2460 domain
= get_valid_domain_for_dev(pdev
);
2464 iommu
= domain_get_iommu(domain
);
2465 size
= aligned_nrpages(paddr
, size
);
2467 iova
= __intel_alloc_iova(hwdev
, domain
, size
<< VTD_PAGE_SHIFT
, pdev
->dma_mask
);
2472 * Check if DMAR supports zero-length reads on write only
2475 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
2476 !cap_zlr(iommu
->cap
))
2477 prot
|= DMA_PTE_READ
;
2478 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
2479 prot
|= DMA_PTE_WRITE
;
2481 * paddr - (paddr + size) might be partial page, we should map the whole
2482 * page. Note: if two part of one page are separately mapped, we
2483 * might have two guest_addr mapping to the same host paddr, but this
2484 * is not a big problem
2486 ret
= domain_pfn_mapping(domain
, mm_to_dma_pfn(iova
->pfn_lo
),
2487 paddr
>> VTD_PAGE_SHIFT
, size
, prot
);
2491 /* it's a non-present to present mapping. Only flush if caching mode */
2492 if (cap_caching_mode(iommu
->cap
))
2493 iommu_flush_iotlb_psi(iommu
, 0, mm_to_dma_pfn(iova
->pfn_lo
), size
);
2495 iommu_flush_write_buffer(iommu
);
2497 start_paddr
= (phys_addr_t
)iova
->pfn_lo
<< PAGE_SHIFT
;
2498 start_paddr
+= paddr
& ~PAGE_MASK
;
2503 __free_iova(&domain
->iovad
, iova
);
2504 printk(KERN_ERR
"Device %s request: %zx@%llx dir %d --- failed\n",
2505 pci_name(pdev
), size
, (unsigned long long)paddr
, dir
);
2509 static dma_addr_t
intel_map_page(struct device
*dev
, struct page
*page
,
2510 unsigned long offset
, size_t size
,
2511 enum dma_data_direction dir
,
2512 struct dma_attrs
*attrs
)
2514 return __intel_map_single(dev
, page_to_phys(page
) + offset
, size
,
2515 dir
, to_pci_dev(dev
)->dma_mask
);
2518 static void flush_unmaps(void)
2524 /* just flush them all */
2525 for (i
= 0; i
< g_num_of_iommus
; i
++) {
2526 struct intel_iommu
*iommu
= g_iommus
[i
];
2530 if (!deferred_flush
[i
].next
)
2533 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
2534 DMA_TLB_GLOBAL_FLUSH
);
2535 for (j
= 0; j
< deferred_flush
[i
].next
; j
++) {
2537 struct iova
*iova
= deferred_flush
[i
].iova
[j
];
2539 mask
= (iova
->pfn_hi
- iova
->pfn_lo
+ 1) << PAGE_SHIFT
;
2540 mask
= ilog2(mask
>> VTD_PAGE_SHIFT
);
2541 iommu_flush_dev_iotlb(deferred_flush
[i
].domain
[j
],
2542 iova
->pfn_lo
<< PAGE_SHIFT
, mask
);
2543 __free_iova(&deferred_flush
[i
].domain
[j
]->iovad
, iova
);
2545 deferred_flush
[i
].next
= 0;
2551 static void flush_unmaps_timeout(unsigned long data
)
2553 unsigned long flags
;
2555 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2557 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2560 static void add_unmap(struct dmar_domain
*dom
, struct iova
*iova
)
2562 unsigned long flags
;
2564 struct intel_iommu
*iommu
;
2566 spin_lock_irqsave(&async_umap_flush_lock
, flags
);
2567 if (list_size
== HIGH_WATER_MARK
)
2570 iommu
= domain_get_iommu(dom
);
2571 iommu_id
= iommu
->seq_id
;
2573 next
= deferred_flush
[iommu_id
].next
;
2574 deferred_flush
[iommu_id
].domain
[next
] = dom
;
2575 deferred_flush
[iommu_id
].iova
[next
] = iova
;
2576 deferred_flush
[iommu_id
].next
++;
2579 mod_timer(&unmap_timer
, jiffies
+ msecs_to_jiffies(10));
2583 spin_unlock_irqrestore(&async_umap_flush_lock
, flags
);
2586 static void intel_unmap_page(struct device
*dev
, dma_addr_t dev_addr
,
2587 size_t size
, enum dma_data_direction dir
,
2588 struct dma_attrs
*attrs
)
2590 struct pci_dev
*pdev
= to_pci_dev(dev
);
2591 struct dmar_domain
*domain
;
2592 unsigned long start_pfn
, last_pfn
;
2594 struct intel_iommu
*iommu
;
2596 if (iommu_no_mapping(pdev
))
2599 domain
= find_domain(pdev
);
2602 iommu
= domain_get_iommu(domain
);
2604 iova
= find_iova(&domain
->iovad
, IOVA_PFN(dev_addr
));
2608 start_pfn
= mm_to_dma_pfn(iova
->pfn_lo
);
2609 last_pfn
= mm_to_dma_pfn(iova
->pfn_hi
+ 1) - 1;
2611 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2612 pci_name(pdev
), start_pfn
, last_pfn
);
2614 /* clear the whole page */
2615 dma_pte_clear_range(domain
, start_pfn
, last_pfn
);
2617 /* free page tables */
2618 dma_pte_free_pagetable(domain
, start_pfn
, last_pfn
);
2620 if (intel_iommu_strict
) {
2621 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_pfn
,
2622 last_pfn
- start_pfn
+ 1);
2624 __free_iova(&domain
->iovad
, iova
);
2626 add_unmap(domain
, iova
);
2628 * queue up the release of the unmap to save the 1/6th of the
2629 * cpu used up by the iotlb flush operation...
2634 static void intel_unmap_single(struct device
*dev
, dma_addr_t dev_addr
, size_t size
,
2637 intel_unmap_page(dev
, dev_addr
, size
, dir
, NULL
);
2640 static void *intel_alloc_coherent(struct device
*hwdev
, size_t size
,
2641 dma_addr_t
*dma_handle
, gfp_t flags
)
2646 size
= PAGE_ALIGN(size
);
2647 order
= get_order(size
);
2648 flags
&= ~(GFP_DMA
| GFP_DMA32
);
2650 vaddr
= (void *)__get_free_pages(flags
, order
);
2653 memset(vaddr
, 0, size
);
2655 *dma_handle
= __intel_map_single(hwdev
, virt_to_bus(vaddr
), size
,
2657 hwdev
->coherent_dma_mask
);
2660 free_pages((unsigned long)vaddr
, order
);
2664 static void intel_free_coherent(struct device
*hwdev
, size_t size
, void *vaddr
,
2665 dma_addr_t dma_handle
)
2669 size
= PAGE_ALIGN(size
);
2670 order
= get_order(size
);
2672 intel_unmap_single(hwdev
, dma_handle
, size
, DMA_BIDIRECTIONAL
);
2673 free_pages((unsigned long)vaddr
, order
);
2676 static void intel_unmap_sg(struct device
*hwdev
, struct scatterlist
*sglist
,
2677 int nelems
, enum dma_data_direction dir
,
2678 struct dma_attrs
*attrs
)
2680 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2681 struct dmar_domain
*domain
;
2682 unsigned long start_pfn
, last_pfn
;
2684 struct intel_iommu
*iommu
;
2686 if (iommu_no_mapping(pdev
))
2689 domain
= find_domain(pdev
);
2692 iommu
= domain_get_iommu(domain
);
2694 iova
= find_iova(&domain
->iovad
, IOVA_PFN(sglist
[0].dma_address
));
2698 start_pfn
= mm_to_dma_pfn(iova
->pfn_lo
);
2699 last_pfn
= mm_to_dma_pfn(iova
->pfn_hi
+ 1) - 1;
2701 /* clear the whole page */
2702 dma_pte_clear_range(domain
, start_pfn
, last_pfn
);
2704 /* free page tables */
2705 dma_pte_free_pagetable(domain
, start_pfn
, last_pfn
);
2707 iommu_flush_iotlb_psi(iommu
, domain
->id
, start_pfn
,
2708 (last_pfn
- start_pfn
+ 1));
2711 __free_iova(&domain
->iovad
, iova
);
2714 static int intel_nontranslate_map_sg(struct device
*hddev
,
2715 struct scatterlist
*sglist
, int nelems
, int dir
)
2718 struct scatterlist
*sg
;
2720 for_each_sg(sglist
, sg
, nelems
, i
) {
2721 BUG_ON(!sg_page(sg
));
2722 sg
->dma_address
= page_to_phys(sg_page(sg
)) + sg
->offset
;
2723 sg
->dma_length
= sg
->length
;
2728 static int intel_map_sg(struct device
*hwdev
, struct scatterlist
*sglist
, int nelems
,
2729 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2732 struct pci_dev
*pdev
= to_pci_dev(hwdev
);
2733 struct dmar_domain
*domain
;
2736 size_t offset_pfn
= 0;
2737 struct iova
*iova
= NULL
;
2739 struct scatterlist
*sg
;
2740 unsigned long start_vpfn
;
2741 struct intel_iommu
*iommu
;
2743 BUG_ON(dir
== DMA_NONE
);
2744 if (iommu_no_mapping(pdev
))
2745 return intel_nontranslate_map_sg(hwdev
, sglist
, nelems
, dir
);
2747 domain
= get_valid_domain_for_dev(pdev
);
2751 iommu
= domain_get_iommu(domain
);
2753 for_each_sg(sglist
, sg
, nelems
, i
)
2754 size
+= aligned_nrpages(sg
->offset
, sg
->length
);
2756 iova
= __intel_alloc_iova(hwdev
, domain
, size
<< VTD_PAGE_SHIFT
,
2759 sglist
->dma_length
= 0;
2764 * Check if DMAR supports zero-length reads on write only
2767 if (dir
== DMA_TO_DEVICE
|| dir
== DMA_BIDIRECTIONAL
|| \
2768 !cap_zlr(iommu
->cap
))
2769 prot
|= DMA_PTE_READ
;
2770 if (dir
== DMA_FROM_DEVICE
|| dir
== DMA_BIDIRECTIONAL
)
2771 prot
|= DMA_PTE_WRITE
;
2773 start_vpfn
= mm_to_dma_pfn(iova
->pfn_lo
);
2775 for_each_sg(sglist
, sg
, nelems
, i
) {
2776 int nr_pages
= aligned_nrpages(sg
->offset
, sg
->length
);
2777 ret
= domain_pfn_mapping(domain
, start_vpfn
+ offset_pfn
,
2778 page_to_dma_pfn(sg_page(sg
)),
2781 /* clear the page */
2782 dma_pte_clear_range(domain
, start_vpfn
,
2783 start_vpfn
+ offset_pfn
);
2784 /* free page tables */
2785 dma_pte_free_pagetable(domain
, start_vpfn
,
2786 start_vpfn
+ offset_pfn
);
2788 __free_iova(&domain
->iovad
, iova
);
2791 sg
->dma_address
= ((dma_addr_t
)(start_vpfn
+ offset_pfn
)
2792 << VTD_PAGE_SHIFT
) + sg
->offset
;
2793 sg
->dma_length
= sg
->length
;
2794 offset_pfn
+= nr_pages
;
2797 /* it's a non-present to present mapping. Only flush if caching mode */
2798 if (cap_caching_mode(iommu
->cap
))
2799 iommu_flush_iotlb_psi(iommu
, 0, start_vpfn
, offset_pfn
);
2801 iommu_flush_write_buffer(iommu
);
2806 static int intel_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
2811 struct dma_map_ops intel_dma_ops
= {
2812 .alloc_coherent
= intel_alloc_coherent
,
2813 .free_coherent
= intel_free_coherent
,
2814 .map_sg
= intel_map_sg
,
2815 .unmap_sg
= intel_unmap_sg
,
2816 .map_page
= intel_map_page
,
2817 .unmap_page
= intel_unmap_page
,
2818 .mapping_error
= intel_mapping_error
,
2821 static inline int iommu_domain_cache_init(void)
2825 iommu_domain_cache
= kmem_cache_create("iommu_domain",
2826 sizeof(struct dmar_domain
),
2831 if (!iommu_domain_cache
) {
2832 printk(KERN_ERR
"Couldn't create iommu_domain cache\n");
2839 static inline int iommu_devinfo_cache_init(void)
2843 iommu_devinfo_cache
= kmem_cache_create("iommu_devinfo",
2844 sizeof(struct device_domain_info
),
2848 if (!iommu_devinfo_cache
) {
2849 printk(KERN_ERR
"Couldn't create devinfo cache\n");
2856 static inline int iommu_iova_cache_init(void)
2860 iommu_iova_cache
= kmem_cache_create("iommu_iova",
2861 sizeof(struct iova
),
2865 if (!iommu_iova_cache
) {
2866 printk(KERN_ERR
"Couldn't create iova cache\n");
2873 static int __init
iommu_init_mempool(void)
2876 ret
= iommu_iova_cache_init();
2880 ret
= iommu_domain_cache_init();
2884 ret
= iommu_devinfo_cache_init();
2888 kmem_cache_destroy(iommu_domain_cache
);
2890 kmem_cache_destroy(iommu_iova_cache
);
2895 static void __init
iommu_exit_mempool(void)
2897 kmem_cache_destroy(iommu_devinfo_cache
);
2898 kmem_cache_destroy(iommu_domain_cache
);
2899 kmem_cache_destroy(iommu_iova_cache
);
2903 static void __init
init_no_remapping_devices(void)
2905 struct dmar_drhd_unit
*drhd
;
2907 for_each_drhd_unit(drhd
) {
2908 if (!drhd
->include_all
) {
2910 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
2911 if (drhd
->devices
[i
] != NULL
)
2913 /* ignore DMAR unit if no pci devices exist */
2914 if (i
== drhd
->devices_cnt
)
2922 for_each_drhd_unit(drhd
) {
2924 if (drhd
->ignored
|| drhd
->include_all
)
2927 for (i
= 0; i
< drhd
->devices_cnt
; i
++)
2928 if (drhd
->devices
[i
] &&
2929 !IS_GFX_DEVICE(drhd
->devices
[i
]))
2932 if (i
< drhd
->devices_cnt
)
2935 /* bypass IOMMU if it is just for gfx devices */
2937 for (i
= 0; i
< drhd
->devices_cnt
; i
++) {
2938 if (!drhd
->devices
[i
])
2940 drhd
->devices
[i
]->dev
.archdata
.iommu
= DUMMY_DEVICE_DOMAIN_INFO
;
2945 #ifdef CONFIG_SUSPEND
2946 static int init_iommu_hw(void)
2948 struct dmar_drhd_unit
*drhd
;
2949 struct intel_iommu
*iommu
= NULL
;
2951 for_each_active_iommu(iommu
, drhd
)
2953 dmar_reenable_qi(iommu
);
2955 for_each_active_iommu(iommu
, drhd
) {
2956 iommu_flush_write_buffer(iommu
);
2958 iommu_set_root_entry(iommu
);
2960 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
2961 DMA_CCMD_GLOBAL_INVL
);
2962 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
2963 DMA_TLB_GLOBAL_FLUSH
);
2964 iommu_disable_protect_mem_regions(iommu
);
2965 iommu_enable_translation(iommu
);
2971 static void iommu_flush_all(void)
2973 struct dmar_drhd_unit
*drhd
;
2974 struct intel_iommu
*iommu
;
2976 for_each_active_iommu(iommu
, drhd
) {
2977 iommu
->flush
.flush_context(iommu
, 0, 0, 0,
2978 DMA_CCMD_GLOBAL_INVL
);
2979 iommu
->flush
.flush_iotlb(iommu
, 0, 0, 0,
2980 DMA_TLB_GLOBAL_FLUSH
);
2984 static int iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
2986 struct dmar_drhd_unit
*drhd
;
2987 struct intel_iommu
*iommu
= NULL
;
2990 for_each_active_iommu(iommu
, drhd
) {
2991 iommu
->iommu_state
= kzalloc(sizeof(u32
) * MAX_SR_DMAR_REGS
,
2993 if (!iommu
->iommu_state
)
2999 for_each_active_iommu(iommu
, drhd
) {
3000 iommu_disable_translation(iommu
);
3002 spin_lock_irqsave(&iommu
->register_lock
, flag
);
3004 iommu
->iommu_state
[SR_DMAR_FECTL_REG
] =
3005 readl(iommu
->reg
+ DMAR_FECTL_REG
);
3006 iommu
->iommu_state
[SR_DMAR_FEDATA_REG
] =
3007 readl(iommu
->reg
+ DMAR_FEDATA_REG
);
3008 iommu
->iommu_state
[SR_DMAR_FEADDR_REG
] =
3009 readl(iommu
->reg
+ DMAR_FEADDR_REG
);
3010 iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
] =
3011 readl(iommu
->reg
+ DMAR_FEUADDR_REG
);
3013 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3018 for_each_active_iommu(iommu
, drhd
)
3019 kfree(iommu
->iommu_state
);
3024 static int iommu_resume(struct sys_device
*dev
)
3026 struct dmar_drhd_unit
*drhd
;
3027 struct intel_iommu
*iommu
= NULL
;
3030 if (init_iommu_hw()) {
3031 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3035 for_each_active_iommu(iommu
, drhd
) {
3037 spin_lock_irqsave(&iommu
->register_lock
, flag
);
3039 writel(iommu
->iommu_state
[SR_DMAR_FECTL_REG
],
3040 iommu
->reg
+ DMAR_FECTL_REG
);
3041 writel(iommu
->iommu_state
[SR_DMAR_FEDATA_REG
],
3042 iommu
->reg
+ DMAR_FEDATA_REG
);
3043 writel(iommu
->iommu_state
[SR_DMAR_FEADDR_REG
],
3044 iommu
->reg
+ DMAR_FEADDR_REG
);
3045 writel(iommu
->iommu_state
[SR_DMAR_FEUADDR_REG
],
3046 iommu
->reg
+ DMAR_FEUADDR_REG
);
3048 spin_unlock_irqrestore(&iommu
->register_lock
, flag
);
3051 for_each_active_iommu(iommu
, drhd
)
3052 kfree(iommu
->iommu_state
);
3057 static struct sysdev_class iommu_sysclass
= {
3059 .resume
= iommu_resume
,
3060 .suspend
= iommu_suspend
,
3063 static struct sys_device device_iommu
= {
3064 .cls
= &iommu_sysclass
,
3067 static int __init
init_iommu_sysfs(void)
3071 error
= sysdev_class_register(&iommu_sysclass
);
3075 error
= sysdev_register(&device_iommu
);
3077 sysdev_class_unregister(&iommu_sysclass
);
3083 static int __init
init_iommu_sysfs(void)
3087 #endif /* CONFIG_PM */
3089 int __init
intel_iommu_init(void)
3093 if (dmar_table_init())
3096 if (dmar_dev_scope_init())
3100 * Check the need for DMA-remapping initialization now.
3101 * Above initialization will also be used by Interrupt-remapping.
3103 if (no_iommu
|| (swiotlb
&& !iommu_pass_through
) || dmar_disabled
)
3106 iommu_init_mempool();
3107 dmar_init_reserved_ranges();
3109 init_no_remapping_devices();
3113 printk(KERN_ERR
"IOMMU: dmar init failed\n");
3114 put_iova_domain(&reserved_iova_list
);
3115 iommu_exit_mempool();
3119 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3121 init_timer(&unmap_timer
);
3124 if (!iommu_pass_through
) {
3126 "Multi-level page-table translation for DMAR.\n");
3127 dma_ops
= &intel_dma_ops
;
3130 "DMAR: Pass through translation for DMAR.\n");
3134 register_iommu(&intel_iommu_ops
);
3139 static void iommu_detach_dependent_devices(struct intel_iommu
*iommu
,
3140 struct pci_dev
*pdev
)
3142 struct pci_dev
*tmp
, *parent
;
3144 if (!iommu
|| !pdev
)
3147 /* dependent device detach */
3148 tmp
= pci_find_upstream_pcie_bridge(pdev
);
3149 /* Secondary interface's bus number and devfn 0 */
3151 parent
= pdev
->bus
->self
;
3152 while (parent
!= tmp
) {
3153 iommu_detach_dev(iommu
, parent
->bus
->number
,
3155 parent
= parent
->bus
->self
;
3157 if (tmp
->is_pcie
) /* this is a PCIE-to-PCI bridge */
3158 iommu_detach_dev(iommu
,
3159 tmp
->subordinate
->number
, 0);
3160 else /* this is a legacy PCI bridge */
3161 iommu_detach_dev(iommu
, tmp
->bus
->number
,
3166 static void domain_remove_one_dev_info(struct dmar_domain
*domain
,
3167 struct pci_dev
*pdev
)
3169 struct device_domain_info
*info
;
3170 struct intel_iommu
*iommu
;
3171 unsigned long flags
;
3173 struct list_head
*entry
, *tmp
;
3175 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3180 spin_lock_irqsave(&device_domain_lock
, flags
);
3181 list_for_each_safe(entry
, tmp
, &domain
->devices
) {
3182 info
= list_entry(entry
, struct device_domain_info
, link
);
3183 /* No need to compare PCI domain; it has to be the same */
3184 if (info
->bus
== pdev
->bus
->number
&&
3185 info
->devfn
== pdev
->devfn
) {
3186 list_del(&info
->link
);
3187 list_del(&info
->global
);
3189 info
->dev
->dev
.archdata
.iommu
= NULL
;
3190 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3192 iommu_disable_dev_iotlb(info
);
3193 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3194 iommu_detach_dependent_devices(iommu
, pdev
);
3195 free_devinfo_mem(info
);
3197 spin_lock_irqsave(&device_domain_lock
, flags
);
3205 /* if there is no other devices under the same iommu
3206 * owned by this domain, clear this iommu in iommu_bmp
3207 * update iommu count and coherency
3209 if (iommu
== device_to_iommu(info
->segment
, info
->bus
,
3215 unsigned long tmp_flags
;
3216 spin_lock_irqsave(&domain
->iommu_lock
, tmp_flags
);
3217 clear_bit(iommu
->seq_id
, &domain
->iommu_bmp
);
3218 domain
->iommu_count
--;
3219 domain_update_iommu_cap(domain
);
3220 spin_unlock_irqrestore(&domain
->iommu_lock
, tmp_flags
);
3223 spin_unlock_irqrestore(&device_domain_lock
, flags
);
3226 static void vm_domain_remove_all_dev_info(struct dmar_domain
*domain
)
3228 struct device_domain_info
*info
;
3229 struct intel_iommu
*iommu
;
3230 unsigned long flags1
, flags2
;
3232 spin_lock_irqsave(&device_domain_lock
, flags1
);
3233 while (!list_empty(&domain
->devices
)) {
3234 info
= list_entry(domain
->devices
.next
,
3235 struct device_domain_info
, link
);
3236 list_del(&info
->link
);
3237 list_del(&info
->global
);
3239 info
->dev
->dev
.archdata
.iommu
= NULL
;
3241 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3243 iommu_disable_dev_iotlb(info
);
3244 iommu
= device_to_iommu(info
->segment
, info
->bus
, info
->devfn
);
3245 iommu_detach_dev(iommu
, info
->bus
, info
->devfn
);
3246 iommu_detach_dependent_devices(iommu
, info
->dev
);
3248 /* clear this iommu in iommu_bmp, update iommu count
3251 spin_lock_irqsave(&domain
->iommu_lock
, flags2
);
3252 if (test_and_clear_bit(iommu
->seq_id
,
3253 &domain
->iommu_bmp
)) {
3254 domain
->iommu_count
--;
3255 domain_update_iommu_cap(domain
);
3257 spin_unlock_irqrestore(&domain
->iommu_lock
, flags2
);
3259 free_devinfo_mem(info
);
3260 spin_lock_irqsave(&device_domain_lock
, flags1
);
3262 spin_unlock_irqrestore(&device_domain_lock
, flags1
);
3265 /* domain id for virtual machine, it won't be set in context */
3266 static unsigned long vm_domid
;
3268 static int vm_domain_min_agaw(struct dmar_domain
*domain
)
3271 int min_agaw
= domain
->agaw
;
3273 i
= find_first_bit(&domain
->iommu_bmp
, g_num_of_iommus
);
3274 for (; i
< g_num_of_iommus
; ) {
3275 if (min_agaw
> g_iommus
[i
]->agaw
)
3276 min_agaw
= g_iommus
[i
]->agaw
;
3278 i
= find_next_bit(&domain
->iommu_bmp
, g_num_of_iommus
, i
+1);
3284 static struct dmar_domain
*iommu_alloc_vm_domain(void)
3286 struct dmar_domain
*domain
;
3288 domain
= alloc_domain_mem();
3292 domain
->id
= vm_domid
++;
3293 memset(&domain
->iommu_bmp
, 0, sizeof(unsigned long));
3294 domain
->flags
= DOMAIN_FLAG_VIRTUAL_MACHINE
;
3299 static int md_domain_init(struct dmar_domain
*domain
, int guest_width
)
3303 init_iova_domain(&domain
->iovad
, DMA_32BIT_PFN
);
3304 spin_lock_init(&domain
->mapping_lock
);
3305 spin_lock_init(&domain
->iommu_lock
);
3307 domain_reserve_special_ranges(domain
);
3309 /* calculate AGAW */
3310 domain
->gaw
= guest_width
;
3311 adjust_width
= guestwidth_to_adjustwidth(guest_width
);
3312 domain
->agaw
= width_to_agaw(adjust_width
);
3314 INIT_LIST_HEAD(&domain
->devices
);
3316 domain
->iommu_count
= 0;
3317 domain
->iommu_coherency
= 0;
3318 domain
->max_addr
= 0;
3320 /* always allocate the top pgd */
3321 domain
->pgd
= (struct dma_pte
*)alloc_pgtable_page();
3324 domain_flush_cache(domain
, domain
->pgd
, PAGE_SIZE
);
3328 static void iommu_free_vm_domain(struct dmar_domain
*domain
)
3330 unsigned long flags
;
3331 struct dmar_drhd_unit
*drhd
;
3332 struct intel_iommu
*iommu
;
3334 unsigned long ndomains
;
3336 for_each_drhd_unit(drhd
) {
3339 iommu
= drhd
->iommu
;
3341 ndomains
= cap_ndoms(iommu
->cap
);
3342 i
= find_first_bit(iommu
->domain_ids
, ndomains
);
3343 for (; i
< ndomains
; ) {
3344 if (iommu
->domains
[i
] == domain
) {
3345 spin_lock_irqsave(&iommu
->lock
, flags
);
3346 clear_bit(i
, iommu
->domain_ids
);
3347 iommu
->domains
[i
] = NULL
;
3348 spin_unlock_irqrestore(&iommu
->lock
, flags
);
3351 i
= find_next_bit(iommu
->domain_ids
, ndomains
, i
+1);
3356 static void vm_domain_exit(struct dmar_domain
*domain
)
3358 /* Domain 0 is reserved, so dont process it */
3362 vm_domain_remove_all_dev_info(domain
);
3364 put_iova_domain(&domain
->iovad
);
3367 dma_pte_clear_range(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
3369 /* free page tables */
3370 dma_pte_free_pagetable(domain
, 0, DOMAIN_MAX_PFN(domain
->gaw
));
3372 iommu_free_vm_domain(domain
);
3373 free_domain_mem(domain
);
3376 static int intel_iommu_domain_init(struct iommu_domain
*domain
)
3378 struct dmar_domain
*dmar_domain
;
3380 dmar_domain
= iommu_alloc_vm_domain();
3383 "intel_iommu_domain_init: dmar_domain == NULL\n");
3386 if (md_domain_init(dmar_domain
, DEFAULT_DOMAIN_ADDRESS_WIDTH
)) {
3388 "intel_iommu_domain_init() failed\n");
3389 vm_domain_exit(dmar_domain
);
3392 domain
->priv
= dmar_domain
;
3397 static void intel_iommu_domain_destroy(struct iommu_domain
*domain
)
3399 struct dmar_domain
*dmar_domain
= domain
->priv
;
3401 domain
->priv
= NULL
;
3402 vm_domain_exit(dmar_domain
);
3405 static int intel_iommu_attach_device(struct iommu_domain
*domain
,
3408 struct dmar_domain
*dmar_domain
= domain
->priv
;
3409 struct pci_dev
*pdev
= to_pci_dev(dev
);
3410 struct intel_iommu
*iommu
;
3415 /* normally pdev is not mapped */
3416 if (unlikely(domain_context_mapped(pdev
))) {
3417 struct dmar_domain
*old_domain
;
3419 old_domain
= find_domain(pdev
);
3421 if (dmar_domain
->flags
& DOMAIN_FLAG_VIRTUAL_MACHINE
||
3422 dmar_domain
->flags
& DOMAIN_FLAG_STATIC_IDENTITY
)
3423 domain_remove_one_dev_info(old_domain
, pdev
);
3425 domain_remove_dev_info(old_domain
);
3429 iommu
= device_to_iommu(pci_domain_nr(pdev
->bus
), pdev
->bus
->number
,
3434 /* check if this iommu agaw is sufficient for max mapped address */
3435 addr_width
= agaw_to_width(iommu
->agaw
);
3436 end
= DOMAIN_MAX_ADDR(addr_width
);
3437 end
= end
& VTD_PAGE_MASK
;
3438 if (end
< dmar_domain
->max_addr
) {
3439 printk(KERN_ERR
"%s: iommu agaw (%d) is not "
3440 "sufficient for the mapped address (%llx)\n",
3441 __func__
, iommu
->agaw
, dmar_domain
->max_addr
);
3445 ret
= domain_add_dev_info(dmar_domain
, pdev
);
3449 ret
= domain_context_mapping(dmar_domain
, pdev
, CONTEXT_TT_MULTI_LEVEL
);
3453 static void intel_iommu_detach_device(struct iommu_domain
*domain
,
3456 struct dmar_domain
*dmar_domain
= domain
->priv
;
3457 struct pci_dev
*pdev
= to_pci_dev(dev
);
3459 domain_remove_one_dev_info(dmar_domain
, pdev
);
3462 static int intel_iommu_map_range(struct iommu_domain
*domain
,
3463 unsigned long iova
, phys_addr_t hpa
,
3464 size_t size
, int iommu_prot
)
3466 struct dmar_domain
*dmar_domain
= domain
->priv
;
3472 if (iommu_prot
& IOMMU_READ
)
3473 prot
|= DMA_PTE_READ
;
3474 if (iommu_prot
& IOMMU_WRITE
)
3475 prot
|= DMA_PTE_WRITE
;
3476 if ((iommu_prot
& IOMMU_CACHE
) && dmar_domain
->iommu_snooping
)
3477 prot
|= DMA_PTE_SNP
;
3479 max_addr
= iova
+ size
;
3480 if (dmar_domain
->max_addr
< max_addr
) {
3484 /* check if minimum agaw is sufficient for mapped address */
3485 min_agaw
= vm_domain_min_agaw(dmar_domain
);
3486 addr_width
= agaw_to_width(min_agaw
);
3487 end
= DOMAIN_MAX_ADDR(addr_width
);
3488 end
= end
& VTD_PAGE_MASK
;
3489 if (end
< max_addr
) {
3490 printk(KERN_ERR
"%s: iommu agaw (%d) is not "
3491 "sufficient for the mapped address (%llx)\n",
3492 __func__
, min_agaw
, max_addr
);
3495 dmar_domain
->max_addr
= max_addr
;
3497 /* Round up size to next multiple of PAGE_SIZE, if it and
3498 the low bits of hpa would take us onto the next page */
3499 size
= aligned_nrpages(hpa
, size
);
3500 ret
= domain_pfn_mapping(dmar_domain
, iova
>> VTD_PAGE_SHIFT
,
3501 hpa
>> VTD_PAGE_SHIFT
, size
, prot
);
3505 static void intel_iommu_unmap_range(struct iommu_domain
*domain
,
3506 unsigned long iova
, size_t size
)
3508 struct dmar_domain
*dmar_domain
= domain
->priv
;
3510 dma_pte_clear_range(dmar_domain
, iova
>> VTD_PAGE_SHIFT
,
3511 (iova
+ size
- 1) >> VTD_PAGE_SHIFT
);
3513 if (dmar_domain
->max_addr
== iova
+ size
)
3514 dmar_domain
->max_addr
= iova
;
3517 static phys_addr_t
intel_iommu_iova_to_phys(struct iommu_domain
*domain
,
3520 struct dmar_domain
*dmar_domain
= domain
->priv
;
3521 struct dma_pte
*pte
;
3524 pte
= pfn_to_dma_pte(dmar_domain
, iova
>> VTD_PAGE_SHIFT
);
3526 phys
= dma_pte_addr(pte
);
3531 static int intel_iommu_domain_has_cap(struct iommu_domain
*domain
,
3534 struct dmar_domain
*dmar_domain
= domain
->priv
;
3536 if (cap
== IOMMU_CAP_CACHE_COHERENCY
)
3537 return dmar_domain
->iommu_snooping
;
3542 static struct iommu_ops intel_iommu_ops
= {
3543 .domain_init
= intel_iommu_domain_init
,
3544 .domain_destroy
= intel_iommu_domain_destroy
,
3545 .attach_dev
= intel_iommu_attach_device
,
3546 .detach_dev
= intel_iommu_detach_device
,
3547 .map
= intel_iommu_map_range
,
3548 .unmap
= intel_iommu_unmap_range
,
3549 .iova_to_phys
= intel_iommu_iova_to_phys
,
3550 .domain_has_cap
= intel_iommu_domain_has_cap
,
3553 static void __devinit
quirk_iommu_rwbf(struct pci_dev
*dev
)
3556 * Mobile 4 Series Chipset neglects to set RWBF capability,
3559 printk(KERN_INFO
"DMAR: Forcing write-buffer flush capability\n");
3563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2a40, quirk_iommu_rwbf
);