arch/ppc/platforms/sandpoint.c

   1 /*
   2  * arch/ppc/platforms/sandpoint_setup.c
   3  *
   4  * Board setup routines for the Motorola SPS Sandpoint Test Platform.
   5  *
   6  * Author: Mark A. Greer
   7  *       mgreer@mvista.com
   8  *
   9  * 2000-2003 (c) MontaVista Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file adds support for the Motorola SPS Sandpoint Test Platform.
  17  * These boards have a PPMC slot for the processor so any combination
  18  * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
  19  * module from Motorola SPS and other closely related cpu/host bridge
  20  * combinations (e.g., 750/755/7400 with MPC107 host bridge).
  21  * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
  22  * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
  23  * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
  24  * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
  25  * but are really 5V).
  26  *
  27  * The firmware on the sandpoint is called DINK (not my acronym :).  This port
  28  * depends on DINK to do some basic initialization (e.g., initialize the memory
  29  * ctlr) and to ensure that the processor is using MAP B (CHRP map).
  30  *
  31  * The switch settings for the Sandpoint board MUST be as follows:
  32  *      S3: down
  33  *      S4: up
  34  *      S5: up
  35  *      S6: down
  36  *
  37  * 'down' is in the direction from the PCI slots towards the PPMC slot;
  38  * 'up' is in the direction from the PPMC slot towards the PCI slots.
  39  * Be careful, the way the sandpoint board is installed in XT chasses will
  40  * make the directions reversed.
  41  *
  42  * Since Motorola listened to our suggestions for improvement, we now have
  43  * the Sandpoint X3 board.  All of the PCI slots are available, it uses
  44  * the serial interrupt interface (just a hardware thing we need to
  45  * configure properly).
  46  *
  47  * Use the default X3 switch settings.  The interrupts are then:
  48  *              EPIC    Source
  49  *                0     SIOINT          (8259, active low)
  50  *                1     PCI #1
  51  *                2     PCI #2
  52  *                3     PCI #3
  53  *                4     PCI #4
  54  *                7     Winbond INTC    (IDE interrupt)
  55  *                8     Winbond INTD    (IDE interrupt)
  56  *
  57  *
  58  * Motorola has finally released a version of DINK32 that correctly
  59  * (seemingly) initalizes the memory controller correctly, regardless
  60  * of the amount of memory in the system.  Once a method of determining
  61  * what version of DINK initializes the system for us, if applicable, is
  62  * found, we can hopefully stop hardcoding 32MB of RAM.
  63  */
  64
  65 #include <linux/config.h>
  66 #include <linux/stddef.h>
  67 #include <linux/kernel.h>
  68 #include <linux/init.h>
  69 #include <linux/errno.h>
  70 #include <linux/reboot.h>
  71 #include <linux/pci.h>
  72 #include <linux/kdev_t.h>
  73 #include <linux/major.h>
  74 #include <linux/initrd.h>
  75 #include <linux/console.h>
  76 #include <linux/delay.h>
  77 #include <linux/ide.h>
  78 #include <linux/seq_file.h>
  79 #include <linux/root_dev.h>
  80 #include <linux/serial.h>
  81 #include <linux/tty.h>  /* for linux/serial_core.h */
  82 #include <linux/serial_core.h>
  83 #include <linux/serial_8250.h>
  84
  85 #include <asm/system.h>
  86 #include <asm/pgtable.h>
  87 #include <asm/page.h>
  88 #include <asm/time.h>
  89 #include <asm/dma.h>
  90 #include <asm/io.h>
  91 #include <asm/machdep.h>
  92 #include <asm/prom.h>
  93 #include <asm/smp.h>
  94 #include <asm/vga.h>
  95 #include <asm/open_pic.h>
  96 #include <asm/i8259.h>
  97 #include <asm/todc.h>
  98 #include <asm/bootinfo.h>
  99 #include <asm/mpc10x.h>
 100 #include <asm/pci-bridge.h>
 101 #include <asm/kgdb.h>
 102 #include <asm/ppc_sys.h>
 103
 104 #include "sandpoint.h"
 105
 106 /* Set non-zero if an X2 Sandpoint detected. */
 107 static int sandpoint_is_x2;
 108
 109 unsigned char __res[sizeof(bd_t)];
 110
 111 static void sandpoint_halt(void);
 112 static void sandpoint_probe_type(void);
 113
 114 /*
 115  * Define all of the IRQ senses and polarities.  Taken from the
 116  * Sandpoint X3 User's manual.
 117  */
 118 static u_char sandpoint_openpic_initsenses[] __initdata = {
 119         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 0: SIOINT */
 120         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 2: PCI Slot 1 */
 121         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 3: PCI Slot 2 */
 122         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 4: PCI Slot 3 */
 123         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 5: PCI Slot 4 */
 124         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 8: IDE (INT C) */
 125         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* 9: IDE (INT D) */
 126 };
 127
 128 /*
 129  * Motorola SPS Sandpoint interrupt routing.
 130  */
 131 static inline int
 132 x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 133 {
 134         static char pci_irq_table[][4] =
 135         /*
 136          *      PCI IDSEL/INTPIN->INTLINE
 137          *         A   B   C   D
 138          */
 139         {
 140                 { 16,  0,  0,  0 },     /* IDSEL 11 - i8259 on Winbond */
 141                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 142                 { 18, 21, 20, 19 },     /* IDSEL 13 - PCI slot 1 */
 143                 { 19, 18, 21, 20 },     /* IDSEL 14 - PCI slot 2 */
 144                 { 20, 19, 18, 21 },     /* IDSEL 15 - PCI slot 3 */
 145                 { 21, 20, 19, 18 },     /* IDSEL 16 - PCI slot 4 */
 146         };
 147
 148         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 149         return PCI_IRQ_TABLE_LOOKUP;
 150 }
 151
 152 static inline int
 153 x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 154 {
 155         static char pci_irq_table[][4] =
 156         /*
 157          *      PCI IDSEL/INTPIN->INTLINE
 158          *         A   B   C   D
 159          */
 160         {
 161                 { 18,  0,  0,  0 },     /* IDSEL 11 - i8259 on Windbond */
 162                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 163                 { 16, 17, 18, 19 },     /* IDSEL 13 - PCI slot 1 */
 164                 { 17, 18, 19, 16 },     /* IDSEL 14 - PCI slot 2 */
 165                 { 18, 19, 16, 17 },     /* IDSEL 15 - PCI slot 3 */
 166                 { 19, 16, 17, 18 },     /* IDSEL 16 - PCI slot 4 */
 167         };
 168
 169         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 170         return PCI_IRQ_TABLE_LOOKUP;
 171 }
 172
 173 static void __init
 174 sandpoint_setup_winbond_83553(struct pci_controller *hose)
 175 {
 176         int             devfn;
 177
 178         /*
 179          * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
 180          * We can't route the IDE interrupt to PCI INTC# or INTD# because those
 181          * woule interfere with the PMC's INTC# and INTD# lines.
 182          */
 183         /*
 184          * Winbond Fcn 0
 185          */
 186         devfn = PCI_DEVFN(11,0);
 187
 188         early_write_config_byte(hose,
 189                                 0,
 190                                 devfn,
 191                                 0x43, /* IDE Interrupt Routing Control */
 192                                 0xef);
 193         early_write_config_word(hose,
 194                                 0,
 195                                 devfn,
 196                                 0x44, /* PCI Interrupt Routing Control */
 197                                 0x0000);
 198
 199         /* Want ISA memory cycles to be forwarded to PCI bus */
 200         early_write_config_byte(hose,
 201                                 0,
 202                                 devfn,
 203                                 0x48, /* ISA-to-PCI Addr Decoder Control */
 204                                 0xf0);
 205
 206         /* Enable Port 92.  */
 207         early_write_config_byte(hose,
 208                                 0,
 209                                 devfn,
 210                                 0x4e,   /* AT System Control Register */
 211                                 0x06);
 212         /*
 213          * Winbond Fcn 1
 214          */
 215         devfn = PCI_DEVFN(11,1);
 216
 217         /* Put IDE controller into native mode. */
 218         early_write_config_byte(hose,
 219                                 0,
 220                                 devfn,
 221                                 0x09,   /* Programming interface Register */
 222                                 0x8f);
 223
 224         /* Init IRQ routing, enable both ports, disable fast 16 */
 225         early_write_config_dword(hose,
 226                                 0,
 227                                 devfn,
 228                                 0x40,   /* IDE Control/Status Register */
 229                                 0x00ff0011);
 230         return;
 231 }
 232
 233 /* On the sandpoint X2, we must avoid sending configuration cycles to
 234  * device #12 (IDSEL addr = AD12).
 235  */
 236 static int
 237 x2_exclude_device(u_char bus, u_char devfn)
 238 {
 239         if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
 240                 return PCIBIOS_DEVICE_NOT_FOUND;
 241         else
 242                 return PCIBIOS_SUCCESSFUL;
 243 }
 244
 245 static void __init
 246 sandpoint_find_bridges(void)
 247 {
 248         struct pci_controller   *hose;
 249
 250         hose = pcibios_alloc_controller();
 251
 252         if (!hose)
 253                 return;
 254
 255         hose->first_busno = 0;
 256         hose->last_busno = 0xff;
 257
 258         if (mpc10x_bridge_init(hose,
 259                                MPC10X_MEM_MAP_B,
 260                                MPC10X_MEM_MAP_B,
 261                                MPC10X_MAPB_EUMB_BASE) == 0) {
 262
 263                 /* Do early winbond init, then scan PCI bus */
 264                 sandpoint_setup_winbond_83553(hose);
 265                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 266
 267                 ppc_md.pcibios_fixup = NULL;
 268                 ppc_md.pcibios_fixup_bus = NULL;
 269                 ppc_md.pci_swizzle = common_swizzle;
 270                 if (sandpoint_is_x2) {
 271                         ppc_md.pci_map_irq = x2_map_irq;
 272                         ppc_md.pci_exclude_device = x2_exclude_device;
 273                 } else
 274                         ppc_md.pci_map_irq = x3_map_irq;
 275         }
 276         else {
 277                 if (ppc_md.progress)
 278                         ppc_md.progress("Bridge init failed", 0x100);
 279                 printk("Host bridge init failed\n");
 280         }
 281
 282         return;
 283 }
 284
 285 static void __init
 286 sandpoint_setup_arch(void)
 287 {
 288         /* Probe for Sandpoint model */
 289         sandpoint_probe_type();
 290         if (sandpoint_is_x2)
 291                 epic_serial_mode = 0;
 292
 293         loops_per_jiffy = 100000000 / HZ;
 294
 295 #ifdef CONFIG_BLK_DEV_INITRD
 296         if (initrd_start)
 297                 ROOT_DEV = Root_RAM0;
 298         else
 299 #endif
 300 #ifdef  CONFIG_ROOT_NFS
 301                 ROOT_DEV = Root_NFS;
 302 #else
 303                 ROOT_DEV = Root_HDA1;
 304 #endif
 305
 306         /* Lookup PCI host bridges */
 307         sandpoint_find_bridges();
 308
 309         if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
 310         {
 311                 bd_t *bp = (bd_t *)__res;
 312                 struct plat_serial8250_port *pdata;
 313
 314                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
 315                 if (pdata)
 316                 {
 317                         pdata[0].uartclk = bp->bi_busfreq;
 318                 }
 319
 320 #ifdef CONFIG_SANDPOINT_ENABLE_UART1
 321                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
 322                 if (pdata)
 323                 {
 324                         pdata[0].uartclk = bp->bi_busfreq;
 325                 }
 326 #else
 327                 ppc_sys_device_remove(MPC10X_UART1);
 328 #endif
 329         }
 330
 331         printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
 332         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 333
 334         /* DINK32 12.3 and below do not correctly enable any caches.
 335          * We will do this now with good known values.  Future versions
 336          * of DINK32 are supposed to get this correct.
 337          */
 338         if (cpu_has_feature(CPU_FTR_SPEC7450))
 339                 /* 745x is different.  We only want to pass along enable. */
 340                 _set_L2CR(L2CR_L2E);
 341         else if (cpu_has_feature(CPU_FTR_L2CR))
 342                 /* All modules have 1MB of L2.  We also assume that an
 343                  * L2 divisor of 3 will work.
 344                  */
 345                 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
 346                                 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
 347 #if 0
 348         /* Untested right now. */
 349         if (cpu_has_feature(CPU_FTR_L3CR)) {
 350                 /* Magic value. */
 351                 _set_L3CR(0x8f032000);
 352         }
 353 #endif
 354 }
 355
 356 #define SANDPOINT_87308_CFG_ADDR                0x15c
 357 #define SANDPOINT_87308_CFG_DATA                0x15d
 358
 359 #define SANDPOINT_87308_CFG_INB(addr, byte) {                           \
 360         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 361         (byte) = inb(SANDPOINT_87308_CFG_DATA);                         \
 362 }
 363
 364 #define SANDPOINT_87308_CFG_OUTB(addr, byte) {                          \
 365         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 366         outb((byte), SANDPOINT_87308_CFG_DATA);                         \
 367 }
 368
 369 #define SANDPOINT_87308_SELECT_DEV(dev_num) {                           \
 370         SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));                      \
 371 }
 372
 373 #define SANDPOINT_87308_DEV_ENABLE(dev_num) {                           \
 374         SANDPOINT_87308_SELECT_DEV(dev_num);                            \
 375         SANDPOINT_87308_CFG_OUTB(0x30, 0x01);                           \
 376 }
 377
 378 /*
 379  * To probe the Sandpoint type, we need to check for a connection between GPIO
 380  * pins 6 and 7 on the NS87308 SuperIO.
 381  */
 382 static void __init sandpoint_probe_type(void)
 383 {
 384         u8 x;
 385         /* First, ensure that the GPIO pins are enabled. */
 386         SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
 387         SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
 388         SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
 389         SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
 390
 391         /* Now, set pin 7 to output and pin 6 to input. */
 392         outb((inb(0x701) | 0x80) & 0xbf, 0x701);
 393         /* Set push-pull output */
 394         outb(inb(0x702) | 0x80, 0x702);
 395         /* Set pull-up on input */
 396         outb(inb(0x703) | 0x40, 0x703);
 397         /* Set output high and check */
 398         x = inb(0x700);
 399         outb(x | 0x80, 0x700);
 400         x = inb(0x700);
 401         sandpoint_is_x2 = ! (x & 0x40);
 402         if (ppc_md.progress && sandpoint_is_x2)
 403                 ppc_md.progress("High output says X2", 0);
 404         /* Set output low and check */
 405         outb(x & 0x7f, 0x700);
 406         sandpoint_is_x2 |= inb(0x700) & 0x40;
 407         if (ppc_md.progress && sandpoint_is_x2)
 408                 ppc_md.progress("Low output says X2", 0);
 409         if (ppc_md.progress && ! sandpoint_is_x2)
 410                 ppc_md.progress("Sandpoint is X3", 0);
 411 }
 412
 413 /*
 414  * Fix IDE interrupts.
 415  */
 416 static int __init
 417 sandpoint_fix_winbond_83553(void)
 418 {
 419         /* Make some 8259 interrupt level sensitive */
 420         outb(0xe0, 0x4d0);
 421         outb(0xde, 0x4d1);
 422
 423         return 0;
 424 }
 425
 426 arch_initcall(sandpoint_fix_winbond_83553);
 427
 428 /*
 429  * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
 430  */
 431 static int __init
 432 sandpoint_setup_natl_87308(void)
 433 {
 434         u_char  reg;
 435
 436         /*
 437          * Enable all the devices on the Super I/O chip.
 438          */
 439         SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
 440         SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
 441         SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
 442         SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
 443         SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
 444         SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
 445         SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
 446         SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
 447         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 448         SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
 449         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 450
 451         /* Set up floppy in PS/2 mode */
 452         outb(0x09, SIO_CONFIG_RA);
 453         reg = inb(SIO_CONFIG_RD);
 454         reg = (reg & 0x3F) | 0x40;
 455         outb(reg, SIO_CONFIG_RD);
 456         outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
 457
 458         return 0;
 459 }
 460
 461 arch_initcall(sandpoint_setup_natl_87308);
 462
 463 static int __init
 464 sandpoint_request_io(void)
 465 {
 466         request_region(0x00,0x20,"dma1");
 467         request_region(0x20,0x20,"pic1");
 468         request_region(0x40,0x20,"timer");
 469         request_region(0x80,0x10,"dma page reg");
 470         request_region(0xa0,0x20,"pic2");
 471         request_region(0xc0,0x20,"dma2");
 472
 473         return 0;
 474 }
 475
 476 arch_initcall(sandpoint_request_io);
 477
 478 /*
 479  * Interrupt setup and service.  Interrrupts on the Sandpoint come
 480  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
 481  * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
 482  * IDE is on EPIC 7 and 8.
 483  */
 484 static void __init
 485 sandpoint_init_IRQ(void)
 486 {
 487         int i;
 488
 489         OpenPIC_InitSenses = sandpoint_openpic_initsenses;
 490         OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
 491
 492         mpc10x_set_openpic();
 493         openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
 494                         i8259_irq);
 495
 496         /*
 497          * The EPIC allows for a read in the range of 0xFEF00000 ->
 498          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 499          */
 500         i8259_init(0xfef00000, 0);
 501 }
 502
 503 static unsigned long __init
 504 sandpoint_find_end_of_memory(void)
 505 {
 506         bd_t *bp = (bd_t *)__res;
 507
 508         if (bp->bi_memsize)
 509                 return bp->bi_memsize;
 510
 511         /* DINK32 13.0 correctly initalizes things, so iff you use
 512          * this you _should_ be able to change this instead of a
 513          * hardcoded value. */
 514 #if 0
 515         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 516 #else
 517         return 32*1024*1024;
 518 #endif
 519 }
 520
 521 static void __init
 522 sandpoint_map_io(void)
 523 {
 524         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 525 }
 526
 527 static void
 528 sandpoint_restart(char *cmd)
 529 {
 530         local_irq_disable();
 531
 532         /* Set exception prefix high - to the firmware */
 533         _nmask_and_or_msr(0, MSR_IP);
 534
 535         /* Reset system via Port 92 */
 536         outb(0x00, 0x92);
 537         outb(0x01, 0x92);
 538         for(;;);        /* Spin until reset happens */
 539 }
 540
 541 static void
 542 sandpoint_power_off(void)
 543 {
 544         local_irq_disable();
 545         for(;;);        /* No way to shut power off with software */
 546         /* NOTREACHED */
 547 }
 548
 549 static void
 550 sandpoint_halt(void)
 551 {
 552         sandpoint_power_off();
 553         /* NOTREACHED */
 554 }
 555
 556 static int
 557 sandpoint_show_cpuinfo(struct seq_file *m)
 558 {
 559         seq_printf(m, "vendor\t\t: Motorola SPS\n");
 560         seq_printf(m, "machine\t\t: Sandpoint\n");
 561
 562         return 0;
 563 }
 564
 565 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 566 /*
 567  * IDE support.
 568  */
 569 static int              sandpoint_ide_ports_known = 0;
 570 static unsigned long    sandpoint_ide_regbase[MAX_HWIFS];
 571 static unsigned long    sandpoint_ide_ctl_regbase[MAX_HWIFS];
 572 static unsigned long    sandpoint_idedma_regbase;
 573
 574 static void
 575 sandpoint_ide_probe(void)
 576 {
 577         struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
 578                         PCI_DEVICE_ID_WINBOND_82C105, NULL);
 579
 580         if (pdev) {
 581                 sandpoint_ide_regbase[0]=pdev->resource[0].start;
 582                 sandpoint_ide_regbase[1]=pdev->resource[2].start;
 583                 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
 584                 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
 585                 sandpoint_idedma_regbase=pdev->resource[4].start;
 586                 pci_dev_put(pdev);
 587         }
 588
 589         sandpoint_ide_ports_known = 1;
 590 }
 591
 592 static int
 593 sandpoint_ide_default_irq(unsigned long base)
 594 {
 595         if (sandpoint_ide_ports_known == 0)
 596                 sandpoint_ide_probe();
 597
 598         if (base == sandpoint_ide_regbase[0])
 599                 return SANDPOINT_IDE_INT0;
 600         else if (base == sandpoint_ide_regbase[1])
 601                 return SANDPOINT_IDE_INT1;
 602         else
 603                 return 0;
 604 }
 605
 606 static unsigned long
 607 sandpoint_ide_default_io_base(int index)
 608 {
 609         if (sandpoint_ide_ports_known == 0)
 610                 sandpoint_ide_probe();
 611
 612         return sandpoint_ide_regbase[index];
 613 }
 614
 615 static void __init
 616 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
 617                 unsigned long ctrl_port, int *irq)
 618 {
 619         unsigned long reg = data_port;
 620         uint    alt_status_base;
 621         int     i;
 622
 623         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 624                 hw->io_ports[i] = reg++;
 625         }
 626
 627         if (data_port == sandpoint_ide_regbase[0]) {
 628                 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
 629                 hw->irq = 14;
 630         }
 631         else if (data_port == sandpoint_ide_regbase[1]) {
 632                 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
 633                 hw->irq = 15;
 634         }
 635         else {
 636                 alt_status_base = 0;
 637                 hw->irq = 0;
 638         }
 639
 640         if (ctrl_port) {
 641                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 642         } else {
 643                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 644         }
 645
 646         if (irq != NULL) {
 647                 *irq = hw->irq;
 648         }
 649 }
 650 #endif
 651
 652 /*
 653  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 654  */
 655 static __inline__ void
 656 sandpoint_set_bat(void)
 657 {
 658         unsigned long bat3u, bat3l;
 659
 660         __asm__ __volatile__(
 661                         " lis %0,0xf800\n       \
 662                         ori %1,%0,0x002a\n      \
 663                         ori %0,%0,0x0ffe\n      \
 664                         mtspr 0x21e,%0\n        \
 665                         mtspr 0x21f,%1\n        \
 666                         isync\n                 \
 667                         sync "
 668                         : "=r" (bat3u), "=r" (bat3l));
 669 }
 670
 671 TODC_ALLOC();
 672
 673 void __init
 674 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 675                 unsigned long r6, unsigned long r7)
 676 {
 677         parse_bootinfo(find_bootinfo());
 678
 679         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 680          * are non-zero, then we should use the board info from the bd_t
 681          * structure and the cmdline pointed to by r6 instead of the
 682          * information from birecs, if any.  Otherwise, use the information
 683          * from birecs as discovered by the preceeding call to
 684          * parse_bootinfo().  This rule should work with both PPCBoot, which
 685          * uses a bd_t board info structure, and the kernel boot wrapper,
 686          * which uses birecs.
 687          */
 688         if (r3 && r6) {
 689                 /* copy board info structure */
 690                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 691                 /* copy command line */
 692                 *(char *)(r7+KERNELBASE) = 0;
 693                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 694         }
 695
 696 #ifdef CONFIG_BLK_DEV_INITRD
 697         /* take care of initrd if we have one */
 698         if (r4) {
 699                 initrd_start = r4 + KERNELBASE;
 700                 initrd_end = r5 + KERNELBASE;
 701         }
 702 #endif /* CONFIG_BLK_DEV_INITRD */
 703
 704         /* Map in board regs, etc. */
 705         sandpoint_set_bat();
 706
 707         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 708         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 709         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 710         ISA_DMA_THRESHOLD = 0x00ffffff;
 711         DMA_MODE_READ = 0x44;
 712         DMA_MODE_WRITE = 0x48;
 713         ppc_do_canonicalize_irqs = 1;
 714
 715         ppc_md.setup_arch = sandpoint_setup_arch;
 716         ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
 717         ppc_md.init_IRQ = sandpoint_init_IRQ;
 718         ppc_md.get_irq = openpic_get_irq;
 719
 720         ppc_md.restart = sandpoint_restart;
 721         ppc_md.power_off = sandpoint_power_off;
 722         ppc_md.halt = sandpoint_halt;
 723
 724         ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
 725         ppc_md.setup_io_mappings = sandpoint_map_io;
 726
 727         TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
 728         ppc_md.time_init = todc_time_init;
 729         ppc_md.set_rtc_time = todc_set_rtc_time;
 730         ppc_md.get_rtc_time = todc_get_rtc_time;
 731         ppc_md.calibrate_decr = todc_calibrate_decr;
 732
 733         ppc_md.nvram_read_val = todc_mc146818_read_val;
 734         ppc_md.nvram_write_val = todc_mc146818_write_val;
 735
 736 #ifdef CONFIG_KGDB
 737         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 738 #endif
 739 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 740         ppc_md.progress = gen550_progress;
 741 #endif
 742
 743 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 744         ppc_ide_md.default_irq = sandpoint_ide_default_irq;
 745         ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
 746         ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
 747 #endif
 748 }