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[PATCH] PCI: make MSI quirk inheritable from the pci bus
[linux-2.6/verdex.git] / drivers / pci / msi.c
blob4de1c17ee573cecbdd1e6588a7c0d964a76249e1
1 /*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9 #include <linux/mm.h>
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18
19 #include <asm/errno.h>
20 #include <asm/io.h>
21 #include <asm/smp.h>
22
23 #include "pci.h"
24 #include "msi.h"
25
26 #define MSI_TARGET_CPU first_cpu(cpu_online_map)
27
28 static DEFINE_SPINLOCK(msi_lock);
29 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
30 static kmem_cache_t* msi_cachep;
31
32 static int pci_msi_enable = 1;
33 static int last_alloc_vector;
34 static int nr_released_vectors;
35 static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
36 static int nr_msix_devices;
37
38 #ifndef CONFIG_X86_IO_APIC
39 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
40 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
41 #endif
42
43 static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
44 {
45 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
46 }
47
48 static int msi_cache_init(void)
49 {
50 msi_cachep = kmem_cache_create("msi_cache",
51 NR_IRQS * sizeof(struct msi_desc),
52 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
53 if (!msi_cachep)
54 return -ENOMEM;
55
56 return 0;
57 }
58
59 static void msi_set_mask_bit(unsigned int vector, int flag)
60 {
61 struct msi_desc *entry;
62
63 entry = (struct msi_desc *)msi_desc[vector];
64 if (!entry || !entry->dev || !entry->mask_base)
65 return;
66 switch (entry->msi_attrib.type) {
67 case PCI_CAP_ID_MSI:
68 {
69 int pos;
70 u32 mask_bits;
71
72 pos = (long)entry->mask_base;
73 pci_read_config_dword(entry->dev, pos, &mask_bits);
74 mask_bits &= ~(1);
75 mask_bits |= flag;
76 pci_write_config_dword(entry->dev, pos, mask_bits);
77 break;
78 }
79 case PCI_CAP_ID_MSIX:
80 {
81 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
82 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
83 writel(flag, entry->mask_base + offset);
84 break;
85 }
86 default:
87 break;
88 }
89 }
90
91 #ifdef CONFIG_SMP
92 static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
93 {
94 struct msi_desc *entry;
95 struct msg_address address;
96 unsigned int irq = vector;
97 unsigned int dest_cpu = first_cpu(cpu_mask);
98
99 entry = (struct msi_desc *)msi_desc[vector];
100 if (!entry || !entry->dev)
101 return;
102
103 switch (entry->msi_attrib.type) {
104 case PCI_CAP_ID_MSI:
105 {
106 int pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI);
107
108 if (!pos)
109 return;
110
111 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
112 &address.lo_address.value);
113 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
114 address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
115 MSI_TARGET_CPU_SHIFT);
116 entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
117 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
118 address.lo_address.value);
119 set_native_irq_info(irq, cpu_mask);
120 break;
121 }
122 case PCI_CAP_ID_MSIX:
123 {
124 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
125 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
126
127 address.lo_address.value = readl(entry->mask_base + offset);
128 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
129 address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
130 MSI_TARGET_CPU_SHIFT);
131 entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
132 writel(address.lo_address.value, entry->mask_base + offset);
133 set_native_irq_info(irq, cpu_mask);
134 break;
135 }
136 default:
137 break;
138 }
139 }
140 #else
141 #define set_msi_affinity NULL
142 #endif /* CONFIG_SMP */
143
144 static void mask_MSI_irq(unsigned int vector)
145 {
146 msi_set_mask_bit(vector, 1);
147 }
148
149 static void unmask_MSI_irq(unsigned int vector)
150 {
151 msi_set_mask_bit(vector, 0);
152 }
153
154 static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
155 {
156 struct msi_desc *entry;
157 unsigned long flags;
158
159 spin_lock_irqsave(&msi_lock, flags);
160 entry = msi_desc[vector];
161 if (!entry || !entry->dev) {
162 spin_unlock_irqrestore(&msi_lock, flags);
163 return 0;
164 }
165 entry->msi_attrib.state = 1; /* Mark it active */
166 spin_unlock_irqrestore(&msi_lock, flags);
167
168 return 0; /* never anything pending */
169 }
170
171 static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
172 {
173 startup_msi_irq_wo_maskbit(vector);
174 unmask_MSI_irq(vector);
175 return 0; /* never anything pending */
176 }
177
178 static void shutdown_msi_irq(unsigned int vector)
179 {
180 struct msi_desc *entry;
181 unsigned long flags;
182
183 spin_lock_irqsave(&msi_lock, flags);
184 entry = msi_desc[vector];
185 if (entry && entry->dev)
186 entry->msi_attrib.state = 0; /* Mark it not active */
187 spin_unlock_irqrestore(&msi_lock, flags);
188 }
189
190 static void end_msi_irq_wo_maskbit(unsigned int vector)
191 {
192 move_native_irq(vector);
193 ack_APIC_irq();
194 }
195
196 static void end_msi_irq_w_maskbit(unsigned int vector)
197 {
198 move_native_irq(vector);
199 unmask_MSI_irq(vector);
200 ack_APIC_irq();
201 }
202
203 static void do_nothing(unsigned int vector)
204 {
205 }
206
207 /*
208 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
209 * which implement the MSI-X Capability Structure.
210 */
211 static struct hw_interrupt_type msix_irq_type = {
212 .typename = "PCI-MSI-X",
213 .startup = startup_msi_irq_w_maskbit,
214 .shutdown = shutdown_msi_irq,
215 .enable = unmask_MSI_irq,
216 .disable = mask_MSI_irq,
217 .ack = mask_MSI_irq,
218 .end = end_msi_irq_w_maskbit,
219 .set_affinity = set_msi_affinity
220 };
221
222 /*
223 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
224 * which implement the MSI Capability Structure with
225 * Mask-and-Pending Bits.
226 */
227 static struct hw_interrupt_type msi_irq_w_maskbit_type = {
228 .typename = "PCI-MSI",
229 .startup = startup_msi_irq_w_maskbit,
230 .shutdown = shutdown_msi_irq,
231 .enable = unmask_MSI_irq,
232 .disable = mask_MSI_irq,
233 .ack = mask_MSI_irq,
234 .end = end_msi_irq_w_maskbit,
235 .set_affinity = set_msi_affinity
236 };
237
238 /*
239 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
240 * which implement the MSI Capability Structure without
241 * Mask-and-Pending Bits.
242 */
243 static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
244 .typename = "PCI-MSI",
245 .startup = startup_msi_irq_wo_maskbit,
246 .shutdown = shutdown_msi_irq,
247 .enable = do_nothing,
248 .disable = do_nothing,
249 .ack = do_nothing,
250 .end = end_msi_irq_wo_maskbit,
251 .set_affinity = set_msi_affinity
252 };
253
254 static void msi_data_init(struct msg_data *msi_data,
255 unsigned int vector)
256 {
257 memset(msi_data, 0, sizeof(struct msg_data));
258 msi_data->vector = (u8)vector;
259 msi_data->delivery_mode = MSI_DELIVERY_MODE;
260 msi_data->level = MSI_LEVEL_MODE;
261 msi_data->trigger = MSI_TRIGGER_MODE;
262 }
263
264 static void msi_address_init(struct msg_address *msi_address)
265 {
266 unsigned int dest_id;
267 unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU);
268
269 memset(msi_address, 0, sizeof(struct msg_address));
270 msi_address->hi_address = (u32)0;
271 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
272 msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE;
273 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
274 msi_address->lo_address.u.dest_id = dest_id;
275 msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT);
276 }
277
278 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
279 static int assign_msi_vector(void)
280 {
281 static int new_vector_avail = 1;
282 int vector;
283 unsigned long flags;
284
285 /*
286 * msi_lock is provided to ensure that successful allocation of MSI
287 * vector is assigned unique among drivers.
288 */
289 spin_lock_irqsave(&msi_lock, flags);
290
291 if (!new_vector_avail) {
292 int free_vector = 0;
293
294 /*
295 * vector_irq[] = -1 indicates that this specific vector is:
296 * - assigned for MSI (since MSI have no associated IRQ) or
297 * - assigned for legacy if less than 16, or
298 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
299 * vector_irq[] = 0 indicates that this vector, previously
300 * assigned for MSI, is freed by hotplug removed operations.
301 * This vector will be reused for any subsequent hotplug added
302 * operations.
303 * vector_irq[] > 0 indicates that this vector is assigned for
304 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
305 * vector-to-IOxAPIC IRQ mapping.
306 */
307 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
308 if (vector_irq[vector] != 0)
309 continue;
310 free_vector = vector;
311 if (!msi_desc[vector])
312 break;
313 else
314 continue;
315 }
316 if (!free_vector) {
317 spin_unlock_irqrestore(&msi_lock, flags);
318 return -EBUSY;
319 }
320 vector_irq[free_vector] = -1;
321 nr_released_vectors--;
322 spin_unlock_irqrestore(&msi_lock, flags);
323 if (msi_desc[free_vector] != NULL) {
324 struct pci_dev *dev;
325 int tail;
326
327 /* free all linked vectors before re-assign */
328 do {
329 spin_lock_irqsave(&msi_lock, flags);
330 dev = msi_desc[free_vector]->dev;
331 tail = msi_desc[free_vector]->link.tail;
332 spin_unlock_irqrestore(&msi_lock, flags);
333 msi_free_vector(dev, tail, 1);
334 } while (free_vector != tail);
335 }
336
337 return free_vector;
338 }
339 vector = assign_irq_vector(AUTO_ASSIGN);
340 last_alloc_vector = vector;
341 if (vector == LAST_DEVICE_VECTOR)
342 new_vector_avail = 0;
343
344 spin_unlock_irqrestore(&msi_lock, flags);
345 return vector;
346 }
347
348 static int get_new_vector(void)
349 {
350 int vector = assign_msi_vector();
351
352 if (vector > 0)
353 set_intr_gate(vector, interrupt[vector]);
354
355 return vector;
356 }
357
358 static int msi_init(void)
359 {
360 static int status = -ENOMEM;
361
362 if (!status)
363 return status;
364
365 if (pci_msi_quirk) {
366 pci_msi_enable = 0;
367 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
368 status = -EINVAL;
369 return status;
370 }
371
372 status = msi_cache_init();
373 if (status < 0) {
374 pci_msi_enable = 0;
375 printk(KERN_WARNING "PCI: MSI cache init failed\n");
376 return status;
377 }
378 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN);
379 if (last_alloc_vector < 0) {
380 pci_msi_enable = 0;
381 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n");
382 status = -EBUSY;
383 return status;
384 }
385 vector_irq[last_alloc_vector] = 0;
386 nr_released_vectors++;
387
388 return status;
389 }
390
391 static int get_msi_vector(struct pci_dev *dev)
392 {
393 return get_new_vector();
394 }
395
396 static struct msi_desc* alloc_msi_entry(void)
397 {
398 struct msi_desc *entry;
399
400 entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
401 if (!entry)
402 return NULL;
403
404 memset(entry, 0, sizeof(struct msi_desc));
405 entry->link.tail = entry->link.head = 0; /* single message */
406 entry->dev = NULL;
407
408 return entry;
409 }
410
411 static void attach_msi_entry(struct msi_desc *entry, int vector)
412 {
413 unsigned long flags;
414
415 spin_lock_irqsave(&msi_lock, flags);
416 msi_desc[vector] = entry;
417 spin_unlock_irqrestore(&msi_lock, flags);
418 }
419
420 static void irq_handler_init(int cap_id, int pos, int mask)
421 {
422 unsigned long flags;
423
424 spin_lock_irqsave(&irq_desc[pos].lock, flags);
425 if (cap_id == PCI_CAP_ID_MSIX)
426 irq_desc[pos].handler = &msix_irq_type;
427 else {
428 if (!mask)
429 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
430 else
431 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
432 }
433 spin_unlock_irqrestore(&irq_desc[pos].lock, flags);
434 }
435
436 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
437 {
438 u16 control;
439
440 pci_read_config_word(dev, msi_control_reg(pos), &control);
441 if (type == PCI_CAP_ID_MSI) {
442 /* Set enabled bits to single MSI & enable MSI_enable bit */
443 msi_enable(control, 1);
444 pci_write_config_word(dev, msi_control_reg(pos), control);
445 } else {
446 msix_enable(control);
447 pci_write_config_word(dev, msi_control_reg(pos), control);
448 }
449 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
450 /* PCI Express Endpoint device detected */
451 pci_intx(dev, 0); /* disable intx */
452 }
453 }
454
455 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
456 {
457 u16 control;
458
459 pci_read_config_word(dev, msi_control_reg(pos), &control);
460 if (type == PCI_CAP_ID_MSI) {
461 /* Set enabled bits to single MSI & enable MSI_enable bit */
462 msi_disable(control);
463 pci_write_config_word(dev, msi_control_reg(pos), control);
464 } else {
465 msix_disable(control);
466 pci_write_config_word(dev, msi_control_reg(pos), control);
467 }
468 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
469 /* PCI Express Endpoint device detected */
470 pci_intx(dev, 1); /* enable intx */
471 }
472 }
473
474 static int msi_lookup_vector(struct pci_dev *dev, int type)
475 {
476 int vector;
477 unsigned long flags;
478
479 spin_lock_irqsave(&msi_lock, flags);
480 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
481 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
482 msi_desc[vector]->msi_attrib.type != type ||
483 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
484 continue;
485 spin_unlock_irqrestore(&msi_lock, flags);
486 /* This pre-assigned MSI vector for this device
487 already exits. Override dev->irq with this vector */
488 dev->irq = vector;
489 return 0;
490 }
491 spin_unlock_irqrestore(&msi_lock, flags);
492
493 return -EACCES;
494 }
495
496 void pci_scan_msi_device(struct pci_dev *dev)
497 {
498 if (!dev)
499 return;
500
501 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0)
502 nr_msix_devices++;
503 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
504 nr_reserved_vectors++;
505 }
506
507 /**
508 * msi_capability_init - configure device's MSI capability structure
509 * @dev: pointer to the pci_dev data structure of MSI device function
510 *
511 * Setup the MSI capability structure of device function with a single
512 * MSI vector, regardless of device function is capable of handling
513 * multiple messages. A return of zero indicates the successful setup
514 * of an entry zero with the new MSI vector or non-zero for otherwise.
515 **/
516 static int msi_capability_init(struct pci_dev *dev)
517 {
518 struct msi_desc *entry;
519 struct msg_address address;
520 struct msg_data data;
521 int pos, vector;
522 u16 control;
523
524 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
525 pci_read_config_word(dev, msi_control_reg(pos), &control);
526 /* MSI Entry Initialization */
527 entry = alloc_msi_entry();
528 if (!entry)
529 return -ENOMEM;
530
531 vector = get_msi_vector(dev);
532 if (vector < 0) {
533 kmem_cache_free(msi_cachep, entry);
534 return -EBUSY;
535 }
536 entry->link.head = vector;
537 entry->link.tail = vector;
538 entry->msi_attrib.type = PCI_CAP_ID_MSI;
539 entry->msi_attrib.state = 0; /* Mark it not active */
540 entry->msi_attrib.entry_nr = 0;
541 entry->msi_attrib.maskbit = is_mask_bit_support(control);
542 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */
543 dev->irq = vector;
544 entry->dev = dev;
545 if (is_mask_bit_support(control)) {
546 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
547 is_64bit_address(control));
548 }
549 /* Replace with MSI handler */
550 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
551 /* Configure MSI capability structure */
552 msi_address_init(&address);
553 msi_data_init(&data, vector);
554 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
555 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
556 pci_write_config_dword(dev, msi_lower_address_reg(pos),
557 address.lo_address.value);
558 if (is_64bit_address(control)) {
559 pci_write_config_dword(dev,
560 msi_upper_address_reg(pos), address.hi_address);
561 pci_write_config_word(dev,
562 msi_data_reg(pos, 1), *((u32*)&data));
563 } else
564 pci_write_config_word(dev,
565 msi_data_reg(pos, 0), *((u32*)&data));
566 if (entry->msi_attrib.maskbit) {
567 unsigned int maskbits, temp;
568 /* All MSIs are unmasked by default, Mask them all */
569 pci_read_config_dword(dev,
570 msi_mask_bits_reg(pos, is_64bit_address(control)),
571 &maskbits);
572 temp = (1 << multi_msi_capable(control));
573 temp = ((temp - 1) & ~temp);
574 maskbits |= temp;
575 pci_write_config_dword(dev,
576 msi_mask_bits_reg(pos, is_64bit_address(control)),
577 maskbits);
578 }
579 attach_msi_entry(entry, vector);
580 /* Set MSI enabled bits */
581 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
582
583 return 0;
584 }
585
586 /**
587 * msix_capability_init - configure device's MSI-X capability
588 * @dev: pointer to the pci_dev data structure of MSI-X device function
589 * @entries: pointer to an array of struct msix_entry entries
590 * @nvec: number of @entries
591 *
592 * Setup the MSI-X capability structure of device function with a
593 * single MSI-X vector. A return of zero indicates the successful setup of
594 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
595 **/
596 static int msix_capability_init(struct pci_dev *dev,
597 struct msix_entry *entries, int nvec)
598 {
599 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
600 struct msg_address address;
601 struct msg_data data;
602 int vector, pos, i, j, nr_entries, temp = 0;
603 u32 phys_addr, table_offset;
604 u16 control;
605 u8 bir;
606 void __iomem *base;
607
608 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
609 /* Request & Map MSI-X table region */
610 pci_read_config_word(dev, msi_control_reg(pos), &control);
611 nr_entries = multi_msix_capable(control);
612 pci_read_config_dword(dev, msix_table_offset_reg(pos),
613 &table_offset);
614 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
615 phys_addr = pci_resource_start (dev, bir);
616 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
617 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
618 if (base == NULL)
619 return -ENOMEM;
620
621 /* MSI-X Table Initialization */
622 for (i = 0; i < nvec; i++) {
623 entry = alloc_msi_entry();
624 if (!entry)
625 break;
626 vector = get_msi_vector(dev);
627 if (vector < 0)
628 break;
629
630 j = entries[i].entry;
631 entries[i].vector = vector;
632 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
633 entry->msi_attrib.state = 0; /* Mark it not active */
634 entry->msi_attrib.entry_nr = j;
635 entry->msi_attrib.maskbit = 1;
636 entry->msi_attrib.default_vector = dev->irq;
637 entry->dev = dev;
638 entry->mask_base = base;
639 if (!head) {
640 entry->link.head = vector;
641 entry->link.tail = vector;
642 head = entry;
643 } else {
644 entry->link.head = temp;
645 entry->link.tail = tail->link.tail;
646 tail->link.tail = vector;
647 head->link.head = vector;
648 }
649 temp = vector;
650 tail = entry;
651 /* Replace with MSI-X handler */
652 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
653 /* Configure MSI-X capability structure */
654 msi_address_init(&address);
655 msi_data_init(&data, vector);
656 entry->msi_attrib.current_cpu =
657 ((address.lo_address.u.dest_id >>
658 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
659 writel(address.lo_address.value,
660 base + j * PCI_MSIX_ENTRY_SIZE +
661 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
662 writel(address.hi_address,
663 base + j * PCI_MSIX_ENTRY_SIZE +
664 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
665 writel(*(u32*)&data,
666 base + j * PCI_MSIX_ENTRY_SIZE +
667 PCI_MSIX_ENTRY_DATA_OFFSET);
668 attach_msi_entry(entry, vector);
669 }
670 if (i != nvec) {
671 i--;
672 for (; i >= 0; i--) {
673 vector = (entries + i)->vector;
674 msi_free_vector(dev, vector, 0);
675 (entries + i)->vector = 0;
676 }
677 return -EBUSY;
678 }
679 /* Set MSI-X enabled bits */
680 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
681
682 return 0;
683 }
684
685 /**
686 * pci_enable_msi - configure device's MSI capability structure
687 * @dev: pointer to the pci_dev data structure of MSI device function
688 *
689 * Setup the MSI capability structure of device function with
690 * a single MSI vector upon its software driver call to request for
691 * MSI mode enabled on its hardware device function. A return of zero
692 * indicates the successful setup of an entry zero with the new MSI
693 * vector or non-zero for otherwise.
694 **/
695 int pci_enable_msi(struct pci_dev* dev)
696 {
697 int pos, temp, status = -EINVAL;
698 u16 control;
699
700 if (!pci_msi_enable || !dev)
701 return status;
702
703 if (dev->no_msi)
704 return status;
705
706 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
707 return -EINVAL;
708
709 temp = dev->irq;
710
711 status = msi_init();
712 if (status < 0)
713 return status;
714
715 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
716 if (!pos)
717 return -EINVAL;
718
719 pci_read_config_word(dev, msi_control_reg(pos), &control);
720 if (control & PCI_MSI_FLAGS_ENABLE)
721 return 0; /* Already in MSI mode */
722
723 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
724 /* Lookup Sucess */
725 unsigned long flags;
726
727 spin_lock_irqsave(&msi_lock, flags);
728 if (!vector_irq[dev->irq]) {
729 msi_desc[dev->irq]->msi_attrib.state = 0;
730 vector_irq[dev->irq] = -1;
731 nr_released_vectors--;
732 spin_unlock_irqrestore(&msi_lock, flags);
733 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
734 return 0;
735 }
736 spin_unlock_irqrestore(&msi_lock, flags);
737 dev->irq = temp;
738 }
739 /* Check whether driver already requested for MSI-X vectors */
740 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
741 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
742 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
743 "Device already has MSI-X vectors assigned\n",
744 pci_name(dev));
745 dev->irq = temp;
746 return -EINVAL;
747 }
748 status = msi_capability_init(dev);
749 if (!status) {
750 if (!pos)
751 nr_reserved_vectors--; /* Only MSI capable */
752 else if (nr_msix_devices > 0)
753 nr_msix_devices--; /* Both MSI and MSI-X capable,
754 but choose enabling MSI */
755 }
756
757 return status;
758 }
759
760 void pci_disable_msi(struct pci_dev* dev)
761 {
762 struct msi_desc *entry;
763 int pos, default_vector;
764 u16 control;
765 unsigned long flags;
766
767 if (!dev)
768 return;
769 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
770 if (!pos)
771 return;
772
773 pci_read_config_word(dev, msi_control_reg(pos), &control);
774 if (!(control & PCI_MSI_FLAGS_ENABLE))
775 return;
776
777 spin_lock_irqsave(&msi_lock, flags);
778 entry = msi_desc[dev->irq];
779 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
780 spin_unlock_irqrestore(&msi_lock, flags);
781 return;
782 }
783 if (entry->msi_attrib.state) {
784 spin_unlock_irqrestore(&msi_lock, flags);
785 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
786 "free_irq() on MSI vector %d\n",
787 pci_name(dev), dev->irq);
788 BUG_ON(entry->msi_attrib.state > 0);
789 } else {
790 vector_irq[dev->irq] = 0; /* free it */
791 nr_released_vectors++;
792 default_vector = entry->msi_attrib.default_vector;
793 spin_unlock_irqrestore(&msi_lock, flags);
794 /* Restore dev->irq to its default pin-assertion vector */
795 dev->irq = default_vector;
796 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
797 PCI_CAP_ID_MSI);
798 }
799 }
800
801 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign)
802 {
803 struct msi_desc *entry;
804 int head, entry_nr, type;
805 void __iomem *base;
806 unsigned long flags;
807
808 spin_lock_irqsave(&msi_lock, flags);
809 entry = msi_desc[vector];
810 if (!entry || entry->dev != dev) {
811 spin_unlock_irqrestore(&msi_lock, flags);
812 return -EINVAL;
813 }
814 type = entry->msi_attrib.type;
815 entry_nr = entry->msi_attrib.entry_nr;
816 head = entry->link.head;
817 base = entry->mask_base;
818 msi_desc[entry->link.head]->link.tail = entry->link.tail;
819 msi_desc[entry->link.tail]->link.head = entry->link.head;
820 entry->dev = NULL;
821 if (!reassign) {
822 vector_irq[vector] = 0;
823 nr_released_vectors++;
824 }
825 msi_desc[vector] = NULL;
826 spin_unlock_irqrestore(&msi_lock, flags);
827
828 kmem_cache_free(msi_cachep, entry);
829
830 if (type == PCI_CAP_ID_MSIX) {
831 if (!reassign)
832 writel(1, base +
833 entry_nr * PCI_MSIX_ENTRY_SIZE +
834 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
835
836 if (head == vector) {
837 /*
838 * Detect last MSI-X vector to be released.
839 * Release the MSI-X memory-mapped table.
840 */
841 int pos, nr_entries;
842 u32 phys_addr, table_offset;
843 u16 control;
844 u8 bir;
845
846 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
847 pci_read_config_word(dev, msi_control_reg(pos),
848 &control);
849 nr_entries = multi_msix_capable(control);
850 pci_read_config_dword(dev, msix_table_offset_reg(pos),
851 &table_offset);
852 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
853 phys_addr = pci_resource_start (dev, bir);
854 phys_addr += (u32)(table_offset &
855 ~PCI_MSIX_FLAGS_BIRMASK);
856 iounmap(base);
857 }
858 }
859
860 return 0;
861 }
862
863 static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec)
864 {
865 int vector = head, tail = 0;
866 int i, j = 0, nr_entries = 0;
867 void __iomem *base;
868 unsigned long flags;
869
870 spin_lock_irqsave(&msi_lock, flags);
871 while (head != tail) {
872 nr_entries++;
873 tail = msi_desc[vector]->link.tail;
874 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr)
875 j = vector;
876 vector = tail;
877 }
878 if (*nvec > nr_entries) {
879 spin_unlock_irqrestore(&msi_lock, flags);
880 *nvec = nr_entries;
881 return -EINVAL;
882 }
883 vector = ((j > 0) ? j : head);
884 for (i = 0; i < *nvec; i++) {
885 j = msi_desc[vector]->msi_attrib.entry_nr;
886 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */
887 vector_irq[vector] = -1; /* Mark it busy */
888 nr_released_vectors--;
889 entries[i].vector = vector;
890 if (j != (entries + i)->entry) {
891 base = msi_desc[vector]->mask_base;
892 msi_desc[vector]->msi_attrib.entry_nr =
893 (entries + i)->entry;
894 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
895 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base +
896 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
897 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
898 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
899 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base +
900 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
901 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
902 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE +
903 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector,
904 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE +
905 PCI_MSIX_ENTRY_DATA_OFFSET);
906 }
907 vector = msi_desc[vector]->link.tail;
908 }
909 spin_unlock_irqrestore(&msi_lock, flags);
910
911 return 0;
912 }
913
914 /**
915 * pci_enable_msix - configure device's MSI-X capability structure
916 * @dev: pointer to the pci_dev data structure of MSI-X device function
917 * @entries: pointer to an array of MSI-X entries
918 * @nvec: number of MSI-X vectors requested for allocation by device driver
919 *
920 * Setup the MSI-X capability structure of device function with the number
921 * of requested vectors upon its software driver call to request for
922 * MSI-X mode enabled on its hardware device function. A return of zero
923 * indicates the successful configuration of MSI-X capability structure
924 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
925 * Or a return of > 0 indicates that driver request is exceeding the number
926 * of vectors available. Driver should use the returned value to re-send
927 * its request.
928 **/
929 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
930 {
931 int status, pos, nr_entries, free_vectors;
932 int i, j, temp;
933 u16 control;
934 unsigned long flags;
935
936 if (!pci_msi_enable || !dev || !entries)
937 return -EINVAL;
938
939 status = msi_init();
940 if (status < 0)
941 return status;
942
943 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
944 if (!pos)
945 return -EINVAL;
946
947 pci_read_config_word(dev, msi_control_reg(pos), &control);
948 if (control & PCI_MSIX_FLAGS_ENABLE)
949 return -EINVAL; /* Already in MSI-X mode */
950
951 nr_entries = multi_msix_capable(control);
952 if (nvec > nr_entries)
953 return -EINVAL;
954
955 /* Check for any invalid entries */
956 for (i = 0; i < nvec; i++) {
957 if (entries[i].entry >= nr_entries)
958 return -EINVAL; /* invalid entry */
959 for (j = i + 1; j < nvec; j++) {
960 if (entries[i].entry == entries[j].entry)
961 return -EINVAL; /* duplicate entry */
962 }
963 }
964 temp = dev->irq;
965 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
966 /* Lookup Sucess */
967 nr_entries = nvec;
968 /* Reroute MSI-X table */
969 if (reroute_msix_table(dev->irq, entries, &nr_entries)) {
970 /* #requested > #previous-assigned */
971 dev->irq = temp;
972 return nr_entries;
973 }
974 dev->irq = temp;
975 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
976 return 0;
977 }
978 /* Check whether driver already requested for MSI vector */
979 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
980 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
981 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
982 "Device already has an MSI vector assigned\n",
983 pci_name(dev));
984 dev->irq = temp;
985 return -EINVAL;
986 }
987
988 spin_lock_irqsave(&msi_lock, flags);
989 /*
990 * msi_lock is provided to ensure that enough vectors resources are
991 * available before granting.
992 */
993 free_vectors = pci_vector_resources(last_alloc_vector,
994 nr_released_vectors);
995 /* Ensure that each MSI/MSI-X device has one vector reserved by
996 default to avoid any MSI-X driver to take all available
997 resources */
998 free_vectors -= nr_reserved_vectors;
999 /* Find the average of free vectors among MSI-X devices */
1000 if (nr_msix_devices > 0)
1001 free_vectors /= nr_msix_devices;
1002 spin_unlock_irqrestore(&msi_lock, flags);
1003
1004 if (nvec > free_vectors) {
1005 if (free_vectors > 0)
1006 return free_vectors;
1007 else
1008 return -EBUSY;
1009 }
1010
1011 status = msix_capability_init(dev, entries, nvec);
1012 if (!status && nr_msix_devices > 0)
1013 nr_msix_devices--;
1014
1015 return status;
1016 }
1017
1018 void pci_disable_msix(struct pci_dev* dev)
1019 {
1020 int pos, temp;
1021 u16 control;
1022
1023 if (!dev)
1024 return;
1025
1026 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1027 if (!pos)
1028 return;
1029
1030 pci_read_config_word(dev, msi_control_reg(pos), &control);
1031 if (!(control & PCI_MSIX_FLAGS_ENABLE))
1032 return;
1033
1034 temp = dev->irq;
1035 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1036 int state, vector, head, tail = 0, warning = 0;
1037 unsigned long flags;
1038
1039 vector = head = dev->irq;
1040 spin_lock_irqsave(&msi_lock, flags);
1041 while (head != tail) {
1042 state = msi_desc[vector]->msi_attrib.state;
1043 if (state)
1044 warning = 1;
1045 else {
1046 vector_irq[vector] = 0; /* free it */
1047 nr_released_vectors++;
1048 }
1049 tail = msi_desc[vector]->link.tail;
1050 vector = tail;
1051 }
1052 spin_unlock_irqrestore(&msi_lock, flags);
1053 if (warning) {
1054 dev->irq = temp;
1055 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
1056 "free_irq() on all MSI-X vectors\n",
1057 pci_name(dev));
1058 BUG_ON(warning > 0);
1059 } else {
1060 dev->irq = temp;
1061 disable_msi_mode(dev,
1062 pci_find_capability(dev, PCI_CAP_ID_MSIX),
1063 PCI_CAP_ID_MSIX);
1064
1065 }
1066 }
1067 }
1068
1069 /**
1070 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
1071 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1072 *
1073 * Being called during hotplug remove, from which the device function
1074 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
1075 * allocated for this device function, are reclaimed to unused state,
1076 * which may be used later on.
1077 **/
1078 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
1079 {
1080 int state, pos, temp;
1081 unsigned long flags;
1082
1083 if (!pci_msi_enable || !dev)
1084 return;
1085
1086 temp = dev->irq; /* Save IOAPIC IRQ */
1087 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1088 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
1089 spin_lock_irqsave(&msi_lock, flags);
1090 state = msi_desc[dev->irq]->msi_attrib.state;
1091 spin_unlock_irqrestore(&msi_lock, flags);
1092 if (state) {
1093 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1094 "called without free_irq() on MSI vector %d\n",
1095 pci_name(dev), dev->irq);
1096 BUG_ON(state > 0);
1097 } else /* Release MSI vector assigned to this device */
1098 msi_free_vector(dev, dev->irq, 0);
1099 dev->irq = temp; /* Restore IOAPIC IRQ */
1100 }
1101 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1102 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1103 int vector, head, tail = 0, warning = 0;
1104 void __iomem *base = NULL;
1105
1106 vector = head = dev->irq;
1107 while (head != tail) {
1108 spin_lock_irqsave(&msi_lock, flags);
1109 state = msi_desc[vector]->msi_attrib.state;
1110 tail = msi_desc[vector]->link.tail;
1111 base = msi_desc[vector]->mask_base;
1112 spin_unlock_irqrestore(&msi_lock, flags);
1113 if (state)
1114 warning = 1;
1115 else if (vector != head) /* Release MSI-X vector */
1116 msi_free_vector(dev, vector, 0);
1117 vector = tail;
1118 }
1119 msi_free_vector(dev, vector, 0);
1120 if (warning) {
1121 /* Force to release the MSI-X memory-mapped table */
1122 u32 phys_addr, table_offset;
1123 u16 control;
1124 u8 bir;
1125
1126 pci_read_config_word(dev, msi_control_reg(pos),
1127 &control);
1128 pci_read_config_dword(dev, msix_table_offset_reg(pos),
1129 &table_offset);
1130 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
1131 phys_addr = pci_resource_start (dev, bir);
1132 phys_addr += (u32)(table_offset &
1133 ~PCI_MSIX_FLAGS_BIRMASK);
1134 iounmap(base);
1135 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1136 "called without free_irq() on all MSI-X vectors\n",
1137 pci_name(dev));
1138 BUG_ON(warning > 0);
1139 }
1140 dev->irq = temp; /* Restore IOAPIC IRQ */
1141 }
1142 }
1143
1144 EXPORT_SYMBOL(pci_enable_msi);
1145 EXPORT_SYMBOL(pci_disable_msi);
1146 EXPORT_SYMBOL(pci_enable_msix);
1147 EXPORT_SYMBOL(pci_disable_msix);
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