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[libata] Remove ->irq_ack() hook, and ata_dummy_irq_on()
[linux-2.6/verdex.git] / drivers / ata / ata_piix.c
blob68bc0ae671c570ed3262669fce61e27d1cb5aeac
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 /* ICH up to UDMA 133 is not supported */
127 ich5_sata = 5,
128 ich6_sata = 6,
129 ich6_sata_ahci = 7,
130 ich6m_sata_ahci = 8,
131 ich8_sata_ahci = 9,
132 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
133 tolapai_sata_ahci = 11,
134
135 /* constants for mapping table */
136 P0 = 0, /* port 0 */
137 P1 = 1, /* port 1 */
138 P2 = 2, /* port 2 */
139 P3 = 3, /* port 3 */
140 IDE = -1, /* IDE */
141 NA = -2, /* not avaliable */
142 RV = -3, /* reserved */
143
144 PIIX_AHCI_DEVICE = 6,
145
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
148 };
149
150 struct piix_map_db {
151 const u32 mask;
152 const u16 port_enable;
153 const int map[][4];
154 };
155
156 struct piix_host_priv {
157 const int *map;
158 };
159
160 static int piix_init_one (struct pci_dev *pdev,
161 const struct pci_device_id *ent);
162 static void piix_pata_error_handler(struct ata_port *ap);
163 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
164 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
165 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
166 static int ich_pata_cable_detect(struct ata_port *ap);
167 #ifdef CONFIG_PM
168 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
169 static int piix_pci_device_resume(struct pci_dev *pdev);
170 #endif
171
172 static unsigned int in_module_init = 1;
173
174 static const struct pci_device_id piix_pci_tbl[] = {
175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
219 /* 82801EB (ICH5) */
220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
221 /* 82801EB (ICH5) */
222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
225 /* 6300ESB pretending RAID */
226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
227 /* 82801FB/FW (ICH6/ICH6W) */
228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
229 /* 82801FR/FRW (ICH6R/ICH6RW) */
230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
239 /* SATA Controller 1 IDE (ICH8) */
240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 /* SATA Controller 2 IDE (ICH8) */
242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
243 /* Mobile SATA Controller IDE (ICH8M) */
244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
251 /* SATA Controller IDE (ICH9M) */
252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
253 /* SATA Controller IDE (ICH9M) */
254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
259
260 { } /* terminate list */
261 };
262
263 static struct pci_driver piix_pci_driver = {
264 .name = DRV_NAME,
265 .id_table = piix_pci_tbl,
266 .probe = piix_init_one,
267 .remove = ata_pci_remove_one,
268 #ifdef CONFIG_PM
269 .suspend = piix_pci_device_suspend,
270 .resume = piix_pci_device_resume,
271 #endif
272 };
273
274 static struct scsi_host_template piix_sht = {
275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
279 .can_queue = ATA_DEF_QUEUE,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = LIBATA_MAX_PRD,
282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = ATA_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
288 .slave_destroy = ata_scsi_slave_destroy,
289 .bios_param = ata_std_bios_param,
290 };
291
292 static const struct ata_port_operations piix_pata_ops = {
293 .port_disable = ata_port_disable,
294 .set_piomode = piix_set_piomode,
295 .set_dmamode = piix_set_dmamode,
296 .mode_filter = ata_pci_default_filter,
297
298 .tf_load = ata_tf_load,
299 .tf_read = ata_tf_read,
300 .check_status = ata_check_status,
301 .exec_command = ata_exec_command,
302 .dev_select = ata_std_dev_select,
303
304 .bmdma_setup = ata_bmdma_setup,
305 .bmdma_start = ata_bmdma_start,
306 .bmdma_stop = ata_bmdma_stop,
307 .bmdma_status = ata_bmdma_status,
308 .qc_prep = ata_qc_prep,
309 .qc_issue = ata_qc_issue_prot,
310 .data_xfer = ata_data_xfer,
311
312 .freeze = ata_bmdma_freeze,
313 .thaw = ata_bmdma_thaw,
314 .error_handler = piix_pata_error_handler,
315 .post_internal_cmd = ata_bmdma_post_internal_cmd,
316 .cable_detect = ata_cable_40wire,
317
318 .irq_handler = ata_interrupt,
319 .irq_clear = ata_bmdma_irq_clear,
320 .irq_on = ata_irq_on,
321
322 .port_start = ata_port_start,
323 };
324
325 static const struct ata_port_operations ich_pata_ops = {
326 .port_disable = ata_port_disable,
327 .set_piomode = piix_set_piomode,
328 .set_dmamode = ich_set_dmamode,
329 .mode_filter = ata_pci_default_filter,
330
331 .tf_load = ata_tf_load,
332 .tf_read = ata_tf_read,
333 .check_status = ata_check_status,
334 .exec_command = ata_exec_command,
335 .dev_select = ata_std_dev_select,
336
337 .bmdma_setup = ata_bmdma_setup,
338 .bmdma_start = ata_bmdma_start,
339 .bmdma_stop = ata_bmdma_stop,
340 .bmdma_status = ata_bmdma_status,
341 .qc_prep = ata_qc_prep,
342 .qc_issue = ata_qc_issue_prot,
343 .data_xfer = ata_data_xfer,
344
345 .freeze = ata_bmdma_freeze,
346 .thaw = ata_bmdma_thaw,
347 .error_handler = piix_pata_error_handler,
348 .post_internal_cmd = ata_bmdma_post_internal_cmd,
349 .cable_detect = ich_pata_cable_detect,
350
351 .irq_handler = ata_interrupt,
352 .irq_clear = ata_bmdma_irq_clear,
353 .irq_on = ata_irq_on,
354
355 .port_start = ata_port_start,
356 };
357
358 static const struct ata_port_operations piix_sata_ops = {
359 .port_disable = ata_port_disable,
360
361 .tf_load = ata_tf_load,
362 .tf_read = ata_tf_read,
363 .check_status = ata_check_status,
364 .exec_command = ata_exec_command,
365 .dev_select = ata_std_dev_select,
366
367 .bmdma_setup = ata_bmdma_setup,
368 .bmdma_start = ata_bmdma_start,
369 .bmdma_stop = ata_bmdma_stop,
370 .bmdma_status = ata_bmdma_status,
371 .qc_prep = ata_qc_prep,
372 .qc_issue = ata_qc_issue_prot,
373 .data_xfer = ata_data_xfer,
374
375 .freeze = ata_bmdma_freeze,
376 .thaw = ata_bmdma_thaw,
377 .error_handler = ata_bmdma_error_handler,
378 .post_internal_cmd = ata_bmdma_post_internal_cmd,
379
380 .irq_handler = ata_interrupt,
381 .irq_clear = ata_bmdma_irq_clear,
382 .irq_on = ata_irq_on,
383
384 .port_start = ata_port_start,
385 };
386
387 static const struct piix_map_db ich5_map_db = {
388 .mask = 0x7,
389 .port_enable = 0x3,
390 .map = {
391 /* PM PS SM SS MAP */
392 { P0, NA, P1, NA }, /* 000b */
393 { P1, NA, P0, NA }, /* 001b */
394 { RV, RV, RV, RV },
395 { RV, RV, RV, RV },
396 { P0, P1, IDE, IDE }, /* 100b */
397 { P1, P0, IDE, IDE }, /* 101b */
398 { IDE, IDE, P0, P1 }, /* 110b */
399 { IDE, IDE, P1, P0 }, /* 111b */
400 },
401 };
402
403 static const struct piix_map_db ich6_map_db = {
404 .mask = 0x3,
405 .port_enable = 0xf,
406 .map = {
407 /* PM PS SM SS MAP */
408 { P0, P2, P1, P3 }, /* 00b */
409 { IDE, IDE, P1, P3 }, /* 01b */
410 { P0, P2, IDE, IDE }, /* 10b */
411 { RV, RV, RV, RV },
412 },
413 };
414
415 static const struct piix_map_db ich6m_map_db = {
416 .mask = 0x3,
417 .port_enable = 0x5,
418
419 /* Map 01b isn't specified in the doc but some notebooks use
420 * it anyway. MAP 01b have been spotted on both ICH6M and
421 * ICH7M.
422 */
423 .map = {
424 /* PM PS SM SS MAP */
425 { P0, P2, NA, NA }, /* 00b */
426 { IDE, IDE, P1, P3 }, /* 01b */
427 { P0, P2, IDE, IDE }, /* 10b */
428 { RV, RV, RV, RV },
429 },
430 };
431
432 static const struct piix_map_db ich8_map_db = {
433 .mask = 0x3,
434 .port_enable = 0x3,
435 .map = {
436 /* PM PS SM SS MAP */
437 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
438 { RV, RV, RV, RV },
439 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
440 { RV, RV, RV, RV },
441 },
442 };
443
444 static const struct piix_map_db tolapai_map_db = {
445 .mask = 0x3,
446 .port_enable = 0x3,
447 .map = {
448 /* PM PS SM SS MAP */
449 { P0, NA, P1, NA }, /* 00b */
450 { RV, RV, RV, RV }, /* 01b */
451 { RV, RV, RV, RV }, /* 10b */
452 { RV, RV, RV, RV },
453 },
454 };
455
456 static const struct piix_map_db *piix_map_db_table[] = {
457 [ich5_sata] = &ich5_map_db,
458 [ich6_sata] = &ich6_map_db,
459 [ich6_sata_ahci] = &ich6_map_db,
460 [ich6m_sata_ahci] = &ich6m_map_db,
461 [ich8_sata_ahci] = &ich8_map_db,
462 [tolapai_sata_ahci] = &tolapai_map_db,
463 };
464
465 static struct ata_port_info piix_port_info[] = {
466 /* piix_pata_33: 0: PIIX4 at 33MHz */
467 {
468 .sht = &piix_sht,
469 .flags = PIIX_PATA_FLAGS,
470 .pio_mask = 0x1f, /* pio0-4 */
471 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
472 .udma_mask = ATA_UDMA_MASK_40C,
473 .port_ops = &piix_pata_ops,
474 },
475
476 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
477 {
478 .sht = &piix_sht,
479 .flags = PIIX_PATA_FLAGS,
480 .pio_mask = 0x1f, /* pio 0-4 */
481 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
482 .udma_mask = ATA_UDMA2, /* UDMA33 */
483 .port_ops = &ich_pata_ops,
484 },
485 /* ich_pata_66: 2 ICH controllers up to 66MHz */
486 {
487 .sht = &piix_sht,
488 .flags = PIIX_PATA_FLAGS,
489 .pio_mask = 0x1f, /* pio 0-4 */
490 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
491 .udma_mask = ATA_UDMA4,
492 .port_ops = &ich_pata_ops,
493 },
494
495 /* ich_pata_100: 3 */
496 {
497 .sht = &piix_sht,
498 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
499 .pio_mask = 0x1f, /* pio0-4 */
500 .mwdma_mask = 0x06, /* mwdma1-2 */
501 .udma_mask = ATA_UDMA5, /* udma0-5 */
502 .port_ops = &ich_pata_ops,
503 },
504
505 /* ich_pata_133: 4 - Not supported - */
506 {
507 .sht = &piix_sht,
508 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
509 .pio_mask = 0x1f, /* pio 0-4 */
510 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
511 .udma_mask = ATA_UDMA6, /* UDMA133 */
512 .port_ops = &ich_pata_ops,
513 },
514
515 /* ich5_sata: 5 */
516 {
517 .sht = &piix_sht,
518 .flags = PIIX_SATA_FLAGS,
519 .pio_mask = 0x1f, /* pio0-4 */
520 .mwdma_mask = 0x07, /* mwdma0-2 */
521 .udma_mask = ATA_UDMA6,
522 .port_ops = &piix_sata_ops,
523 },
524
525 /* ich6_sata: 6 */
526 {
527 .sht = &piix_sht,
528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
529 .pio_mask = 0x1f, /* pio0-4 */
530 .mwdma_mask = 0x07, /* mwdma0-2 */
531 .udma_mask = ATA_UDMA6,
532 .port_ops = &piix_sata_ops,
533 },
534
535 /* ich6_sata_ahci: 7 */
536 {
537 .sht = &piix_sht,
538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
539 PIIX_FLAG_AHCI,
540 .pio_mask = 0x1f, /* pio0-4 */
541 .mwdma_mask = 0x07, /* mwdma0-2 */
542 .udma_mask = ATA_UDMA6,
543 .port_ops = &piix_sata_ops,
544 },
545
546 /* ich6m_sata_ahci: 8 */
547 {
548 .sht = &piix_sht,
549 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
550 PIIX_FLAG_AHCI,
551 .pio_mask = 0x1f, /* pio0-4 */
552 .mwdma_mask = 0x07, /* mwdma0-2 */
553 .udma_mask = ATA_UDMA6,
554 .port_ops = &piix_sata_ops,
555 },
556
557 /* ich8_sata_ahci: 9 */
558 {
559 .sht = &piix_sht,
560 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
561 PIIX_FLAG_AHCI,
562 .pio_mask = 0x1f, /* pio0-4 */
563 .mwdma_mask = 0x07, /* mwdma0-2 */
564 .udma_mask = ATA_UDMA6,
565 .port_ops = &piix_sata_ops,
566 },
567
568 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
569 {
570 .sht = &piix_sht,
571 .flags = PIIX_PATA_FLAGS,
572 .pio_mask = 0x1f, /* pio0-4 */
573 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
574 .port_ops = &piix_pata_ops,
575 },
576
577 /* tolapai_sata_ahci: 11: */
578 {
579 .sht = &piix_sht,
580 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
581 PIIX_FLAG_AHCI,
582 .pio_mask = 0x1f, /* pio0-4 */
583 .mwdma_mask = 0x07, /* mwdma0-2 */
584 .udma_mask = ATA_UDMA6,
585 .port_ops = &piix_sata_ops,
586 },
587 };
588
589 static struct pci_bits piix_enable_bits[] = {
590 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
591 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
592 };
593
594 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
595 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
596 MODULE_LICENSE("GPL");
597 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
598 MODULE_VERSION(DRV_VERSION);
599
600 struct ich_laptop {
601 u16 device;
602 u16 subvendor;
603 u16 subdevice;
604 };
605
606 /*
607 * List of laptops that use short cables rather than 80 wire
608 */
609
610 static const struct ich_laptop ich_laptop[] = {
611 /* devid, subvendor, subdev */
612 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
613 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
614 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
615 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
616 /* end marker */
617 { 0, }
618 };
619
620 /**
621 * ich_pata_cable_detect - Probe host controller cable detect info
622 * @ap: Port for which cable detect info is desired
623 *
624 * Read 80c cable indicator from ATA PCI device's PCI config
625 * register. This register is normally set by firmware (BIOS).
626 *
627 * LOCKING:
628 * None (inherited from caller).
629 */
630
631 static int ich_pata_cable_detect(struct ata_port *ap)
632 {
633 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
634 const struct ich_laptop *lap = &ich_laptop[0];
635 u8 tmp, mask;
636
637 /* Check for specials - Acer Aspire 5602WLMi */
638 while (lap->device) {
639 if (lap->device == pdev->device &&
640 lap->subvendor == pdev->subsystem_vendor &&
641 lap->subdevice == pdev->subsystem_device) {
642 return ATA_CBL_PATA40_SHORT;
643 }
644 lap++;
645 }
646
647 /* check BIOS cable detect results */
648 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
649 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
650 if ((tmp & mask) == 0)
651 return ATA_CBL_PATA40;
652 return ATA_CBL_PATA80;
653 }
654
655 /**
656 * piix_pata_prereset - prereset for PATA host controller
657 * @link: Target link
658 * @deadline: deadline jiffies for the operation
659 *
660 * LOCKING:
661 * None (inherited from caller).
662 */
663 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
664 {
665 struct ata_port *ap = link->ap;
666 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
667
668 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
669 return -ENOENT;
670 return ata_std_prereset(link, deadline);
671 }
672
673 static void piix_pata_error_handler(struct ata_port *ap)
674 {
675 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
676 ata_std_postreset);
677 }
678
679 /**
680 * piix_set_piomode - Initialize host controller PATA PIO timings
681 * @ap: Port whose timings we are configuring
682 * @adev: um
683 *
684 * Set PIO mode for device, in host controller PCI config space.
685 *
686 * LOCKING:
687 * None (inherited from caller).
688 */
689
690 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
691 {
692 unsigned int pio = adev->pio_mode - XFER_PIO_0;
693 struct pci_dev *dev = to_pci_dev(ap->host->dev);
694 unsigned int is_slave = (adev->devno != 0);
695 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
696 unsigned int slave_port = 0x44;
697 u16 master_data;
698 u8 slave_data;
699 u8 udma_enable;
700 int control = 0;
701
702 /*
703 * See Intel Document 298600-004 for the timing programing rules
704 * for ICH controllers.
705 */
706
707 static const /* ISP RTC */
708 u8 timings[][2] = { { 0, 0 },
709 { 0, 0 },
710 { 1, 0 },
711 { 2, 1 },
712 { 2, 3 }, };
713
714 if (pio >= 2)
715 control |= 1; /* TIME1 enable */
716 if (ata_pio_need_iordy(adev))
717 control |= 2; /* IE enable */
718
719 /* Intel specifies that the PPE functionality is for disk only */
720 if (adev->class == ATA_DEV_ATA)
721 control |= 4; /* PPE enable */
722
723 /* PIO configuration clears DTE unconditionally. It will be
724 * programmed in set_dmamode which is guaranteed to be called
725 * after set_piomode if any DMA mode is available.
726 */
727 pci_read_config_word(dev, master_port, &master_data);
728 if (is_slave) {
729 /* clear TIME1|IE1|PPE1|DTE1 */
730 master_data &= 0xff0f;
731 /* Enable SITRE (seperate slave timing register) */
732 master_data |= 0x4000;
733 /* enable PPE1, IE1 and TIME1 as needed */
734 master_data |= (control << 4);
735 pci_read_config_byte(dev, slave_port, &slave_data);
736 slave_data &= (ap->port_no ? 0x0f : 0xf0);
737 /* Load the timing nibble for this slave */
738 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
739 << (ap->port_no ? 4 : 0);
740 } else {
741 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
742 master_data &= 0xccf0;
743 /* Enable PPE, IE and TIME as appropriate */
744 master_data |= control;
745 /* load ISP and RCT */
746 master_data |=
747 (timings[pio][0] << 12) |
748 (timings[pio][1] << 8);
749 }
750 pci_write_config_word(dev, master_port, master_data);
751 if (is_slave)
752 pci_write_config_byte(dev, slave_port, slave_data);
753
754 /* Ensure the UDMA bit is off - it will be turned back on if
755 UDMA is selected */
756
757 if (ap->udma_mask) {
758 pci_read_config_byte(dev, 0x48, &udma_enable);
759 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
760 pci_write_config_byte(dev, 0x48, udma_enable);
761 }
762 }
763
764 /**
765 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
766 * @ap: Port whose timings we are configuring
767 * @adev: Drive in question
768 * @udma: udma mode, 0 - 6
769 * @isich: set if the chip is an ICH device
770 *
771 * Set UDMA mode for device, in host controller PCI config space.
772 *
773 * LOCKING:
774 * None (inherited from caller).
775 */
776
777 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
778 {
779 struct pci_dev *dev = to_pci_dev(ap->host->dev);
780 u8 master_port = ap->port_no ? 0x42 : 0x40;
781 u16 master_data;
782 u8 speed = adev->dma_mode;
783 int devid = adev->devno + 2 * ap->port_no;
784 u8 udma_enable = 0;
785
786 static const /* ISP RTC */
787 u8 timings[][2] = { { 0, 0 },
788 { 0, 0 },
789 { 1, 0 },
790 { 2, 1 },
791 { 2, 3 }, };
792
793 pci_read_config_word(dev, master_port, &master_data);
794 if (ap->udma_mask)
795 pci_read_config_byte(dev, 0x48, &udma_enable);
796
797 if (speed >= XFER_UDMA_0) {
798 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
799 u16 udma_timing;
800 u16 ideconf;
801 int u_clock, u_speed;
802
803 /*
804 * UDMA is handled by a combination of clock switching and
805 * selection of dividers
806 *
807 * Handy rule: Odd modes are UDMATIMx 01, even are 02
808 * except UDMA0 which is 00
809 */
810 u_speed = min(2 - (udma & 1), udma);
811 if (udma == 5)
812 u_clock = 0x1000; /* 100Mhz */
813 else if (udma > 2)
814 u_clock = 1; /* 66Mhz */
815 else
816 u_clock = 0; /* 33Mhz */
817
818 udma_enable |= (1 << devid);
819
820 /* Load the CT/RP selection */
821 pci_read_config_word(dev, 0x4A, &udma_timing);
822 udma_timing &= ~(3 << (4 * devid));
823 udma_timing |= u_speed << (4 * devid);
824 pci_write_config_word(dev, 0x4A, udma_timing);
825
826 if (isich) {
827 /* Select a 33/66/100Mhz clock */
828 pci_read_config_word(dev, 0x54, &ideconf);
829 ideconf &= ~(0x1001 << devid);
830 ideconf |= u_clock << devid;
831 /* For ICH or later we should set bit 10 for better
832 performance (WR_PingPong_En) */
833 pci_write_config_word(dev, 0x54, ideconf);
834 }
835 } else {
836 /*
837 * MWDMA is driven by the PIO timings. We must also enable
838 * IORDY unconditionally along with TIME1. PPE has already
839 * been set when the PIO timing was set.
840 */
841 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
842 unsigned int control;
843 u8 slave_data;
844 const unsigned int needed_pio[3] = {
845 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
846 };
847 int pio = needed_pio[mwdma] - XFER_PIO_0;
848
849 control = 3; /* IORDY|TIME1 */
850
851 /* If the drive MWDMA is faster than it can do PIO then
852 we must force PIO into PIO0 */
853
854 if (adev->pio_mode < needed_pio[mwdma])
855 /* Enable DMA timing only */
856 control |= 8; /* PIO cycles in PIO0 */
857
858 if (adev->devno) { /* Slave */
859 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
860 master_data |= control << 4;
861 pci_read_config_byte(dev, 0x44, &slave_data);
862 slave_data &= (ap->port_no ? 0x0f : 0xf0);
863 /* Load the matching timing */
864 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
865 pci_write_config_byte(dev, 0x44, slave_data);
866 } else { /* Master */
867 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
868 and master timing bits */
869 master_data |= control;
870 master_data |=
871 (timings[pio][0] << 12) |
872 (timings[pio][1] << 8);
873 }
874
875 if (ap->udma_mask) {
876 udma_enable &= ~(1 << devid);
877 pci_write_config_word(dev, master_port, master_data);
878 }
879 }
880 /* Don't scribble on 0x48 if the controller does not support UDMA */
881 if (ap->udma_mask)
882 pci_write_config_byte(dev, 0x48, udma_enable);
883 }
884
885 /**
886 * piix_set_dmamode - Initialize host controller PATA DMA timings
887 * @ap: Port whose timings we are configuring
888 * @adev: um
889 *
890 * Set MW/UDMA mode for device, in host controller PCI config space.
891 *
892 * LOCKING:
893 * None (inherited from caller).
894 */
895
896 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
897 {
898 do_pata_set_dmamode(ap, adev, 0);
899 }
900
901 /**
902 * ich_set_dmamode - Initialize host controller PATA DMA timings
903 * @ap: Port whose timings we are configuring
904 * @adev: um
905 *
906 * Set MW/UDMA mode for device, in host controller PCI config space.
907 *
908 * LOCKING:
909 * None (inherited from caller).
910 */
911
912 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
913 {
914 do_pata_set_dmamode(ap, adev, 1);
915 }
916
917 #ifdef CONFIG_PM
918 static int piix_broken_suspend(void)
919 {
920 static const struct dmi_system_id sysids[] = {
921 {
922 .ident = "TECRA M3",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
926 },
927 },
928 {
929 .ident = "TECRA M5",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
932 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
933 },
934 },
935 {
936 .ident = "TECRA M7",
937 .matches = {
938 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
939 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
940 },
941 },
942 {
943 .ident = "Satellite U200",
944 .matches = {
945 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
946 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
947 },
948 },
949 {
950 .ident = "Satellite U205",
951 .matches = {
952 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
953 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
954 },
955 },
956 {
957 .ident = "Portege M500",
958 .matches = {
959 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
961 },
962 },
963
964 { } /* terminate list */
965 };
966 static const char *oemstrs[] = {
967 "Tecra M3,",
968 };
969 int i;
970
971 if (dmi_check_system(sysids))
972 return 1;
973
974 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
975 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
976 return 1;
977
978 return 0;
979 }
980
981 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
982 {
983 struct ata_host *host = dev_get_drvdata(&pdev->dev);
984 unsigned long flags;
985 int rc = 0;
986
987 rc = ata_host_suspend(host, mesg);
988 if (rc)
989 return rc;
990
991 /* Some braindamaged ACPI suspend implementations expect the
992 * controller to be awake on entry; otherwise, it burns cpu
993 * cycles and power trying to do something to the sleeping
994 * beauty.
995 */
996 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
997 pci_save_state(pdev);
998
999 /* mark its power state as "unknown", since we don't
1000 * know if e.g. the BIOS will change its device state
1001 * when we suspend.
1002 */
1003 if (pdev->current_state == PCI_D0)
1004 pdev->current_state = PCI_UNKNOWN;
1005
1006 /* tell resume that it's waking up from broken suspend */
1007 spin_lock_irqsave(&host->lock, flags);
1008 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1009 spin_unlock_irqrestore(&host->lock, flags);
1010 } else
1011 ata_pci_device_do_suspend(pdev, mesg);
1012
1013 return 0;
1014 }
1015
1016 static int piix_pci_device_resume(struct pci_dev *pdev)
1017 {
1018 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1019 unsigned long flags;
1020 int rc;
1021
1022 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1023 spin_lock_irqsave(&host->lock, flags);
1024 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1025 spin_unlock_irqrestore(&host->lock, flags);
1026
1027 pci_set_power_state(pdev, PCI_D0);
1028 pci_restore_state(pdev);
1029
1030 /* PCI device wasn't disabled during suspend. Use
1031 * pci_reenable_device() to avoid affecting the enable
1032 * count.
1033 */
1034 rc = pci_reenable_device(pdev);
1035 if (rc)
1036 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1037 "device after resume (%d)\n", rc);
1038 } else
1039 rc = ata_pci_device_do_resume(pdev);
1040
1041 if (rc == 0)
1042 ata_host_resume(host);
1043
1044 return rc;
1045 }
1046 #endif
1047
1048 #define AHCI_PCI_BAR 5
1049 #define AHCI_GLOBAL_CTL 0x04
1050 #define AHCI_ENABLE (1 << 31)
1051 static int piix_disable_ahci(struct pci_dev *pdev)
1052 {
1053 void __iomem *mmio;
1054 u32 tmp;
1055 int rc = 0;
1056
1057 /* BUG: pci_enable_device has not yet been called. This
1058 * works because this device is usually set up by BIOS.
1059 */
1060
1061 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1062 !pci_resource_len(pdev, AHCI_PCI_BAR))
1063 return 0;
1064
1065 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1066 if (!mmio)
1067 return -ENOMEM;
1068
1069 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1070 if (tmp & AHCI_ENABLE) {
1071 tmp &= ~AHCI_ENABLE;
1072 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1073
1074 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1075 if (tmp & AHCI_ENABLE)
1076 rc = -EIO;
1077 }
1078
1079 pci_iounmap(pdev, mmio);
1080 return rc;
1081 }
1082
1083 /**
1084 * piix_check_450nx_errata - Check for problem 450NX setup
1085 * @ata_dev: the PCI device to check
1086 *
1087 * Check for the present of 450NX errata #19 and errata #25. If
1088 * they are found return an error code so we can turn off DMA
1089 */
1090
1091 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1092 {
1093 struct pci_dev *pdev = NULL;
1094 u16 cfg;
1095 int no_piix_dma = 0;
1096
1097 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1098 {
1099 /* Look for 450NX PXB. Check for problem configurations
1100 A PCI quirk checks bit 6 already */
1101 pci_read_config_word(pdev, 0x41, &cfg);
1102 /* Only on the original revision: IDE DMA can hang */
1103 if (pdev->revision == 0x00)
1104 no_piix_dma = 1;
1105 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1106 else if (cfg & (1<<14) && pdev->revision < 5)
1107 no_piix_dma = 2;
1108 }
1109 if (no_piix_dma)
1110 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1111 if (no_piix_dma == 2)
1112 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1113 return no_piix_dma;
1114 }
1115
1116 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1117 struct ata_port_info *pinfo,
1118 const struct piix_map_db *map_db)
1119 {
1120 u16 pcs, new_pcs;
1121
1122 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1123
1124 new_pcs = pcs | map_db->port_enable;
1125
1126 if (new_pcs != pcs) {
1127 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1128 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1129 msleep(150);
1130 }
1131 }
1132
1133 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1134 struct ata_port_info *pinfo,
1135 const struct piix_map_db *map_db)
1136 {
1137 struct piix_host_priv *hpriv = pinfo[0].private_data;
1138 const unsigned int *map;
1139 int i, invalid_map = 0;
1140 u8 map_value;
1141
1142 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1143
1144 map = map_db->map[map_value & map_db->mask];
1145
1146 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1147 for (i = 0; i < 4; i++) {
1148 switch (map[i]) {
1149 case RV:
1150 invalid_map = 1;
1151 printk(" XX");
1152 break;
1153
1154 case NA:
1155 printk(" --");
1156 break;
1157
1158 case IDE:
1159 WARN_ON((i & 1) || map[i + 1] != IDE);
1160 pinfo[i / 2] = piix_port_info[ich_pata_100];
1161 pinfo[i / 2].private_data = hpriv;
1162 i++;
1163 printk(" IDE IDE");
1164 break;
1165
1166 default:
1167 printk(" P%d", map[i]);
1168 if (i & 1)
1169 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1170 break;
1171 }
1172 }
1173 printk(" ]\n");
1174
1175 if (invalid_map)
1176 dev_printk(KERN_ERR, &pdev->dev,
1177 "invalid MAP value %u\n", map_value);
1178
1179 hpriv->map = map;
1180 }
1181
1182 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1183 {
1184 static const struct dmi_system_id sysids[] = {
1185 {
1186 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1187 * isn't used to boot the system which
1188 * disables the channel.
1189 */
1190 .ident = "M570U",
1191 .matches = {
1192 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1193 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1194 },
1195 },
1196
1197 { } /* terminate list */
1198 };
1199 u32 iocfg;
1200
1201 if (!dmi_check_system(sysids))
1202 return;
1203
1204 /* The datasheet says that bit 18 is NOOP but certain systems
1205 * seem to use it to disable a channel. Clear the bit on the
1206 * affected systems.
1207 */
1208 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1209 if (iocfg & (1 << 18)) {
1210 dev_printk(KERN_INFO, &pdev->dev,
1211 "applying IOCFG bit18 quirk\n");
1212 iocfg &= ~(1 << 18);
1213 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1214 }
1215 }
1216
1217 /**
1218 * piix_init_one - Register PIIX ATA PCI device with kernel services
1219 * @pdev: PCI device to register
1220 * @ent: Entry in piix_pci_tbl matching with @pdev
1221 *
1222 * Called from kernel PCI layer. We probe for combined mode (sigh),
1223 * and then hand over control to libata, for it to do the rest.
1224 *
1225 * LOCKING:
1226 * Inherited from PCI layer (may sleep).
1227 *
1228 * RETURNS:
1229 * Zero on success, or -ERRNO value.
1230 */
1231
1232 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1233 {
1234 static int printed_version;
1235 struct device *dev = &pdev->dev;
1236 struct ata_port_info port_info[2];
1237 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1238 struct piix_host_priv *hpriv;
1239 unsigned long port_flags;
1240
1241 if (!printed_version++)
1242 dev_printk(KERN_DEBUG, &pdev->dev,
1243 "version " DRV_VERSION "\n");
1244
1245 /* no hotplugging support (FIXME) */
1246 if (!in_module_init)
1247 return -ENODEV;
1248
1249 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1250 if (!hpriv)
1251 return -ENOMEM;
1252
1253 port_info[0] = piix_port_info[ent->driver_data];
1254 port_info[1] = piix_port_info[ent->driver_data];
1255 port_info[0].private_data = hpriv;
1256 port_info[1].private_data = hpriv;
1257
1258 port_flags = port_info[0].flags;
1259
1260 if (port_flags & PIIX_FLAG_AHCI) {
1261 u8 tmp;
1262 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1263 if (tmp == PIIX_AHCI_DEVICE) {
1264 int rc = piix_disable_ahci(pdev);
1265 if (rc)
1266 return rc;
1267 }
1268 }
1269
1270 /* Initialize SATA map */
1271 if (port_flags & ATA_FLAG_SATA) {
1272 piix_init_sata_map(pdev, port_info,
1273 piix_map_db_table[ent->driver_data]);
1274 piix_init_pcs(pdev, port_info,
1275 piix_map_db_table[ent->driver_data]);
1276 }
1277
1278 /* apply IOCFG bit18 quirk */
1279 piix_iocfg_bit18_quirk(pdev);
1280
1281 /* On ICH5, some BIOSen disable the interrupt using the
1282 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1283 * On ICH6, this bit has the same effect, but only when
1284 * MSI is disabled (and it is disabled, as we don't use
1285 * message-signalled interrupts currently).
1286 */
1287 if (port_flags & PIIX_FLAG_CHECKINTR)
1288 pci_intx(pdev, 1);
1289
1290 if (piix_check_450nx_errata(pdev)) {
1291 /* This writes into the master table but it does not
1292 really matter for this errata as we will apply it to
1293 all the PIIX devices on the board */
1294 port_info[0].mwdma_mask = 0;
1295 port_info[0].udma_mask = 0;
1296 port_info[1].mwdma_mask = 0;
1297 port_info[1].udma_mask = 0;
1298 }
1299 return ata_pci_init_one(pdev, ppi);
1300 }
1301
1302 static int __init piix_init(void)
1303 {
1304 int rc;
1305
1306 DPRINTK("pci_register_driver\n");
1307 rc = pci_register_driver(&piix_pci_driver);
1308 if (rc)
1309 return rc;
1310
1311 in_module_init = 0;
1312
1313 DPRINTK("done\n");
1314 return 0;
1315 }
1316
1317 static void __exit piix_exit(void)
1318 {
1319 pci_unregister_driver(&piix_pci_driver);
1320 }
1321
1322 module_init(piix_init);
1323 module_exit(piix_exit);
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