1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/seq_file.h>
17 #include "falcon_hwdefs.h"
19 #include "workarounds.h"
22 /* We expect these MMDs to be in the package. SFT9001 also has a
23 * clause 22 extension MMD, but since it doesn't have all the generic
24 * MMD registers it is pointless to include it here.
26 #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
31 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
32 (1 << LOOPBACK_PCS) | \
33 (1 << LOOPBACK_PMAPMD) | \
34 (1 << LOOPBACK_NETWORK))
36 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
37 (1 << LOOPBACK_PHYXS) | \
38 (1 << LOOPBACK_PCS) | \
39 (1 << LOOPBACK_PMAPMD) | \
40 (1 << LOOPBACK_NETWORK))
42 /* We complain if we fail to see the link partner as 10G capable this many
43 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
45 #define MAX_BAD_LP_TRIES (5)
47 /* Extended control register */
48 #define PMA_PMD_XCONTROL_REG 49152
49 #define PMA_PMD_EXT_GMII_EN_LBN 1
50 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
51 #define PMA_PMD_EXT_CLK_OUT_LBN 2
52 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
53 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
54 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
55 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
56 #define PMA_PMD_EXT_CLK312_WIDTH 1
57 #define PMA_PMD_EXT_LPOWER_LBN 12
58 #define PMA_PMD_EXT_LPOWER_WIDTH 1
59 #define PMA_PMD_EXT_ROBUST_LBN 14
60 #define PMA_PMD_EXT_ROBUST_WIDTH 1
61 #define PMA_PMD_EXT_SSR_LBN 15
62 #define PMA_PMD_EXT_SSR_WIDTH 1
64 /* extended status register */
65 #define PMA_PMD_XSTATUS_REG 49153
66 #define PMA_PMD_XSTAT_FLP_LBN (12)
68 /* LED control register */
69 #define PMA_PMD_LED_CTRL_REG 49159
70 #define PMA_PMA_LED_ACTIVITY_LBN (3)
72 /* LED function override register */
73 #define PMA_PMD_LED_OVERR_REG 49161
74 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
75 #define PMA_PMD_LED_LINK_LBN (0)
76 #define PMA_PMD_LED_SPEED_LBN (2)
77 #define PMA_PMD_LED_TX_LBN (4)
78 #define PMA_PMD_LED_RX_LBN (6)
79 /* Override settings */
80 #define PMA_PMD_LED_AUTO (0) /* H/W control */
81 #define PMA_PMD_LED_ON (1)
82 #define PMA_PMD_LED_OFF (2)
83 #define PMA_PMD_LED_FLASH (3)
84 #define PMA_PMD_LED_MASK 3
85 /* All LEDs under hardware control */
86 #define PMA_PMD_LED_FULL_AUTO (0)
87 /* Green and Amber under hardware control, Red off */
88 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
90 #define PMA_PMD_SPEED_ENABLE_REG 49192
91 #define PMA_PMD_100TX_ADV_LBN 1
92 #define PMA_PMD_100TX_ADV_WIDTH 1
93 #define PMA_PMD_1000T_ADV_LBN 2
94 #define PMA_PMD_1000T_ADV_WIDTH 1
95 #define PMA_PMD_10000T_ADV_LBN 3
96 #define PMA_PMD_10000T_ADV_WIDTH 1
97 #define PMA_PMD_SPEED_LBN 4
98 #define PMA_PMD_SPEED_WIDTH 4
100 /* Cable diagnostics - SFT9001 only */
101 #define PMA_PMD_CDIAG_CTRL_REG 49213
102 #define CDIAG_CTRL_IMMED_LBN 15
103 #define CDIAG_CTRL_BRK_LINK_LBN 12
104 #define CDIAG_CTRL_IN_PROG_LBN 11
105 #define CDIAG_CTRL_LEN_UNIT_LBN 10
106 #define CDIAG_CTRL_LEN_METRES 1
107 #define PMA_PMD_CDIAG_RES_REG 49174
108 #define CDIAG_RES_A_LBN 12
109 #define CDIAG_RES_B_LBN 8
110 #define CDIAG_RES_C_LBN 4
111 #define CDIAG_RES_D_LBN 0
112 #define CDIAG_RES_WIDTH 4
113 #define CDIAG_RES_OPEN 2
114 #define CDIAG_RES_OK 1
115 #define CDIAG_RES_INVALID 0
116 /* Set of 4 registers for pairs A-D */
117 #define PMA_PMD_CDIAG_LEN_REG 49175
119 /* Serdes control registers - SFT9001 only */
120 #define PMA_PMD_CSERDES_CTRL_REG 64258
121 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
122 #define PMA_PMD_CSERDES_DEFAULT 0x000f
124 /* Misc register defines - SFX7101 only */
125 #define PCS_CLOCK_CTRL_REG 55297
126 #define PLL312_RST_N_LBN 2
128 #define PCS_SOFT_RST2_REG 55302
129 #define SERDES_RST_N_LBN 13
130 #define XGXS_RST_N_LBN 12
132 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
133 #define CLK312_EN_LBN 3
135 /* PHYXS registers */
136 #define PHYXS_XCONTROL_REG 49152
137 #define PHYXS_RESET_LBN 15
138 #define PHYXS_RESET_WIDTH 1
140 #define PHYXS_TEST1 (49162)
141 #define LOOPBACK_NEAR_LBN (8)
142 #define LOOPBACK_NEAR_WIDTH (1)
144 /* Boot status register */
145 #define PCS_BOOT_STATUS_REG 53248
146 #define PCS_BOOT_FATAL_ERROR_LBN 0
147 #define PCS_BOOT_PROGRESS_LBN 1
148 #define PCS_BOOT_PROGRESS_WIDTH 2
149 #define PCS_BOOT_PROGRESS_INIT 0
150 #define PCS_BOOT_PROGRESS_WAIT_MDIO 1
151 #define PCS_BOOT_PROGRESS_CHECKSUM 2
152 #define PCS_BOOT_PROGRESS_JUMP 3
153 #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
154 #define PCS_BOOT_CODE_STARTED_LBN 4
156 /* 100M/1G PHY registers */
157 #define GPHY_XCONTROL_REG 49152
158 #define GPHY_ISOLATE_LBN 10
159 #define GPHY_ISOLATE_WIDTH 1
160 #define GPHY_DUPLEX_LBN 8
161 #define GPHY_DUPLEX_WIDTH 1
162 #define GPHY_LOOPBACK_NEAR_LBN 14
163 #define GPHY_LOOPBACK_NEAR_WIDTH 1
165 #define C22EXT_STATUS_REG 49153
166 #define C22EXT_STATUS_LINK_LBN 2
167 #define C22EXT_STATUS_LINK_WIDTH 1
169 #define C22EXT_MSTSLV_CTRL 49161
170 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
171 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
173 #define C22EXT_MSTSLV_STATUS 49162
174 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
175 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
177 /* Time to wait between powering down the LNPGA and turning off the power
179 #define LNPGA_PDOWN_WAIT (HZ / 5)
181 struct tenxpress_phy_data
{
182 enum efx_loopback_mode loopback_mode
;
183 enum efx_phy_mode phy_mode
;
187 static ssize_t
show_phy_short_reach(struct device
*dev
,
188 struct device_attribute
*attr
, char *buf
)
190 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
193 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
);
194 return sprintf(buf
, "%d\n", !!(reg
& MDIO_PMA_10GBT_TXPWR_SHORT
));
197 static ssize_t
set_phy_short_reach(struct device
*dev
,
198 struct device_attribute
*attr
,
199 const char *buf
, size_t count
)
201 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
204 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
,
205 MDIO_PMA_10GBT_TXPWR_SHORT
,
206 count
!= 0 && *buf
!= '0');
207 efx_reconfigure_port(efx
);
213 static DEVICE_ATTR(phy_short_reach
, 0644, show_phy_short_reach
,
214 set_phy_short_reach
);
216 int sft9001_wait_boot(struct efx_nic
*efx
)
218 unsigned long timeout
= jiffies
+ HZ
+ 1;
222 boot_stat
= efx_mdio_read(efx
, MDIO_MMD_PCS
,
223 PCS_BOOT_STATUS_REG
);
224 if (boot_stat
>= 0) {
225 EFX_LOG(efx
, "PHY boot status = %#x\n", boot_stat
);
227 ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
228 (3 << PCS_BOOT_PROGRESS_LBN
) |
229 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
230 (1 << PCS_BOOT_CODE_STARTED_LBN
))) {
231 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
232 (PCS_BOOT_PROGRESS_CHECKSUM
<<
233 PCS_BOOT_PROGRESS_LBN
)):
234 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
235 (PCS_BOOT_PROGRESS_INIT
<<
236 PCS_BOOT_PROGRESS_LBN
) |
237 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
239 case ((PCS_BOOT_PROGRESS_WAIT_MDIO
<<
240 PCS_BOOT_PROGRESS_LBN
) |
241 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
242 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
244 case ((PCS_BOOT_PROGRESS_JUMP
<<
245 PCS_BOOT_PROGRESS_LBN
) |
246 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
247 case ((PCS_BOOT_PROGRESS_JUMP
<<
248 PCS_BOOT_PROGRESS_LBN
) |
249 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
250 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
251 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
254 if (boot_stat
& (1 << PCS_BOOT_FATAL_ERROR_LBN
))
260 if (time_after_eq(jiffies
, timeout
))
267 static int tenxpress_init(struct efx_nic
*efx
)
271 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
272 /* Enable 312.5 MHz clock */
273 efx_mdio_write(efx
, MDIO_MMD_PCS
, PCS_TEST_SELECT_REG
,
276 /* Enable 312.5 MHz clock and GMII */
277 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
278 reg
|= ((1 << PMA_PMD_EXT_GMII_EN_LBN
) |
279 (1 << PMA_PMD_EXT_CLK_OUT_LBN
) |
280 (1 << PMA_PMD_EXT_CLK312_LBN
) |
281 (1 << PMA_PMD_EXT_ROBUST_LBN
));
283 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
284 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
,
285 GPHY_XCONTROL_REG
, 1 << GPHY_ISOLATE_LBN
,
289 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
290 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
291 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_CTRL_REG
,
292 1 << PMA_PMA_LED_ACTIVITY_LBN
, true);
293 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
,
294 PMA_PMD_LED_DEFAULT
);
300 static int tenxpress_phy_init(struct efx_nic
*efx
)
302 struct tenxpress_phy_data
*phy_data
;
305 phy_data
= kzalloc(sizeof(*phy_data
), GFP_KERNEL
);
308 efx
->phy_data
= phy_data
;
309 phy_data
->phy_mode
= efx
->phy_mode
;
311 if (!(efx
->phy_mode
& PHY_MODE_SPECIAL
)) {
312 if (efx
->phy_type
== PHY_TYPE_SFT9001A
) {
314 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
315 PMA_PMD_XCONTROL_REG
);
316 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
317 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
318 PMA_PMD_XCONTROL_REG
, reg
);
322 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
326 rc
= efx_mdio_check_mmds(efx
, TENXPRESS_REQUIRED_DEVS
, 0);
331 rc
= tenxpress_init(efx
);
335 if (efx
->phy_type
== PHY_TYPE_SFT9001B
) {
336 rc
= device_create_file(&efx
->pci_dev
->dev
,
337 &dev_attr_phy_short_reach
);
342 schedule_timeout_uninterruptible(HZ
/ 5); /* 200ms */
344 /* Let XGXS and SerDes out of reset */
345 falcon_reset_xaui(efx
);
350 kfree(efx
->phy_data
);
351 efx
->phy_data
= NULL
;
355 /* Perform a "special software reset" on the PHY. The caller is
356 * responsible for saving and restoring the PHY hardware registers
357 * properly, and masking/unmasking LASI */
358 static int tenxpress_special_reset(struct efx_nic
*efx
)
362 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
363 * a special software reset can glitch the XGMAC sufficiently for stats
364 * requests to fail. */
365 efx_stats_disable(efx
);
368 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
369 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
370 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
374 /* Wait for the blocks to come out of reset */
375 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
379 /* Try and reconfigure the device */
380 rc
= tenxpress_init(efx
);
384 /* Wait for the XGXS state machine to churn */
387 efx_stats_enable(efx
);
391 static void sfx7101_check_bad_lp(struct efx_nic
*efx
, bool link_ok
)
393 struct tenxpress_phy_data
*pd
= efx
->phy_data
;
400 /* Check that AN has started but not completed. */
401 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_STAT1
);
402 if (!(reg
& MDIO_AN_STAT1_LPABLE
))
403 return; /* LP status is unknown */
404 bad_lp
= !(reg
& MDIO_AN_STAT1_COMPLETE
);
409 /* Nothing to do if all is well and was previously so. */
410 if (!pd
->bad_lp_tries
)
413 /* Use the RX (red) LED as an error indicator once we've seen AN
414 * failure several times in a row, and also log a message. */
415 if (!bad_lp
|| pd
->bad_lp_tries
== MAX_BAD_LP_TRIES
) {
416 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
417 PMA_PMD_LED_OVERR_REG
);
418 reg
&= ~(PMA_PMD_LED_MASK
<< PMA_PMD_LED_RX_LBN
);
420 reg
|= PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
;
422 reg
|= PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
;
423 EFX_ERR(efx
, "appears to be plugged into a port"
424 " that is not 10GBASE-T capable. The PHY"
425 " supports 10GBASE-T ONLY, so no link can"
426 " be established\n");
428 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
429 PMA_PMD_LED_OVERR_REG
, reg
);
430 pd
->bad_lp_tries
= bad_lp
;
434 static bool sfx7101_link_ok(struct efx_nic
*efx
)
436 return efx_mdio_links_ok(efx
,
442 static bool sft9001_link_ok(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
446 if (efx_phy_mode_disabled(efx
->phy_mode
))
448 else if (efx
->loopback_mode
== LOOPBACK_GPHY
)
450 else if (efx
->loopback_mode
)
451 return efx_mdio_links_ok(efx
,
455 /* We must use the same definition of link state as LASI,
456 * otherwise we can miss a link state transition
458 if (ecmd
->speed
== 10000) {
459 reg
= efx_mdio_read(efx
, MDIO_MMD_PCS
, MDIO_PCS_10GBRT_STAT1
);
460 return reg
& MDIO_PCS_10GBRT_STAT1_BLKLK
;
462 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_STATUS_REG
);
463 return reg
& (1 << C22EXT_STATUS_LINK_LBN
);
467 static void tenxpress_ext_loopback(struct efx_nic
*efx
)
469 efx_mdio_set_flag(efx
, MDIO_MMD_PHYXS
, PHYXS_TEST1
,
470 1 << LOOPBACK_NEAR_LBN
,
471 efx
->loopback_mode
== LOOPBACK_PHYXS
);
472 if (efx
->phy_type
!= PHY_TYPE_SFX7101
)
473 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, GPHY_XCONTROL_REG
,
474 1 << GPHY_LOOPBACK_NEAR_LBN
,
475 efx
->loopback_mode
== LOOPBACK_GPHY
);
478 static void tenxpress_low_power(struct efx_nic
*efx
)
480 if (efx
->phy_type
== PHY_TYPE_SFX7101
)
481 efx_mdio_set_mmds_lpower(
482 efx
, !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
),
483 TENXPRESS_REQUIRED_DEVS
);
486 efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
,
487 1 << PMA_PMD_EXT_LPOWER_LBN
,
488 !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
));
491 static void tenxpress_phy_reconfigure(struct efx_nic
*efx
)
493 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
494 struct ethtool_cmd ecmd
;
495 bool phy_mode_change
, loop_reset
;
497 if (efx
->phy_mode
& (PHY_MODE_OFF
| PHY_MODE_SPECIAL
)) {
498 phy_data
->phy_mode
= efx
->phy_mode
;
502 tenxpress_low_power(efx
);
504 phy_mode_change
= (efx
->phy_mode
== PHY_MODE_NORMAL
&&
505 phy_data
->phy_mode
!= PHY_MODE_NORMAL
);
506 loop_reset
= (LOOPBACK_OUT_OF(phy_data
, efx
, efx
->phy_op
->loopbacks
) ||
507 LOOPBACK_CHANGED(phy_data
, efx
, 1 << LOOPBACK_GPHY
));
509 if (loop_reset
|| phy_mode_change
) {
512 efx
->phy_op
->get_settings(efx
, &ecmd
);
514 if (loop_reset
|| phy_mode_change
) {
515 tenxpress_special_reset(efx
);
517 /* Reset XAUI if we were in 10G, and are staying
518 * in 10G. If we're moving into and out of 10G
519 * then xaui will be reset anyway */
521 falcon_reset_xaui(efx
);
524 rc
= efx
->phy_op
->set_settings(efx
, &ecmd
);
528 efx_mdio_transmit_disable(efx
);
529 efx_mdio_phy_reconfigure(efx
);
530 tenxpress_ext_loopback(efx
);
532 phy_data
->loopback_mode
= efx
->loopback_mode
;
533 phy_data
->phy_mode
= efx
->phy_mode
;
535 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
536 efx
->link_speed
= 10000;
538 efx
->link_up
= sfx7101_link_ok(efx
);
540 efx
->phy_op
->get_settings(efx
, &ecmd
);
541 efx
->link_speed
= ecmd
.speed
;
542 efx
->link_fd
= ecmd
.duplex
== DUPLEX_FULL
;
543 efx
->link_up
= sft9001_link_ok(efx
, &ecmd
);
545 efx
->link_fc
= efx_mdio_get_pause(efx
);
548 /* Poll PHY for interrupt */
549 static void tenxpress_phy_poll(struct efx_nic
*efx
)
551 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
554 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
555 bool link_ok
= sfx7101_link_ok(efx
);
556 if (link_ok
!= efx
->link_up
) {
559 unsigned int link_fc
= efx_mdio_get_pause(efx
);
560 if (link_fc
!= efx
->link_fc
)
563 sfx7101_check_bad_lp(efx
, link_ok
);
564 } else if (efx
->loopback_mode
) {
565 bool link_ok
= sft9001_link_ok(efx
, NULL
);
566 if (link_ok
!= efx
->link_up
)
569 int status
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
571 if (status
& MDIO_PMA_LASI_LSALARM
)
576 falcon_sim_phy_event(efx
);
578 if (phy_data
->phy_mode
!= PHY_MODE_NORMAL
)
582 static void tenxpress_phy_fini(struct efx_nic
*efx
)
586 if (efx
->phy_type
== PHY_TYPE_SFT9001B
)
587 device_remove_file(&efx
->pci_dev
->dev
,
588 &dev_attr_phy_short_reach
);
590 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
591 /* Power down the LNPGA */
592 reg
= (1 << PMA_PMD_LNPGA_POWERDOWN_LBN
);
593 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
595 /* Waiting here ensures that the board fini, which can turn
596 * off the power to the PHY, won't get run until the LNPGA
597 * powerdown has been given long enough to complete. */
598 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT
); /* 200 ms */
601 kfree(efx
->phy_data
);
602 efx
->phy_data
= NULL
;
606 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
607 * (which probably aren't wired anyway) are left in AUTO mode */
608 void tenxpress_phy_blink(struct efx_nic
*efx
, bool blink
)
613 reg
= (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_TX_LBN
) |
614 (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
) |
615 (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_LINK_LBN
);
617 reg
= PMA_PMD_LED_DEFAULT
;
619 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
, reg
);
622 static const char *const sfx7101_test_names
[] = {
627 sfx7101_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
631 if (!(flags
& ETH_TEST_FL_OFFLINE
))
634 /* BIST is automatically run after a special software reset */
635 rc
= tenxpress_special_reset(efx
);
636 results
[0] = rc
? -1 : 1;
640 static const char *const sft9001_test_names
[] = {
642 "cable.pairA.status",
643 "cable.pairB.status",
644 "cable.pairC.status",
645 "cable.pairD.status",
646 "cable.pairA.length",
647 "cable.pairB.length",
648 "cable.pairC.length",
649 "cable.pairD.length",
652 static int sft9001_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
654 struct ethtool_cmd ecmd
;
655 int rc
= 0, rc2
, i
, ctrl_reg
, res_reg
;
657 if (flags
& ETH_TEST_FL_OFFLINE
)
658 efx
->phy_op
->get_settings(efx
, &ecmd
);
660 /* Initialise cable diagnostic results to unknown failure */
661 for (i
= 1; i
< 9; ++i
)
664 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
665 * A cable fault is not a self-test failure, but a timeout is. */
666 ctrl_reg
= ((1 << CDIAG_CTRL_IMMED_LBN
) |
667 (CDIAG_CTRL_LEN_METRES
<< CDIAG_CTRL_LEN_UNIT_LBN
));
668 if (flags
& ETH_TEST_FL_OFFLINE
) {
669 /* Break the link in order to run full diagnostics. We
670 * must reset the PHY to resume normal service. */
671 ctrl_reg
|= (1 << CDIAG_CTRL_BRK_LINK_LBN
);
673 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
,
676 while (efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
) &
677 (1 << CDIAG_CTRL_IN_PROG_LBN
)) {
684 res_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_RES_REG
);
685 for (i
= 0; i
< 4; i
++) {
687 (res_reg
>> (CDIAG_RES_A_LBN
- i
* CDIAG_RES_WIDTH
))
688 & ((1 << CDIAG_RES_WIDTH
) - 1);
689 int len_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
690 PMA_PMD_CDIAG_LEN_REG
+ i
);
691 if (pair_res
== CDIAG_RES_OK
)
693 else if (pair_res
== CDIAG_RES_INVALID
)
696 results
[1 + i
] = -pair_res
;
697 if (pair_res
!= CDIAG_RES_INVALID
&&
698 pair_res
!= CDIAG_RES_OPEN
&&
700 results
[5 + i
] = len_reg
;
704 if (flags
& ETH_TEST_FL_OFFLINE
) {
705 /* Reset, running the BIST and then resuming normal service. */
706 rc2
= tenxpress_special_reset(efx
);
707 results
[0] = rc2
? -1 : 1;
711 rc2
= efx
->phy_op
->set_settings(efx
, &ecmd
);
720 tenxpress_get_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
722 u32 adv
= 0, lpa
= 0;
725 if (efx
->phy_type
!= PHY_TYPE_SFX7101
) {
726 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
);
727 if (reg
& (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
))
728 adv
|= ADVERTISED_1000baseT_Full
;
729 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_STATUS
);
730 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN
))
731 lpa
|= ADVERTISED_1000baseT_Half
;
732 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN
))
733 lpa
|= ADVERTISED_1000baseT_Full
;
735 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
);
736 if (reg
& MDIO_AN_10GBT_CTRL_ADV10G
)
737 adv
|= ADVERTISED_10000baseT_Full
;
738 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_STAT
);
739 if (reg
& MDIO_AN_10GBT_STAT_LP10G
)
740 lpa
|= ADVERTISED_10000baseT_Full
;
742 mdio45_ethtool_gset_npage(&efx
->mdio
, ecmd
, adv
, lpa
);
744 if (efx
->phy_type
!= PHY_TYPE_SFX7101
)
745 ecmd
->supported
|= (SUPPORTED_100baseT_Full
|
746 SUPPORTED_1000baseT_Full
);
748 /* In loopback, the PHY automatically brings up the correct interface,
749 * but doesn't advertise the correct speed. So override it */
750 if (efx
->loopback_mode
== LOOPBACK_GPHY
)
751 ecmd
->speed
= SPEED_1000
;
752 else if (LOOPBACK_MASK(efx
) & efx
->phy_op
->loopbacks
)
753 ecmd
->speed
= SPEED_10000
;
756 static int tenxpress_set_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
761 return efx_mdio_set_settings(efx
, ecmd
);
764 static void sfx7101_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
766 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
767 MDIO_AN_10GBT_CTRL_ADV10G
,
768 advertising
& ADVERTISED_10000baseT_Full
);
771 static void sft9001_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
773 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
,
774 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
,
775 advertising
& ADVERTISED_1000baseT_Full
);
776 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
777 MDIO_AN_10GBT_CTRL_ADV10G
,
778 advertising
& ADVERTISED_10000baseT_Full
);
781 struct efx_phy_operations falcon_sfx7101_phy_ops
= {
783 .init
= tenxpress_phy_init
,
784 .reconfigure
= tenxpress_phy_reconfigure
,
785 .poll
= tenxpress_phy_poll
,
786 .fini
= tenxpress_phy_fini
,
787 .clear_interrupt
= efx_port_dummy_op_void
,
788 .get_settings
= tenxpress_get_settings
,
789 .set_settings
= tenxpress_set_settings
,
790 .set_npage_adv
= sfx7101_set_npage_adv
,
791 .num_tests
= ARRAY_SIZE(sfx7101_test_names
),
792 .test_names
= sfx7101_test_names
,
793 .run_tests
= sfx7101_run_tests
,
794 .mmds
= TENXPRESS_REQUIRED_DEVS
,
795 .loopbacks
= SFX7101_LOOPBACKS
,
798 struct efx_phy_operations falcon_sft9001_phy_ops
= {
799 .macs
= EFX_GMAC
| EFX_XMAC
,
800 .init
= tenxpress_phy_init
,
801 .reconfigure
= tenxpress_phy_reconfigure
,
802 .poll
= tenxpress_phy_poll
,
803 .fini
= tenxpress_phy_fini
,
804 .clear_interrupt
= efx_port_dummy_op_void
,
805 .get_settings
= tenxpress_get_settings
,
806 .set_settings
= tenxpress_set_settings
,
807 .set_npage_adv
= sft9001_set_npage_adv
,
808 .num_tests
= ARRAY_SIZE(sft9001_test_names
),
809 .test_names
= sft9001_test_names
,
810 .run_tests
= sft9001_run_tests
,
811 .mmds
= TENXPRESS_REQUIRED_DEVS
,
812 .loopbacks
= SFT9001_LOOPBACKS
,