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ixgbe: Use generic MDIO definitions and functions
[linux-2.6/verdex.git] / drivers / net / ixgbe / ixgbe_phy.c
blob6d385ea3c2a17c4f76e6a73b8b7cf754f4e1b2c3
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
34
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49
50 /**
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
57 {
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
64 ixgbe_get_phy_id(hw);
65 hw->phy.type =
66 ixgbe_get_phy_type_from_id(hw->phy.id);
67 status = 0;
68 break;
69 }
70 }
71 } else {
72 status = 0;
73 }
74
75 return status;
76 }
77
78 /**
79 * ixgbe_get_phy_id - Get the phy type
80 * @hw: pointer to hardware structure
81 *
82 **/
83 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
84 {
85 u32 status;
86 u16 phy_id_high = 0;
87 u16 phy_id_low = 0;
88
89 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
90 &phy_id_high);
91
92 if (status == 0) {
93 hw->phy.id = (u32)(phy_id_high << 16);
94 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
95 &phy_id_low);
96 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
97 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
98 }
99 return status;
100 }
101
102 /**
103 * ixgbe_get_phy_type_from_id - Get the phy type
104 * @hw: pointer to hardware structure
105 *
106 **/
107 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
108 {
109 enum ixgbe_phy_type phy_type;
110
111 switch (phy_id) {
112 case TN1010_PHY_ID:
113 phy_type = ixgbe_phy_tn;
114 break;
115 case QT2022_PHY_ID:
116 phy_type = ixgbe_phy_qt;
117 break;
118 case ATH_PHY_ID:
119 phy_type = ixgbe_phy_nl;
120 break;
121 default:
122 phy_type = ixgbe_phy_unknown;
123 break;
124 }
125
126 return phy_type;
127 }
128
129 /**
130 * ixgbe_reset_phy_generic - Performs a PHY reset
131 * @hw: pointer to hardware structure
132 **/
133 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
134 {
135 /*
136 * Perform soft PHY reset to the PHY_XS.
137 * This will cause a soft reset to the PHY
138 */
139 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
140 MDIO_CTRL1_RESET);
141 }
142
143 /**
144 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
145 * @hw: pointer to hardware structure
146 * @reg_addr: 32 bit address of PHY register to read
147 * @phy_data: Pointer to read data from PHY register
148 **/
149 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
150 u32 device_type, u16 *phy_data)
151 {
152 u32 command;
153 u32 i;
154 u32 data;
155 s32 status = 0;
156 u16 gssr;
157
158 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
159 gssr = IXGBE_GSSR_PHY1_SM;
160 else
161 gssr = IXGBE_GSSR_PHY0_SM;
162
163 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
164 status = IXGBE_ERR_SWFW_SYNC;
165
166 if (status == 0) {
167 /* Setup and write the address cycle command */
168 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
169 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
170 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
171 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
172
173 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
174
175 /*
176 * Check every 10 usec to see if the address cycle completed.
177 * The MDI Command bit will clear when the operation is
178 * complete
179 */
180 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
181 udelay(10);
182
183 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
184
185 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
186 break;
187 }
188
189 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
190 hw_dbg(hw, "PHY address command did not complete.\n");
191 status = IXGBE_ERR_PHY;
192 }
193
194 if (status == 0) {
195 /*
196 * Address cycle complete, setup and write the read
197 * command
198 */
199 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
200 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
201 (hw->phy.mdio.prtad <<
202 IXGBE_MSCA_PHY_ADDR_SHIFT) |
203 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
204
205 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
206
207 /*
208 * Check every 10 usec to see if the address cycle
209 * completed. The MDI Command bit will clear when the
210 * operation is complete
211 */
212 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
213 udelay(10);
214
215 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
216
217 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
218 break;
219 }
220
221 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
222 hw_dbg(hw, "PHY read command didn't complete\n");
223 status = IXGBE_ERR_PHY;
224 } else {
225 /*
226 * Read operation is complete. Get the data
227 * from MSRWD
228 */
229 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
230 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
231 *phy_data = (u16)(data);
232 }
233 }
234
235 ixgbe_release_swfw_sync(hw, gssr);
236 }
237
238 return status;
239 }
240
241 /**
242 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
243 * @hw: pointer to hardware structure
244 * @reg_addr: 32 bit PHY register to write
245 * @device_type: 5 bit device type
246 * @phy_data: Data to write to the PHY register
247 **/
248 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
249 u32 device_type, u16 phy_data)
250 {
251 u32 command;
252 u32 i;
253 s32 status = 0;
254 u16 gssr;
255
256 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
257 gssr = IXGBE_GSSR_PHY1_SM;
258 else
259 gssr = IXGBE_GSSR_PHY0_SM;
260
261 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
262 status = IXGBE_ERR_SWFW_SYNC;
263
264 if (status == 0) {
265 /* Put the data in the MDI single read and write data register*/
266 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
267
268 /* Setup and write the address cycle command */
269 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
270 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
271 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
272 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
273
274 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
275
276 /*
277 * Check every 10 usec to see if the address cycle completed.
278 * The MDI Command bit will clear when the operation is
279 * complete
280 */
281 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
282 udelay(10);
283
284 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
285
286 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
287 break;
288 }
289
290 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
291 hw_dbg(hw, "PHY address cmd didn't complete\n");
292 status = IXGBE_ERR_PHY;
293 }
294
295 if (status == 0) {
296 /*
297 * Address cycle complete, setup and write the write
298 * command
299 */
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
302 (hw->phy.mdio.prtad <<
303 IXGBE_MSCA_PHY_ADDR_SHIFT) |
304 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
305
306 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
307
308 /*
309 * Check every 10 usec to see if the address cycle
310 * completed. The MDI Command bit will clear when the
311 * operation is complete
312 */
313 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
314 udelay(10);
315
316 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
317
318 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
319 break;
320 }
321
322 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
323 hw_dbg(hw, "PHY address cmd didn't complete\n");
324 status = IXGBE_ERR_PHY;
325 }
326 }
327
328 ixgbe_release_swfw_sync(hw, gssr);
329 }
330
331 return status;
332 }
333
334 /**
335 * ixgbe_setup_phy_link_generic - Set and restart autoneg
336 * @hw: pointer to hardware structure
337 *
338 * Restart autonegotiation and PHY and waits for completion.
339 **/
340 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
341 {
342 s32 status = IXGBE_NOT_IMPLEMENTED;
343 u32 time_out;
344 u32 max_time_out = 10;
345 u16 autoneg_reg;
346
347 /*
348 * Set advertisement settings in PHY based on autoneg_advertised
349 * settings. If autoneg_advertised = 0, then advertise default values
350 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
351 * for a 1G.
352 */
353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
354
355 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
356 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
357 else
358 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
359
360 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
361
362 /* Restart PHY autonegotiation and wait for completion */
363 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
364
365 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
366
367 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
368
369 /* Wait for autonegotiation to finish */
370 for (time_out = 0; time_out < max_time_out; time_out++) {
371 udelay(10);
372 /* Restart PHY autonegotiation and wait for completion */
373 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
374 &autoneg_reg);
375
376 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
377 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
378 status = 0;
379 break;
380 }
381 }
382
383 if (time_out == max_time_out)
384 status = IXGBE_ERR_LINK_SETUP;
385
386 return status;
387 }
388
389 /**
390 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
391 * @hw: pointer to hardware structure
392 * @speed: new link speed
393 * @autoneg: true if autonegotiation enabled
394 **/
395 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
396 ixgbe_link_speed speed,
397 bool autoneg,
398 bool autoneg_wait_to_complete)
399 {
400
401 /*
402 * Clear autoneg_advertised and set new values based on input link
403 * speed.
404 */
405 hw->phy.autoneg_advertised = 0;
406
407 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
408 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
409
410 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
411 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
412
413 /* Setup link based on the new speed settings */
414 hw->phy.ops.setup_link(hw);
415
416 return 0;
417 }
418
419 /**
420 * ixgbe_reset_phy_nl - Performs a PHY reset
421 * @hw: pointer to hardware structure
422 **/
423 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
424 {
425 u16 phy_offset, control, eword, edata, block_crc;
426 bool end_data = false;
427 u16 list_offset, data_offset;
428 u16 phy_data = 0;
429 s32 ret_val = 0;
430 u32 i;
431
432 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
433
434 /* reset the PHY and poll for completion */
435 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
436 (phy_data | MDIO_CTRL1_RESET));
437
438 for (i = 0; i < 100; i++) {
439 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
440 &phy_data);
441 if ((phy_data & MDIO_CTRL1_RESET) == 0)
442 break;
443 msleep(10);
444 }
445
446 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
447 hw_dbg(hw, "PHY reset did not complete.\n");
448 ret_val = IXGBE_ERR_PHY;
449 goto out;
450 }
451
452 /* Get init offsets */
453 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
454 &data_offset);
455 if (ret_val != 0)
456 goto out;
457
458 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
459 data_offset++;
460 while (!end_data) {
461 /*
462 * Read control word from PHY init contents offset
463 */
464 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
465 control = (eword & IXGBE_CONTROL_MASK_NL) >>
466 IXGBE_CONTROL_SHIFT_NL;
467 edata = eword & IXGBE_DATA_MASK_NL;
468 switch (control) {
469 case IXGBE_DELAY_NL:
470 data_offset++;
471 hw_dbg(hw, "DELAY: %d MS\n", edata);
472 msleep(edata);
473 break;
474 case IXGBE_DATA_NL:
475 hw_dbg(hw, "DATA: \n");
476 data_offset++;
477 hw->eeprom.ops.read(hw, data_offset++,
478 &phy_offset);
479 for (i = 0; i < edata; i++) {
480 hw->eeprom.ops.read(hw, data_offset, &eword);
481 hw->phy.ops.write_reg(hw, phy_offset,
482 MDIO_MMD_PMAPMD, eword);
483 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
484 phy_offset);
485 data_offset++;
486 phy_offset++;
487 }
488 break;
489 case IXGBE_CONTROL_NL:
490 data_offset++;
491 hw_dbg(hw, "CONTROL: \n");
492 if (edata == IXGBE_CONTROL_EOL_NL) {
493 hw_dbg(hw, "EOL\n");
494 end_data = true;
495 } else if (edata == IXGBE_CONTROL_SOL_NL) {
496 hw_dbg(hw, "SOL\n");
497 } else {
498 hw_dbg(hw, "Bad control value\n");
499 ret_val = IXGBE_ERR_PHY;
500 goto out;
501 }
502 break;
503 default:
504 hw_dbg(hw, "Bad control type\n");
505 ret_val = IXGBE_ERR_PHY;
506 goto out;
507 }
508 }
509
510 out:
511 return ret_val;
512 }
513
514 /**
515 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
516 * the PHY type.
517 * @hw: pointer to hardware structure
518 *
519 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
520 **/
521 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
522 {
523 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
524 u32 vendor_oui = 0;
525 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
526 u8 identifier = 0;
527 u8 comp_codes_1g = 0;
528 u8 comp_codes_10g = 0;
529 u8 oui_bytes[3] = {0, 0, 0};
530 u8 transmission_media = 0;
531 u16 enforce_sfp = 0;
532
533 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
534 &identifier);
535
536 if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
537 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
538 goto out;
539 }
540
541 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
542 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
543 &comp_codes_1g);
544 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
545 &comp_codes_10g);
546 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
547 &transmission_media);
548
549 /* ID Module
550 * =========
551 * 0 SFP_DA_CU
552 * 1 SFP_SR
553 * 2 SFP_LR
554 * 3 SFP_DA_CORE0 - 82599-specific
555 * 4 SFP_DA_CORE1 - 82599-specific
556 * 5 SFP_SR/LR_CORE0 - 82599-specific
557 * 6 SFP_SR/LR_CORE1 - 82599-specific
558 */
559 if (hw->mac.type == ixgbe_mac_82598EB) {
560 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
561 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
562 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
563 hw->phy.sfp_type = ixgbe_sfp_type_sr;
564 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
565 hw->phy.sfp_type = ixgbe_sfp_type_lr;
566 else
567 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
568 } else if (hw->mac.type == ixgbe_mac_82599EB) {
569 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
570 if (hw->bus.lan_id == 0)
571 hw->phy.sfp_type =
572 ixgbe_sfp_type_da_cu_core0;
573 else
574 hw->phy.sfp_type =
575 ixgbe_sfp_type_da_cu_core1;
576 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
577 if (hw->bus.lan_id == 0)
578 hw->phy.sfp_type =
579 ixgbe_sfp_type_srlr_core0;
580 else
581 hw->phy.sfp_type =
582 ixgbe_sfp_type_srlr_core1;
583 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
584 if (hw->bus.lan_id == 0)
585 hw->phy.sfp_type =
586 ixgbe_sfp_type_srlr_core0;
587 else
588 hw->phy.sfp_type =
589 ixgbe_sfp_type_srlr_core1;
590 else
591 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
592 }
593
594 if (hw->phy.sfp_type != stored_sfp_type)
595 hw->phy.sfp_setup_needed = true;
596
597 /* Determine if the SFP+ PHY is dual speed or not. */
598 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
599 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
600 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
601 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
602 hw->phy.multispeed_fiber = true;
603
604 /* Determine PHY vendor */
605 if (hw->phy.type != ixgbe_phy_nl) {
606 hw->phy.id = identifier;
607 hw->phy.ops.read_i2c_eeprom(hw,
608 IXGBE_SFF_VENDOR_OUI_BYTE0,
609 &oui_bytes[0]);
610 hw->phy.ops.read_i2c_eeprom(hw,
611 IXGBE_SFF_VENDOR_OUI_BYTE1,
612 &oui_bytes[1]);
613 hw->phy.ops.read_i2c_eeprom(hw,
614 IXGBE_SFF_VENDOR_OUI_BYTE2,
615 &oui_bytes[2]);
616
617 vendor_oui =
618 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
619 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
620 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
621
622 switch (vendor_oui) {
623 case IXGBE_SFF_VENDOR_OUI_TYCO:
624 if (transmission_media &
625 IXGBE_SFF_TWIN_AX_CAPABLE)
626 hw->phy.type = ixgbe_phy_tw_tyco;
627 break;
628 case IXGBE_SFF_VENDOR_OUI_FTL:
629 hw->phy.type = ixgbe_phy_sfp_ftl;
630 break;
631 case IXGBE_SFF_VENDOR_OUI_AVAGO:
632 hw->phy.type = ixgbe_phy_sfp_avago;
633 break;
634 case IXGBE_SFF_VENDOR_OUI_INTEL:
635 hw->phy.type = ixgbe_phy_sfp_intel;
636 break;
637 default:
638 if (transmission_media &
639 IXGBE_SFF_TWIN_AX_CAPABLE)
640 hw->phy.type = ixgbe_phy_tw_unknown;
641 else
642 hw->phy.type = ixgbe_phy_sfp_unknown;
643 break;
644 }
645 }
646
647 /* All DA cables are supported */
648 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) {
649 status = 0;
650 goto out;
651 }
652
653 /* 1G SFP modules are not supported */
654 if (comp_codes_10g == 0) {
655 hw->phy.type = ixgbe_phy_sfp_unsupported;
656 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
657 goto out;
658 }
659
660 /* Anything else 82598-based is supported */
661 if (hw->mac.type == ixgbe_mac_82598EB) {
662 status = 0;
663 goto out;
664 }
665
666 /* This is guaranteed to be 82599, no need to check for NULL */
667 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
668 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
669 /* Make sure we're a supported PHY type */
670 if (hw->phy.type == ixgbe_phy_sfp_intel) {
671 status = 0;
672 } else {
673 hw_dbg(hw, "SFP+ module not supported\n");
674 hw->phy.type = ixgbe_phy_sfp_unsupported;
675 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
676 }
677 } else {
678 status = 0;
679 }
680 }
681
682 out:
683 return status;
684 }
685
686 /**
687 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
688 * if it supports a given SFP+ module type, if so it returns the offsets to the
689 * phy init sequence block.
690 * @hw: pointer to hardware structure
691 * @list_offset: offset to the SFP ID list
692 * @data_offset: offset to the SFP data block
693 **/
694 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
695 u16 *list_offset,
696 u16 *data_offset)
697 {
698 u16 sfp_id;
699
700 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
701 return IXGBE_ERR_SFP_NOT_SUPPORTED;
702
703 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
704 return IXGBE_ERR_SFP_NOT_PRESENT;
705
706 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
707 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
708 return IXGBE_ERR_SFP_NOT_SUPPORTED;
709
710 /* Read offset to PHY init contents */
711 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
712
713 if ((!*list_offset) || (*list_offset == 0xFFFF))
714 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
715
716 /* Shift offset to first ID word */
717 (*list_offset)++;
718
719 /*
720 * Find the matching SFP ID in the EEPROM
721 * and program the init sequence
722 */
723 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
724
725 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
726 if (sfp_id == hw->phy.sfp_type) {
727 (*list_offset)++;
728 hw->eeprom.ops.read(hw, *list_offset, data_offset);
729 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
730 hw_dbg(hw, "SFP+ module not supported\n");
731 return IXGBE_ERR_SFP_NOT_SUPPORTED;
732 } else {
733 break;
734 }
735 } else {
736 (*list_offset) += 2;
737 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
738 return IXGBE_ERR_PHY;
739 }
740 }
741
742 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
743 hw_dbg(hw, "No matching SFP+ module found\n");
744 return IXGBE_ERR_SFP_NOT_SUPPORTED;
745 }
746
747 return 0;
748 }
749
750 /**
751 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
752 * @hw: pointer to hardware structure
753 * @byte_offset: EEPROM byte offset to read
754 * @eeprom_data: value read
755 *
756 * Performs byte read operation to SFP module's EEPROM over I2C interface.
757 **/
758 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
759 u8 *eeprom_data)
760 {
761 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
762 IXGBE_I2C_EEPROM_DEV_ADDR,
763 eeprom_data);
764 }
765
766 /**
767 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
768 * @hw: pointer to hardware structure
769 * @byte_offset: EEPROM byte offset to write
770 * @eeprom_data: value to write
771 *
772 * Performs byte write operation to SFP module's EEPROM over I2C interface.
773 **/
774 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
775 u8 eeprom_data)
776 {
777 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
778 IXGBE_I2C_EEPROM_DEV_ADDR,
779 eeprom_data);
780 }
781
782 /**
783 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
784 * @hw: pointer to hardware structure
785 * @byte_offset: byte offset to read
786 * @data: value read
787 *
788 * Performs byte read operation to SFP module's EEPROM over I2C interface at
789 * a specified deivce address.
790 **/
791 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
792 u8 dev_addr, u8 *data)
793 {
794 s32 status = 0;
795 u32 max_retry = 1;
796 u32 retry = 0;
797 bool nack = 1;
798
799 do {
800 ixgbe_i2c_start(hw);
801
802 /* Device Address and write indication */
803 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
804 if (status != 0)
805 goto fail;
806
807 status = ixgbe_get_i2c_ack(hw);
808 if (status != 0)
809 goto fail;
810
811 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
812 if (status != 0)
813 goto fail;
814
815 status = ixgbe_get_i2c_ack(hw);
816 if (status != 0)
817 goto fail;
818
819 ixgbe_i2c_start(hw);
820
821 /* Device Address and read indication */
822 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
823 if (status != 0)
824 goto fail;
825
826 status = ixgbe_get_i2c_ack(hw);
827 if (status != 0)
828 goto fail;
829
830 status = ixgbe_clock_in_i2c_byte(hw, data);
831 if (status != 0)
832 goto fail;
833
834 status = ixgbe_clock_out_i2c_bit(hw, nack);
835 if (status != 0)
836 goto fail;
837
838 ixgbe_i2c_stop(hw);
839 break;
840
841 fail:
842 ixgbe_i2c_bus_clear(hw);
843 retry++;
844 if (retry < max_retry)
845 hw_dbg(hw, "I2C byte read error - Retrying.\n");
846 else
847 hw_dbg(hw, "I2C byte read error.\n");
848
849 } while (retry < max_retry);
850
851 return status;
852 }
853
854 /**
855 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
856 * @hw: pointer to hardware structure
857 * @byte_offset: byte offset to write
858 * @data: value to write
859 *
860 * Performs byte write operation to SFP module's EEPROM over I2C interface at
861 * a specified device address.
862 **/
863 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
864 u8 dev_addr, u8 data)
865 {
866 s32 status = 0;
867 u32 max_retry = 1;
868 u32 retry = 0;
869
870 do {
871 ixgbe_i2c_start(hw);
872
873 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
874 if (status != 0)
875 goto fail;
876
877 status = ixgbe_get_i2c_ack(hw);
878 if (status != 0)
879 goto fail;
880
881 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
882 if (status != 0)
883 goto fail;
884
885 status = ixgbe_get_i2c_ack(hw);
886 if (status != 0)
887 goto fail;
888
889 status = ixgbe_clock_out_i2c_byte(hw, data);
890 if (status != 0)
891 goto fail;
892
893 status = ixgbe_get_i2c_ack(hw);
894 if (status != 0)
895 goto fail;
896
897 ixgbe_i2c_stop(hw);
898 break;
899
900 fail:
901 ixgbe_i2c_bus_clear(hw);
902 retry++;
903 if (retry < max_retry)
904 hw_dbg(hw, "I2C byte write error - Retrying.\n");
905 else
906 hw_dbg(hw, "I2C byte write error.\n");
907 } while (retry < max_retry);
908
909 return status;
910 }
911
912 /**
913 * ixgbe_i2c_start - Sets I2C start condition
914 * @hw: pointer to hardware structure
915 *
916 * Sets I2C start condition (High -> Low on SDA while SCL is High)
917 **/
918 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
919 {
920 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
921
922 /* Start condition must begin with data and clock high */
923 ixgbe_set_i2c_data(hw, &i2cctl, 1);
924 ixgbe_raise_i2c_clk(hw, &i2cctl);
925
926 /* Setup time for start condition (4.7us) */
927 udelay(IXGBE_I2C_T_SU_STA);
928
929 ixgbe_set_i2c_data(hw, &i2cctl, 0);
930
931 /* Hold time for start condition (4us) */
932 udelay(IXGBE_I2C_T_HD_STA);
933
934 ixgbe_lower_i2c_clk(hw, &i2cctl);
935
936 /* Minimum low period of clock is 4.7 us */
937 udelay(IXGBE_I2C_T_LOW);
938
939 }
940
941 /**
942 * ixgbe_i2c_stop - Sets I2C stop condition
943 * @hw: pointer to hardware structure
944 *
945 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
946 **/
947 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
948 {
949 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
950
951 /* Stop condition must begin with data low and clock high */
952 ixgbe_set_i2c_data(hw, &i2cctl, 0);
953 ixgbe_raise_i2c_clk(hw, &i2cctl);
954
955 /* Setup time for stop condition (4us) */
956 udelay(IXGBE_I2C_T_SU_STO);
957
958 ixgbe_set_i2c_data(hw, &i2cctl, 1);
959
960 /* bus free time between stop and start (4.7us)*/
961 udelay(IXGBE_I2C_T_BUF);
962 }
963
964 /**
965 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
966 * @hw: pointer to hardware structure
967 * @data: data byte to clock in
968 *
969 * Clocks in one byte data via I2C data/clock
970 **/
971 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
972 {
973 s32 status = 0;
974 s32 i;
975 bool bit = 0;
976
977 for (i = 7; i >= 0; i--) {
978 status = ixgbe_clock_in_i2c_bit(hw, &bit);
979 *data |= bit << i;
980
981 if (status != 0)
982 break;
983 }
984
985 return status;
986 }
987
988 /**
989 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
990 * @hw: pointer to hardware structure
991 * @data: data byte clocked out
992 *
993 * Clocks out one byte data via I2C data/clock
994 **/
995 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
996 {
997 s32 status = 0;
998 s32 i;
999 u32 i2cctl;
1000 bool bit = 0;
1001
1002 for (i = 7; i >= 0; i--) {
1003 bit = (data >> i) & 0x1;
1004 status = ixgbe_clock_out_i2c_bit(hw, bit);
1005
1006 if (status != 0)
1007 break;
1008 }
1009
1010 /* Release SDA line (set high) */
1011 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1012 i2cctl |= IXGBE_I2C_DATA_OUT;
1013 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1014
1015 return status;
1016 }
1017
1018 /**
1019 * ixgbe_get_i2c_ack - Polls for I2C ACK
1020 * @hw: pointer to hardware structure
1021 *
1022 * Clocks in/out one bit via I2C data/clock
1023 **/
1024 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1025 {
1026 s32 status;
1027 u32 i = 0;
1028 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1029 u32 timeout = 10;
1030 bool ack = 1;
1031
1032 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1033
1034 if (status != 0)
1035 goto out;
1036
1037 /* Minimum high period of clock is 4us */
1038 udelay(IXGBE_I2C_T_HIGH);
1039
1040 /* Poll for ACK. Note that ACK in I2C spec is
1041 * transition from 1 to 0 */
1042 for (i = 0; i < timeout; i++) {
1043 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1044 ack = ixgbe_get_i2c_data(&i2cctl);
1045
1046 udelay(1);
1047 if (ack == 0)
1048 break;
1049 }
1050
1051 if (ack == 1) {
1052 hw_dbg(hw, "I2C ack was not received.\n");
1053 status = IXGBE_ERR_I2C;
1054 }
1055
1056 ixgbe_lower_i2c_clk(hw, &i2cctl);
1057
1058 /* Minimum low period of clock is 4.7 us */
1059 udelay(IXGBE_I2C_T_LOW);
1060
1061 out:
1062 return status;
1063 }
1064
1065 /**
1066 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1067 * @hw: pointer to hardware structure
1068 * @data: read data value
1069 *
1070 * Clocks in one bit via I2C data/clock
1071 **/
1072 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1073 {
1074 s32 status;
1075 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1076
1077 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1078
1079 /* Minimum high period of clock is 4us */
1080 udelay(IXGBE_I2C_T_HIGH);
1081
1082 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1083 *data = ixgbe_get_i2c_data(&i2cctl);
1084
1085 ixgbe_lower_i2c_clk(hw, &i2cctl);
1086
1087 /* Minimum low period of clock is 4.7 us */
1088 udelay(IXGBE_I2C_T_LOW);
1089
1090 return status;
1091 }
1092
1093 /**
1094 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1095 * @hw: pointer to hardware structure
1096 * @data: data value to write
1097 *
1098 * Clocks out one bit via I2C data/clock
1099 **/
1100 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1101 {
1102 s32 status;
1103 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1104
1105 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1106 if (status == 0) {
1107 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1108
1109 /* Minimum high period of clock is 4us */
1110 udelay(IXGBE_I2C_T_HIGH);
1111
1112 ixgbe_lower_i2c_clk(hw, &i2cctl);
1113
1114 /* Minimum low period of clock is 4.7 us.
1115 * This also takes care of the data hold time.
1116 */
1117 udelay(IXGBE_I2C_T_LOW);
1118 } else {
1119 status = IXGBE_ERR_I2C;
1120 hw_dbg(hw, "I2C data was not set to %X\n", data);
1121 }
1122
1123 return status;
1124 }
1125 /**
1126 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1127 * @hw: pointer to hardware structure
1128 * @i2cctl: Current value of I2CCTL register
1129 *
1130 * Raises the I2C clock line '0'->'1'
1131 **/
1132 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1133 {
1134 s32 status = 0;
1135
1136 *i2cctl |= IXGBE_I2C_CLK_OUT;
1137
1138 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1139
1140 /* SCL rise time (1000ns) */
1141 udelay(IXGBE_I2C_T_RISE);
1142
1143 return status;
1144 }
1145
1146 /**
1147 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1148 * @hw: pointer to hardware structure
1149 * @i2cctl: Current value of I2CCTL register
1150 *
1151 * Lowers the I2C clock line '1'->'0'
1152 **/
1153 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1154 {
1155
1156 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1157
1158 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1159
1160 /* SCL fall time (300ns) */
1161 udelay(IXGBE_I2C_T_FALL);
1162 }
1163
1164 /**
1165 * ixgbe_set_i2c_data - Sets the I2C data bit
1166 * @hw: pointer to hardware structure
1167 * @i2cctl: Current value of I2CCTL register
1168 * @data: I2C data value (0 or 1) to set
1169 *
1170 * Sets the I2C data bit
1171 **/
1172 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1173 {
1174 s32 status = 0;
1175
1176 if (data)
1177 *i2cctl |= IXGBE_I2C_DATA_OUT;
1178 else
1179 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1180
1181 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1182
1183 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1184 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1185
1186 /* Verify data was set correctly */
1187 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1188 if (data != ixgbe_get_i2c_data(i2cctl)) {
1189 status = IXGBE_ERR_I2C;
1190 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1191 }
1192
1193 return status;
1194 }
1195
1196 /**
1197 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1198 * @hw: pointer to hardware structure
1199 * @i2cctl: Current value of I2CCTL register
1200 *
1201 * Returns the I2C data bit value
1202 **/
1203 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1204 {
1205 bool data;
1206
1207 if (*i2cctl & IXGBE_I2C_DATA_IN)
1208 data = 1;
1209 else
1210 data = 0;
1211
1212 return data;
1213 }
1214
1215 /**
1216 * ixgbe_i2c_bus_clear - Clears the I2C bus
1217 * @hw: pointer to hardware structure
1218 *
1219 * Clears the I2C bus by sending nine clock pulses.
1220 * Used when data line is stuck low.
1221 **/
1222 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1223 {
1224 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1225 u32 i;
1226
1227 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1228
1229 for (i = 0; i < 9; i++) {
1230 ixgbe_raise_i2c_clk(hw, &i2cctl);
1231
1232 /* Min high period of clock is 4us */
1233 udelay(IXGBE_I2C_T_HIGH);
1234
1235 ixgbe_lower_i2c_clk(hw, &i2cctl);
1236
1237 /* Min low period of clock is 4.7us*/
1238 udelay(IXGBE_I2C_T_LOW);
1239 }
1240
1241 /* Put the i2c bus back to default state */
1242 ixgbe_i2c_stop(hw);
1243 }
1244
1245 /**
1246 * ixgbe_check_phy_link_tnx - Determine link and speed status
1247 * @hw: pointer to hardware structure
1248 *
1249 * Reads the VS1 register to determine if link is up and the current speed for
1250 * the PHY.
1251 **/
1252 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1253 bool *link_up)
1254 {
1255 s32 status = 0;
1256 u32 time_out;
1257 u32 max_time_out = 10;
1258 u16 phy_link = 0;
1259 u16 phy_speed = 0;
1260 u16 phy_data = 0;
1261
1262 /* Initialize speed and link to default case */
1263 *link_up = false;
1264 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1265
1266 /*
1267 * Check current speed and link status of the PHY register.
1268 * This is a vendor specific register and may have to
1269 * be changed for other copper PHYs.
1270 */
1271 for (time_out = 0; time_out < max_time_out; time_out++) {
1272 udelay(10);
1273 status = hw->phy.ops.read_reg(hw,
1274 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1275 MDIO_MMD_VEND1,
1276 &phy_data);
1277 phy_link = phy_data &
1278 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1279 phy_speed = phy_data &
1280 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1281 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1282 *link_up = true;
1283 if (phy_speed ==
1284 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1285 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1286 break;
1287 }
1288 }
1289
1290 return status;
1291 }
1292
1293 /**
1294 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1295 * @hw: pointer to hardware structure
1296 * @firmware_version: pointer to the PHY Firmware Version
1297 **/
1298 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1299 u16 *firmware_version)
1300 {
1301 s32 status = 0;
1302
1303 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1304 firmware_version);
1305
1306 return status;
1307 }
1308
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