drivers/net/sh_eth.h

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008 Renesas Solutions Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *  You should have received a copy of the GNU General Public License along with
  16  *  this program; if not, write to the Free Software Foundation, Inc.,
  17  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *  The full GNU General Public License is included in this distribution in
  20  *  the file called "COPYING".
  21  */
  22
  23 #ifndef __SH_ETH_H__
  24 #define __SH_ETH_H__
  25
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/phy.h>
  32
  33 #define CARDNAME        "sh-eth"
  34 #define TX_TIMEOUT      (5*HZ)
  35
  36 #define TX_RING_SIZE    128     /* Tx ring size */
  37 #define RX_RING_SIZE    128     /* Rx ring size */
  38 #define RX_OFFSET               2       /* skb offset */
  39 #define ETHERSMALL              60
  40 #define PKT_BUF_SZ              1538
  41
  42 /* Chip Base Address */
  43 #define SH_TSU_ADDR 0xA7000804
  44
  45 /* Chip Registers */
  46 /* E-DMAC */
  47 #define EDMR    0x0000
  48 #define EDTRR   0x0004
  49 #define EDRRR   0x0008
  50 #define TDLAR   0x000C
  51 #define RDLAR   0x0010
  52 #define EESR    0x0014
  53 #define EESIPR  0x0018
  54 #define TRSCER  0x001C
  55 #define RMFCR   0x0020
  56 #define TFTR    0x0024
  57 #define FDR             0x0028
  58 #define RMCR    0x002C
  59 #define EDOCR   0x0030
  60 #define FCFTR   0x0034
  61 #define RPADIR  0x0038
  62 #define TRIMD   0x003C
  63 #define RBWAR   0x0040
  64 #define RDFAR   0x0044
  65 #define TBRAR   0x004C
  66 #define TDFAR   0x0050
  67 /* Ether Register */
  68 #define ECMR    0x0160
  69 #define ECSR    0x0164
  70 #define ECSIPR  0x0168
  71 #define PIR             0x016C
  72 #define MAHR    0x0170
  73 #define MALR    0x0174
  74 #define RFLR    0x0178
  75 #define PSR             0x017C
  76 #define TROCR   0x0180
  77 #define CDCR    0x0184
  78 #define LCCR    0x0188
  79 #define CNDCR   0x018C
  80 #define CEFCR   0x0194
  81 #define FRECR   0x0198
  82 #define TSFRCR  0x019C
  83 #define TLFRCR  0x01A0
  84 #define RFCR    0x01A4
  85 #define MAFCR   0x01A8
  86 #define IPGR    0x01B4
  87 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
  88 #define APR             0x01B8
  89 #define MPR     0x01BC
  90 #define TPAUSER 0x1C4
  91 #define BCFR    0x1CC
  92 #endif /* CONFIG_CPU_SH7710 */
  93
  94 #define ARSTR   0x0800
  95
  96 /* TSU */
  97 #define TSU_CTRST       0x004
  98 #define TSU_FWEN0       0x010
  99 #define TSU_FWEN1       0x014
 100 #define TSU_FCM         0x018
 101 #define TSU_BSYSL0      0x020
 102 #define TSU_BSYSL1      0x024
 103 #define TSU_PRISL0      0x028
 104 #define TSU_PRISL1      0x02C
 105 #define TSU_FWSL0       0x030
 106 #define TSU_FWSL1       0x034
 107 #define TSU_FWSLC       0x038
 108 #define TSU_QTAGM0      0x040
 109 #define TSU_QTAGM1      0x044
 110 #define TSU_ADQT0       0x048
 111 #define TSU_ADQT1       0x04C
 112 #define TSU_FWSR        0x050
 113 #define TSU_FWINMK      0x054
 114 #define TSU_ADSBSY      0x060
 115 #define TSU_TEN         0x064
 116 #define TSU_POST1       0x070
 117 #define TSU_POST2       0x074
 118 #define TSU_POST3       0x078
 119 #define TSU_POST4       0x07C
 120 #define TXNLCR0         0x080
 121 #define TXALCR0         0x084
 122 #define RXNLCR0         0x088
 123 #define RXALCR0         0x08C
 124 #define FWNLCR0         0x090
 125 #define FWALCR0         0x094
 126 #define TXNLCR1         0x0A0
 127 #define TXALCR1         0x0A4
 128 #define RXNLCR1         0x0A8
 129 #define RXALCR1         0x0AC
 130 #define FWNLCR1         0x0B0
 131 #define FWALCR1         0x0B4
 132
 133 #define TSU_ADRH0       0x0100
 134 #define TSU_ADRL0       0x0104
 135 #define TSU_ADRL31      0x01FC
 136
 137 /* Register's bits */
 138
 139 /* EDMR */
 140 enum DMAC_M_BIT {
 141         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
 142 };
 143
 144 /* EDTRR */
 145 enum DMAC_T_BIT {
 146         EDTRR_TRNS = 0x01,
 147 };
 148
 149 /* EDRRR*/
 150 enum EDRRR_R_BIT {
 151         EDRRR_R = 0x01,
 152 };
 153
 154 /* TPAUSER */
 155 enum TPAUSER_BIT {
 156         TPAUSER_TPAUSE = 0x0000ffff,
 157         TPAUSER_UNLIMITED = 0,
 158 };
 159
 160 /* BCFR */
 161 enum BCFR_BIT {
 162         BCFR_RPAUSE = 0x0000ffff,
 163         BCFR_UNLIMITED = 0,
 164 };
 165
 166 /* PIR */
 167 enum PIR_BIT {
 168         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 169 };
 170
 171 /* PSR */
 172 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 173
 174 /* EESR */
 175 enum EESR_BIT {
 176         EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
 177         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 178         EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
 179         EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
 180         EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
 181         EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
 182         EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
 183         EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
 184         EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
 185         EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
 186         EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
 187 };
 188
 189 #define EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 190                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 191
 192 /* EESIPR */
 193 enum DMAC_IM_BIT {
 194         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 195         DMAC_M_RABT = 0x02000000,
 196         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 197         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 198         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 199         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 200         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 201         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 202         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 203         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 204         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 205         DMAC_M_RINT1 = 0x00000001,
 206 };
 207
 208 /* Receive descriptor bit */
 209 enum RD_STS_BIT {
 210         RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
 211         RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
 212         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 213         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 214         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 215         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 216         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 217         RD_RFS1 = 0x00000001,
 218 };
 219 #define RDF1ST  RC_RFP1
 220 #define RDFEND  RC_RFP0
 221 #define RD_RFP  (RC_RFP1|RC_RFP0)
 222
 223 /* FCFTR */
 224 enum FCFTR_BIT {
 225         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 226         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 227         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 228 };
 229 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 230 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 231
 232 /* Transfer descriptor bit */
 233 enum TD_STS_BIT {
 234         TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 235         TD_TFP0 = 0x10000000,
 236 };
 237 #define TDF1ST  TD_TFP1
 238 #define TDFEND  TD_TFP0
 239 #define TD_TFP  (TD_TFP1|TD_TFP0)
 240
 241 /* RMCR */
 242 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 243 /* ECMR */
 244 enum FELIC_MODE_BIT {
 245         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 246         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 247         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 248         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 249         ECMR_PRM = 0x00000001,
 250 };
 251
 252 /* ECSR */
 253 enum ECSR_STATUS_BIT {
 254         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
 255         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 256 };
 257
 258 /* ECSIPR */
 259 enum ECSIPR_STATUS_MASK_BIT {
 260         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
 261         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 262 };
 263
 264 /* APR */
 265 enum APR_BIT {
 266         APR_AP = 0x00000001,
 267 };
 268
 269 /* MPR */
 270 enum MPR_BIT {
 271         MPR_MP = 0x00000001,
 272 };
 273
 274 /* TRSCER */
 275 enum DESC_I_BIT {
 276         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 277         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 278         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 279         DESC_I_RINT1 = 0x0001,
 280 };
 281
 282 /* RPADIR */
 283 enum RPADIR_BIT {
 284         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 285         RPADIR_PADR = 0x0003f,
 286 };
 287
 288 /* FDR */
 289 enum FIFO_SIZE_BIT {
 290         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 291 };
 292 enum phy_offsets {
 293         PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 294         PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 295         PHY_16 = 16,
 296 };
 297
 298 /* PHY_CTRL */
 299 enum PHY_CTRL_BIT {
 300         PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 301         PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 302         PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 303 };
 304 #define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 305
 306 /* PHY_STAT */
 307 enum PHY_STAT_BIT {
 308         PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 309         PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 310         PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 311         PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 312 };
 313
 314 /* PHY_ANA */
 315 enum PHY_ANA_BIT {
 316         PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 317         PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 318         PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 319         PHY_A_SEL = 0x001f,
 320 };
 321 /* PHY_ANL */
 322 enum PHY_ANL_BIT {
 323         PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 324         PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 325         PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 326         PHY_L_SEL = 0x001f,
 327 };
 328
 329 /* PHY_ANE */
 330 enum PHY_ANE_BIT {
 331         PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 332         PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 333 };
 334
 335 /* DM9161 */
 336 enum PHY_16_BIT {
 337         PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 338         PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 339         PHY_16_TXselect = 0x0400,
 340         PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 341         PHY_16_Force100LNK = 0x0080,
 342         PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 343         PHY_16_RPDCTR_EN = 0x0010,
 344         PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 345         PHY_16_Sleepmode = 0x0002,
 346         PHY_16_RemoteLoopOut = 0x0001,
 347 };
 348
 349 #define POST_RX         0x08
 350 #define POST_FW         0x04
 351 #define POST0_RX        (POST_RX)
 352 #define POST0_FW        (POST_FW)
 353 #define POST1_RX        (POST_RX >> 2)
 354 #define POST1_FW        (POST_FW >> 2)
 355 #define POST_ALL        (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
 356
 357 /* ARSTR */
 358 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 359
 360 /* TSU_FWEN0 */
 361 enum TSU_FWEN0_BIT {
 362         TSU_FWEN0_0 = 0x00000001,
 363 };
 364
 365 /* TSU_ADSBSY */
 366 enum TSU_ADSBSY_BIT {
 367         TSU_ADSBSY_0 = 0x00000001,
 368 };
 369
 370 /* TSU_TEN */
 371 enum TSU_TEN_BIT {
 372         TSU_TEN_0 = 0x80000000,
 373 };
 374
 375 /* TSU_FWSL0 */
 376 enum TSU_FWSL0_BIT {
 377         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 378         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 379         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 380 };
 381
 382 /* TSU_FWSLC */
 383 enum TSU_FWSLC_BIT {
 384         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 385         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 386         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 387         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 388         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 389 };
 390
 391 /*
 392  * The sh ether Tx buffer descriptors.
 393  * This structure should be 20 bytes.
 394  */
 395 struct sh_eth_txdesc {
 396         u32 status;             /* TD0 */
 397 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 398         u16 pad0;               /* TD1 */
 399         u16 buffer_length;      /* TD1 */
 400 #else
 401         u16 buffer_length;      /* TD1 */
 402         u16 pad0;               /* TD1 */
 403 #endif
 404         u32 addr;               /* TD2 */
 405         u32 pad1;               /* padding data */
 406 };
 407
 408 /*
 409  * The sh ether Rx buffer descriptors.
 410  * This structure should be 20 bytes.
 411  */
 412 struct sh_eth_rxdesc {
 413         u32 status;             /* RD0 */
 414 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 415         u16 frame_length;       /* RD1 */
 416         u16 buffer_length;      /* RD1 */
 417 #else
 418         u16 buffer_length;      /* RD1 */
 419         u16 frame_length;       /* RD1 */
 420 #endif
 421         u32 addr;               /* RD2 */
 422         u32 pad0;               /* padding data */
 423 };
 424
 425 struct sh_eth_private {
 426         dma_addr_t rx_desc_dma;
 427         dma_addr_t tx_desc_dma;
 428         struct sh_eth_rxdesc *rx_ring;
 429         struct sh_eth_txdesc *tx_ring;
 430         struct sk_buff **rx_skbuff;
 431         struct sk_buff **tx_skbuff;
 432         struct net_device_stats stats;
 433         struct timer_list timer;
 434         spinlock_t lock;
 435         u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 436         u32 cur_tx, dirty_tx;
 437         u32 rx_buf_sz;          /* Based on MTU+slack. */
 438         /* MII transceiver section. */
 439         u32 phy_id;                                     /* PHY ID */
 440         struct mii_bus *mii_bus;        /* MDIO bus control */
 441         struct phy_device *phydev;      /* PHY device control */
 442         enum phy_state link;
 443         int msg_enable;
 444         int speed;
 445         int duplex;
 446         u32 rx_int_var, tx_int_var;     /* interrupt control variables */
 447         char post_rx;           /* POST receive */
 448         char post_fw;           /* POST forward */
 449         struct net_device_stats tsu_stats;      /* TSU forward status */
 450 };
 451
 452 static void swaps(char *src, int len)
 453 {
 454 #ifdef __LITTLE_ENDIAN__
 455         u32 *p = (u32 *)src;
 456         u32 *maxp;
 457         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 458
 459         for (; p < maxp; p++)
 460                 *p = swab32(*p);
 461 #endif
 462 }
 463
 464 #endif